Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a body structure and an outer edge structure, and the outer edge structure is located at the periphery of the bottom of the body structure. The body structure comprises a top face and a bottom face which are arranged oppositely, and a side face located between the top face and the outer edge structure. The side face comprises a first side face connected with the outer edge structure, and the transverse distance of the first side face relative to the outer edge structure is gradually reduced in the direction from the top face to the bottom face.

Description

Semiconductor device and method for manufacturing the same Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to a semiconductor device and a method for making the same. Background Art

[0002] NAND memory devices are non-volatile storage products with low power consumption, lightweight, and high performance, and are widely used in electronic products. Planar NAND devices have reached their practical scalability limits. To further increase storage capacity and reduce the cost per bit, 3D NAND memory has been proposed. In a 3D NAND memory structure, multiple layers of data storage cells are stacked vertically to create a stacked memory architecture.

[0003] In the manufacturing process, a wafer is first prepared and then cut into multiple storage particles along the cutting lines. When preparing bonded wafers, the edges of the bonded wafers need to be cut. The cut surface formed by the existing cutting process is likely to have a negative impact on the device in subsequent processes. Technical Solutions

[0004] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, aiming to make the corners between the side surfaces of the main structure and the peripheral structure smoother, thereby reducing the impact of subsequent processes on the semiconductor device.

[0005] In one aspect, the present disclosure provides a semiconductor device, comprising:

[0006] Body structure;

[0007] An outer edge structure, located at the periphery of the bottom of the main body structure;

[0008] In which, the main body structure includes a top surface and a bottom surface arranged back to back, and a side surface located between the top surface and the outer edge structure; the side surface includes a first side surface connected to the outer edge structure, and the lateral distance of the first side surface relative to the outer edge structure gradually decreases from the top surface to the bottom surface.

[0009] In some embodiments, the body structure comprises:

[0010] carrier;

[0011] a device structure, located on the carrier;

[0012] The outer edge structure is located on the side wall of the carrier, and the thickness of the outer edge structure is less than or equal to the thickness of the carrier.

[0013] In some embodiments, an orthographic projection of the device structure on the carrier is located within the carrier.

[0014] In some embodiments, the outer edge structure comprises:

[0015] a first surface connected to the side surface;

[0016] a second surface, parallel to the first surface and coplanar with the bottom surface of the body structure;

[0017] The first side surface is an inclined surface, and the angle between the inclined surface and the first surface is an obtuse angle.

[0018] In some embodiments, the first side comprises a curved surface.

[0019] In some embodiments, the side surface further includes a second side surface connected to the first side surface, and a lateral distance of the second side surface relative to the outer edge structure gradually decreases from the top surface to the bottom surface.

[0020] In some embodiments, the second side surface is an inclined surface or a curved surface.

[0021] In some embodiments, both the second side surface and the first side surface are inclined surfaces, and the second side surface and the first side surface have the same degree of inclination.

[0022] In some embodiments, the semiconductor device includes a first semiconductor structure and a second semiconductor structure bonded to each other, the first semiconductor structure includes the carrier and a circuit layer located between the carrier and the second semiconductor structure, and the circuit layer and the second semiconductor structure constitute the device structure.

[0023] In some embodiments, the top surface of the body structure is a surface of the second semiconductor structure facing away from the first semiconductor structure, and the bottom surface of the body structure is a surface of the carrier facing away from the circuit layer.

[0024] In some embodiments, the second semiconductor structure includes a memory array connected to the circuit layer.

[0025] In another aspect, the present disclosure provides a method for preparing a semiconductor device, comprising:

[0026] A main body structure and an outer edge structure located at the bottom periphery of the main body structure are formed, wherein the main body structure includes a top surface and a bottom surface disposed opposite to each other, and a side surface located between the top surface and the outer edge structure; the side surface includes a first side surface adjacent to the outer edge structure, wherein a lateral distance of the first side surface relative to the outer edge structure gradually decreases from the top surface toward the bottom surface;

[0027] Adhesive tape is applied to the main body structure and the outer edge structure.

[0028] In some embodiments, after the step of attaching tape to the main structure and the peripheral structure, the method for preparing a semiconductor device further includes:

[0029] The bottom surface of the main body structure and the side of the peripheral structure close to the bottom surface are ground and thinned.

[0030] In some embodiments, the step of forming the main body structure and the peripheral structure located at the bottom periphery of the main body structure includes:

[0031] providing a carrier and an edge structure located on a sidewall of the carrier;

[0032] forming a device structure on the carrier, wherein the carrier and the device structure constitute the main body structure;

[0033] The edges of the body structure are trimmed to form the side surfaces.

[0034] In some embodiments, the step of forming a device structure on the carrier includes:

[0035] forming a circuit layer on the carrier to form a first semiconductor structure including the carrier and the circuit layer;

[0036] A second semiconductor structure is provided, and the second semiconductor structure is bonded to the circuit layer of the first semiconductor structure.

[0037] In some embodiments, the second semiconductor structure includes a memory array and a common source layer connected to the memory array, and a surface of the common source layer facing away from the first semiconductor structure is the top surface of the body structure; and the method for preparing the semiconductor device further includes:

[0038] forming a photoresist layer on the top surface and side surfaces of the main structure;

[0039] Performing a photolithography process on the photoresist layer using a mask to form a patterned photoresist layer;

[0040] Lead-out contacts are formed on the top surface using the patterned photoresist layer.

[0041] In some embodiments, the semiconductor device includes a plurality of dicing streets, and the method for preparing the semiconductor device further includes:

[0042] The semiconductor device is cut into a plurality of memory particles along the cutting streets.

[0043] The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a main body structure and an outer edge structure, wherein the outer edge structure is located at the periphery of the bottom of the main body structure. The main body structure includes a top surface and a bottom surface disposed opposite to each other, and a side surface located between the top surface and the outer edge structure. The side surface includes a first side surface connected to the outer edge structure, and the lateral distance of the first side surface relative to the outer edge structure gradually decreases from the top surface to the bottom surface. Therefore, the corner between the first side surface of the main body structure and the outer edge structure is relatively smooth, which is conducive to reducing the gap formed by the adhesive tape at the corner, thereby reducing the impact of subsequent processes on the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The technical solutions and other beneficial effects of the present disclosure will be made apparent by describing the specific embodiments of the present disclosure in detail below in conjunction with the accompanying drawings.

[0045] FIG1 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0046] FIG2 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0047] FIG3 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0048] FIG4 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0049] FIG5 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0050] FIG6 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0051] 7a-7d are schematic structural diagrams of semiconductor devices provided by some embodiments of the present disclosure during relevant preparation processes corresponding to the preparation method shown in FIG. 6 ;

[0052] FIG8 is a schematic structural diagram of a storage system provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0054] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of this disclosure.

[0055] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0056] As used herein, the term "layer" refers to a portion of a material including an area with a thickness. A layer may extend over the entire underlying or superstructure, or may have a range that is smaller than the range of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer (wherein contacts, interconnect lines, and / or vertical interconnect access (VIA) are formed) and one or more dielectric layers.

[0057] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate.

[0058] It should be noted that the illustrations provided in the embodiments of the present disclosure are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed at will, and the component layout may also be more complicated.

[0059] Please refer to Figure 1, which is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present disclosure. The semiconductor device 100 may be a wafer, which, after dicing, can be formed into multiple memory chips, such as a three-dimensional memory. Three-dimensional memory can be applied to communications products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data. Consumer electronics products include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, and gaming products.

[0060] The semiconductor device 100 includes a main body structure 10 and an outer edge structure 20, wherein the outer edge structure 20 is located at the periphery of the bottom of the main body structure 10. Specifically, the outer edge structure 20 extends from the bottom edge of the main body structure 10 in a horizontal direction (X) to protrude from the main body structure 10. The main body structure 10 refers to the internal main structure of an entire wafer, and the outer edge structure 20 is the outer edge or edge of the entire wafer, rather than the outer edge of a single storage particle.

[0061] The main body structure 10 includes a top surface 11 and a bottom surface 12 disposed opposite each other, and a side surface 13 located between the top surface 11 and the peripheral structure 20. The top surface 11 and the bottom surface 12 can be arranged parallel to each other. The side surface 13 includes a first side surface 131 connected to the peripheral structure 20. The lateral distance D1 of the first side surface 131 relative to the peripheral structure 20 gradually decreases from the top surface 11 to the bottom surface 12. For example, the direction from the top surface 11 to the bottom surface 12 is Y, and the first side surface 131 has positions P1 and P2 along the Y direction. Then, the lateral distance D1 from P1 to the peripheral structure 20 is greater than the lateral distance from P2 to the peripheral structure 20. For clarity of the diagram, only the lateral distance D1 from P2 to the peripheral structure 20 is shown.

[0062] In some embodiments, both the top surface 11 and the bottom surface 12 may be circular in top view, and the area of ​​the bottom surface 12 may be larger than that of the top surface 11, that is, the orthographic projection of the top surface 11 on the bottom surface 12 is located within the bottom surface 12. The top of the side surface 13 is disposed around the top surface 11, that is, connected to the top surface 11, and the bottom of the side surface 13 may also form a circle.

[0063] It should be noted that the top surface 11 and the bottom surface 12 refer to relative orientations in the diagram. If the overall structure is inverted, the top surface 11 can be referred to as the bottom surface, and the bottom surface 12 can be referred to as the top surface. Figure 1 is a cross-sectional view of the semiconductor device 100 along the XY direction, and the side surface 13 refers to the side surface of the cross-section. In practice, in a three-dimensional structure, the side surface of the semiconductor device 100 is a continuous surface formed by the side surfaces 13, such as the side surface of a truncated cone.

[0064] In some embodiments, the side surface 13 further includes a second side surface 132 connected to the first side surface 131. The lateral distance of the second side surface 132 relative to the outer edge structure 20 gradually decreases from the top surface 11 toward the bottom surface 12. For example, the second side surface 132 has positions P3 and P4 along the Y direction, and the lateral distance from P3 to the outer edge structure 20 is greater than the lateral distance from P4 to the outer edge structure 20.

[0065] In some embodiments, the first side surface 131 may include at least one of an inclined surface and a curved surface. The second side surface 132 may also include at least one of an inclined surface and a curved surface. For example, as shown in FIG1 , the first side surface 131 is an inclined surface, the second side surface 132 is an inclined surface, and the first side surface 131 and the second side surface 132 have the same degree of inclination, that is, the first side surface 131 and the second side surface 132 are coplanar. Because the first side surface 131 and the second side surface 132 are coplanar, the boundary between the first side surface 131 and the second side surface 132 can be located anywhere on the side surface 13 .

[0066] When the first side surface 131 and the second side surface 132 are inclined surfaces and coplanar, the side surface 13 formed by the first side surface 131 and the second side surface 132 can be a side surface of a truncated cone. In some embodiments, the first side surface 131 is an inclined surface, and the angle between the inclined surface and the first surface 21 is an obtuse angle.

[0067] In some embodiments, the inclined surface may be composed of a plurality of continuous small steps.

[0068] The outer edge structure 20 may include a first surface 21 and a second surface 22 that are parallel to each other, wherein the first surface 21 is connected to the side surface 13, that is, connected to the first side surface 131. The second surface 22 is coplanar with the bottom surface 12 of the main body structure 10, that is, the bottom surface of the outer edge structure 20 is coplanar with the bottom surface 12 of the main body structure 10.

[0069] The body structure 10 may include a carrier 110 and a device structure 120, with the device structure 120 located on the carrier 110. The peripheral structure 20 is located on the sidewall of the carrier 110, and the thickness of the peripheral structure 20 in the Y direction is less than or equal to the thickness of the carrier 110 in the Y direction. As shown in FIG1 , the thickness of the peripheral structure 20 is less than the thickness of the carrier 110, so the first side surface 131 includes a portion of the side surface of the carrier 110.

[0070] In some embodiments, an orthographic projection of the device structure 120 on the carrier 110 is located within the carrier 110 .

[0071] In some embodiments, the semiconductor device 100 may include a first semiconductor structure 130 and a second semiconductor structure 140 bonded to each other. The first semiconductor structure 130 includes a carrier 110 and a circuit layer 111, wherein the circuit layer 111 is located between the carrier 110 and the second semiconductor structure 140. The circuit layer 111 and the second semiconductor structure 140 constitute the device structure 120. The device structure 120 may further include a bonding layer located between the circuit layer 111 and the second semiconductor structure 140.

[0072] The top surface 11 of the body structure 10 may be a surface of the second semiconductor structure 140 facing away from the first semiconductor structure 130 , and the bottom surface 12 of the body structure 10 may be a surface of the carrier 110 facing away from the circuit layer 111 .

[0073] The circuit layer 111 in the first semiconductor structure 130 may be a CMOS (complementary metal oxide semiconductor), and the second semiconductor structure 140 may include a memory array connected to the circuit layer 111. The memory array may include a stacked structure and a memory channel structure 141 that runs through the stacked structure along the stacking direction (Y) of the stacked structure, and the stacked structure includes alternating gate layers and insulating layers. The second semiconductor structure 140 may also include a common source layer 142 connected to one end of the memory channel structure 141, and the other end of the memory channel structure 141 is connected to the circuit layer 111. The common source layer 142 is also connected to the circuit layer 111.

[0074] It should be noted that the diagram only shows the storage array in one storage particle in a wafer. In reality, there may be multiple storage particles in the wafer, and the present disclosure does not limit the number of storage particles in the wafer.

[0075] In some embodiments, the semiconductor device 100 may further include a third semiconductor structure (not shown), the third semiconductor structure including a memory array, and the third semiconductor structure may be bonded to the first semiconductor structure 130 .

[0076] In some embodiments, the semiconductor device 100 may further include a fourth semiconductor structure (not shown), which may include a circuit layer such as CMOS. The fourth semiconductor structure may be bonded to a side of the second semiconductor structure 140 facing away from the first semiconductor structure 130 .

[0077] Please refer to Figure 2, which is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present disclosure. For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiments, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment.

[0078] In this semiconductor device 200, both the first side surface 131a and the second side surface 132a are inclined surfaces, and the inclination of the first side surface 131a and the second side surface 132a is the same. The thickness of the outer edge structure 20a is equal to the thickness of the carrier 110, so the first side surface 131a only includes the side surface 13 of the device structure 120. The difference between Figure 2 and Figure 1 lies in the depth of the first side surface 131a. In the embodiment of Figure 2, the bottom of the first side surface 131a is flush with the bottom of the device structure 120, while in the embodiment of Figure 1, the bottom of the first side surface 131a extends below the bottom of the device structure 120.

[0079] Please refer to Figure 3, which is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present disclosure. For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiments, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment.

[0080] In this semiconductor device 300, the first side surface 131b is a curved surface, and the second side surface 132b is an inclined surface. The thickness of the peripheral structure 20b is less than that of the carrier 110. The first side surface 131b includes a portion of the side surface of the carrier 110. The second side surface 132b includes the side surface of the device structure 120. Therefore, the junction between the first side surface 131b and the second side surface 132b is the junction between the carrier 110 and the device structure 120.

[0081] The transverse distance between the second side surface 132b and the outer edge structure 20b is greater than the transverse distance between the first side surface 131b and the outer edge structure 20b.

[0082] Please refer to Figure 4, which is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present disclosure. For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiment, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment.

[0083] In the semiconductor device 400, the first side surface 131c is a curved surface, and the second side surface 132c is an inclined surface. The thickness of the outer edge structure 20c is less than the thickness of the carrier 110. The first side surface 131c extends from the carrier 110 to the circuit layer 111. The second side surface 132c includes a side surface of the second semiconductor structure 140. The junction between the first side surface 131c and the second side surface 132c can be the bottom of the second semiconductor structure 140. The first side surface 131c or the second side surface 132c can include a bonding layer.

[0084] The transverse distance between the second side surface 132 c and the outer edge structure 20 is greater than the transverse distance between the first side surface 131 c and the outer edge structure 20 .

[0085] Please refer to Figure 5, which is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present disclosure. For ease of understanding and brief description, the same reference numerals are used for the same structures in this embodiment as in the above embodiment, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment.

[0086] In the semiconductor device 500 , the first side surface 131d and the second side surface 132d are curved surfaces. The thickness of the peripheral structure 20d is less than that of the carrier 110 . The first side surface 131d includes a portion of the side surface of the carrier 110 , and the second side surface 132d includes a portion of the side surface of the second semiconductor structure 140 .

[0087] The first side surface 131d and the second side surface 132d may form a continuous curved surface, and the junction of the first side surface 131d and the second side surface 132d may be at any position on the side surface 13d.

[0088] The semiconductor device provided by the embodiment of the present disclosure includes a main body structure 10 and an outer edge structure, wherein the outer edge structure is located at the periphery of the bottom of the main body structure 10. The main body structure 10 includes a top surface 11 and a bottom surface 12 arranged in opposite directions, and a side surface located between the top surface 11 and the outer edge structure 20. The side surface includes a first side surface connected to the outer edge structure 20, and the lateral distance of the first side surface relative to the outer edge structure gradually decreases from the top surface 11 to the bottom surface 12. Therefore, the corner between the first side surface of the main body structure 10 and the outer edge structure is relatively smooth, which helps to reduce the gap formed by the adhesive tape at the corner, thereby reducing the impact of subsequent processes on the semiconductor device.

[0089] Please refer to Figure 6, which is a flow chart of the method for preparing a semiconductor device provided in some embodiments of the present disclosure. Please also refer to Figure 6 and Figures 7a-7d, which are structural schematic diagrams of the semiconductor device provided in some embodiments of the present disclosure corresponding to the preparation method shown in Figure 6 during the relevant preparation process. In order to illustrate the structural changes of the semiconductor device during the preparation process, Figures 7a-7d only illustrate the simple structural composition of the semiconductor device during the preparation process. This embodiment takes the preparation of the above-mentioned semiconductor device 100 as an example to illustrate the method for preparing the semiconductor device. Therefore, please refer to Figure 1 and continue to use the numbers in Figure 1. The method for preparing the semiconductor device includes the following steps S1-S3.

[0090] Step S1: Form a main body structure 10 and an outer edge structure 20 located at the bottom periphery of the main body structure 10, wherein the main body structure 10 includes a top surface 11 and a bottom surface 12 arranged opposite to each other, and a side surface 13 located between the top surface 11 and the outer edge structure 20; the side surface 13 includes a first side surface 131 close to the outer edge structure 20, and the lateral distance of the first side surface 131 relative to the outer edge structure 20 gradually decreases from the top surface 11 to the bottom surface 12.

[0091] The step S1 may include the following steps.

[0092] 1) Providing a carrier 110A and an outer edge structure 20A located on a sidewall of the carrier 110A.

[0093] As shown in FIG. 7 a , the carrier 110A and the peripheral structure 20A may be a substrate, and the substrate includes the carrier 110A and the peripheral structure 20A located on the sidewall of the carrier 110A.

[0094] The substrate may be a semiconductor substrate, for example, a silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe.

[0095] 2) forming a device structure 120A on the carrier 110A. The carrier 110A and the device structure 120A constitute the body structure 10A.

[0096] Specifically, a circuit layer 111A can be formed on a carrier 110A to form a first semiconductor structure 130A including the carrier 110A and the circuit layer 111A. A second semiconductor structure 140A (e.g., a CMOS) is then provided and bonded to the circuit layer 111A of the first semiconductor structure 130A. The device structure 120A includes the circuit layer 111A and the second semiconductor structure 140A. The body structure 10A includes a top surface 11A and a bottom surface 12 disposed opposite each other.

[0097] 3) Trimming the edges of the main structure 10A to form the side surfaces 13 .

[0098] As shown in FIG7b , the edge portion of the main structure 10A can be cut along the Y direction. During the cutting process, the semiconductor device is moved in the direction opposite to the X direction to form the side surface 13. The outer edge structure 20A is then cut along the direction opposite to the X direction to form the outer edge structure 20 connected to the side surface 13. After cutting, the structure of the main structure 10, top surface 11, carrier 110, circuit layer 111, second semiconductor structure 140, first semiconductor structure 130, and second semiconductor structure 140 is shown in FIG7b .

[0099] Step S2: applying adhesive tape 30 to the main body structure 10 and the peripheral structure 20 .

[0100] As shown in Figure 7c, the tape 30 is attached to the main structure 10 and the outer edge structure 20. Since the lateral distance of the first side surface 131 relative to the outer edge structure 20 gradually decreases along the Y direction, the corner between the first side surface 131 and the first surface 21 of the outer edge structure 20 is relatively smooth, and the tape 30 can be tightly attached at the corner, so the gap of the tape 30 at the corner is smaller.

[0101] Step S3: grinding and thinning the bottom surface 12 of the main body structure 10 and the side of the peripheral structure 20 close to the bottom surface 12 .

[0102] As shown in FIG7d , the semiconductor device can be inverted and placed in the vacuum adsorption area VA of a grinding machine for fixation. The bottom surface 12 of the main structure 10 and the side of the peripheral structure 20 close to the bottom surface 12 are ground to thin the carrier 110 and the peripheral structure 20. The main function of the tape 30 is to protect the structures on the other side, such as the circuit layer 111 and the second semiconductor structure 140, during transportation and grinding.

[0103] After step S3, the semiconductor device is turned over again. The method for preparing the semiconductor device may further include: 1) forming a photoresist layer (not shown in the figure) on the top surface 11 and the side surface 13 of the main body structure 10; 2) performing a photolithography process on the photoresist layer using a mask to form a patterned photoresist layer; 3) forming lead-out contacts using the patterned photoresist layer. For example, the lead-out contacts may include source lead-out contacts, through-silicon contacts, and other contact structures that need to be formed by etching using a patterned photoresist layer. In the process of forming the lead-out contacts, the photoresist layer will be formed on the side surface 13. Since the angle between the side surface 13 and the first surface 21 is relatively smooth, the accumulation of the photoresist layer on the side surface 13 can be reduced, thereby reducing the formation of bulges on the side surface 13.

[0104] In some embodiments, the semiconductor device further includes a plurality of dicing streets, and the method for preparing the semiconductor device further includes: cutting the semiconductor device into a plurality of memory particles along the dicing streets. Because the quality of the memory particles at the edge of the semiconductor device (e.g., the memory particles near the side surface 13) is poor, to ensure the quality of the memory particles, memory particles cut from the middle of the semiconductor device may be used.

[0105] The inventors have discovered that if the corner between the first side surface 131 and the outer edge structure 20 is a right angle, the tape 30 is likely to form a gap at the corner. During the grinding process, the gap will cause stress mismatch at various locations, which will cause the structure to crack and produce fragments. The generated fragments will cause the grinding process to damage the circuit layer 111.

[0106] In the method for fabricating a semiconductor device provided by an embodiment of the present disclosure, the lateral distance between the first side surface 131 formed by the main structure 10 and the peripheral structure 20 gradually decreases from the top surface 11 to the bottom surface 12. The corner between the first side surface 131 formed by cutting and the peripheral structure 20 is not a right angle but is relatively smooth, allowing the tape 30 to fit tightly at the corner. Therefore, the gaps in the tape 30 at the corners are smaller, which can alleviate stress mismatch issues, reduce the generation of debris, and thus reduce damage to the circuit layer 111 during the grinding process.

[0107] Some embodiments of the present disclosure further provide a memory device fabricated using the semiconductor device fabrication method of any of the above embodiments, the memory device may include the memory device of the above embodiments, and may be a three-dimensional memory device, such as a 3D NAND or 3D NOR memory device.

[0108] Please refer to Figure 8, which is a schematic diagram of the structure of a storage system provided in some embodiments of the present disclosure. The storage system 600 includes a memory 601 and a controller 602. The memory 601 may be the memory described in the above embodiments and may include the storage particles described in the above embodiments. The controller 602 is electrically connected to the memory 601 and is configured to control the memory 601 to store data. The memory 601 may perform data storage operations based on the control of the controller 602.

[0109] In some embodiments, the storage system 600 may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a PCI-Express (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0110] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present disclosure; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: Body structure; An outer edge structure, located at the periphery of the bottom of the main body structure; Among them, the main body structure includes a top surface and a bottom surface arranged back to back, and a side surface located between the top surface and the outer edge structure; the side surface includes a first side surface connected to the outer edge structure, and the lateral distance of the first side surface relative to the outer edge structure gradually decreases from the top surface toward the bottom surface.

2. The semiconductor device according to claim 1, wherein The main body structure comprises: Carrier; A device structure, located on the carrier; Wherein, the outer edge structure is located on the side wall of the carrier, and the thickness of the outer edge structure is less than or equal to the thickness of the carrier.

3. The semiconductor device according to claim 2, wherein: An orthographic projection of the device structure on the carrier is located within the carrier.

4. The semiconductor device according to claim 1, wherein: The outer edge structure comprises: a first surface connected to the side surface; A second surface, parallel to the first surface and coplanar with the bottom surface of the main body structure; The first side surface is an inclined surface, and the angle between the inclined surface and the first surface is an obtuse angle.

5. The semiconductor device according to claim 1, wherein The first side surface includes a curved surface.

6. The semiconductor device according to claim 1, wherein The side surface further includes a second side surface connected to the first side surface, and a lateral distance of the second side surface relative to the outer edge structure gradually decreases from the top surface to the bottom surface.

7. The semiconductor device according to claim 6, wherein: The second side surface is an inclined surface or a curved surface.

8. The semiconductor device according to claim 7, wherein: The second side surface and the first side surface are both inclined surfaces, and the second side surface and the first side surface have the same inclination degree.

9. The semiconductor device according to claim 2, wherein: The semiconductor device comprises a first semiconductor structure and a second semiconductor structure bonded to each other, the first semiconductor structure comprises the carrier and a circuit layer located between the carrier and the second semiconductor structure, and the circuit layer and the second semiconductor structure constitute the device structure.

10. The semiconductor device according to claim 9, wherein The top surface of the body structure is a surface of the second semiconductor structure facing away from the first semiconductor structure, and the bottom surface of the body structure is a surface of the carrier facing away from the circuit layer.

11. The semiconductor device according to claim 9, wherein: The second semiconductor structure includes a memory array, and the memory array is connected to the circuit layer.

12. A method for preparing a semiconductor device, comprising: A main body structure and an outer edge structure located at the periphery of the bottom of the main body structure are formed, wherein the main body structure includes a top surface and a bottom surface disposed opposite to each other, and a side surface located between the top surface and the outer edge structure; the side surface includes a first side surface close to the outer edge structure, and the lateral distance of the first side surface relative to the outer edge structure gradually decreases from the top surface to the bottom surface; Adhesive tape is applied to the main body structure and the outer edge structure.

13. The method for preparing a semiconductor device according to claim 12, wherein: After the step of attaching the tape to the main structure and the peripheral structure, the method for preparing the semiconductor device further includes: The bottom surface of the main body structure and the side of the peripheral structure close to the bottom surface are ground and thinned.

14. The method for preparing a semiconductor device according to claim 12, wherein: The step of forming the main body structure and the peripheral structure located at the bottom periphery of the main body structure comprises: providing a carrier and an outer edge structure located on a side wall of the carrier; forming a device structure on the carrier, wherein the carrier and the device structure constitute the main body structure; The edges of the body structure are trimmed to form the side surfaces.

15. The method for preparing a semiconductor device according to claim 14, wherein: The step of forming a device structure on the carrier comprises: forming a circuit layer on the carrier to form a first semiconductor structure including the carrier and the circuit layer; Providing a second semiconductor structure and connecting the second semiconductor structure to the first semiconductor structure The circuit layers are bonded.

16. The method for preparing a semiconductor device according to claim 15, wherein: The second semiconductor structure includes a memory array and a common source layer connected to the memory array, and a surface of the common source layer facing away from the first semiconductor structure is the top surface of the body structure; The method for preparing the semiconductor device further includes: forming a photoresist layer on the top surface and the side surface of the main structure; Performing a photolithography process on the photoresist layer using a mask to form a patterned photoresist layer; The patterned photoresist layer is used to form lead-out contacts on the top surface.

17. The method for preparing a semiconductor device according to claim 12, wherein: The semiconductor device includes a plurality of cutting paths, and the method for preparing the semiconductor device further includes: The semiconductor device is cut into a plurality of storage particles along the cutting streets.

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