Semiconductor device and method for manufacturing semiconductor device

Abstract

The semiconductor device includes: a first nitride semiconductor layer containing gallium; and a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing gallium, the second nitride semiconductor layer having a plurality of third nitride semiconductor layers and a plurality of fourth nitride semiconductor layers, the plurality of third nitride semiconductor layers and the plurality of fourth nitride semiconductor layers are alternately laminated on the first nitride semiconductor layer, the third nitride semiconductor layers containing a first conductivity type impurity at a first concentration, and the fourth nitride semiconductor layers containing a second conductivity type impurity at a second concentration. The fourth nitride semiconductor layer contains the impurities of the first conductivity type at a second concentration higher than the first concentration, and the first concentration is 1 * 1020 cm <-3 > or more.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] This application claims the benefit of priority based on Japanese Application No. 2022-096882, filed on June 15, 2022, and incorporates all the contents described in the aforementioned Japanese Application by reference. Background Art

[0003] In order to reduce the contact resistance and the like in a semiconductor device using a nitride semiconductor, a structure in which a nitride semiconductor layer containing impurities at a high concentration is regrowthed has been proposed.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2008-270749

[0007] Patent Document 2: Japanese Patent Application Publication No. 2019-041113

[0008] Patent Document 3: Japanese Patent Application Publication No. 2017-059671

[0009] Non-patent literature

[0010] Non-patent document 1: Applied Physics Express, 2 (2009) 051001 Summary of the invention

[0011] The semiconductor device disclosed in the present invention comprises: a first nitride semiconductor layer including gallium; and a second nitride semiconductor layer formed on the first nitride semiconductor layer and including gallium, wherein the second nitride semiconductor layer comprises a plurality of third nitride semiconductor layers and a plurality of fourth nitride semiconductor layers, wherein the plurality of third nitride semiconductor layers and the plurality of fourth nitride semiconductor layers are alternately stacked on the first nitride semiconductor layer, wherein the third nitride semiconductor layer contains a first conductivity type impurity at a first concentration, and the fourth nitride semiconductor layer contains the first conductivity type impurity at a second concentration higher than the first concentration, wherein the first concentration is 1×10 20 cm -3 above. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0013] Figure 2 It is a cross-sectional view showing the n-type GaN layer in the first embodiment.

[0014] Figure 3 This is a diagram showing the relationship between the depth from the surface of the n-type GaN layer and the concentration of impurities in the first embodiment.

[0015] Figure 4 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (Part 1).

[0016] Figure 5 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (part 2).

[0017] Figure 6 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (Part 3).

[0018] Figure 7 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (Part 4).

[0019] Figure 8 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (Part 5).

[0020] Fig. 9 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (part 6).

[0021] Fig.10 It is a timing chart showing the method of forming the n-type GaN layer in the first embodiment.

[0022] Fig.11 This is a cross-sectional view showing the method for forming the n-type GaN layer in the first embodiment (Part 1).

[0023] Fig.12 This is a cross-sectional view showing the method for forming the n-type GaN layer in the first embodiment (part 2).

[0024] Fig.13 This is a cross-sectional view showing the method for forming the n-type GaN layer in the first embodiment (Part 3).

[0025] Fig.14 This is a cross-sectional view showing the method for forming the n-type GaN layer in the first embodiment (Part 4).

[0026] Fig.15 This is a cross-sectional view showing the method for forming the n-type GaN layer in the first embodiment (Part 5).

[0027] Fig.16 This is a diagram showing another example of the relationship between the depth from the surface of the n-type GaN layer and the concentration of impurities in the first embodiment.

[0028] Fig.17 It is a graph showing the relationship between the continuous supply time of Ga, the size L1 of the droplet, and the difference between the migration length L2 and the size L1 of the droplet.

[0029] Fig.18 This is a cross-sectional view (part 1) showing a phenomenon when the continuous supply time of Ga is too long.

[0030] Fig.19 This is a cross-sectional view showing a phenomenon when the continuous supply time of Ga is too long (part 2).

[0031] Fig. 20 It is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0032] Fig.21 It is a cross-sectional view showing an n-type GaN layer in the second embodiment.

[0033] Fig. 22 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment (Part 1).

[0034] Fig.23 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment (Part 2).

[0035] Fig.24 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment (Part 3).

[0036] Fig.25 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment.

[0037] Fig.26 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment (Part 4).

[0038] Fig. 27 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment (Part 5). DETAILED DESCRIPTION

[0039] [Problems to be Solved by the Present Disclosure]

[0040] In conventional semiconductor devices, there is a concern that electrical characteristics may be degraded due to precipitation of impurity elements.

[0041] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress the degradation of electrical characteristics accompanying the precipitation of impurity elements.

[0042] [Effects of the present disclosure]

[0043] According to the present disclosure, it is possible to suppress the degradation of electrical characteristics due to the precipitation of impurity elements.

[0044] [Description of Embodiments of the Present Disclosure]

[0045] First, embodiments of the present disclosure will be described by way of examples.

[0046] [1] A semiconductor device according to one embodiment of the present disclosure comprises: a first nitride semiconductor layer comprising gallium; and a second nitride semiconductor layer formed on the first nitride semiconductor layer and comprising gallium, wherein the second nitride semiconductor layer comprises a plurality of third nitride semiconductor layers and a plurality of fourth nitride semiconductor layers, wherein the plurality of third nitride semiconductor layers and the plurality of fourth nitride semiconductor layers are alternately stacked on the first nitride semiconductor layer, wherein the third nitride semiconductor layers contain impurities of a first conductivity type at a first concentration, and wherein the fourth nitride semiconductor layers contain impurities of the first conductivity type at a second concentration higher than the first concentration, wherein the first concentration is 1×10 20 cm -3 above.

[0047] The third nitride semiconductor layer has a thickness of 1×10 20 cm -3 The first concentration above contains impurities of the first conductivity type, and the fourth nitride semiconductor layer contains impurities of the first conductivity type at a second concentration higher than the first concentration. Therefore, it is possible to suppress the degradation of electrical characteristics accompanying the precipitation of impurity elements. In addition, since the third nitride semiconductor layer and the fourth nitride semiconductor layer having different impurity concentrations are alternately stacked, good crystallinity can be obtained despite the high concentration of impurities. Moreover, the third nitride semiconductor layer and the fourth nitride semiconductor layer can be formed, for example, by physical vapor deposition. That is, the third nitride semiconductor layer and the fourth nitride semiconductor layer having good crystallinity can be formed using existing film forming equipment.

[0048] [2] In [1], the third nitride semiconductor layer and the fourth nitride semiconductor layer may be stacked at a period of 8 nm or less. The smaller the period, the easier it is to obtain good crystallinity in the second nitride semiconductor layer.

[0049] [3] In [1] or [2], the difference between the first concentration and the second concentration may be 1×10 20 cm -3 Above and 7×10 20 cm -3 Regardless of whether the concentration difference is too small or too large, it may be difficult to obtain good crystallinity in the second nitride semiconductor layer.

[0050] [4] In any one of [1] to [3], the impurity may be germanium or silicon. When the impurity is germanium or silicon, low resistance is easily obtained in the second nitride semiconductor layer.

[0051] [5] In any one of [1] to [4], the semiconductor device may include an ohmic electrode formed on the second nitride semiconductor layer. In this case, low resistance can be obtained between the first nitride semiconductor layer and the ohmic electrode.

[0052] [6] In any one of [1] to [5], the surface of the first nitride semiconductor layer that contacts the lower surface of the second nitride semiconductor layer may be a nitrogen polar surface. In this case, it is easy to achieve low resistance.

[0053] [7] In [6], the first nitride semiconductor layer may include: a barrier layer; and a channel layer provided on the barrier layer. In this case, it is easy to achieve low resistance.

[0054] [8] In [6] or [7], the semiconductor device may include an insulating layer formed on the first nitride semiconductor layer, the insulating layer may include an opening for exposing the first nitride semiconductor layer, and the second nitride semiconductor layer may be formed in the opening. In this case, it is easy to achieve low resistance while protecting the first nitride semiconductor layer with the insulating layer.

[0055] [9] In any one of [1] to [5], the surface of the first nitride semiconductor layer that contacts the lower surface of the second nitride semiconductor layer may be a gallium-polar surface. In this case, it is easy to grow the first nitride semiconductor layer, and it is easy to obtain good etching resistance on the upper surface of the first nitride semiconductor layer.

[0056]

[10] In [9], the first nitride semiconductor layer may include: a channel layer; and a barrier layer disposed above the channel layer. In this case, it is easy to grow the first nitride semiconductor layer, and it is easy to obtain good etching resistance on the upper surface of the first nitride semiconductor layer.

[0057]

[11] In [9] or

[10] , a recess may be formed in the first nitride semiconductor layer, and the second nitride semiconductor layer may be formed in the recess. In this case, it is easy to achieve low resistance.

[0058]

[12] A method for manufacturing a semiconductor device according to another embodiment of the present invention comprises the following steps: forming a second nitride semiconductor layer containing gallium on a first nitride semiconductor layer containing gallium by physical vapor deposition, the step of forming the second nitride semiconductor layer comprises the step of repeatedly performing the following steps: forming a third nitride semiconductor layer containing impurities of a first conductivity type at a first concentration, and forming droplets of an alloy of gallium and the impurities on a surface of the third nitride semiconductor layer; and evaporating a portion of the gallium from the droplets, and while introducing the impurities in the droplets, nitriding another portion of the gallium in the droplets, thereby forming a fourth nitride semiconductor layer containing impurities of the first conductivity type at a second concentration higher than the first concentration.

[0059] When the second nitride semiconductor layer is formed by physical vapor deposition, the formation of the third nitride semiconductor layer and the formation of the fourth nitride semiconductor layer are repeated. When the third nitride semiconductor layer is formed, droplets of an alloy of gallium and impurities are formed on the surface of the third nitride semiconductor layer, and when the fourth nitride semiconductor layer is formed, part of the gallium is evaporated from the droplets, and while the impurities in the droplets are introduced, the other part of the gallium in the droplets is nitrided. Therefore, even if the third nitride semiconductor layer is formed with a thickness of, for example, 1×10 20 cm -3 Even when the first conductivity type impurities are contained at high concentrations as described above, good crystallinity can be obtained in the third nitride semiconductor layer and the fourth nitride semiconductor layer. Therefore, the impurities remaining on the surface of the second nitride semiconductor layer can be suppressed, and the degradation of electrical characteristics caused by the precipitates can be suppressed.

[0060]

[13] In

[12] , the liquid droplets may be eliminated in the step of forming the fourth nitride semiconductor layer. If the liquid droplets remain, the crystallinity of the fourth nitride semiconductor layer may be reduced.

[0061]

[14] In

[12] or

[13] , the time for forming the fourth nitride semiconductor layer may be longer than the time for forming the third nitride semiconductor layer. In this case, the liquid droplets can be easily eliminated.

[0062]

[15] In any one of

[12] to

[14] , the third nitride semiconductor layer and the fourth nitride semiconductor layer may be formed in a chamber, and in the step of forming the third nitride semiconductor layer and the step of forming the fourth nitride semiconductor layer, at a temperature in the chamber, a saturated vapor pressure of gallium is lower than a pressure in the chamber. In this case, droplets containing gallium can be easily and stably formed.

[0063]

[16] In any one of

[12] to

[15] , the first nitride semiconductor layer may be formed on a substrate, and the temperature of the substrate when forming the third nitride semiconductor layer and the fourth nitride semiconductor layer may be 200° C. or higher and 650° C. or lower. This is because if the temperature of the substrate is too low, it is difficult to form the third nitride semiconductor layer and the fourth nitride semiconductor layer, and if the temperature of the substrate is too high, the already formed first nitride semiconductor layer may be damaged.

[0064] [Details of the embodiments of the present disclosure]

[0065] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. It should be noted that in the present specification and the drawings, for components having substantially the same functional configuration, repeated descriptions may be omitted by marking the same reference numerals.

[0066] (First Embodiment)

[0067] First, a first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figure 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0068] like Figure 1 As shown, the semiconductor device 100 of the first embodiment mainly includes a substrate 101, a nitride semiconductor layer 110, an insulating layer 121, an n-type GaN (gallium nitride) layer 131S, an n-type GaN layer 131D, a gate electrode 141, a source electrode 132S, a drain electrode 132D and an insulating layer 142.

[0069] The substrate 101 is, for example, a substrate for growing GaN-based semiconductors, and in one example is a semi-insulating SiC (silicon carbide) substrate. When the substrate 101 is a SiC substrate, the surface of the substrate 101 is a carbon (C) polar surface. When the surface of the substrate 101 is a C polar surface, the nitride semiconductor layer 110 can grow crystals with the nitrogen (N) polar surface as the growth surface. It should be noted that a sapphire substrate can also be used as a substrate for growing GaN-based semiconductors. In addition, the substrate 101 may not be a substrate for crystal growth. In this case, the substrate may be removed from the nitride semiconductor layer 110 grown on other substrates, and the substrate 101 may be bonded to the nitride semiconductor layer 110. In this case, as the substrate 101, a semi-insulating substrate of various materials may be used, for example, a sapphire substrate, a Si (silicon) substrate, a SiC substrate, an AlN (aluminum nitride) substrate, a sintered body, etc.

[0070] The nitride semiconductor layer 110 includes a buffer layer 111, a barrier layer 112, and a channel layer 113. The nitride semiconductor layer 110 is an example of a first nitride semiconductor layer.

[0071] The buffer layer 111 is, for example, an AlN layer. The thickness of the AlN layer is, for example, greater than 5 nm and less than 100 nm. The buffer layer 111 may also include an AlN layer and a GaN layer or an AlGaN (aluminum gallium nitride) layer on the AlN layer. The thickness of the GaN layer or the AlGaN layer is, for example, greater than 300 nm and less than 2000 nm.

[0072] The barrier layer 112 is, for example, an AlGaN layer. The band gap of the barrier layer 112 is greater than the band gap of the channel layer 113 described later. The thickness of the barrier layer 112 is, for example, in the range of 5 nm to 50 nm, and is 30 nm in one embodiment. x Ga 1－x In the case of an N layer, its Al composition x is, for example, greater than 0.15 and less than 0.55, and in one embodiment is 0.35. The conductivity type of the barrier layer 112 is, for example, n-type or non-doped (i-type). An InAlN (indium aluminum nitride) layer or an InAlGaN (indium aluminum gallium nitride) layer may be used instead of the AlGaN layer.

[0073] The channel layer 113 is, for example, a GaN layer. The band gap of the channel layer 113 is smaller than the band gap of the barrier layer 112. The thickness of the channel layer 113 is, for example, in the range of 5 nm to 30 nm, and in one embodiment is 9 nm. Between the channel layer 113 and the barrier layer 112, strain is generated due to their different lattice constants, and the strain induces piezoelectric charge at the interface between the two. As a result, a two-dimensional electron gas (2DEG) is generated in the region on the barrier layer 112 side of the channel layer 113, forming a channel region 113c. The conductivity type of the channel layer 113 is, for example, n-type or non-doped (i-type). The surface of the channel layer 113 constitutes the surface 110A of the nitride semiconductor layer 110. In addition, a spacer layer may be formed between the barrier layer 112 and the channel layer 113. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, in the range of 0.5 nm to 3.0 nm, and in one embodiment is 1.0 nm.

[0074] On the C polarity surface of the SiC substrate, the buffer layer 111, the barrier layer 112, and the channel layer 113 are crystal-grown with the N polarity surface as the growth surface. Therefore, the surface of the buffer layer 111, the barrier layer 112, and the channel layer 113 on the side opposite to the substrate 101 side is the N polarity surface, and the back surface of the buffer layer 111, the barrier layer 112, and the channel layer 113 on the substrate 101 side is the gallium (Ga) polarity surface.

[0075] The insulating layer 121 is in contact with the surface 110A of the nitride semiconductor layer 110. The insulating layer 121 is, for example, a silicon nitride (SiN) layer. An opening 121S and an opening 121D are formed in the insulating layer 121. A portion of the nitride semiconductor layer 110 is exposed from the opening 121S, and another portion of the nitride semiconductor layer 110 is exposed from the opening 121D.

[0076] The n-type GaN layer 131S is formed on the nitride semiconductor layer 110 in the opening 121S. The n-type GaN layer 131D is formed on the nitride semiconductor layer 110 in the opening 121D. The n-type GaN layer 131S and the n-type GaN layer 131D contain Ge (germanium) or Si as an n-type impurity. The n-type GaN layer 131S and the n-type GaN layer 131D are examples of the second nitride semiconductor layer.

[0077] Here, the details of the n-type GaN layer 131S and the n-type GaN layer 131D are described. Figure 2 It is a cross-sectional view showing the n-type GaN layer 131S and the n-type GaN layer 131D in the first embodiment. Figure 3 1 is a diagram showing the relationship between the depth from the surface and the concentration of impurities in the n-type GaN layer 131S and the n-type GaN layer 131D in the first embodiment.

[0078] like Figure 2 As shown, the n-type GaN layer 131S and the n-type GaN layer 131D as an example of the second nitride semiconductor layer include a plurality of n-type GaN layers 150 and a plurality of n-type GaN layers 160. The n-type GaN layers 150 and the n-type GaN layers 160 are alternately stacked on the nitride semiconductor layer 110. For example, the n-type GaN layers 150 and the n-type GaN layers 160 are stacked on the nitride semiconductor layer 110 at a period of 8 nm or less. The n-type GaN layers 150 are stacked at a period of 1×10 20 cm -3 The n-type GaN layer 150 contains n-type impurities at the first concentration. 20 cm -3 The n-type GaN layer 160 contains n-type impurities at a first concentration higher than the first concentration, for example, 9×10 20 cm -3 Contains n-type impurities. In this example, the difference between the first concentration and the second concentration is 6×10 20 cm -3 Therefore, if Figure 3As shown, in the n-type GaN layer 131S and the n-type GaN layer 131D, the concentration of impurities changes periodically in the depth direction. The n-type GaN layer 131S and the n-type GaN layer 131D have, for example, an n-type GaN layer 150 at the bottom layer and an n-type GaN layer 160 at the top layer. The n-type GaN layer 150 is an example of the third nitride semiconductor layer, and the n-type GaN layer 160 is an example of the fourth nitride semiconductor layer.

[0079] like Figure 1 As shown, the source electrode 132S is formed on the n-type GaN layer 131S, and the drain electrode 132D is formed on the n-type GaN layer 131D. The source electrode 132S and the drain electrode 132D include, for example, a stack of Ta (tantalum) films, Al films, and Ta films stacked in sequence. The source electrode 132S and the drain electrode 132D may also include, for example, a stack of Ti (titanium) films, Al films, and Ti films stacked in sequence, or a stack of Ni (nickel) films and Au (gold) films stacked in sequence. The source electrode 132S and the drain electrode 132D are examples of ohmic electrodes.

[0080] The gate electrode 141 is formed on the insulating layer 121 between the source electrode 132S and the drain electrode 132D. The gate electrode 141 includes, for example, a stack of a Ni film, a Pd (palladium) film, and an Au film stacked in this order. The insulating layer 142 is formed on the insulating layer 121 to cover the gate electrode 141.

[0081] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 4 to 9 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0082] First, if Figure 4 As shown, a nitride semiconductor layer 110 is formed on a substrate 101 by, for example, metal organic chemical vapor deposition (MOCVD). In the formation of the nitride semiconductor layer 110, a buffer layer 111, a barrier layer 112, and a channel layer 113 are formed in sequence. Between the channel layer 113 and the barrier layer 112, strain is generated due to the difference in their lattice constants, and the strain causes piezoelectric charge at the interface between the two. As a result, 2DEG is generated in the region on the barrier layer 112 side in the channel layer 113, forming a channel region 113c.

[0083] Then, if Figure 5As shown, an insulating layer 121 is formed in contact with the surface 110A of the nitride semiconductor layer 110. The insulating layer 121 can be formed, for example, by a low pressure chemical vapor deposition (LPCVD) method. The insulating layer 121 can also be formed continuously with the buffer layer 111, the barrier layer 112, and the channel layer 113 by, for example, an MOCVD method in a manner that does not expose the surface of the channel layer 113 to the atmosphere.

[0084] Then, if Figure 6 As shown, an opening 121S and an opening 121D are formed in the insulating layer 121. The opening 121S and the opening 121D can be formed by, for example, reactive ion etching (RIE) using a resist pattern (not shown) as a mask. In RIE, for example, a fluorine-based gas is used as a reactive gas.

[0085] Then, if Figure 7 As shown, an n-type GaN layer 131S is formed on the nitride semiconductor layer 110 in the opening 121S, and an n-type GaN layer 131D is formed on the nitride semiconductor layer 110 in the opening 121D. The upper surfaces of the n-type GaN layer 131S and the n-type GaN layer 131D may be set to be flush with the upper surface of the insulating layer 121, or may not be set to be flush with the upper surface of the insulating layer 121. The n-type GaN layer 131S and the n-type GaN layer 131D may be formed by a physical vapor deposition (PVD) method such as evaporation, sputtering, or molecular beam epitaxy (MBE). When the n-type GaN layer 131S and the n-type GaN layer 131D are formed, for example, a film is formed using a growth mask (not shown), and then the growth mask is removed together with the n-type GaN layer (not shown) formed on the growth mask, wherein the growth mask has an opening formed in the region where the n-type GaN layer 131S and the n-type GaN layer 131D are to be formed. In other words, lift-off is performed. Details of the method for forming the n-type GaN layer 131S and the n-type GaN layer 131D will be described later.

[0086] Then, if Figure 8As shown, a source electrode 132S is formed on the n-type GaN layer 131S, and a drain electrode 132D is formed on the n-type GaN layer 131D. In forming the source electrode 132S and the drain electrode 132D, first, a metal layer (not shown) constituting the source electrode 132S and the drain electrode 132D is formed. When forming the metal layer, for example, film formation using a growth mask (not shown) is performed, and then the growth mask is removed together with the metal layer (not shown) formed on the growth mask, wherein the growth mask has an opening formed in the region where the metal layer is to be formed. In other words, lift-off is performed.

[0087] Then, if Fig. 9 As shown, a gate electrode 141 is formed on the insulating layer 121 between the source electrode 132S and the drain electrode 132D. When the gate electrode 141 is formed, for example, a metal layer is formed using a growth mask (not shown), and then the growth mask is removed together with the metal layer (not shown) formed on the growth mask, wherein the growth mask has an opening formed in the region where the gate electrode 141 is to be formed. In other words, lift-off is performed. After the gate electrode 141 is formed, an insulating layer 142 is formed on the insulating layer 121, for example, by a plasma CVD method, and the gate electrode 141 is covered by the insulating layer 142.

[0088] In this way, the semiconductor device 100 can be manufactured.

[0089] Next, a method for forming the n-type GaN layer 131S and the n-type GaN layer 131D will be described. Here, it is assumed that the n-type GaN layer 131S and the n-type GaN layer 131D are formed by sputtering. In addition, it is assumed that Ge is used as the n-type impurity. Fig.10 It is a timing chart showing a method of forming the n-type GaN layer 131S and the n-type GaN layer 131D. Fig.10 2 shows whether Ga, Ge, and N radicals are supplied to the nitride semiconductor layer 110 during the formation of the n-type GaN layer 131S and the n-type GaN layer 131D. Fig.10 "ON" means there is supply, and "OFF" means there is no supply. Figures 11 to 15 It is a cross-sectional view showing a method of forming the n-type GaN layer 131S and the n-type GaN layer 131D.

[0090] After the substrate 101 formed with the nitride semiconductor layer 110 and the like is placed in the film forming chamber, the temperature in the film forming chamber is set to a predetermined temperature, and the pressure is set to a predetermined pressure. The predetermined temperature and the predetermined pressure are selected so that the saturated vapor pressure of Ga at the predetermined temperature is lower than the predetermined pressure. For example, the predetermined temperature is 600° C., and the predetermined pressure is higher than the saturated vapor pressure of Ga at 600° C. It should be noted that the saturated vapor pressure of Ge is lower than the saturated vapor pressure of Ga.

[0091] When the temperature and pressure in the chamber are stabilized at the specified temperature and the specified pressure, respectively, at time t11, the supply of N radicals 152 to the nitride semiconductor layer 110 is started, and at time t12, the supply of N radicals 152 is stopped. By supplying N radicals 152 from time t11 to time t12, the surface of the nitride semiconductor layer 110 is purified. For example, the N radicals 152 are generated by inductively coupled plasma (ICP).

[0092] At a later time t1, the supply of Ga, Ge, and N radicals 152 to the nitride semiconductor layer 110 is started, and at a later time t2, the supply of Ga and Ge is stopped while the supply of N radicals 152 is continued. By supplying Ga, Ge, and N radicals 152 from time t1 to time t2, as shown in FIG. Fig.11 As shown, an n-type GaN layer 150 is formed. In addition, while forming the n-type GaN layer 150, a droplet 151 of an alloy of Ga and Ge is also formed on the surface of the n-type GaN layer 150. For example, Ga is supplied by RF (radiofrequency) sputtering, and Ge is supplied by direct current (DC) pulse sputtering. The time from time t1 to time t2 is, for example, more than 10 seconds and less than 30 seconds, preferably more than 20 seconds and less than 30 seconds.

[0093] For example, the number density of droplet 151 is 6.1×10 4 cm -2 The average diameter of the droplets 151 is about 300 nm, and the height of the droplets 151 is about 57 nm.

[0094] At the subsequent time t3, similarly to the time t1, the supply of Ga and Ge is started while the supply of the N radicals 152 is continued.

[0095] During the period from time t2 to time t3, since the supply of Ga is stopped, Fig.12 As shown in FIG. 1 , a part of Ga evaporates from the liquid droplet 151 to become gaseous Ga 153. On the other hand, although the supply of Ge is also stopped, Ge remains in the liquid droplet 151 because the saturated vapor pressure of Ge is lower than that of Ga. In addition, since the supply of N radicals 152 is continued, Ga in the liquid droplet 151 is nitrided while being introduced into Ge. As a result, as shown in FIG. Fig.13As shown, an n-type GaN layer 160 is formed. When the n-type GaN layer 160 is formed, Ge remains in the droplet 151 and a part of Ga evaporates to become gaseous Ga 153, so the ratio of Ge in the droplet 151 to the total amount of Ga and Ge is higher than the ratio of Ge in the n-type GaN layer 150 to the total amount of Ga and Ge. Therefore, the n-type GaN layer 160 formed by the droplet 151 in which Ga evaporates contains Ge at a higher concentration than the n-type GaN layer 150. The time from time t2 to time t3 is, for example, 15 seconds or more and 120 seconds or less.

[0096] In addition, even if the proportion of Ge in the droplet 151 increases with the evaporation of Ga, Ge will not condense to the extent of forming a critical crystal nucleus. Even if fine single-substance Ge is temporarily generated, the supply of Ge is also stopped during the period from time t2 to time t3, so the single-substance Ge will decompose before growing to a critical crystal nucleus. Therefore, when the n-type GaN layer 160 is formed, Ge precipitates will not be generated.

[0097] At the subsequent time t2, the supply of N radicals is continued while the supply of Ga and Ge is stopped. By supplying Ga, Ge and N radicals from time t3 (t1) to time t2, as shown in FIG. Fig.14 As shown, while the n-type GaN layer 150 is being formed again, droplets 151 of an alloy of Ga and Ge are formed on the surface of the n-type GaN layer 150 .

[0098] After that, the process from time t1 to time t3 is repeated. Fig.15 As shown, n-type GaN layer 131S and n-type GaN layer 131D are formed by alternately stacking n-type GaN layer 150 and n-type GaN layer 160. Each of n-type GaN layer 150 and n-type GaN layer 160 may be directly in contact with nitride semiconductor layer 110, for example.

[0099] In the semiconductor device 100 of the first embodiment, the n-type GaN layer 150 is 1×10 20 cm -3 The above first concentration contains n-type impurities such as Ge, and the n-type GaN layer 160 contains n-type impurities such as Ge at a second concentration higher than the first concentration. Therefore, the resistance of the n-type GaN layer 131S and the n-type GaN layer 131D can be sufficiently reduced. It should be noted that the thickness of the n-type GaN layer 131S and the n-type GaN layer 131D is preferably greater than 20nm and less than 100nm, more preferably greater than 30nm and less than 100nm, and further preferably greater than 40nm and less than 100nm.

[0100] In addition, since the n-type GaN layer 150 and the n-type GaN layer 160 having different concentrations of n-type impurities are alternately stacked, good crystallinity can be obtained despite the high concentration of n-type impurities. Moreover, the n-type GaN layer 150 and the n-type GaN layer 160 can be formed by the PVD method at a temperature that is low in damaging the nitride semiconductor layer 110 formed before their formation. In addition, when the n-type GaN layer 150 is formed, a droplet 151 is formed, and the n-type GaN layer 160 is formed using the droplet 151. Therefore, it is not easy for Ge precipitates to remain on the outermost surface of the n-type GaN layer 131S and the n-type GaN layer 131D. In the case of forming a GaN layer containing Ge at a high concentration by a pulse sputtering method, Ge precipitates are easily left on the surface of the GaN layer, and according to this embodiment, the residue of Ge precipitates can be suppressed, and the decrease in electrical characteristics caused by the precipitates can be suppressed. By lowering the formation temperature of the n-type GaN layer 150 and the n-type GaN layer 160 , it is also possible to achieve the effects of improving productivity and reducing the emission of greenhouse gases.

[0101] In the first embodiment, the surface of the nitride semiconductor layer 110 that contacts the lower surface of the n-type GaN layer 131S and the n-type GaN layer 131D is an N-polar surface, and the channel layer 113 is located above the barrier layer 112. Therefore, it is easy to shorten the distance between the channel region 113c and the source electrode 132S and the drain electrode 132D, and it is easy to achieve low resistance. In addition, the n-type GaN layer 131S and the n-type GaN layer 131D are respectively formed in the opening 121S and the opening 121D, and the opening 121S and the opening 121D are formed in the insulating layer 121, so it is easy to protect the nitride semiconductor layer 110 by the insulating layer 121 and achieve low resistance.

[0102] The period of the n-type GaN layer 150 and the n-type GaN layer 160 in the thickness direction is preferably less than 8 nm, more preferably less than 6 nm, and further preferably less than 4 nm. The smaller the period of the n-type GaN layer 150 and the n-type GaN layer 160, the easier it is to obtain good crystallinity in the n-type GaN layer 131S and the n-type GaN layer 131D. For example, in the case where the n-type GaN layer 150 is too thick, a large droplet 151 is formed when the n-type GaN layer 150 is formed. The n-type GaN layer 160 is formed by the migration of Ga atoms in the droplet 151 at the surface of the n-type GaN layer 150, and in the case where a large droplet 151 is formed, Ga nitridation may occur at a stage where the migration of Ga atoms does not fully occur. In this case, it may be difficult to obtain a good n-type GaN layer 160.

[0103] The difference between the first concentration and the second concentration is preferably 1×10 20 cm -3 Above and 7×1020 cm -3 Below, more preferably 2×10 20 cm -3 Above and 6×10 20 cm -3 Below, more preferably 3×10 20 cm -3 Above and 5×10 20 cm -3 Regardless of whether the concentration difference is too small or too large, it may be difficult to obtain good crystallinity in the n-type GaN layer 131S and the n-type GaN layer 131D.

[0104] The n-type impurity is not particularly limited, but when the n-type impurity is Ge or Si, low resistance can be easily obtained in the n-type GaN layer 150 and the n-type GaN layer 160 .

[0105] The concentration of impurities such as Ge and Si contained in the n-type GaN layer 131S and the n-type GaN layer 131D can be measured by secondary ion mass spectrometry (SIMS). Figure 3 In the example, the impurity concentration changes in a rectangular wave shape, but the impurity concentration measurement result can also be as follows Fig.16 In this case, the ranges of the n-type GaN layer 150 and the n-type GaN layer 160 can be determined by making the concentration distribution of the impurities approximate to a rectangular wave.

[0106] It should be noted that, preferably, when forming the n-type GaN layer 160, the droplets 151 formed on the surface of the n-type GaN layer 150 are eliminated by evaporation or nitridation. This is because if the droplets 151 remain, the crystallinity of the n-type GaN layer 160 may be reduced. A portion of Ga in the droplets 151 may also be introduced into the n-type GaN layer 150.

[0107] Preferably, the time from time t2 to time t3 is longer than the time from time t1 to time t2. That is, preferably, the time for forming the n-type GaN layer 160 by supplying the continuous N radicals 152 after the formation of the n-type GaN layer 150 is longer than the time for forming the n-type GaN layer 150. This is because the droplet 151 is easily eliminated.

[0108] The temperature of the substrate 101 when forming the n-type GaN layer 150 and the n-type GaN layer 160 is preferably 200° C. or higher and 650° C. or lower, more preferably 250° C. or higher and 600° C. or lower, and further preferably 300° C. or higher and 550° C. or lower. This is because if the temperature of the substrate 101 is too low, it is difficult to form the n-type GaN layer 150 and the n-type GaN layer 160, and if the temperature of the substrate 101 is too high, the already formed nitride semiconductor layer 110 and the like may be damaged.

[0109] If the time from time t1 to time t2, that is, the continuous supply time of Ga is too long, the droplet 151 will be formed large. Fig.17 It is a graph showing the relationship between the continuous supply time of Ga and the size L1 of the droplet. Fig.17 3 also shows the relationship between the continuous supply time of Ga and the difference (L2-L1) between the migration length L2 and the size L1 of the droplet. Fig.17 The horizontal axis represents the continuous supply time of Ga, the vertical axis on the left represents L1, and the vertical axis on the right represents L2-L1. Fig.18 and Fig.19 It is a cross-sectional view showing a phenomenon when the continuous supply time of Ga is too long.

[0110] As described above, the n-type GaN layer 160 is formed by the migration of Ga atoms in the droplet 151. Although the migration length L2 also depends on the conditions such as temperature and pressure during the period from time t2 to time t1, the migration length L2 is approximately 1 μm or more and 3 μm or less. Here, the migration length L2 is set to the movement distance from the start of the movement of the Ga atom to the deactivation of the Ga atom. In addition, the size L1 of the droplet is set to the length of the shortest path from the top of the droplet to the surface of the n-type GaN layer at the surface of the droplet when the shape of the droplet is approximated to an ellipsoid.

[0111] When the continuous supply time of Ga is too long, Fig.18 As shown, a thick n-type GaN layer 150X is formed to replace the n-type GaN layer 150, and a large droplet 151X of an alloy of Ga and Ge is formed on the surface of the n-type GaN layer 150X. In this case, the size L1 of the droplet may be greater than the migration length L2 (L2-L1<0). In the case where the size L1 of the droplet is greater than the migration length L2, the Ga atoms in the droplet 151X are nitrided before diffusing to the surface of the n-type GaN layer 150X, as shown in FIG. Fig.19As shown, before the droplet 151X disappears, the surface of the droplet 151X is covered by the n-type GaN layer 160X. When the surface of the droplet 151X is covered by the n-type GaN layer 160X, it is difficult to obtain good flatness. For example, when the time from time t1 to time t2 is about 600 seconds, the size L1 of the droplet is about 3.5 μm, and the surface of the droplet 151X may be covered by the n-type GaN layer 160X.

[0112] On the other hand, if the time from time t1 to time t2 is greater than 10 seconds and less than 30 seconds, the droplet size L1 is about 0.15 μm, which is smaller than the migration length L2 (L2-L1>0), and a good n-type GaN layer 160 can be formed.

[0113] (Second Embodiment)

[0114] Next, a second embodiment will be described. The second embodiment relates to a semiconductor device including a GaN-based HEMT. Fig. 20 It is a cross-sectional view showing a semiconductor device according to a second embodiment.

[0115] like Fig. 20 As shown, the semiconductor device 200 of the second embodiment mainly includes a substrate 201 , a nitride semiconductor layer 210 , an insulating layer 121 , an n-type GaN layer 231S, an n-type GaN layer 231D, a gate electrode 141 , a source electrode 132S, a drain electrode 132D, and an insulating layer 142 .

[0116] The substrate 201 is, for example, a substrate for growing GaN-based semiconductors, and in one example is a semi-insulating SiC substrate. When the substrate 201 is a SiC substrate, the surface of the substrate 201 is a silicon (Si) polar surface. When the surface of the substrate 201 is a Si polar surface, the nitride semiconductor layer 210 can be crystal-grown with the Ga polar surface as the growth surface.

[0117] The nitride semiconductor layer 210 includes a channel layer 211, a barrier layer 212, and a cap layer 213. The nitride semiconductor layer 210 is an example of a first nitride semiconductor layer.

[0118] The channel layer 211 is, for example, a GaN layer. The thickness of the channel layer 211 is, for example, in the range of 200 nm to 2000 nm, and in one embodiment is 1000 nm. A buffer layer may be provided between the channel layer 211 and the substrate 201 .

[0119] The barrier layer 212 is, for example, an AlGaN layer. The band gap of the barrier layer 212 is greater than the band gap of the channel layer 211. The thickness of the barrier layer 212 is, for example, in the range of 5 nm to 30 nm, and in one embodiment is 15 nm.x Ga 1－x In the case of an N layer, its Al composition x is, for example, greater than 0.15 and less than 0.35, and in one embodiment is 0.25. Between the channel layer 211 and the barrier layer 212, strain is generated due to their different lattice constants, and the strain causes piezoelectric charge at the interface between the two. As a result, 2DEG is generated in the region on the barrier layer 212 side in the channel layer 211, forming a channel region 211c. An InAlN layer or an InAlGaN layer can also be used instead of the AlGaN layer. In addition, a spacer layer can also be provided between the channel layer 211 and the barrier layer 212. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, in the range of greater than 0.5 nm and less than 3.0 nm, and in one embodiment is 1.0 nm.

[0120] The cap layer 213 is, for example, a GaN layer. The thickness of the cap layer 213 is, for example, in the range of 0 nm to 5 nm, and is 2 nm in one embodiment. The surface of the cap layer 213 constitutes the surface 210A of the nitride semiconductor layer 210 .

[0121] On the Si polar surface of the SiC substrate, the channel layer 211, the barrier layer 212, and the cap layer 213 grow crystals with the Ga polar surface as the growth surface. Therefore, the surface of the channel layer 211, the barrier layer 212, and the cap layer 213 on the side opposite to the substrate 201 side is a Ga polar surface, and the back surface of the channel layer 211, the barrier layer 212, and the cap layer 213 on the substrate 201 side is an N polar surface.

[0122] A recess 210S and a recess 210D are formed in the nitride semiconductor layer 210. The recess 210S and the recess 210D are formed to a depth that penetrates the channel region 211c. That is, based on the surface 210A of the nitride semiconductor layer 210, the depths of the recess 210S and the recess 210D are greater than the depth of the channel region 211c. It should be noted that the bottom surfaces of the recess 210S and the recess 210D may also be located in the barrier layer 212.

[0123] The insulating layer 121 is in contact with the surface 210A of the nitride semiconductor layer 210. An opening 121S and an opening 121D are formed in the insulating layer 121. The opening 121S is connected to the recessed portion 210S, and the opening 121D is connected to the recessed portion 210D.

[0124] The n-type GaN layer 231S is formed on the nitride semiconductor layer 210 in the recess 210S and the opening 121S. The n-type GaN layer 231D is formed on the nitride semiconductor layer 210 in the recess 210D and the opening 121D. The n-type GaN layer 231S and the n-type GaN layer 231D contain Ge or Si as an n-type impurity. The n-type GaN layer 231S and the n-type GaN layer 231D are examples of the second nitride semiconductor layer.

[0125] Here, the details of the n-type GaN layer 231S and the n-type GaN layer 231D are described. Fig.21 It is a cross-sectional view showing the n-type GaN layer 231S and the n-type GaN layer 231D in the second embodiment.

[0126] like Fig.21 As shown, the n-type GaN layer 231S and the n-type GaN layer 231D as an example of the second nitride semiconductor layer include a plurality of n-type GaN layers 250 and a plurality of n-type GaN layers 260. The n-type GaN layers 250 and the n-type GaN layers 260 are alternately stacked on the nitride semiconductor layer 210. For example, the n-type GaN layers 250 and the n-type GaN layers 260 are stacked on the nitride semiconductor layer 210 at a period of 8 nm or less. The n-type GaN layers 250 and 260 are stacked at a period of 1×10 20 cm -3 The n-type GaN layer 250 contains n-type impurities at the first concentration. 20 cm -3 The n-type GaN layer 260 contains n-type impurities at a first concentration higher than the first concentration, for example, 9×10 20 cm -3 Contains n-type impurities. In this example, the difference between the first concentration and the second concentration is 6×10 20 cm -3 Therefore, in the n-type GaN layer 231S and the n-type GaN layer 231D, the concentration of impurities changes periodically in the depth direction. The n-type GaN layer 250 is an example of the third nitride semiconductor layer, and the n-type GaN layer 260 is an example of the fourth nitride semiconductor layer.

[0127] like Fig. 20 As shown, the source electrode 132S is formed on the n-type GaN layer 231S, and the drain electrode 132D is formed on the n-type GaN layer 231D.

[0128] An opening 121G is formed in the insulating layer 121 between the source electrode 132S and the drain electrode 132D. A portion of the nitride semiconductor layer 210 is exposed through the opening 121G. The gate electrode 141 is formed on the insulating layer 121 so as to pass through the opening 121G and be in contact with the nitride semiconductor layer 210 .

[0129] The other configurations are the same as those of the first embodiment.

[0130] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figure 22 to Figure 27 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0131] First, if Fig. 22 As shown, a nitride semiconductor layer 210 is formed on a substrate 201 by, for example, an MOCVD method. In the formation of the nitride semiconductor layer 210, a channel layer 211, a barrier layer 212, and a cap layer 213 are sequentially formed. Between the channel layer 211 and the barrier layer 212, strain is generated due to the difference in their lattice constants, and the strain causes piezoelectric charge at the interface between the two. As a result, 2DEG is generated in the region on the barrier layer 212 side in the channel layer 211, forming a channel region 211c.

[0132] Then, if Fig.23 As shown, an insulating layer 121 is formed in contact with the surface 210A of the nitride semiconductor layer 210. The insulating layer 121 can be formed, for example, by a low-pressure CVD method. The insulating layer 121 can also be formed continuously with the channel layer 211, the barrier layer 212, and the cap layer 213 by, for example, an MOCVD method in a manner that does not expose the surface of the cap layer 213 to the atmosphere.

[0133] Then, if Fig.24 As shown, openings 121S and 121D are formed in the insulating layer 121, and recesses 210S and 210D are formed in the nitride semiconductor layer 210. The openings 121S and 121D and the recesses 210S and 210D can be formed, for example, by RIE using a resist pattern (not shown) as a mask. For example, in the RIE of the insulating layer 121, a fluorine-based gas is used as a reactive gas, and in the RIE of the nitride semiconductor layer 210, a chlorine-based gas is used as a reactive gas.

[0134] Then, if Fig.25As shown, an n-type GaN layer 231S is formed on the nitride semiconductor layer 210 in the opening 121S and the recess 210S, and an n-type GaN layer 231D is formed on the nitride semiconductor layer 210 in the opening 121D and the recess 210D. The upper surfaces of the n-type GaN layer 231S and the n-type GaN layer 231D may be set flush with the upper surface of the insulating layer 121, or may not be set flush with the upper surface of the insulating layer 121. The n-type GaN layer 231S and the n-type GaN layer 231D may be formed by the same method as the n-type GaN layer 131S and the n-type GaN layer 131D. The n-type GaN layer 250 and the n-type GaN layer 260 may each be directly in contact with the nitride semiconductor layer 110, for example.

[0135] It should be noted that when forming the n-type GaN layer 231S and the n-type GaN layer 231D, droplets of the alloy of Ga and Ge are also formed. However, in this embodiment, since the growth surface is different from that in the first embodiment, the density and size of the droplets are different. For example, the number density of the droplets is 1.0×10 7 cm -2 The average diameter of the droplets is about 60 nm to about 100 nm, and the height of the droplets is about 20 nm.

[0136] Then, if Fig.26 As shown in FIG. 1 , a source electrode 132S is formed on the n-type GaN layer 131S, and a drain electrode 132D is formed on the n-type GaN layer 131D. The source electrode 132S and the drain electrode 132D can be formed by the same method as in the first embodiment.

[0137] Then, if Fig. 27 As shown, an opening 121G is formed in the insulating layer 121 between the source electrode 132S and the drain electrode 132D. A portion of the nitride semiconductor layer 210 is exposed from the opening 121G. Next, a gate electrode 141 is formed through the opening 121G to contact the nitride semiconductor layer 210. The gate electrode 141 can be formed by the same method as in the first embodiment.

[0138] In this way, the semiconductor device 200 can be manufactured.

[0139] In the semiconductor device 200 of the second embodiment, the n-type GaN layer 250 is 1×10 20 cm -3 The n-type impurity such as Ge is contained at the first concentration, and the n-type GaN layer 260 contains the n-type impurity such as Ge at a second concentration higher than the first concentration. Therefore, the resistance of the n-type GaN layer 231S and the n-type GaN layer 231D can be sufficiently reduced.

[0140] In addition, since the n-type GaN layer 250 and the n-type GaN layer 260 having different concentrations of n-type impurities are alternately stacked, good crystallinity can be obtained despite the high concentration of n-type impurities. Moreover, the n-type GaN layer 250 and the n-type GaN layer 260 can be formed by the PVD method at a temperature that causes little damage to the nitride semiconductor layer 210 formed before their formation. In other words, the n-type GaN layer 250 and the n-type GaN layer 260 having good crystallinity can be formed using an existing film forming device. By lowering the formation temperature of the n-type GaN layer 250 and the n-type GaN layer 260, the effect of improving production capacity and reducing the emission of greenhouse gases can also be obtained.

[0141] In the second embodiment, the surface of the nitride semiconductor layer 210 that contacts the lower surface of the n-type GaN layer 231S and the n-type GaN layer 231D is a Ga polar surface, and the barrier layer 212 is located above the channel layer 211. Therefore, it is easy to grow the nitride semiconductor layer 210, and it is easy to obtain good etching resistance on the upper surface of the nitride semiconductor layer 210. In addition, the n-type GaN layer 231S and the n-type GaN layer 231D are formed in the recessed portion 210S and the recessed portion 210D, respectively, and the recessed portion 210S and the recessed portion 210D are formed in the nitride semiconductor layer 210, so it is easy to shorten the distance between the channel region 211c and the n-type GaN layer 231S and the n-type GaN layer 231D, and it is easy to achieve low resistance.

[0142] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope described in the claims.

[0143] Description of Reference Numerals

[0144] 100, 200: semiconductor devices;

[0145] 101, 201: substrate;

[0146] 110, 210: nitride semiconductor layer;

[0147] 110A, 210A: surface;

[0148] 111: buffer layer;

[0149] 112, 212: barrier layer;

[0150] 113, 211: channel layer;

[0151] 113c, 211c: channel region;

[0152] 121, 142: insulation layer;

[0153] 121D, 121G, 121S: Open;

[0154] 131D, 131S, 150, 150X, 160, 160X, 231D, 231S, 250, 260: n-type GaN layer;

[0155] 132D: drain electrode;

[0156] 132S: source electrode;

[0157] 141: gate electrode;

[0158] 151, 151X: droplets;

[0159] 152: N radical;

[0160] 153: gaseous Ga;

[0161] 210D, 210S: concave part;

[0162] 213: Cap layer.

Claims

1. A semiconductor device comprising: A first nitride semiconductor layer includes gallium; and a second nitride semiconductor layer, formed on the first nitride semiconductor layer and comprising gallium, The second nitride semiconductor layer includes a plurality of third nitride semiconductor layers and a plurality of fourth nitride semiconductor layers, and the plurality of third nitride semiconductor layers and the plurality of fourth nitride semiconductor layers are alternately stacked on the first nitride semiconductor layer. The third nitride semiconductor layer contains impurities of the first conductivity type at a first concentration, the fourth nitride semiconductor layer contains the first conductivity type impurity at a second concentration higher than the first concentration, The first concentration is 1×10 20 cm -3 above.

2. The semiconductor device according to claim 1, wherein The third nitride semiconductor layer and the fourth nitride semiconductor layer are stacked at a period of 8 nm or less.

3. The semiconductor device according to claim 1 or 2, wherein: The difference between the first concentration and the second concentration is 1×10 20 cm -3 Above and 7×10 20 cm -3 the following.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The impurity is germanium or silicon.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The semiconductor device has an ohmic electrode formed on the second nitride semiconductor layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein: A surface of the first nitride semiconductor layer in contact with a lower surface of the second nitride semiconductor layer is a nitrogen polar surface.

7. The semiconductor device according to claim 6, wherein: The first nitride semiconductor layer has: a barrier layer; and The channel layer is disposed above the barrier layer.

8. The semiconductor device according to claim 6 or 7, wherein: The semiconductor device includes an insulating layer formed on the first nitride semiconductor layer. An opening is formed in the insulating layer to expose the first nitride semiconductor layer. The second nitride semiconductor layer is formed in the opening.

9. The semiconductor device according to any one of claims 1 to 5, wherein: A surface of the first nitride semiconductor layer in contact with a lower surface of the second nitride semiconductor layer is a gallium-polarity surface.

10. The semiconductor device according to claim 9, wherein: The first nitride semiconductor layer has: a channel layer; and The barrier layer is disposed above the channel layer.

11. The semiconductor device according to claim 9 or 10, wherein: A recess is formed in the first nitride semiconductor layer, The second nitride semiconductor layer is formed in the recessed portion.

12. A method for manufacturing a semiconductor device, comprising the following steps: forming a second nitride semiconductor layer including gallium on the first nitride semiconductor layer including gallium by physical vapor deposition, The step of forming the second nitride semiconductor layer includes repeatedly performing the following steps: forming a third nitride semiconductor layer containing an impurity of a first conductivity type at a first concentration, and forming droplets of an alloy of gallium and the impurity on a surface of the third nitride semiconductor layer; and A portion of gallium is evaporated from the droplet, and while the impurity in the droplet is introduced, another portion of gallium in the droplet is nitrided, thereby forming a fourth nitride semiconductor layer containing the first conductivity type impurity at a second concentration higher than the first concentration.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: In the step of forming the fourth nitride semiconductor layer, the liquid droplets are caused to disappear.

14. The method for manufacturing a semiconductor device according to claim 12 or 13, wherein: The time required for forming the fourth nitride semiconductor layer is longer than the time required for forming the third nitride semiconductor layer.

15. The method for manufacturing a semiconductor device according to any one of claims 12 to 14, wherein: The third nitride semiconductor layer and the fourth nitride semiconductor layer are formed in a chamber, In the step of forming the third nitride semiconductor layer and the step of forming the fourth nitride semiconductor layer, at a temperature in the chamber, a saturated vapor pressure of gallium is lower than a pressure in the chamber.

16. The method for manufacturing a semiconductor device according to any one of claims 12 to 15, wherein: The first nitride semiconductor layer is formed on a substrate, The temperature of the substrate when forming the third nitride semiconductor layer and the fourth nitride semiconductor layer is 200° C. or higher and 650° C. or lower.

Images