Data processing method, processor, computing equipment and device

Abstract

The invention discloses a data processing method, a processor, computing equipment and a device, and relates to the technical field of computers. The method comprises the steps that a processor obtains an executable code generated after a source code is compiled, the executable code comprises a code corresponding to an extension instruction, the extension instruction is used for indicating that target data need to reside in a cache, and the target data are data needing to be called for multiple times in the process of executing the executable code. And the processor executes the executable code after obtaining the executable code, and obtains the target data and stores the target data in the cache when executing a code corresponding to the extension instruction in the executable code. According to the technical scheme, the extension instruction is directly carried in the executable code obtained by the processor, and the processor can reside the target data in the cache by executing the code corresponding to the first extension instruction, so that the cache can effectively and accurately store the data frequently called by the processor, and the data read-write rate of the processor is effectively ensured.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application with application number CN202210724755.0 filed on June 23, 2022, and invention name “A High Bandwidth Memory HBM Allocation Method”, the entire contents of which are incorporated by reference into this application.

[0003] This application is a divisional application. The application number of the original application is 202211103960.1, and the original application date is September 9, 2022. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0004] The present application relates to the field of computer technology, and in particular to a data processing method, a processor, a computing device and an apparatus. Background Art

[0005] In a traditional processor architecture, a cache is usually set between the processor and the memory. The cache serves as a temporary storage for data access between the processor and the memory and can be used to store some data.

[0006] If the data stored in the cache is data that the processor needs to call frequently, the processor can access the data directly from the cache and no longer needs to access the data from the memory. This can speed up the data access rate and improve the data processing speed of the processor.

[0007] High bandwidth memory (HBM) can be used as a cache, especially as the last level cache in the cache. HBM has the HBM bypass feature, with which HBM can analyze and determine which data can be retained in HBM, so that when the processor reads this data later, HBM can transfer this data to the previous level cache, which can speed up the data access rate to a certain extent.

[0008] However, the HBM bypass feature of HBM relies on the learning ability of HBM itself in a short period of time. The data retained in the HBM determined by the final analysis may not necessarily be the data that the processor will frequently call, and cannot effectively speed up the data access rate. Summary of the invention

[0009] The present application provides a data processing method, a processor, a computing device and an apparatus for caching data frequently called by a storage processor.

[0010] In a first aspect, a data processing method is provided, which can be executed by a processor, in which the processor obtains executable code generated after source code compilation, and the executable code includes code corresponding to an extended instruction, and the extended instruction is used to indicate that target data needs to reside in a cache, and the target data is data that needs to be frequently called during the execution of the executable code. After obtaining the executable code, the processor executes the executable code, and when executing the code corresponding to the extended instruction in the executable code, the processor obtains the target data and stores the target data in the cache. In order to distinguish it from the extended instruction that appears below, the extended instruction here is called the first extended instruction.

[0011] Through the above method, the executable code obtained by the processor directly carries the first extended instruction. The processor can store the target data in the cache by executing the code corresponding to the first extended instruction, so that the cache can effectively and accurately store the data that the processor will frequently call, effectively ensuring the data reading and writing rate of the processor.

[0012] In a possible implementation, in order to obtain executable code, the processor first analyzes the source code and finds target data with a reuse score greater than a threshold from the data called by the executable code in the running process. The reuse score of the target data represents the reuse degree of the target data, and the reuse degree can represent the number of times or frequency that the target data is called. After determining the target data, the processor inserts the first extension instruction into the source code, and compiles the source code into which the first extension instruction is inserted to generate executable code.

[0013] The processor may include a compiler with compiling capabilities, and the above operations may be performed by the compiler, which may be a software program run by the processor or a hardware module on the processor. Here, the compiler is only used as an example to illustrate that it is a part of the processor. In some possible scenarios, the compiler may also be a software program or hardware module independent of the processor, such as a software program or hardware module deployed on other processors. In this scenario, the compiler may send the executable code to the processor after compiling to generate the executable code, so that the processor executes the executable code.

[0014] Through the above method, the processor can determine the target data by analyzing the source code, so that the target data finally determined is the data that the processor will frequently call during operation. Compared with the data determined based on the bypass characteristics of HBM, the target data determined by analyzing the source code is more accurate.

[0015] In a possible implementation, when storing the target data in the cache, the processor may send a residency instruction to the cache, where the residency instruction is used to indicate that the target data is stored in the cache, so as to indicate that the cache can obtain and store the target data according to the residency instruction.

[0016] For the cache, after receiving the residency instruction, the cache obtains the target data and stores the target data according to the residency instruction. The cache here can be any level of cache in the multi-level cache between the processor and the memory.

[0017] Through the above method, the processor ensures that the cache can effectively store the target data in the cache by sending the resident instruction, thereby avoiding the processor from obtaining the target data from the memory.

[0018] In a possible implementation manner, the cached LLC is HBM, and the first extended instruction indicates that the target data resides in the LLC.

[0019] Through the above method, HBM has high bandwidth and supports large-capacity data storage, so that a large amount of target data can be stored in HBM, and the processor can obtain the target data from HBM at high speed.

[0020] In a possible implementation, for a cache, such as any level of cache, a data replacement strategy may be configured in the cache, and the data replacement strategy indicates that other data other than the target data should be preferentially removed. For example, when the free space in the cache is less than a threshold, the cache needs to remove some data, and the cache may first remove other data other than the target data from the stored data.

[0021] Through the above method, the cache is configured with a data replacement strategy, which can effectively increase the residence time of the target data in the cache.

[0022] In one possible implementation, the processor (such as a compiler in the processor) can also update the target data and update the executable code. For example, the processor can obtain events recorded by the PMU, such as events related to the cache and events related to the processor executing the executable code. The processor updates the target data according to the events recorded by the PMU, such as adding new target data or deleting some target data. The processor inserts a second extended instruction into the source code, and the second extended instruction is used to indicate that the updated target data must reside in the cache. The processor recompiles the source code after the second extended instruction is inserted, and executes the executable code generated by the recompilation. The way in which the processor executes the executable code generated by the recompilation is similar to the way in which the aforementioned processor executes the executable code, which will not be repeated here.

[0023] Through the above method, the processor can update the target data to ensure that the data frequently called by the processor can reside in the cache.

[0024] In a possible implementation, the present application does not limit the position where the processor inserts the first extension instruction or the second extension instruction in the source code. Taking the insertion of the first extension instruction as an example, the processor may insert the first extension instruction in an adjacent line of the code that first calls the target data in the source code, such as inserting the first extension instruction in the line before or after the line of the code that first calls the target data in the source code.

[0025] Through the above method, the processor inserts the first extension instruction at a position in the source code close to the code that first calls the target data, so that the target data can reside in the cache as early as possible during the subsequent execution of the executable code.

[0026] In a possible implementation, when the processor analyzes the source code to determine the target data, some functions containing loops can be determined from the source code, and the loop sequence of each function in the source code can be determined, and the loop sequence of the function includes at least one loop of the function. For the loop sequence of any function, the processor calculates the reuse score of the data corresponding to the access node included in each loop in the loop sequence of the function. The processor determines the target data according to the reuse score of the data corresponding to the access node.

[0027] Through the above method, the loop in the function needs to be executed frequently, and the data corresponding to the memory access nodes in the loop must include the data frequently called by the processor in the process of executing the executable code. The processor can effectively determine the target data by calculating the reuse score of the data corresponding to the access nodes included in the loop.

[0028] In a second aspect, a data processing device is provided, which has the function of implementing the behavior in the method example of the first aspect above. The beneficial effects can be referred to the description of the first aspect and will not be repeated here. The function can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. In a possible design, the structure of the data processing device includes a compilation module and an execution module, which can execute the corresponding functions in the method example of the first aspect above. For details, please refer to the detailed description in the method example, which will not be repeated here.

[0029] In a third aspect, the present application provides a processor, comprising a logic circuit and a power supply circuit, the power supply circuit being used to supply power to the logic circuit, and the logic circuit being used to execute the operating steps of the method described in the first aspect or any possible implementation method of the first aspect.

[0030] In a fourth aspect, the present application also provides a chip, which is connected to a memory, and includes a processor and a cache. The processor is used to read and execute computer program codes stored in the memory, and execute the methods described in the above-mentioned first aspect and various possible implementations of the first aspect.

[0031] In a fifth aspect, the present application further provides a computing device, which includes the chip mentioned in the third aspect, or the computing device includes a cache and a processor. Optionally, the computing device also includes a memory, which is used to store source code and executable code. The processor has the function of implementing the behavior in the method example described in the first aspect or any possible implementation of the first aspect above. The beneficial effects can be found in the description of the first aspect and will not be repeated here.

[0032] In a sixth aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect and each possible implementation manner of the first aspect.

[0033] In a seventh aspect, the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the above-mentioned first aspect and various possible implementations of the first aspect.

[0034] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the architecture of a system provided for this application;

[0036] Figure 2 A schematic diagram of a data processing method provided for this application;

[0037] Figure 3 A schematic diagram of a method for determining target data provided in this application;

[0038] Figure 4A A schematic diagram of direct memory access and access node tracing provided by this application;

[0039] Figure 4B A schematic diagram of indirect memory access and access node tracing provided by this application;

[0040] Figure 5 A schematic diagram of the structure of a data processing device provided in this application;

[0041] Figure 6 A schematic diagram of a computing device provided for the present application. DETAILED DESCRIPTION

[0042] Before describing a data processing method provided by the present application, some concepts involved in the present application are described first.

[0043] (1) Source code and executable code.

[0044] Source code is a text file written by programmers. Programmers write code as source code in a human-readable language like Java, C++, C#, etc. Source code is written according to the conventions and rules of a particular language. Source code is readable by humans, but is not recognizable by machines (such as processors).

[0045] Executable code is machine-readable and can be executed by the machine, and contains machine-readable binary instructions. The compiler can convert source code into executable code.

[0046] (2) Performance monitoring unit (PMU).

[0047] PMU is a hardware device that is mainly used to track and count some low-level hardware events of the system, such as events related to the processor (such as the number of executions of each instruction, the number of exceptions captured by the processor, the number of processor clock cycles, etc.), and events related to the cache (such as the number of times each level of cache is accessed, the number of misses in the cache, etc.). These events can characterize the behavior of the processor in the process of executing executable code.

[0048] In the present application, the processor (such as a compiler in the processor) can analyze the execution process of the executable code containing the extended instructions with the help of the events collected by the PMU, such as the processor can analyze the branch probability of each branch in the function, and can also determine the degree of reuse of the target data in the process of executing the executable code. The processor can adjust the key loop sequence of the function according to the branch probability obtained by the analysis, and the processor can also update the target data according to the degree of reuse of the data, remove some data with a low degree of reuse from the target data, or add some data with a high degree of reuse.

[0049] (3) Functions and loops.

[0050] The source code must meet certain writing standards during the writing process, such as object-oriented programming (OOP), procedure-oriented programming (POP), etc. The programming languages ​​for object-oriented programming include C++, Java, C#, etc., and the programming languages ​​for procedure-oriented programming include fortran, C, etc.

[0051] Source code written using certain writing standards may include code elements such as functions / methods, fields / variables, etc.

[0052] Function / method refers to a subroutine in a class. A method is usually composed of a series of statements and can perform a function. It is called a method in the writing specifications of object-oriented programming and a function in the writing specifications of process-oriented programming. In the embodiments of the present application, it is collectively referred to as a "function".

[0053] A loop is a type of program that may be included in a function. A loop is a program that needs to be executed multiple times when a condition is met. If the condition is not met, the loop can be jumped out.

[0054] Fields / variables store some data, such as integers and characters, strings, hash tables, pointers, etc. Fields / variables can be used as target data mentioned in the embodiments of the present application.

[0055] (4) Memory access instructions and memory access nodes.

[0056] A memory access node refers to an operation in the source code that requires data access or storage. The access node includes a base address and an index. A memory access node can be represented as [A, index], where A represents the base address, which is the address used to store data, and index indicates the index, which is used to represent the location of the data that needs to be accessed or stored at the base address.

[0057] A memory access instruction is an instruction that includes an access node. There are many types of memory access instructions. Here is one of them. For example, in an assignment instruction, the data at the position pointed to by index I on base address A is assigned to variable P. In executing the assignment instruction, it is necessary to read data from the position pointed to by index I on base address A to determine the value assigned to variable P. Memory access instructions with different semantics include different memory access nodes and different numbers of memory access nodes.

[0058] (5) Basic blocks.

[0059] For any function, the compiler splits the function into multiple independent instruction sets according to the preset standard. Any independent instruction set is a basic block. The first basic block executed in a function is the entry basic block of the function, and the last basic block executed is the exit basic block of the function. The first basic block executed in a loop is the head basic block of the loop.

[0060] (6) Branches and branch probabilities.

[0061] There is a position in the function where it can jump to multiple execution paths. This position is usually where statements such as if statements, while statements, and else statements where judgment situations exist. When executing at this position, only one of the multiple execution paths can be executed at a time. Any execution path can be called a branch. The probability of any branch being executed is called the branch probability. The branch probability is related to the statement where the judgment situation exists at this position. In this application, the compiler can analyze the specific semantics of the statement where the judgment situation exists at this position to estimate the branch probability of each branch. For example, the value range of x is an integer from 1 to 10. If the statement where the judgment situation exists at this position is if x>8, then it can be explained that this will be divided into two branches, one branch is the branch of x>8, and the other branch is the branch of x<8. Based on the value range of x, the branch probability of the branch of x>8 can be 20%, and the branch probability of the branch of x<8 can be 80%.

[0062] The data processing method provided by the present application is further described below in conjunction with the accompanying drawings.

[0063] In order to improve the effectiveness of the data resident in the cache 200, the present application provides a data processing method, the processor 100 can analyze the source code to determine the target data, the target data is the data that the executable code corresponding to the source code needs to call frequently during the execution process. The processor 100 can insert an extended instruction for the target data in the source code, and the extended instruction is used to indicate that the target data resides in the cache 200. The processor 100 compiles the source code with the extended instruction inserted into an executable code and executes the executable code. When the processor 100 executes the executable code, when the code corresponding to the extended instruction is executed, the target data is obtained and stored in the cache 200. In the present application, when the processor 100 executes the code corresponding to the extended instruction, the target data can be written into the cache 200 in advance to improve the data reading and writing efficiency of the processor 100.

[0064] like Figure 1As shown, it is a schematic diagram of a system structure provided by the present application, and the system structure includes a processor 100, and a cache 200, and optionally, a memory 300. The memory 300 can be understood as the memory of the processor 100. The processor 100 includes a compiler 110 and a PMU 120. The present application does not limit the specific form of the system, and the system can be a computer chip, such as a system on chip (SoC).

[0065] The compiler 110 may be a software program running on the processor 100, or may be a partial hardware module of the processor 100. The PMU 120 may be located inside the processor 100 as a hardware module.

[0066] Figure 1 The system structure shown is only one possible system structure. In some examples, the compiler 110 and the PMU 120 may be a hardware module or software program independent of the processor 100 and located outside the processor 100. Figure 1 The system structure shown is used as an example for explanation. For a scenario where the compiler 110 and the PMU 120 can be independent of the processor 100, from a functional perspective, the processor 100, the compiler 110, and the PMU 120 are similar and will not be described in detail here.

[0067] The present application does not limit the type of the processor 100, and any processor 100 that can be used to execute executable code is applicable to the embodiments of the present application. The processor 100 may be a central processing unit (CPU), a graphics processing unit (GPU), etc. The processor 100 may also be implemented by an application-specific integrated circuit (ASIC), or a programmable logic device (PLD), and the PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0068] In an embodiment of the present application, the cache 200 in the system includes a multi-level cache, wherein the last level cache 210 in the multi-level cache can be a high bandwidth memory (HBM). The "multi-level cache" divides the cache 200 into multiple levels, and the smaller the cache level is, the faster the read and write speed is, and the smaller the capacity is. In other words, the last level cache 210 (LLC) in the multi-level cache is the cache farthest from the core of the processor 100 and has the largest capacity in the multi-level cache. LLC210 can be used to cache data for interaction between the processor 100 and the memory. From the perspective of the processor 100, the LLC can be understood as the cache of the processor 100. From the perspective of the memory, the LLC can also be used as a cache for the memory.

[0069] Compared with the case where static random-access memory (SRAM) is used as the last level cache 210, HBM supports large-capacity data storage and can effectively expand the capacity of the cache 200. HBM also has a higher bandwidth, which can effectively improve the data read and write rate of the cache 200 and is more suitable for concurrent access scenarios.

[0070] The compiler 110 is a software program running on the processor 100 or a hardware module of the processor 100, and may also be a software program running on other processors 100 or a hardware module of the processor 100. The compiler 110 has a compiling capability, and can compile the source code that the processor 100 needs to execute into an executable code that the processor 100 can recognize. In the present application, the compiler 110 has an analyzing capability, and can determine the target data that the source code needs to call frequently by analyzing the source code, and the extended instructions for the target data in the source code, and the extended instructions are used to indicate that the target data needs to reside in the LLC. Afterwards, the compiler 110 compiles the source code with the extended instructions inserted to generate the executable code that the processor 100 needs to execute.

[0071] It should be noted that, taking the example of the extended instruction indicating that the target data needs to reside in LLC210, in some scenarios, the extended instruction may also indicate that the target data resides in other levels of cache included in the cache 200.

[0072] The processor 100 can obtain the executable code compiled by the compiler 110 and execute the executable code. In the process of executing the executable code, the processor 100 can migrate the data to be processed from the memory 300 to the cache 200, and can also store the processed data in the cache 200. When the processor 100 executes the code corresponding to the extended instruction in the executable code, it can initiate a resident instruction to the LLC, and the resident instruction is used to instruct the LLC to store the target data.

[0073] When the processor 100 executes the executable code, the PMU 120 may monitor the process and record events related to the processor 100 (especially events during the execution of the executable code by the processor 100 ) and events related to the cache 200 .

[0074] The compiler 110 may retrieve the events recorded by the PMU 120, update the determined target data, add extension instructions to the source code for the updated target data, and compile to generate new executable code. The processor 100 may obtain the new executable code and execute the new executable code.

[0075] The memory 300 is usually used to store computer program codes that the processor 100 needs to execute, etc. In the embodiment of the present application, the memory 300 can be used to store the executable code of the compiler 110, and the processor 100 can run the compiler 110 by calling the executable code. The memory 300 can also store the source code that the compiler 110 needs to compile, and the compiler 110 can call the source code from the memory 300 to analyze and compile the source code. The memory 300 can also store the executable code generated after the source code is compiled. After the compiler 110 compiles and obtains the executable code, the executable code can be stored in the memory 300, and the processor 100 can call the executable code and execute the executable code.

[0076] The memory 300 usually uses a dynamic random access memory (DRAM) as the memory 300. In addition to DRAM, the memory 300 can also be other random access memories, such as SRAM, etc. In addition, the memory 300 can also be a read-only memory (ROM). As for the read-only memory, for example, it can be a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), etc. The memory 300 can also be a dual in-line memory module or a dual-line memory module (DIMM), that is, a module composed of a dynamic random access memory (DRAM), and can also be a solid-state disk (SSD). The memory 300 can also be a combination of the above memories, and the embodiment of the present application does not limit the number and type of the memory 300.

[0077] In the above description, the target data is obtained by the compiler 110 by analyzing the loop in the function in the source code, and the target data may be part of the data that needs to be called during the operation of the function in the source code. In practical applications, programmers may mark some data that needs to be called frequently during the process of writing the source code. The compiler 110 may be able to recognize the mark and use the marked data as the target data.

[0078] The difference is that the compiler 110 provided in the embodiment of the present application has the ability to analyze, can determine the target data, and the compiler 110 also has the ability to insert extended instructions, can insert extended instructions for the target data in the source code, and can compile the extended instructions. Due to the existence of the compiler 110, the executable code required to be executed by the processor 100 is increased to indicate that the target data resides in the cache 200. The relevant code (code corresponding to the extended instruction) enables the processor 100 to write the target data to the cache 200 in advance, avoiding the processor 100 from repeatedly reading the target data from the memory, and improving the data reading rate. In addition, the compiler 110 can also update the target data, and then generate a new executable code. The updated target data is more in line with the actual situation of the processor 100 executing the executable code. In the process of the processor 100 executing the new executable code, the data that is often called can also be written to the cache 200 in advance, further ensuring the data reading rate of the processor 100.

[0079] Combine the following Figure 2 A data processing method provided in this application is described, and the method includes:

[0080] Step 201: The processor 100 obtains source code. The processor 100 may obtain source code to be compiled from the memory 300 .

[0081] Step 202: The processor 100 analyzes the source code to determine target data. The target data is data that needs to be frequently called during the execution of the executable code compiled from the source code, and the target data has a reuse score greater than a threshold. The reuse score of the data is used to characterize the degree of reuse of the data.

[0082] Steps 201 and 202 may be executed by the compiler 110 in the processor 100 . In the following description, steps 201 and 202 are described as being executed by the processor 100 .

[0083] This application provides two methods for determining target data, which are described below:

[0084] Method 1: Identify the data with annotations in the source code.

[0085] The source code is written by a programmer using a human-readable language. By understanding the source code, the programmer or other personnel can better understand the meaning of the source code and can also clarify the data in the source code that needs to be frequently called. To this end, the programmer or other personnel can determine the frequently called data based on their understanding of the source code and mark these data. For example, the programmer or other personnel adds a mark before or after the data when the data is first introduced to indicate that the data is frequently called data. The mark is set in a format pre-agreed with the processor 100.

[0086] When analyzing the source code, the processor 100 may identify the data with the annotation and use the data with the annotation as the target data.

[0087] Method 2: Analyze the source code and determine the target data.

[0088] When the processor 100 executes the executable code generated by the source code, it will execute the executable code according to the logic of the source code. The data that can be frequently called in the source code is usually the data involved in the loop. A loop is a section of code that may be included in a function. When the processor 100 executes the loop, if the loop condition is met (such as whether the value of a certain variable is less than a threshold or greater than a threshold), the loop will be executed multiple times until the loop condition is not met. When the loop condition is not met, the loop will be called out and the related code after the loop will be executed.

[0089] Since the loop may be executed multiple times, the data called in the loop may be the target data. Therefore, the processor 100 may analyze the source code to determine the loop included in the source code. The target data is determined according to the data called in the loop.

[0090] The processor 100 can directly use the data called in each loop as the target data. The processor 100 can also analyze the loop to determine the target loop whose loop count or the number of times the data is called in the loop is greater than a threshold, and use the data called in the target loop as the target data. In this case, the number of loops of the target loop or the number of times the data is called in the loop is characterized as the reuse degree of the target data, that is, the number of loops of the target loop or the number of times the data is called in the loop can be used as the reuse score of the data, and the data involved in the target loop is selected as the target data.

[0091] The embodiment of the present application does not limit the method in which the processor 100 determines the target data according to the data called by each loop in the source code. Any method that can determine the target data according to the data called by each loop in the source code is applicable to the embodiment of the present application.

[0092] For method 2, such as Figure 3 As shown, this application provides a method for determining target data, which can be specifically referred to as follows:

[0093] Step 2021: The processor 100 filters a critical loop from the source code. The critical loop refers to a loop that satisfies a first screening condition, and the first screening condition includes part or all of the following: the number of accessed nodes in the loop is greater than a node threshold, and the ratio of accessed instructions in the loop to all instructions in the loop is greater than a ratio threshold. The node threshold and the ratio threshold can be preset.

[0094] When executing step 2021 , the processor 100 may filter the source code at different granularities in sequence.

[0095] First, the processor 100 can filter the source code at the function granularity, remove complex functions in the source code, and some functions that are executed only once, and find a first candidate function from the source code. The first candidate function satisfies some or all of the following:

[0096] 1. The function includes a loop.

[0097] 2. The function does not belong to the library function.

[0098] 3. No new operations are defined in the function.

[0099] Afterwards, the processor 100 further screens the first candidate function from the granularity of the loop, removes loops including multiple branches or functions that need to cooperate with other data outside the function (such as files or functions), and screens out the second candidate function. The second candidate function satisfies some or all of the following:

[0100] 1. The loop in the function consists of only a single exit edge.

[0101] 2. The loop in the function does not involve multiple branches.

[0102] 3. The loop in the function is not a loop defined by a macro.

[0103] 4. The loop in the function does not call any files other than the source code.

[0104] 5. Do not call other functions in the loop of a function.

[0105] 6. The custom operations in the function are not called in the loop of the function.

[0106] Finally, the processor 100 can determine the number of memory access nodes included in the loop in the second candidate function and the proportion of access instructions to all instructions in the loop from the second candidate function, and further determine the critical loop that meets the screening condition.

[0107] It should be noted that in some source codes, there are nested loops, for example, loop A also includes loop B, and loop C also includes loop D, and loop D also includes loop E. Since the innermost loop (such as loop B and loop D) is the loop with the most execution times, the processor 100 can only consider the innermost loop when screening the key loop. That is, the key loop is the innermost loop. Of course, the processor 100 can also consider the outer loop when screening the key loop, that is, the key loop can be the innermost loop or the outer loop.

[0108] Step 2022: The processor 100 determines a critical loop sequence of each function in the source code. The critical loop sequence of a function includes at least one critical loop of the function, and at least one critical loop in the critical loop sequence of the function can be sorted in execution order.

[0109] In step 2022, the processor 100 determines the critical loop. The processor 100 can analyze each function in the source code, determine the target function including the critical loop, and arrange each critical loop in the target function in execution order to generate a critical loop sequence of the function.

[0110] It should be noted that when there are multiple branches in a function, and the key loops of the function are distributed on the multiple branches, the processor 100 can select the key loops distributed on the branch with the highest branch probability among the multiple branches, sort these key loops according to the execution order on the branch, and generate the key loop sequence of the function. That is, the key loop sequence of the function is the key loop sequence of the branch with the highest branch probability in the function, and the key loop in the key loop sequence of the branch is the key loop on the branch.

[0111] The processor 100 may also sort the key loops on each branch according to the execution order of the branch to generate a key loop sequence for each branch, and the processor 100 combines the key loop sequences of each branch to generate a key loop sequence of the function, that is, the key loop sequence of the function includes the key loop sequences of each branch.

[0112] This application provides a method for obtaining the key loop sequence of a function, the specific method is as follows:

[0113] For any function, the processor 100 can traverse the function with the basic block as the granularity to obtain the key loop sequence of the function. The processor 100 can also traverse the source code with the basic block as the granularity from the entry basic block in the function to the exit basic block of the function. Each time the processor 100 traverses a basic block, it can perform the following steps:

[0114] Step 1: Determine whether the basic block is the head basic block of the loop. If yes, execute step 2; otherwise, execute step 5.

[0115] Step 2: Determine whether the loop has not been traversed. If so, execute step 3; otherwise, execute step 5.

[0116] Step 3: Determine whether the loop is a critical loop. If so, go to step 4; otherwise, go to step 5.

[0117] Step 4: Add the loop to the key loop sequence and mark the loop as a traversed loop.

[0118] Step 5: End the traversal of the basic block, extract the next basic block, and execute step 1.

[0119] It should be noted that, when executing step 5, if the function includes multiple branches, the next basic block may select a basic block on the branch with the highest branch probability.

[0120] The processor 100 (specifically, the compiler in the processor) executes the above steps 1 to 5 cyclically, and after traversing from the entry basic block to the exit basic block, a critical loop sequence of the function can be generated.

[0121] Step 2023: For a key loop sequence of any function, the processor 100 traces back the memory access nodes of the memory access instructions of each key loop of the key loop sequence to determine the data corresponding to the memory access node, which is the data stored at the base address of the memory access node.

[0122] Step 2024: The processor 100 calculates the reuse score of the data corresponding to each memory access node. The processor 100 may calculate the reuse score of the data corresponding to each memory access node according to the calling mode of the data corresponding to each memory access node.

[0123] The calling mode of the data corresponding to the memory access node describes the mode used when calling the data. The calling mode includes but is not limited to: data multiplexing mode, memory access mode indicated by the memory access node, and data reading and writing mode.

[0124] 1), data multiplexing method.

[0125] The data reuse method refers to the execution relationship between multiple calls to data.

[0126] When executing the executable code corresponding to the source code, the data can be called at the same time. This type of call is usually reflected in the source code with a preamble that represents parallel computing. The data called after this type of parallel computing preamble is the data that needs to be reused in parallel. Accordingly, this data reuse method is a parallel reuse method. Of course, the data can also be called one by one. This data call reuse method is a serial reuse method.

[0127] Different data reuse modes may result in different data reuse times. The data reuse times indicates the number of times the data is called.

[0128] 2) The memory access method indicated by the memory access node.

[0129] The memory access mode indicated by the memory access node is divided into direct memory access and indirect memory access. Among them, direct memory access means that the index in the memory access node is directly indicated, that is, the index part in the memory access node is the specific value of the index.

[0130] In order to facilitate the understanding of the memory access method indicated by the memory access node, the following Figure 4A as well as Figure 4B Provide explanation.

[0131] like Figure 4A As shown, it is a schematic diagram of direct memory access and access node tracing provided by the present application. Figure 4A The source code includes 5 instructions. Each line of code is an instruction, and the number before each line of code is the number of the instruction. Figure 4AThe tree structure on the left describes the relationship between the five instructions, where the arrow indicates the tracing direction. The numbers in the nodes in the tree structure represent the instruction numbers, and the characters under the numbers indicate the types of the instructions. Among them, load represents a load instruction, addr represents fetching data at an address, add represents an addition instruction, mult represents a multiplication instruction, and conv represents a forced conversion instruction. The u in the node represents the variable u that appears in instruction 3.

[0132] Among them, the instruction numbered 4 is a memory access instruction, which carries a memory access node, which is the part represented by "[]". The part after base is the base address. The part after Index is the index. The memory access node directly indicates the index and base address, which belongs to direct memory access.

[0133] Indirect memory access means that the index in the memory access node is indirectly indicated, that is, the index part in the memory access node is not a specific value, but needs to be further dereferenced.

[0134] like Figure 4B As shown, a schematic diagram of indirect memory access and access node tracing is provided for the present application. Figure 4B The source code includes 5 instructions. Each line of code is an instruction, and the number before each line of code is the number of the instruction. Figure 4B The tree structure on the left describes the relationship between the five instructions, where the arrow indicates the tracing direction. The numbers in the nodes in the tree structure represent the instruction numbers, and the characters under the numbers indicate the operations represented by the instructions. Among them, addr represents the data at the address, add represents the addition instruction, mult represents the multiplication instruction, and mem represents the memory access instruction. The psi in the node is used to represent the variable psi that appears in instruction 4.

[0135] Among them, the instruction numbered 5 is a memory access instruction, which carries a memory access node, which is the part represented by "[]". The inside of [] does not directly indicate the base address and index, and needs to be further dereferenced, which belongs to indirect memory access.

[0136] 3) How to read and write data.

[0137] The data reading and writing mode indicates writing data or reading data. It is generally considered that the power consumption when writing data is greater than the power consumption when reading data.

[0138] The reuse score Level of any data x can be calculated using the following formula:

[0139] Level=parallel(x)*(reuse(x)+regular(x)+cost(x))

[0140] Among them, parallel(x) indicates whether data x is multiplexed in parallel or in series. Parallel multiplexing and serial multiplexing take different values, and the value of parallel multiplexing can be greater than the value of serial multiplexing. reuse(x) is used to indicate the number of times data x is multiplexed in series. regular(x) indicates the memory access method of data. Direct memory access and indirect memory access can correspond to different values ​​of regular(x). cost(x) is used to indicate the data reading and writing method. Writing data or reading data can correspond to different values ​​of cost(x).

[0141] The reuse score of the data corresponding to each memory access node represents the reuse degree of the data. The greater the reuse degree, the more times the data is called. Correspondingly, the higher the reuse score of the data.

[0142] Step 2025: The processor 100 uses the N data with the largest reuse scores as target data, where N is a preset positive integer.

[0143] Step 203: The processor 100 inserts an extension instruction at the relevant position of the first call to the target data in the source code. The extension instruction is used to indicate that the target data resides in the LLC.

[0144] The relevant position of the first call to the target data may be an adjacent line or several lines before and after the code that first calls the target data in the source code. For example, the relevant position of the first call to the target data may be located before the code that first calls the target data, such as the line before the code that first calls the target data, or the first K lines, where K is a positive integer. For another example, the relevant position of the first call to the target data may also be located after the code that first introduces the target data, such as the line after the code that first calls the target data, or the last K lines, where K is a positive integer.

[0145] Step 204: The processor 100 compiles the source code into which the extended instruction is inserted, and generates an executable code including the code corresponding to the extended instruction. After generating the executable code, the processor 100 may store the executable code in the memory 300.

[0146] In the embodiment of the present application, the processor 100 has the ability to compile the extended instruction, and can compile the extended instruction into an assembly instruction that can be recognized by the machine. The processor 100 can compile the instruction in the source code inserted with the extended instruction to generate an executable code.

[0147] Step 205: The processor 100 executes the executable code. When the processor 100 executes the code corresponding to the extended instruction (that is, executes the assembly instruction corresponding to the extended instruction), the processor 100 can send a resident instruction to LLC210, and the resident instruction is used to instruct LLC210 to store the target data.

[0148] If the executable code is stored in the memory 300 , the processor 100 may first obtain the executable code from the memory 300 , and then execute the executable code after obtaining the executable code.

[0149] Step 206: After receiving the residency instruction, LLC210 obtains the target data (eg, LLC210 may obtain the data from the memory) and stores the target data.

[0150] That is to say, the processor 100 will execute step 205 for any target data, so that the data in LLC210 can be divided into two categories, one is the target data indicated by the resident instruction, and the other is other data.

[0151] In order to further increase the storage time of the target data in LLC210 (that is, the residence time of the target data in LLC210), a data replacement strategy can be configured in LLC210. ​​The data replacement strategy indicates that when data in LLC210 needs to be removed (such as the free space in LLC210 is less than a threshold), other data except the target data should be removed first.

[0152] The embodiment of the present application does not limit the manner in which LLC210 executes the data replacement strategy. Two possible execution manners are listed below.

[0153] Method 1: In LLC210, LLC210 may be able to set the type of data, the first type of data is the target data indicated by the resident instruction, and the second type of data is other data. For example, when LLC210 receives the resident instruction, it may set the type of data indicated by the resident instruction to the first type. Other data is correspondingly set to the second type.

[0154] LLC210 can also set a resident value for different types of data. The resident value has a preset value range, that is, the maximum and minimum values ​​of the resident value are determined. The resident value of the first type of data takes the minimum value.

[0155] Initially, the resident value of the second type of data can be set to a value greater than the resident value of the first type of data, or can be set to a minimum value. This application does not limit the specific value of the resident value of the second type of data, and the resident values ​​of different second types of data can be the same or different.

[0156] When there is no free space in LLC210 or the free space is less than a threshold and new data cannot be stored, LLC210 may delete the stored data. LLC210 may preferentially delete data whose resident value is equal to the maximum value.

[0157] If the LLC 210 does not contain data with a resident value equal to the maximum value, the LLC 210 may increase the resident value of the second type of data and remove the data with the maximum resident value. If the resident value of the second type of data is increased and the LLC 210 still does not contain data with a resident value equal to the maximum value, the resident value of the second type of data may continue to be increased.

[0158] Method 2: In LLC210, LLC210 may be able to set the type of data, the first type of data is the target data indicated by the resident instruction, and the second type of data is other data. For example, when LLC210 receives the resident instruction, it may set the type of data indicated by the resident instruction to the first type. Other data is correspondingly set to the second type.

[0159] LLC210 can also set a resident value for different types of data. The resident value has a preset value range, that is, the maximum and minimum values ​​of the resident value are determined. The resident value of the first type of data takes the minimum value.

[0160] LLC 210 may also set a count value, which is used to record the number of times LLC 210 modifies the resident value of the second type of data. Each time the resident value of the second type of data is modified, the count value increases by one.

[0161] Initially, the resident value of the second type of data can be set to a value greater than the resident value of the first type of data, or can be set to a minimum value. This application does not limit the specific value of the resident value of the second type of data, and the resident values ​​of different second types of data can be the same or different.

[0162] When there is no free space in LLC210 or the free space is less than a threshold and new data cannot be stored, LLC210 may delete the stored data. LLC210 may preferentially delete data whose resident value is equal to the maximum value.

[0163] If the data with a resident value equal to the maximum value does not exist in the LLC210, it is first determined whether the count value is greater than the set value. If the calculated value is not greater than the set value, the LLC210 can increase the resident value of the second type of data, increase the count value by one, and remove the data with the resident value equal to the maximum value. If the count value is greater than the set value, the LLC210 can uniformly increase the resident value of the first type of data and remove the data with the resident value equal to the maximum value.

[0164] If after increasing the resident value of the second type or the second type of data, LLC210 still does not have data with the maximum resident value, the aforementioned operation can be continued, that is, determining whether the count value is greater than the set value. If the count value is not greater than the set value, LLC210 can increase the resident value of the second type of data, increase the count value by one, and eliminate the data with the maximum resident value. If the count value is greater than the set value, LLC210 can uniformly increase the resident value of the first type of data and eliminate the data with the resident value equal to the maximum value.

[0165] In the embodiment of the present application, the processor 100 can also update the target data, such as increasing the target data or reducing the target data. The processor 100 can insert an extended instruction for the updated target data in the source code, and compile and generate a new executable code. The processor 100 executes the new executable code. The way in which the processor 100 updates the target data can be seen in step 206.

[0166] Step 207 : The processor 100 obtains the events recorded by the PMU 120 , and updates the target data according to the events recorded by the PMU 120 .

[0167] The processor 100 can analyze the branch probability of each branch in the source code function according to the events recorded by the PMU 120 (such as the number of executions of each instruction and the event of data not hitting the cache 200). For example, the events recorded by the PMU 120 include the event of data not hitting the cache 200. When the data does not hit in the cache 200, the branch that calls the data will not be executed, indicating that the branch probability of each branch when the executable code is actually executed will be different from the branch probability obtained by analyzing the source code. The events recorded by the PMU 120 include the number of executions of each instruction. The number of executions of instructions in different branches can indicate the number of executions of each branch, and then determine the branch probability of each branch.

[0168] The processor 100 can determine the branch probabilities of each branch when the executable code is actually executed through the events recorded by the PMU 120. The processor 100 can regenerate the critical loop sequence of the function based on the determined branch probabilities (applicable to the scenario where the critical loop sequence of the function is the critical loop sequence of the branch with the highest branch probability in the function).

[0169] In addition, when calculating the reuse score of data, the processor 100 may also refer to the events recorded by the PMU 120. For example, when the events recorded by the PMU 120 and related to the cache 200 show that a certain data has been missed in the cache 200 for many times, it indicates that the reuse degree of the data is high, and the processor 100 may improve the reuse score of the data. Specifically, the processor 100 may add a weight value related to the events recorded by the PMU 120 and related to the cache 200 to the calculation formula of the reuse score of the data. When the events recorded by the PMU 120 and related to the cache 200 show that the number of times a certain data has been missed in the cache 200 is greater than a certain value, the value of the weight value may be changed to a larger value to improve the reuse score of the data.

[0170] Step 208: The processor 100 inserts an extension instruction at the relevant position of the updated target data introduced for the first time. The extension instruction is used to indicate that the updated target data resides in the LLC. The processor 100 performs step 207 in a similar manner to the manner of performing step 203. For details, please refer to the above description, which will not be repeated here.

[0171] Step 209: The processor 100 compiles the source code into which the extended instruction is inserted, and generates an executable code including the code corresponding to the extended instruction. The way in which the processor 100 executes step 208 is similar to the way in which the processor 100 executes step 204, and the details can be found in the above description, which will not be described again here. Afterwards, the processor 100 can send the executable code to the processor 100, and the processor 100 executes the new executable code. The way in which the processor 100 executes the executable code can be found in the relevant descriptions of steps 205 to 206, which will not be described again here.

[0172] In the present application, the processor 100 can analyze the source code and then determine the target data that the processor 100 will frequently call during the execution of the executable code. The target data determined from the source code itself is more accurate and is the data that the processor 100 will frequently call in the true sense. After determining the target data, the processor 100 can insert the extended instructions of the target data in the source code, and then compile the source code to generate the executable code, so that the executable code includes the code corresponding to the extended instructions. In the process of the processor 100 executing the executable code, when the code corresponding to the extended instruction is executed, the processor 100 can obtain the target data according to the extended instruction and store the target data in the cache 200. In this way, the target data can be stored in advance in the cache 200 to avoid the processor 100 from calling the target data from the memory when the target data needs to be called. The data read and write rate of the processor 100 is effectively improved. In addition, since the processor 100 can update the target data according to the events recorded by the PMU 120 during the execution of the executable code, and then update the executable code, the accuracy of the target data is improved. It can ensure that the target data that is actually frequently called by the processor 100 is stored in the cache 200 , further increasing the data reading and writing rate of the processor 100 .

[0173] Based on the same inventive concept as the method embodiment, the present application also provides a data processing device, which is used to execute the above-mentioned Figure 2 or Figure 3 The method executed by the processor 100 in the method example shown in the figure, the relevant features can be found in the above method example, and will not be repeated here. Figure 5 As shown, the data processing device 500 includes a compiling module 501 and an executing module 502 .

[0174] Compilation module 501 is used to obtain executable code, the executable code includes code corresponding to the first extended instruction, the first extended instruction is used to indicate that the target data needs to reside in the cache, and the target data is data that needs to be called multiple times during the execution of the executable code. Figure 2 The extended instructions mentioned in the illustrated embodiment.

[0175] The execution module 502 is used to execute the code corresponding to the first extended instruction in the executable code, obtain the target data and store the target data in the cache.

[0176] It should be understood that the data processing device 500 of the embodiment of the present invention can be implemented by a central processing unit (CPU), an application-specific integrated circuit (ASIC), or a programmable logic device (PLD), and the above PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a data processing unit (DPU), a system on chip (SoC) or any combination thereof. It can also be implemented by software Figure 2 or Figure 3 When the data processing method is shown, the device 500 and its various modules may also be software modules.

[0177] In a possible implementation, when obtaining the executable code, the compiling module 501 may analyze the source code to determine the target data, the reuse score of the target data being greater than a threshold, and the reuse score of the target data being used to indicate the reuse degree of the target data. The compiling module 501 inserts the first extension instruction into the source code, and compiles the source code into which the first extension instruction is inserted to generate the executable code.

[0178] In a possible implementation, the execution module 502 sends a residency instruction to the cache when acquiring the target data and storing the target data in the cache, and the residency instruction is used to indicate that the target data is stored in the cache. In this way, after receiving the residency instruction, the cache acquires the target data and stores the target data according to the residency instruction.

[0179] In a possible implementation manner, the cached LLC is HBM, and the first extended instruction indicates that the target data resides in the LLC.

[0180] In a possible implementation, the compiling module 501 can update the target data and thus update the executable code. The compiling module 501 obtains the events recorded by the PMU. The compiling module 501 updates the target data according to the events recorded by the PMU. After the compiling module 501 inserts the second extended instruction into the source code, it recompiles the source code into which the second extended instruction is inserted to generate the executable code. The second extended instruction is used to indicate that the updated target data needs to reside in the cache. The second extended instruction corresponds to Figure 2The execution module 502 executes the recompiled executable code.

[0181] In a possible implementation, when inserting the first extension instruction into the source code, the compiling module 501 inserts the first extension instruction into the adjacent line of the first call to the target data in the source code.

[0182] In a possible implementation, when the compilation module 501 analyzes the source code to determine the target data, the loop sequence of each function in the source code is determined, and the loop sequence of the function includes at least one loop in the function. For the loop sequence of any function, the compilation module 501 calculates the reuse score of the data corresponding to the access node included in the loop in the loop sequence of the function, and the reuse score indicates the reuse degree of the data in the source code; the compilation module 501 determines the target data according to the reuse score of the data corresponding to the access node.

[0183] It should be noted that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. The functional modules in the embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0184] The present application also provides a computing device. Figure 6 As shown, it is a schematic diagram of the structure of a computing device, and the computing device 10 includes a processor 100, a cache 200, a memory 300, a bus 400, and a communication interface 600. The processor 100, the cache 200, the memory 300, and the communication interface 600 communicate with each other through the bus 400. The bus 400 can be a line based on the peripheral component interconnect express (PCIe) standard, or it can be other types of buses.

[0185] The description of the processor 100 , the cache 200 , and the memory 300 may refer to the above description, which will not be repeated here.

[0186] The present application also provides a processor, the processor includes a logic circuit and a power supply circuit, the power supply circuit is used to supply power to the logic circuit, the logic circuit is used to execute Figure 2 or Figure 3 The operation steps of the method implemented by the processor in the method example described in the figure are not repeated here for the sake of brevity.

[0187] The present application also provides a chip, the chip is connected to the memory, the chip includes a processor and a cache, the processor is used to read and execute the computer program code stored in the memory, Figure 2 or Figure 3 The operation steps of the method implemented by the processor in the method example described in the figure are not repeated here for the sake of brevity.

[0188] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0189] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0190] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0191] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0192] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0193] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

[0194] The above is only a specific implementation of the present application. Those skilled in the art may conceive of changes or substitutions based on the specific implementation provided by the present application, which should all be included in the protection scope of the present application.

Claims

1. A data processing method, characterized in that: include: The processor obtains an executable code including a code corresponding to a first extended instruction, wherein the first extended instruction is used to indicate that target data needs to reside in a cache, and the target data is data that needs to be frequently called during the execution of the executable code; The processor executes the code corresponding to the first extended instruction, obtains the target data, and stores the target data in the cache.

2. The method according to claim 1, characterized in that The processor obtains executable code including a code corresponding to the first extended instruction, including: Analyze the source code to determine the target data, the reuse score of the target data being greater than a threshold, and the reuse score of the target data being used to indicate the reuse degree of the target data; After the first extended instruction is inserted into the source code, the executable code is generated by compiling the source code.

3. The method according to claim 1 or 2, characterized in that The processor acquires the target data and stores the target data in the cache, including: A residency instruction is sent to the cache, where the residency instruction is used to instruct the target data to be stored in the cache, so as to instruct the cache to obtain the target data and store the target data according to the residency instruction.

4. The method according to any one of claims 1 to 3, characterized in that The last level cache LLC of the cache is a high bandwidth memory HBM, and the first extended instruction indicates that the target data resides in the LLC.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: When the free space in the cache is less than a threshold, the cache clears data other than the target data in the cache.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: Get the events recorded by the performance monitoring unit PMU; updating the target data according to the event; After inserting the second extension instruction into the source code, recompiling to generate executable code is performed, and the recompiled executable code is executed, wherein the second extension instruction is used to indicate that the updated target data needs to reside in the cache.

7. The method according to any one of claims 1 to 6, characterized in that: The processor inserts a first extension instruction into the source code, comprising: The first extension instruction is inserted into a line adjacent to a line of code that first calls the target data in the source code.

8. The method according to any one of claims 1 to 7, characterized in that: The processor analyzes the source code to determine the target data, including: Determine a loop sequence of each function in the source code, wherein the loop sequence of the function includes at least one loop of the function; For a loop sequence of any function, calculating a reuse score of data corresponding to an access node included in each loop in the loop sequence of the function; The target data is determined according to a reuse score of data corresponding to the access node.

9. A processor, characterized in that: The processor comprises a logic circuit and a power supply circuit, wherein the power supply circuit is used to supply power to the logic circuit, and the logic circuit is used to execute the operation steps of the method according to any one of claims 1 to 8.

10. A chip, characterized in that: The computer chip comprises a processor and a cache, and the processor is used to execute the operation steps of the method according to any one of claims 1 to 8 to store target data in the cache.

11. A computing device, characterized in that: The computing device comprises a processor, a cache and a memory, wherein the memory is used to store computer program codes, and the processor is used to execute the operation steps of the method according to any one of claims 1 to 8.

12. A data processing device, characterized in that: The device comprises: A compiling module, used to obtain an executable code including a code corresponding to a first extended instruction, wherein the first extended instruction is used to indicate that target data needs to reside in a cache, and the target data is data that needs to be frequently called during the execution of the executable code; The execution module is used to execute the code corresponding to the first extended instruction in the executable code, obtain the target data, and store the target data in the cache.

13. The device according to claim 12, characterized in that The compilation module is used to: Analyze the source code to determine the target data, the reuse score of the target data being greater than a threshold, and the reuse score of the target data being used to indicate the reuse degree of the target data; After the first extended instruction is inserted into the source code, the executable code is generated by compiling the source code.

14. The device according to claim 12 or 13, characterized in that The execution module acquires the target data and stores the target data in the cache, and is used to: A residency instruction is sent to the cache, where the residency instruction is used to instruct the target data to be stored in the cache, so as to instruct the cache to obtain the target data and store the target data according to the residency instruction.

15. The device according to any one of claims 12 to 14, characterized in that The last level cache LLC of the cache is a high bandwidth memory HBM, and the first extended instruction indicates that the target data resides in the LLC.

16. The device according to any one of claims 12 to 15, characterized in that: The compiling module is further used to: obtain events recorded by a performance monitoring unit PMU; update the target data according to the events; and recompile and generate executable code after inserting a second extended instruction into the source code, wherein the second extended instruction is used to indicate that the updated target data needs to reside in the cache; The execution module is specifically used to execute the executable code generated by recompilation.

17. The device according to any one of claims 12 to 16, characterized in that: The compiling module inserts a first extension instruction into the source code, for: The first extension instruction is inserted into a line adjacent to a line of code that first calls the target data in the source code.

18. The device according to any one of claims 12 to 17, characterized in that: The compiling module analyzes the source code to determine the target data, which is used to: Determine a loop sequence of each function in the source code, wherein the loop sequence of the function includes at least one loop in the function; For a loop sequence of any function, calculating a reuse score of data corresponding to access nodes looped in the loop sequence of the function, wherein the reuse score indicates a reuse degree of the data in the source code; The target data is determined according to a reuse score of data corresponding to the access node.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes instructions, which, when executed on a computer, enable the computer to execute the operating steps of any one of the methods of claims 1 to 8.

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