Data processing method, processor, computing device and apparatus

Abstract

A data processing method, processor, computing device and apparatus, relating to the technical field of computer. The method comprises: the processor acquires executable code generated after source code compilation, the executable code comprising code corresponding to an extension instruction, the extension instruction being used to indicate that target data needs to reside in a cache, the target data being data that needs to be called multiple times in the process of executing the executable code. After acquiring the executable code, the processor executes the executable code, and when executing the code corresponding to the extension instruction in the executable code, the processor acquires the target data and stores the target data in the cache. The executable code acquired by the processor directly carries the extension instruction, and the processor can reside the target data in the cache by executing the code corresponding to the first extension instruction, so that the cache can effectively and accurately store data that the processor will frequently call, thereby effectively ensuring the data read / write rate of the processor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. CN202210724755.0, filed on June 23, 2022, entitled "A High Bandwidth Memory HBM Allocation Method", the entire contents of which are incorporated herein by reference.

[0003] This application is a divisional application. The original application has the application number 202211103960.1 and the original application date is September 9, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field

[0004] This application relates to the field of computer technology, and in particular to a data processing method, processor, computing device and apparatus. Background Technology

[0005] In traditional processor architectures, a cache is typically placed between the processor and memory. The cache serves as a temporary storage for data access between the processor and memory and can be used to store some data.

[0006] If the data stored in the cache is data that the processor frequently needs to access, the processor can access the data directly from the cache instead of accessing the data from memory. This can speed up data access and improve the processor's data processing speed.

[0007] High bandwidth memory (HBM) can be used as a cache, especially as the last level of cache. HBM has an HBM bypass feature, which allows HBM to analyze and determine which data can be retained in HBM. When the processor reads this data later, HBM can transfer the data to the next higher level cache, which can speed up data access to some extent.

[0008] However, HBM's HBM bypass feature relies on HBM's own learning ability in a short period of time. The data that is ultimately determined to be retained in HBM may not necessarily be the data that the processor will frequently access, and therefore cannot effectively speed up the data access rate. Summary of the Invention

[0009] This application provides a data processing method, processor, computing device, and apparatus for storing data frequently accessed by the processor in a cache.

[0010] In a first aspect, a data processing method is provided, which can be executed by a processor. In the method, the processor acquires executable code generated after compiling source code, the executable code including code corresponding to a first extension instruction. The first extension instruction is used to indicate that target data needs to reside in a cache, and the target data is data frequently called in a process of executing the executable code. After acquiring the executable code, the processor executes the executable code. When the code corresponding to the first extension instruction is executed, the processor acquires the target data and stores the target data in the cache.

[0011] Through the above method, the executable code acquired by the processor directly carries the first extension instruction. The processor can make the cache effectively and accurately store data frequently called by the processor by storing the target data in the cache through the code corresponding to the first extension instruction, thereby effectively ensuring the data read-write rate of the processor.

[0012] In a possible implementation, in order to acquire the executable code, the processor first analyzes the source code, and finds target data with a reuse score greater than a threshold from data called in a running process of the executable code. The reuse score of the target data represents the reuse degree of the target data, and the reuse degree can represent the number or frequency of calls of the target data. After determining the target data, the processor inserts the first extension instruction into the source code, and compiles the source code with the inserted first extension instruction to generate the executable code.

[0013] The processor can include a compiler with compiling capability. The above operation can be executed by the compiler. The compiler can be a software program running on the processor, or a hardware module on the processor. Here, the compiler is taken as an example of being part of the processor. In some possible scenarios, the compiler can also be a software program or a hardware module independent of the processor, such as a software program or a hardware module deployed on another processor. In this scenario, the compiler can send the executable code to the processor after compiling to generate the executable code, so that the processor executes the executable code.

[0014] Through the above method, the processor can determine the target data by analyzing the source code, so that the finally determined target data is data frequently called in a running process of the processor. Compared with data determined based on the bypass feature of the HBM, the target data determined by analyzing the source code is more accurate.

[0015] In a possible implementation, when storing the target data in the cache, the processor can send a residence instruction to the cache, where the residence instruction is used to indicate that the target data is stored in the cache, so that the cache can acquire and store the target data according to the residence instruction.

[0016] For the cache, after receiving the residence instruction, the cache acquires the target data and stores the target data according to the residence instruction. Here, the cache can be any level of cache between the processor and the memory.

[0017] Through the above method, the processor ensures that the cache can effectively save the target data in the cache by sending the residence instruction, so as to avoid the processor acquiring the target data from the memory.

[0018] In a possible implementation, the LLC of the cache is HBM, and the first extension instruction indicates that the target data resides in the LLC.

[0019] Through the above method, the HBM has high bandwidth and supports large-capacity data storage, so that a large amount of target data can be stored in the HBM, and the processor can acquire the target data from the HBM at a high speed.

[0020] In a possible implementation, for the cache, such as for any level of cache, the cache can be configured with a data replacement policy, which indicates that other data except the target data is preferentially removed. For example, when the free space in the cache is less than a threshold, the cache needs to remove some data, and the cache can first remove other data except the target data from the stored data.

[0021] Through the above method, the data replacement policy configured in the cache can effectively increase the residence duration of the target data in the cache.

[0022] In a possible implementation, the processor (such as a compiler in the processor) can also update the target data and update the executable code. For example, the processor can acquire events recorded by the PMU, such as events related to the cache and events related to the processor executing the executable code. The processor updates the target data according to the events recorded by the PMU, such as adding new target data or deleting some target data. The processor inserts a second extension instruction in the source code, where the second extension instruction is used to indicate that the updated target data needs to reside in the cache. The processor recompiles the source code after the second extension instruction is inserted, and executes the executable code generated by the recompilation. The processor executes the executable code generated by the recompilation in a manner similar to the manner in which the processor executes the executable code, which will not be described herein again.

[0023] Through the above method, the processor can update the target data, so that the data frequently called by the processor can reside in the cache.

[0024] In a possible implementation, the present application does not limit the processor to insert the first extended instruction or the second extended instruction at the position of the source code. Taking the insertion of the first extended instruction as an example, the processor can insert the first extended instruction at a line adjacent to the first call of the target data in the source code, such as a line before or after the first call of the target data in the source code.

[0025] Through the above method, the processor inserts the first extended instruction at a position close to the first call of the target data in the source code, so that the target data can be resident in the cache as early as possible in the subsequent execution of the executable code.

[0026] In a possible implementation, when the processor analyzes the source code to determine the target data, the processor can determine some functions containing loops from the source code, determine a loop sequence of each function in the source code, and the loop sequence of the function includes at least one loop of the function. For the loop sequence of any function, the processor calculates a reuse score of data corresponding to an access node included in each loop in the loop sequence of the function. The processor determines the target data according to the reuse score of the data corresponding to the access node.

[0027] Through the above method, the loop in the function needs to be frequently executed, and the data corresponding to the access node in the loop must include the data frequently called in the process of executing the executable code by the processor. The processor can effectively determine the target data by calculating the reuse score of the data corresponding to the access node included in the loop.

[0028] In a second aspect, a data processing apparatus is provided, which has functions to implement the behaviors in the method examples of the first aspect, and the advantages can be referred to the description of the first aspect and will not be repeated here. The functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. In a possible design, the data processing apparatus includes a compiling module and an executing module, which can perform the corresponding functions in the method examples of the first aspect, and the specific implementation can be referred to the detailed description in the method examples, which will not be repeated here.

[0029] In a third aspect, the present application provides a processor, which includes a logic circuit and a power supply circuit, the power supply circuit is configured to supply power to the logic circuit, and the logic circuit is configured to perform the operation steps of the method according to the first aspect or any possible implementation manner of the first aspect.

[0030] In a fourth aspect, the present application provides a chip connected with a memory, the chip comprising a processor and a cache, the processor being configured to read and execute computer program codes stored in the memory, and execute the method of the first aspect and the possible implementation manners of the first aspect.

[0031] In a fifth aspect, the present application provides a computing device comprising the chip of the third aspect, or the computing device comprising the cache and the processor. Optionally, the computing device further comprises a memory configured to store source codes and executable codes. The processor has the function of implementing the method of the first aspect or the method of the possible implementation manners of the first aspect, and the beneficial effects can be referred to the description of the first aspect.

[0032] In a sixth aspect, the present application provides a computer readable storage medium, the computer readable storage medium storing instructions, when the instructions are executed on a computer, causing the computer to execute the method of the first aspect and the possible implementation manners of the first aspect.

[0033] In a seventh aspect, the present application provides a computer program product comprising instructions, when the instructions are executed on a computer, causing the computer to execute the method of the first aspect and the possible implementation manners of the first aspect.

[0034] On the basis of the implementation manners of the above aspects, the present application can be further combined to provide more implementation manners. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 A schematic diagram of a system architecture provided by the present application;

[0036] Figure 2 A schematic diagram of a data processing method provided by the present application;

[0037] Figure 3 A schematic diagram of a method for determining target data provided by the present application;

[0038] Figure 4A A schematic diagram of direct memory access and access node tracing provided by the present application;

[0039] Figure 4B A schematic diagram of indirect memory access and access node tracing provided by the present application;

[0040] Figure 5 A schematic diagram of a data processing apparatus provided by the present application;

[0041] Figure 6 A schematic diagram of a computing device provided by the present application. DETAILED DESCRIPTION

[0042] Before the data processing method provided in the present application is described, some concepts involved in the present application are described first.

[0043] (1) Source code, executable code.

[0044] The source code is a text file written by a programmer. The programmer writes the code as source code in a human-readable language, such as Java, C++, C#, and the like. The source code is written according to the conventions and rules of a certain specific language. The source code is human-readable, but machines (such as processors) cannot recognize it.

[0045] The executable code is machine-recognizable and executable by the machine, and contains machine-recognizable binary instructions. The compiler can convert the source code into executable code.

[0046] (2) Performance monitoring unit (PMU).

[0047] The PMU is a hardware device, and the PMU is mainly used to track and count some underlying hardware events of the system, such as processor-related events (such as the number of executions of each instruction, the number of processor-captured exception conditions, the number of processor clock cycles, etc.), cache-related events (such as the number of times each level of cache in the cache is accessed, the number of misses in the cache, etc.). These events can represent the behavior of the processor in the process of executing the executable code.

[0048] In the present application, the processor (such as the compiler in the processor) can analyze the execution process of the executable code containing the extended instruction by means of the events collected by the PMU, such as the processor can analyze the branch probability of each branch in the function, and can also determine the degree of reuse of the target data in the process of executing the executable code. The processor can adjust the key loop sequence of the function according to the branch probability obtained by the analysis, and the processor can also update the target data according to the degree of reuse of the data, remove some data with low degree of reuse from the target data, or add some data with high degree of reuse.

[0049] (3) Function, loop.

[0050] The source code needs to meet certain writing specifications during writing, such as object-oriented programming (OOP), procedure-oriented programming (POP), and the like. The program languages of the object-oriented programming include C++, Java, C#, and the like, and the program languages of the procedure-oriented programming include fortran, C, and the like.

[0051] The source code written according to certain writing specifications can include code elements such as functions / methods and fields / variables.

[0052] A function / method refers to a subprogram in a class. A method is usually composed of a series of statements and can complete a function. In the writing specification of object-oriented programming, it is referred to as a method, and in the writing specification of procedure-oriented programming, it is referred to as a function. In the embodiments of the present application, it is collectively referred to as a “function”.

[0053] A loop is a type of program that can be included in a function. A loop refers to a program that needs to be executed multiple times when a condition is met, and the loop can be exited when the condition is not met.

[0054] A field / variable stores some data, such as integers and characters, strings, hash tables, pointers, and the like. The field / variable can be used as the target data mentioned in the embodiments of the present application.

[0055] (4) Memory access instruction, memory access node.

[0056] A memory access node refers to an operation of data access or storage in the source code. The memory access node includes a base address and an index. The memory access node can be represented as [A, index], where A represents the base address, which is the address used for storing data, and index indicates the index, which is used to represent the position of the data to be accessed or stored in the base address.

[0057] A memory access instruction refers to an instruction including a memory access node. There are many types of memory access instructions. Here, one of them is listed. For example, in the assignment instruction, the data at the position indicated by the index I in the base address A is assigned to the variable P. In the execution of the assignment instruction, the data at the position indicated by the index I in the base address A needs to be read to determine the value of the variable P. The memory access nodes included in the memory access instructions with different semantics are different, and the number of the memory access nodes included is also different.

[0058] (5) Basic block.

[0059] For any function, the compiler splits the function into a plurality of independent instruction sets according to preset standards. Any independent instruction set is a basic block. The first executed basic block in a function is the entry basic block of the function, and the last executed basic block is the exit basic block of the function. The first executed basic block in a loop is the head basic block of the loop.

[0060] (6) Branch, branch probability.

[0061] A function has a position at which a plurality of execution paths can be jumped to. The position is usually where a statement with a judgment condition, such as an if statement, a while statement, an else statement, etc., is located. When the position is executed, only one of the plurality of execution paths can be executed each time. Any execution path can be referred to as a branch. The probability of execution of any branch is referred to as the branch probability. The branch probability is related to the statement with a judgment condition at the position. In this application, the compiler can analyze the specific semantics of the statement with a judgment condition at the position to estimate the branch probability of each branch. For example, the value range of x is an integer from 1 to 10, and if the statement with a judgment condition at the position is if x>8, it can be shown that the position will be divided into two branches, one branch is x>8 branch, and one branch is x<8 branch, based on the value range of x, the branch probability of x>8 branch is 20%, and the branch probability of x<8 branch is 80%.

[0062] The data processing method provided by the present application will be further described below in combination with the accompanying drawings.

[0063] In order to improve the effectiveness of the data residing in the cache 200, the present application provides a data processing method. The processor 100 can analyze the source code to determine the target data, which is the data that needs to be frequently called in the execution process of the executable code corresponding to the source code. The processor 100 can insert an extension instruction for the target data in the source code, and the extension instruction is used to indicate that the target data is to be resided in the cache 200. The processor 100 compiles the source code with the inserted extension instruction into executable code and executes the executable code. When the processor 100 executes the executable code and executes the code corresponding to the extension instruction, the target data is obtained and stored in the cache 200. In this application, when the processor 100 executes the code corresponding to the extension instruction, the target data can be written into the cache 200 in advance to improve the data read-write efficiency of the processor 100.

[0064] As Figure 1As shown, a system structure provided by the present application includes a processor 100, a cache 200, and optionally a memory 300. The memory 300 can be understood as an internal memory of the processor 100. The processor 100 includes a compiler 110 and a PMU 120. The present application does not limit the specific form of the system, and the system can be a computer chip, such as a system on chip (SoC).

[0065] For the compiler 110, the compiler 110 can be a software program running on the processor 100, or a part of a hardware module of the processor 100. The PMU 120 can be a hardware module inside the processor 100.

[0066] Figure 1 As shown, the system structure is only one possible system structure. In some examples, the compiler 110 and the PMU 120 can be a hardware module or a software program independent of the processor 100 and outside the processor 100. In the embodiments of the present application, the compiler 110 and the PMU 120 are only taken as examples of the hardware module inside the processor 100. Figure 1 For the compiler 110 and the PMU 120 in the scenario independent of the processor 100, from the functional point of view, the processor 100, the compiler 110, and the PMU 120 are similar, and details are not described herein.

[0067] The present application does not limit the type of the processor 100, and any processor 100 capable of executing executable code is applicable to the embodiments of the present application. The processor 100 can be a central processing unit (CPU), a graphics processing unit (GPU), or the like. The processor 100 can also be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), which can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0068] In an embodiment of the present application, the cache 200 in the system comprises a multi-level cache, wherein the last level cache 210 in the multi-level cache can be a high bandwidth memory (HBM). The "multi-level cache" divides the cache 200 into multiple levels, and the cache level closer to the core of the processor 100 is smaller and faster in reading and writing, and has a relatively small capacity. That is, the last level cache 210 (LLC) in the multi-level cache is the cache farthest from the core of the processor 100 and has the largest capacity in the multi-level cache. The LLC 210 can be used to cache data exchanged between the processor 100 and the memory by the cache 200. From the perspective of the processor 100, the LLC can be understood as the cache of the processor 100. From the perspective of the memory, the LLC can also be used as the cache of the memory.

[0069] Compared with the case where a static random-access memory (SRAM) is used as the last level cache 210, the HBM supports large-capacity data storage and can effectively expand the capacity of the cache 200. The HBM also has higher bandwidth and can effectively improve the data reading and writing rate of the cache 200, and is more suitable for concurrent access scenarios.

[0070] The compiler 110 can be a software program running on the processor 100 or a hardware module of the processor 100, or a software program running on another processor 100 or a hardware module of the processor 100. The compiler 110 has a compiling capability and can compile source code required to be executed by the processor 100 into executable code recognizable by the processor 100. In the present application, the compiler 110 has an analyzing capability and can determine target data frequently called by the source code by analyzing the source code, and an extension instruction in the source code for the target data, the extension instruction being used to indicate that the target data needs to reside in the LLC. Then, the compiler 110 compiles the source code with the inserted extension instruction to generate executable code required to be executed by the processor 100.

[0071] It should be noted that the case of using the extension instruction to indicate that the target data needs to reside in the LLC 210 is taken as an example, and in some scenarios, the extension instruction can also indicate that the target data resides in other levels of the cache 200.

[0072] The processor 100 can obtain the executable code compiled by the compiler 110 and execute the executable code. In the process of executing the executable code, the processor 100 can migrate the data to be processed from the memory 300 to the cache 200, and also store the processed data in the cache 200. When the processor 100 executes the code corresponding to the extended instruction in the executable code, the processor 100 can initiate a resident instruction to the LLC, and the resident instruction is used to instruct the LLC to store the target data.

[0073] In the process of executing the executable code by the processor 100, the PMU 120 can monitor the process, record the events related to the processor 100 (especially the events in the process of executing the executable code by the processor 100), and the events related to the cache 200.

[0074] The compiler 110 can call the events recorded by the PMU 120, update the determined target data, add the extended instruction in the source code for the updated target data, and compile to generate a new executable code. The processor 100 can obtain the new executable code and execute the new executable code.

[0075] The memory 300 is usually used to store the computer program code and the like required to be executed by the processor 100. In the embodiment of the present application, the memory 300 can be used to store the executable code of the compiler 110, and the processor 100 can run the compiler 110 by calling the executable code. The memory 300 can also store the source code required to be compiled by the compiler 110, and the compiler 110 can call the source code from the memory 300 to analyze and compile the source code. The memory 300 can also store the executable code generated after the source code is compiled. The compiler 110 can store the executable code in the memory 300 after the executable code is compiled, and the processor 100 can call the executable code and execute the executable code.

[0076] The memory 300 is usually a dynamic random access memory (DRAM) as the memory 300. In addition to the DRAM, the memory 300 can also be other random access memories, such as SRAM, etc. In addition, the memory 300 can also be a read only memory (ROM). For the read only memory, for example, it can be a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), etc. The memory 300 can also be a dual in-line memory module (DIMM), i.e., a module composed of dynamic random access memories (DRAM), and can also be a solid state disk (SSD). The memory 300 can also be a combination of the above memories, and the number and type of the memory 300 are not limited by the embodiments of the present application.

[0077] In the above description, the target data is obtained by the compiler 110 by analyzing the loop in the function in the source code, and the target data can be part of the data that needs to be called in the running process of the function in the source code. In actual application, the programmer can mark some frequently called data in the process of writing the source code. The compiler 110 can recognize the mark and take the data with the mark as the target data.

[0078] Different from the compiler 110 with only compiling capability, the compiler 110 provided in the embodiments of the present application has analyzing capability and can determine the target data. The compiler 110 also has the capability of inserting the extension instruction and can compile the extension instruction. Due to the existence of the compiler 110, the executable code required to be executed by the processor 100 is increased with the code (code corresponding to the extension instruction) indicating that the target data resides in the cache 200, so that the processor 100 can write the target data into the cache 200 in advance, avoiding the processor 100 from reading the target data from the memory multiple times, and improving the data reading rate. In addition, the compiler 110 can also update the target data and generate new executable code. The updated target data is more consistent with the actual situation of the processor 100 executing the executable code. In the process of executing the new executable code, the processor 100 can also write the data that is really frequently called into the cache 200 in advance, further ensuring the data reading rate of the processor 100.

[0079] The following describes Figure 2 A data processing method is provided in the present application, which comprises the following steps:

[0080] Step 201: The processor 100 acquires the source code. The processor 100 can acquire the source code to be compiled from the memory 300.

[0081] Step 202: The processor 100 analyzes the source code and determines the target data. The target data is the data frequently called in the execution process of the executable code compiled from the source code, and the data whose reuse score is greater than a threshold value. The reuse score of the data is used to represent the reuse degree of the data.

[0082] Steps 201-202 can be executed by the compiler 110 in the processor 100, and the following description is based on the processor 100 executing steps 201-202.

[0083] The present application provides two ways to determine the target data, which are described as follows:

[0084] Method one: identifying the data with annotations in the source code.

[0085] The source code is written by a programmer using a human-readable language, and the programmer or other personnel can understand the meaning of the source code and determine the data frequently called in the source code by understanding the source code. Therefore, the programmer or other personnel can determine the frequently called data according to their understanding of the source code and annotate the data. For example, the programmer or other personnel can add annotations before or after the data to indicate that the data is frequently called when the data is first introduced. The annotations are set in a format agreed in advance with the processor 100.

[0086] When analyzing the source code, the processor 100 can identify the data with annotations and take the data with annotations as the target data.

[0087] Method two: analyzing the source code to determine the target data.

[0088] When executing the executable code generated from the source code, the processor 100 executes the executable code according to the logic of the source code. The data frequently called in the source code is usually the data involved in the loop. The loop is a section of code that can be included in a function. When executing the loop, the processor 100 will execute the loop multiple times until the loop condition is not met, and will call out the loop and execute the relevant code after the loop when the loop condition is not met.

[0089] Since the loop can be executed multiple times, the data called in the loop can be target data. Therefore, the processor 100 can analyze the source code to determine the loops included in the source code. The target data is determined according to the data called in the loop.

[0090] The processor 100 can directly take the data called in each loop as target data, or the processor 100 can analyze the loop to determine a target loop whose loop times or times of calling data in the loop are greater than a threshold, and take the data called in the target loop as target data. In this case, the loop times or times of calling data in the loop of the target loop represent the degree of multiplexing of the target data, that is, the loop times or times of calling data in the loop of the target loop can be taken as a multiplexing score of the data, and the data involved in the target loop is selected as the target data.

[0091] The embodiments of the present application do not limit the way in which the processor 100 determines the target data according to the data called in each loop in the source code, and any way that can determine the target data according to the data called in each loop in the source code is applicable to the embodiments of the present application.

[0092] For mode 2, as shown in Figure 3 The present application provides a way to determine target data, which can be specifically seen from the following steps:

[0093] Step 2021: The processor 100 screens a key loop from the source code. The key loop refers to a loop that meets a first screening condition, and the first screening condition includes part or all of the following: the number of nodes accessed in the loop is greater than a node threshold, and the proportion of instructions accessing the loop in all instructions in the loop is greater than a proportion threshold. The node threshold and the proportion threshold can be pre-set.

[0094] When performing step 2021, the processor 100 can screen the source code from different granularities in turn.

[0095] First, the processor 100 can screen the source code from the function granularity, remove complex functions and some functions that are executed only once in the source code, and find a first candidate function from the source code. The first candidate function meets part or all of the following:

[0096] 1. The function includes a loop.

[0097] 2. The function is not a library function.

[0098] 3. No new operation is defined in the function.

[0099] Afterwards, the processor 100 further screens the first candidate functions from the granularity of the loops, removes the loops including multiple branches or the functions requiring cooperation with other data (such as files or functions) outside the functions, and screens out second candidate functions. The second candidate functions satisfy some or all of the following:

[0100] 1. The loop in the function only includes a single exit edge.

[0101] 2. The loop in the function does not involve multiple branches.

[0102] 3. The loop in the function is not a loop defined by a macro.

[0103] 4. The loop in the function does not call files other than the source code.

[0104] 5. The loop in the function does not call other functions.

[0105] 6. The loop in the function does not call the custom operations in the function.

[0106] Finally, the processor 100 can determine the number of memory access nodes included in the loop in the second candidate function and the proportion of access instructions to all instructions in the loop from the second candidate function, and then determine the key loop satisfying the screening condition.

[0107] It should be noted that in some source codes, there are nested loops, for example, loop A also includes loop B inside, for example, loop C also includes loop D inside, and loop D also includes loop E inside. Since the innermost loop (such as loop B and loop D) is the loop with the most execution times, the processor 100 can only consider the innermost loop when screening the key loop. That is, the key loop is the innermost loop. Of course, the processor 100 can also consider the outer loop when screening the key loop, that is, the key loop can be the innermost loop or the outer loop.

[0108] Step 2022: The processor 100 determines the key loop sequence of each function in the source code. The key loop sequence of a function includes at least one key loop of the function, and the at least one key loop in the key loop sequence of the function can be sorted according to the execution order.

[0109] In step 2022, the processor 100 determines the key loop. The processor 100 can analyze each function in the source code, determine a target function including the key loop, arrange each key loop in the target function according to the execution order to generate the key loop sequence of the function.

[0110] It should be noted that when there are multiple branches in the function, the critical loops of the function are distributed on the multiple branches, and the processor 100 can select the critical loops distributed on the branch with the highest branch probability in the multiple branches, sort the critical loops according to the execution order on the branch, and generate the critical loop sequence of the function. That is, the critical loop sequence of the function is the critical loop sequence of the branch with the highest branch probability in the function, and the critical loop in the critical loop sequence of the branch is the critical loop on the branch.

[0111] The processor 100 can also sort the critical loops on each branch according to the execution order of the branch, generate the critical loop sequence of each branch, and the processor 100 combines the critical loop sequence of each branch to generate the critical loop sequence of the function. That is, the critical loop sequence of the function includes the critical loop sequence of each branch.

[0112] The present application provides a method for obtaining the critical loop sequence of a function, and the specific method is as follows:

[0113] For any function, the processor 100 can traverse the function in the granularity of basic blocks to obtain the critical loop sequence of the function. The processor 100 can also traverse the function starting from the entry basic block of the source code in the granularity of basic blocks until the exit basic block of the function. The processor 100 can perform the following steps after traversing each basic block:

[0114] Step 1, determine whether the basic block is the head basic block of a loop. If yes, perform step 2, otherwise perform step 5.

[0115] Step 2, determine whether the loop has not been traversed. If yes, perform step 3, otherwise perform step 5.

[0116] Step 3, determine whether the loop is a critical loop. If yes, perform step 4, otherwise perform step 5.

[0117] Step 4, add the loop to the critical loop sequence and mark the loop as having been traversed.

[0118] Step 5, end the traversal of the basic block, extract the next basic block, and perform step 1.

[0119] It should be noted that when step 5 is performed, if the function includes multiple branches, the next basic block can be selected from the basic block on the branch with the highest branch probability.

[0120] The processor 100 (specifically, the compiler in the processor) repeatedly performs steps 1-5 above, and after traversing from the entry basic block to the exit basic block, the critical loop sequence of the function can be generated.

[0121] Step 2023: For any function of the key loop sequence, the processor 100 traces the memory access node of the memory access instruction of each key loop of the key loop sequence, and determines the data corresponding to the memory access node. The data corresponding to the memory access node is the data stored on the base address of the memory access node.

[0122] Step 2024: The processor 100 calculates the reuse score of the data corresponding to each memory access node. The processor 100 can calculate the reuse score of the data corresponding to each memory access node according to the calling mode of the data corresponding to each memory access node.

[0123] The calling mode of the data corresponding to the memory access node describes the mode adopted when the data is called. The calling mode includes but is not limited to: data reuse mode, memory access mode indicated by the memory access node, and read-write mode of the data.

[0124] 1) Data reuse mode.

[0125] The data reuse mode refers to the execution relationship between multiple calls of the data.

[0126] When the executable code corresponding to the source code is executed, the data can be called at the same time. Such a call is usually characterized by a parallel computing guide in the source code. The data called after such a parallel computing guide is the data that needs to be reused in parallel. Accordingly, this data reuse mode is a parallel reuse mode. Of course, the call of the data can also be sequential. Such a data call reuse mode is a serial reuse mode.

[0127] Different data reuse modes can have different reuse times of the data. The reuse time of the data indicates the number of times the data is called.

[0128] 2) Memory access mode indicated by the memory access node.

[0129] The memory access mode indicated by the memory access node includes direct memory access and indirect memory access. The direct memory access refers to the index in the memory access node being directly indicated, i.e., the index part in the memory access node being the specific value of the index.

[0130] To facilitate understanding of the memory access mode indicated by the memory access node, the following will be described in conjunction with Figure 4A and Figure 4B .

[0131] As shown in Figure 4A , it is a schematic diagram of direct memory access and memory access node tracing provided by the present application. Figure 4A The source code shown in Figure 4AThe tree structure on the left describes the relationship of the 5 instructions, where the arrow indicates the trace direction. The number in the node of the tree structure represents the number of the instruction, and the character under the number is used to indicate the type of the instruction. Among them, load represents the load instruction, addr represents the data on the address, add represents the addition instruction, mult represents the multiplication instruction, and conv represents the conversion instruction. The u in the node is used to represent the variable u appearing in instruction 3.

[0132] The instruction numbered 4 is a memory access instruction, which carries a memory access node, which is the part represented in "[]". The part after base is the base address. The part after index is the index. The memory access node directly indicates the index and the base address, which is direct memory access.

[0133] Indirect memory access refers to that the index in the memory access node is indirectly indicated, that is, the index part in the memory access node is not a specific value, but needs to be further resolved.

[0134] As shown in Figure 4B , a trace diagram of indirect memory access and access node is provided. Figure 4B The source code including 5 instructions is shown in the figure. Each line of code is an instruction, and the number before each line of code is the number of the instruction. Figure 4B The tree structure on the left describes the relationship of the 5 instructions, where the arrow indicates the trace direction. The number in the node of the tree structure represents the number of the instruction, and the character under the number is used to indicate the type of the instruction. Among them, addr represents the data on the address, add represents the addition instruction, mult represents the multiplication instruction, and conv represents the conversion instruction. The u in the node is used to represent the variable u appearing in instruction 3.

[0135] The instruction numbered 5 is a memory access instruction, which carries a memory access node, which is the part represented in "[]". The part inside [] does not directly indicate the base address and the index, and needs to be further resolved, which is indirect memory access.

[0136] 3), the data read-write mode.

[0137] The data read-write mode indicates writing data or reading data. It is generally considered that the power consumption when writing data is greater than that when reading data.

[0138] The reuse score Level of any data x can be calculated by the following formula:

[0139] Level = parallel (x) * (reuse (x) + regular (x) + cost (x))

[0140] Here, `parallel(x)` represents whether data `x` is multiplexed in parallel or serially. Parallel and serial multiplexing take different values, and the value for parallel multiplexing can be greater than the value for serial multiplexing. `reuse(x)` indicates the number of times data `x` is serially multiplexed. `regular(x)` represents the memory access method of the data; direct memory access and indirect memory access can correspond to different values ​​of `regular(x)`. `cost(x)` indicates the read / write method of the data; writing data or reading data can correspond to different values ​​of `cost(x)`.

[0141] The reuse score of the data corresponding to each memory access node represents the degree of data reuse. The greater the degree of reuse, the more times the data is accessed, and correspondingly, the higher the data reuse score.

[0142] Step 2025: The processor 100 reuses the N data with the highest scores as target data, where N is a preset positive integer.

[0143] Step 203: Processor 100 inserts an extension instruction at the location in the source code where the target data is first called. This extension instruction is used to instruct the processor to keep the target data residing in the LLC.

[0144] The first call to the target data can be located on the adjacent line or a few lines before or after the code that first calls the target data in the source code. For example, the first call to the target data can be located before the code that first calls the target data, such as the line before the code that first calls the target data, or the first K lines, where K is a positive integer. Alternatively, the first call to the target data can be located after the code that first introduces the target data, such as the line after the code that first calls the target data, or the next K lines, where K is a positive integer.

[0145] Step 204: The processor 100 compiles the source code containing the inserted extended instructions to generate executable code that includes the code corresponding to the extended instructions. After generating the executable code, the processor 100 can store the executable code in the memory 300.

[0146] In this embodiment, the processor 100 has the capability to compile extended instructions into machine-readable assembly instructions. The processor 100 can compile the instructions in the source code containing the inserted extended instructions to generate executable code.

[0147] Step 205: The processor 100 executes the executable code. When the processor 100 executes the code corresponding to the extended instruction (that is, when it executes the assembly instruction corresponding to the extended instruction), the processor 100 can send a resident instruction to the LLC210. ​​The resident instruction is used to instruct the LLC210 to store the target data.

[0148] If the executable code is stored in the memory 300, the processor 100 can first acquire the executable code from the memory 300, and execute the executable code after acquiring the executable code.

[0149] Step 206: After receiving the residence instruction, the LLC 210 acquires the target data (e.g., the LLC 210 can acquire the data from the memory), and stores the target data.

[0150] That is, the processor 100 executes step 205 for any target data, so that the data in the LLC 210 can be divided into two categories, one category is the target data indicated by the residence instruction, and the other category is other data.

[0151] In order to further improve the storage time (i.e., residence time) of the target data in the LLC 210, the LLC 210 can be configured with a data replacement policy, which indicates that when it is necessary to evict data in the LLC 210 (e.g., the free space in the LLC 210 is less than a threshold), the data other than the target data is preferentially evicted.

[0152] Embodiments of the present application do not limit the manner in which the LLC 210 executes the data replacement policy, and two possible execution manners are listed below.

[0153] Manner one: In the LLC 210, the LLC 210 can be capable of setting the type of data, the first type of data is the target data indicated by the residence instruction, and the second type of data is other data. For example, the LLC 210 can set the type of data indicated by the residence instruction as the first type when receiving the residence instruction. Other data is correspondingly set as the second type.

[0154] The LLC 210 can also set the residence value for different types of data, and the residence value has a preset value range, i.e., the maximum value and the minimum value of the residence value are determined. The residence value of the first type of data takes the minimum value.

[0155] Initially, the residence value of the second type of data can be set to a value greater than the residence value of the first type of data, or can be set to the minimum value. The present application does not limit the specific value of the residence value of the second type of data, and the residence values of different second types of data can be the same or different.

[0156] When there is no free space or the free space is less than a threshold in the LLC 210, and it is impossible to continue to store new data, the LLC 210 can evict the stored data, and the LLC 210 can preferentially evict the data whose residence value is equal to the maximum value.

[0157] If there is no data in the LLC 210 with the residence value equal to the maximum value, the LLC 210 can increase the residence value of the second type of data and remove the data with the residence value equal to the maximum value. If there is still no data in the LLC 210 with the residence value equal to the maximum value after the residence value of the second type of data is increased, the LLC 210 can continue to increase the residence value of the second type of data.

[0158] Method two: In the LLC 210, the LLC 210 can be able to set the type of data, the first type of data being the target data indicated by the residence instruction, and the second type of data being other data. For example, the LLC 210 can set the type of data indicated by the residence instruction as the first type when receiving the residence instruction. Other data is correspondingly set as the second type.

[0159] The LLC 210 can also set the residence value for different types of data, and the residence value has a preset value range, that is, the maximum value and the minimum value of the residence value are determined. The residence value of the first type of data takes the minimum value.

[0160] The LLC 210 can also set a count value, which is used to record the number of times the LLC 210 modifies the residence value of the second type of data. Each time the residence value of the second type of data is modified, the count value is incremented by one.

[0161] Initially, the residence value of the second type of data can be set to a value greater than the residence value of the first type of data, or can be set to the minimum value. The present application does not limit the specific value of the residence value of the second type of data. Different residence values of the second type of data can be the same or different.

[0162] When there is no free space in the LLC 210 or the free space is less than a threshold value, and the LLC 210 cannot continue to store new data, the LLC 210 can remove the stored data. The LLC 210 can preferentially remove the data with the residence value equal to the maximum value.

[0163] If there is no data in the LLC 210 with the residence value equal to the maximum value, the LLC 210 can first determine whether the count value is greater than a set value. If the count value is not greater than the set value, the LLC 210 can increase the residence value of the second type of data, increment the count value, and remove the data with the residence value equal to the maximum value. If the count value is greater than the set value, the LLC 210 can uniformly increase the residence value of the first type of data and remove the data with the residence value equal to the maximum value.

[0164] If the LLC 210 still does not have data with the maximum residence value after increasing the residence value of the second type or the data of the second type, the LLC 210 can continue to perform the foregoing operation, i.e., determine whether the count value is greater than the set value. If the count value is not greater than the set value, the LLC 210 can increase the residence value of the data of the second type, increase the count value by one, and discard the data with the maximum residence value. If the count value is greater than the set value, the LLC 210 can uniformly increase the residence value of the data of the first type and discard the data with the residence value equal to the maximum value.

[0165] In the embodiment of the present application, the processor 100 can also update the target data, such as increasing the target data or decreasing the target data. The processor 100 can insert an extended instruction for the updated target data in the source code and compile to generate a new executable code. The processor 100 executes the new executable code. The processor 100 can update the target data in the manner of step 206.

[0166] Step 207: The processor 100 acquires the events recorded by the PMU 120 and updates the target data according to the events recorded by the PMU 120.

[0167] The processor 100 can analyze the branch probabilities of each branch in the source code function according to the events recorded by the PMU 120, such as the execution times of each instruction and the events of cache 200 missing data. For example, the events recorded by the PMU 120 include the events of the cache 200 missing data. When the data is not hit in the cache 200, the branch calling the data will not be executed, which indicates that the branch probabilities of each branch when actually executing the executable code will be different from the branch probabilities obtained by analyzing the source code. The events recorded by the PMU 120 include the execution times of each instruction, and the execution times of the instructions in different branches can indicate the execution times of each branch, and further determine the branch probabilities of each branch.

[0168] The processor 100 can determine the branch probabilities of each branch when actually executing the executable code through the events recorded by the PMU 120. The processor 100 can regenerate the critical loop sequence of the function according to the determined branch probabilities of each branch (the scenario suitable for the critical loop sequence of the function is the critical loop sequence of the branch with the maximum branch probability in the function).

[0169] In addition, the processor 100 can also refer to the events recorded by the PMU 120 when calculating the multiplexing score of the data. For example, when the events recorded by the PMU 120 and related to the cache 200 show that a certain data is missed in the cache 200 for multiple times, it indicates that the multiplexing degree of the data is high, and the processor 100 can increase the multiplexing score of the data. Specifically, the processor 100 can add a weight value related to the events recorded by the PMU 120 and related to the cache 200 in the calculation formula of the multiplexing score of the data. When the number of times that the events recorded by the PMU 120 and related to the cache 200 show that a certain data is missed in the cache 200 is greater than a certain specific value, the weight value can be changed to a larger value to increase the multiplexing score of the data.

[0170] Step 208: The processor 100 inserts an extension instruction at the position related to the target data after the first update. The extension instruction is used to indicate that the updated target data is resident in the LLC. The processor 100 performs step 207 in a manner similar to that of step 203, and details can be referred to the foregoing description, which will not be repeated here.

[0171] Step 209: The processor 100 compiles the source code with the inserted extension instruction to generate executable code including the code corresponding to the extension instruction. The processor 100 performs step 208 in a manner similar to that of step 204, and details can be referred to the foregoing description, which will not be repeated here. Then, the processor 100 can send the executable code to the processor 100, and the processor 100 executes the new executable code. The processor 100 executes the executable code in a manner as described in steps 205-206, and details will not be repeated here.

[0172] In the present application, the processor 100 can analyze the source code and determine the target data that the processor 100 will frequently call in the process of executing the executable code. The target data determined from the source code itself is more accurate, which is the data that the processor 100 will frequently call in a true sense. After the processor 100 determines the target data, the processor 100 can insert an extension instruction that normalizes the target data in the source code, and then compile the source code to generate executable code. In this way, the executable code includes the code corresponding to the extension instruction. When the processor 100 executes the code corresponding to the extension instruction in the process of executing the executable code, the processor 100 can obtain the target data according to the extension instruction and store the target data in the cache 200. In this way, the target data can be stored in the cache 200 in advance, so that the processor 100 does not need to call the target data from the memory when the target data needs to be called. The data read / write rate of the processor 100 is effectively improved. In addition, since the processor 100 can update the target data according to the events recorded by the PMU 120 in the process of executing the executable code, and then update the executable code, the accuracy of the target data is improved. The target data that the processor 100 will frequently call can be stored in the cache 200, and the data read / write rate of the processor 100 is further improved.

[0173] Based on the same inventive concept as the method embodiment, the present application also provides a data processing apparatus for executing the method performed by the processor 100 in the method examples as shown in Figure 2 or Figure 3 The related features can be referred to the above method examples, which will not be described here. As shown in Figure 5 The data processing apparatus 500 includes a compilation module 501 and an execution module 502.

[0174] The compilation module 501 is configured to obtain executable code, the executable code including code corresponding to a first extension instruction, the first extension instruction being used to indicate that target data needs to be resident in a cache, the target data being data that needs to be called multiple times in the process of executing the executable code. The first extension instruction is for the extension instruction mentioned in the embodiments as shown in Figure 2 .

[0175] The execution module 502 is configured to execute the code corresponding to the first extension instruction in the executable code, obtain the target data, and store the target data in the cache.

[0176] It should be understood that the data processing apparatus 500 of the embodiments of the present application can be implemented by a central processing unit (CPU), or by an application-specific integrated circuit (ASIC), or by a programmable logic device (PLD), which can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a data processing unit (DPU), a system on chip (SoC), or any combination thereof. It can also be implemented by software Figure 2 or Figure 3 When the data processing method shown in the figure is implemented by software, the apparatus 500 and each module thereof can also be software modules.

[0177] In a possible implementation, when the compiling module 501 obtains the executable code, it can analyze the source code to determine target data, and the reuse score of the target data is greater than a threshold value, the reuse score of the target data being used to indicate the reuse degree of the target data. The compiling module 501 inserts a first extension instruction in the source code, and compiles the source code in which the first extension instruction is inserted to generate the executable code.

[0178] In a possible implementation, when the executing module 502 obtains the target data and stores the target data in the cache, it sends a residence instruction to the cache, the residence instruction being used to indicate that the target data is stored in the cache. In this way, after receiving the residence instruction, the cache obtains the target data and stores the target data according to the residence instruction.

[0179] In a possible implementation, the LLC of the cache is HBM, and the first extension instruction indicates that the target data resides in the LLC.

[0180] In a possible implementation, the compiling module 501 can update the target data, and further update the executable code. The compiling module 501 obtains an event recorded by a PMU. The compiling module 501 updates the target data according to the event recorded by the PMU. The compiling module 501 recompiles the source code in which a second extension instruction is inserted to generate the executable code, the second extension instruction being used to indicate that the updated target data needs to reside in the cache. The second extension instruction corresponds to the first extension instruction. Figure 2The extension instruction is directed to the updated target data. The execution module 502 executes the recompiled executable code.

[0181] In a possible implementation, the compiling module 501 inserts the first extension instruction in the source code at a first call of the adjacent line of the target data in the source code.

[0182] In a possible implementation, the compiling module 501 analyzes the source code to determine the target data, and determines a loop sequence of each function in the source code, the loop sequence of the function including at least one loop in the function. For the loop sequence of any function, the compiling module 501 calculates a reuse score of data corresponding to an access node included in the loop in the loop sequence of the function, the reuse score indicating a reuse degree of the data in the source code; and the compiling module 501 determines the target data according to the reuse score of the data corresponding to the access node.

[0183] It should be noted that the division of the modules in the embodiments of the present application is illustrative, and is merely a logical function division. In actual implementation, another division manner can be used. The function modules in the embodiments of the present application can be integrated in one processing module, or each module can be physically present alone, or two or more modules can be integrated in one module. The integrated module can be implemented in the form of hardware or in the form of a software function module.

[0184] The present application also provides a computing device. As shown in Figure 6 FIG. 1 is a structural schematic diagram of the computing device, and the computing device 10 includes a processor 100, a cache 200, a memory 300, a bus 400, and a communication interface 600. The processor 100, the cache 200, the memory 300, and the communication interface 600 communicate through the bus 400. The bus 400 can be a line based on a peripheral component interconnect express (PCIe) standard, or can be another type of bus.

[0185] The processor 100, the cache 200, and the memory 300 are described above, and will not be described herein again.

[0186] The present application also provides a processor, which includes a logic circuit and a power supply circuit, the power supply circuit being configured to supply power to the logic circuit, and the logic circuit being configured to execute Figure 2 or Figure 3 the operation steps of the method implemented by the processor in the method examples described in the foregoing

[0187] The application further provides a chip connected with the memory, the chip comprising a processor and a cache, the processor being configured to read and execute computer program codes stored in the memory, Figure 2 or Figure 3 the operation steps of the method implemented by the processor in the method examples described in the above embodiments. For brevity, the above will not be repeated here.

[0188] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer program instructions. When the computer program instructions are loaded or executed on a computer, the above-mentioned processes or functions are generated in whole or in part according to the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer program instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. containing one or more available medium sets. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0189] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes.

[0190] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0191] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0192] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0193] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the claims and their equivalents, the application can be practiced otherwise than as specifically described.

[0194] The above description is only specific implementation of the present application. Those skilled in the art can make changes or replacements according to the specific implementation provided by the present application, and all changes or replacements should be covered within the protection scope of the present application.

Claims

1. A data processing method, characterized in that, include: The processor analyzes the source code to determine target data, which is data that needs to be frequently called during the execution of the executable code corresponding to the source code. The determination of the target data is related to at least two of the following factors: data reuse method, data memory access method, and data read / write method. Alternatively, the determination of the target data is related to the data reuse method or the data memory access method. The data reuse method includes parallel reuse method or serial reuse method. The data memory access method includes direct memory access or indirect memory access. The data read / write method indicates writing data or reading data. The processor inserts a first extension instruction into the source code and compiles the executable code based on the source code with the first extension instruction inserted; the first extension instruction is used to indicate that the target data needs to reside in the cache; The processor executes the code corresponding to the first extended instruction, obtains the target data, and stores the target data in the cache.

2. The method as described in claim 1, characterized in that, The reuse score of the target data is greater than the threshold, and the reuse score of the target data is used to indicate the degree of reuse of the target data.

3. The method as described in claim 1 or 2, characterized in that, The processor acquires the target data and stores the target data in the cache, including: A residency instruction is sent to the cache, the residency instruction being used to instruct the target data to be stored in the cache, so as to instruct the cache to retrieve the target data and store the target data according to the residency instruction.

4. The method as described in claim 1 or 2, characterized in that, The last-level cache LLC of the cache is a high-bandwidth memory (HBM), and the first extended instruction indicates that the target data resides in the LLC.

5. The method as described in claim 1 or 2, characterized in that, The method further includes: When the free space in the cache is less than a threshold, the cache is cleaned up of all data except the target data.

6. The method as described in claim 1 or 2, characterized in that, The method further includes: Retrieve events recorded by the Performance Monitoring Unit (PMU); Update the target data based on the event; After inserting a second extension instruction into the source code, the executable code is recompiled and executed. The second extension instruction is used to indicate that the updated target data should reside in the cache.

7. The method as described in claim 1 or 2, characterized in that, The processor inserts a first extended instruction into the source code, including: The first extended instruction is inserted in the line adjacent to the code that first calls the target data in the source code.

8. The method as described in claim 1 or 2, characterized in that, The processor analyzes the source code to determine the target data, including: Determine the loop sequence of each function in the source code, wherein the loop sequence of the function includes at least one loop of the function; For any loop sequence of a function, calculate the reuse score of the data corresponding to the access nodes included in each loop of the loop sequence of the function; The target data is determined based on the reuse score of the data corresponding to the access node.

9. A processor, characterized in that, The processor includes a logic circuit and a power supply circuit, the power supply circuit being used to supply power to the logic circuit, and the logic circuit being used to perform the operation steps of the method as described in any one of claims 1 to 8.

10. A chip, characterized in that, The chip includes a processor and a cache, the processor being configured to perform the operational steps of the method as described in any one of claims 1 to 8 to store the target data in the cache.

11. A computing device, characterized in that, The computing device includes a processor, a cache, and a memory, the memory being used to store computer program code, and the processor being used to perform the operational steps of the method as described in any one of claims 1 to 8.

12. A data processing apparatus, characterized in that, The device includes: A compilation module is used to analyze source code to determine target data. The target data is data that needs to be frequently accessed during the execution of the executable code corresponding to the source code. The determination of the target data is related to at least two of the following factors: data reuse method, data access method, and data read / write method. Alternatively, the determination of the target data is related to either the data reuse method or the data access method. The data reuse method includes parallel reuse or serial reuse; the data access method includes direct access or indirect access; and the data read / write method indicates writing or reading data. A first extension instruction is inserted into the source code, and the executable code is generated based on the source code with the inserted first extension instruction. The first extension instruction is used to indicate that the target data needs to reside in a cache. The execution module is used to execute the code corresponding to the first extended instruction in the executable code, obtain the target data, and store the target data in the cache.

13. The apparatus as claimed in claim 12, characterized in that, The reuse score of the target data is greater than the threshold, and the reuse score of the target data is used to indicate the degree of reuse of the target data.

14. The apparatus as claimed in claim 12 or 13, characterized in that, The execution module acquires the target data and stores it in the cache, for the following purposes: A residency instruction is sent to the cache, the residency instruction being used to instruct the target data to be stored in the cache, so as to instruct the cache to retrieve the target data and store the target data according to the residency instruction.

15. The apparatus as claimed in claim 12 or 13, characterized in that, The last-level cache LLC of the cache is a high-bandwidth memory (HBM), and the first extended instruction indicates that the target data resides in the LLC.

16. The apparatus as claimed in claim 12 or 13, characterized in that, The compilation module is further configured to: acquire events recorded by the performance monitoring unit (PMU); update the target data according to the events; and recompile to generate executable code after inserting a second extension instruction into the source code, wherein the second extension instruction is used to indicate that the updated target data should reside in the cache. The execution module is specifically used to execute the recompiled executable code.

17. The apparatus as claimed in claim 12 or 13, characterized in that, The compilation module inserts a first extension instruction into the source code for: The first extended instruction is inserted in the line adjacent to the code that first calls the target data in the source code.

18. The apparatus as claimed in claim 12 or 13, characterized in that, The compilation module analyzes the source code to determine the target data, which is used for: Determine the loop sequence of each function in the source code, wherein the loop sequence of the function includes at least one loop in the function; For any loop sequence of a function, calculate the reuse score of the data corresponding to the access nodes included in each loop of the loop sequence of the function, wherein the reuse score indicates the degree of reuse of the data in the source code; The target data is determined based on the reuse score of the data corresponding to the access node.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes instructions that, when executed on a computer, cause the computer to perform the operational steps of any one of the methods described in claims 1 to 8.

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