Storage system and computing system including the same

Abstract

A storage system and a computing system including the same are disclosed. The storage system includes: a first device connected to a host through an interface including a first switch and a second switch; and the second device is connected to the host through the interface. The first device comprises a first controller; a first memory; and a first shared memory including information on the first degradation of the first memory. The second device comprises a second controller; a second memory; and a second shared memory including information about a second degradation of the second memory, the second shared memory being accessible by the first controller through the first switch, and wherein the first controller is configured to: receive a command related to an operation of the first memory from a host, and, on the basis of identifying that the first degradation is higher than the second degradation, determine whether the first degradation is higher than the second degradation; the second controller is controlled instead of the first controller to execute the command.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0092308 filed on July 17, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The disclosure relates to storage systems and computing systems including storage systems. Background Art

[0003] With the development of technologies such as artificial intelligence (AI), big data, and edge computing, there is a need to process large amounts of data faster in electronic devices. That is, high-bandwidth applications that perform complex calculations require faster data processing and more efficient memory access.

[0004] However, because most host devices including computing units such as a central processing unit (CPU) and a graphics processing unit (GPU) are connected to a semiconductor device including a memory through, for example, a peripheral component interconnect express (PCIe) protocol, the host device has relatively low bandwidth and long latency, and thus problems with memory sharing and consistency with the semiconductor device occur. Summary of the invention

[0005] A storage system with improved reliability and a computing system with improved reliability are provided.

[0006] The aspects of the disclosure are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0007] According to one aspect of the disclosure, a storage system includes: a first CXL storage device configured to be connected to a host through a compute express link (CXL) interface including a first CXL switch and a second CXL switch; and a second CXL storage device configured to be connected to the host through the CXL interface, wherein the first CXL storage device includes: a first CXL storage controller; a first non-volatile memory controlled by the first CXL storage controller; and a first shared memory including information about a first degradation degree of the first non-volatile memory, wherein the second CXL storage device includes: a second CXL storage controller; a second non-volatile memory controlled by the second CXL storage controller; and a second shared memory including information about a second degradation degree of the second non-volatile memory, the second shared memory being accessible to the first CXL storage controller through the first CXL switch, and wherein the first CXL storage controller is configured to: receive a command related to an operation of the first non-volatile memory from the host, and based on recognizing that the first degradation degree is higher than the second degradation degree, control the second CXL storage controller to execute the command instead of the first CXL storage controller executing the command.

[0008] According to one aspect of the disclosure, a storage system includes: a first compute express link (CXL) storage device configured to be connected to a host through a CXL interface; and a second CXL storage device configured to be connected to the host through the CXL interface, wherein the first CXL storage device includes: a first CXL storage controller; a first non-volatile memory controlled by the first CXL storage controller; and a first shared memory including information about a first degradation degree of the first non-volatile memory, wherein the second CXL storage device includes: a second CXL storage controller; a second non-volatile memory controlled by the second CXL storage controller; and a second shared memory including information about a second degradation degree of the second non-volatile memory, the second shared memory being accessible to the first CXL storage controller through the CXL interface, and wherein the first CXL storage controller is configured to: receive a command related to an operation of the first non-volatile memory from the host, and control the second CXL storage controller to execute the command based on recognizing that the command is not processed in the first CXL storage device.

[0009] According to one aspect of the disclosure, a computing system includes: a host; and a storage system including a first compute fast link (CXL) storage device and a second CXL storage device, the first CXL storage device and the second CXL storage device being configured to be connected to the host through a CXL interface, wherein the first CXL storage device includes: a first CXL storage controller; a first non-volatile memory controlled by the first CXL storage controller; and a first shared memory including information about a first degradation degree of the first non-volatile memory, wherein the second CXL storage device includes: a second CXL storage controller; a second non-volatile memory controlled by the second CXL storage controller; and a second shared memory including information about a second degradation degree of the second non-volatile memory, the second shared memory being accessible by the first CXL storage controller through the CXL interface, and wherein the first CXL storage controller is configured to: receive a command related to an operation of the first non-volatile memory from the host, and based on recognizing that the first degradation degree is higher than the second degradation degree, control the second CXL storage controller to execute the command instead of the first CXL storage controller executing the command.

[0010] The disclosed effects are not limited to the above-described effects, and other effects of the disclosure will be apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the disclosure will become more apparent by describing in detail example embodiments of the disclosure with reference to the accompanying drawings, in which

[0012] Figure 1 is an exemplary diagram for explaining a computing system to which a storage system according to some embodiments is applied.

[0013] Figure 2 For detailed explanation Figure 1 An exemplary diagram of components of a host and a CXL storage device.

[0014] Figure 3 It is used to explain Figure 1 An exemplary diagram of a computing system.

[0015] Figure 4 is an exemplary flow chart for describing the operation of a computing system according to some embodiments.

[0016] Figure 5 It is used to explain Figure 4 An exemplary diagram of the operation of a computing system.

[0017] Figure 6 and Figure 7 is an exemplary flow chart for describing the operation of a computing system according to some embodiments.

[0018] Figure 8 It is used to explain Figure 6 and Figure 7 An exemplary diagram of the operation of a computing system.

[0019] Fig. 9 and Fig.10 is an exemplary flow chart for describing the operation of a computing system according to some embodiments.

[0020] Fig.11 It is used to explain Fig. 9 and Fig.10 An exemplary diagram of the operation of a computing system.

[0021] Fig.12 is an exemplary diagram for describing a computing system according to some other embodiments.

[0022] Fig.13 It is used to explain Fig.12 An exemplary flow chart of the operation of a computing system.

[0023] Fig.14 It is used to explain Fig.13 An exemplary diagram of the operation of a computing system.

[0024] Fig.15 is an exemplary diagram for describing a computing system according to some other embodiments.

[0025] Fig.16 and Fig.17 It is used to explain Fig.15 An exemplary flow chart of the operation of a computing system.

[0026] Fig.18 It is used to explain Fig.15 An exemplary diagram of the operation of a computing system.

[0027] Fig.19 is an exemplary diagram for describing a computing system according to some other embodiments.

[0028] Fig. 20 It is used to describe in detail Fig.19 An exemplary diagram of components of a host and a CXL memory device.

[0029] Fig.21 It is used to explain Fig.19 An exemplary diagram of a computing system.

[0030] Fig. 22 is an exemplary diagram for explaining a data center to which a computing system according to some embodiments is applied. DETAILED DESCRIPTION

[0031] The description only illustrates the principles of the disclosure. Although not explicitly described herein, one skilled in the art will be able to design one or more arrangements that embody the principles of the disclosure. In addition, all examples listed herein are primarily intended to be used explicitly only for explanatory purposes to help the reader understand the principles of the disclosure and the concepts contributed by the inventors to promote the art, and should be interpreted as not being limited to these specifically listed examples and conditions. In addition, all statements listing the principles, aspects, and embodiments of the disclosure and their specific examples are intended to cover their equivalents.

[0032] The terms used in the present disclosure are only used to describe specific embodiments, and may not be intended to limit the scope of other embodiments. Unless the meaning is clearly different in the context, singular expressions may include plural expressions. The terms used herein (including technical terms or scientific terms) may have the same meaning as the meanings commonly understood by ordinary technicians in the technical field described in the present disclosure. The terms defined in the general dictionary among the terms used in the present disclosure can be interpreted with the same or similar meanings as the contextual meanings of the relevant technology, and unless clearly defined in the present disclosure, are not interpreted with idealized or overly formalized meanings. In some cases, even the terms defined in the present disclosure cannot be interpreted as excluding disclosed embodiments.

[0033] In one or more embodiments of the disclosure described below, a hardware method is described as an example. However, since one or more embodiments of the disclosure include techniques using both hardware and software, various embodiments of the present disclosure do not exclude software-based methods.

[0034] In addition, in the disclosure, in order to determine whether a specific condition is satisfied or fulfilled, the expression greater than or less than may be used, but this is only a description for expressing an example and does not exclude the description of greater than or equal to or less than or equal to. The condition described as "greater than or equal to" may be replaced with "greater than", the condition described as "less than or equal to" may be replaced with "less than", and the condition described as "greater than or equal to and less than" may be replaced with "greater than and less than or equal to". In addition, in the following, "A" to "B" means at least one of the elements from A (including A) to B (including B).

[0035] The term "combination" and its derivatives refer to any direct or indirect communication between two or more elements, whether or not these elements are physically in contact with each other. The terms "send", "receive" and "communication" and their derivatives cover both direct and indirect communication. The terms "include" and "comprise" and their derivatives refer to including but not limited to. The term "or" is an inclusive term representing "and / or". The phrase "associated with..." and its derivatives refer to including, being included in, interconnected with, being included in, being connected to or connected with, being combined with, being combined with, being able to communicate with, being coordinated with, being interleaved, being juxtaposed, being close to, being bound to, being bound with, having, having the nature of, having a relationship with, or having a relationship with, etc. The term "controller" refers to any device, system or part thereof that controls at least one operation. Such a controller can be implemented in hardware or a combination of hardware and software and / or firmware. The functions associated with any particular controller can be centralized or distributed, whether local or remote. The phrase "at least one of..." when used with a list of items means that different combinations of one or more of the listed items may be used, and only one item in the list may be needed. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C, and any variations thereof. The expression "at least one of a, b, or c" may indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. Similarly, the term "set" means one or more. Thus, a set of items may be a single item or a set of two or more items.

[0036] A memory system and a computing system including the memory system according to some embodiments will be described below with reference to the accompanying drawings.

[0037] Figure 1 is an exemplary diagram for explaining a computing system to which a storage system according to some embodiments is applied.

[0038] Reference Figure 1, the computing system 100 may include hosts 101, 102, and 103 (or referred to as host 1 101, host 2 102, and host 3 103), a plurality of memory devices 111a, 111b, 112a, 112b, 113a, and 113b, and a plurality of CXL storage devices 130, 140, and 150 (respectively "CXL SD 1", "CXL SD 2", and "CXL SD 3"). The plurality of CXL storage devices 130, 140, and 150 may constitute the storage system 100S. In some embodiments, the computing system 100 may be included in a user device (such as a personal computer, a laptop computer, a server, a media player, a digital camera) or a vehicle device (such as a navigation, a black box, a vehicle electronic device). In some embodiments, the computing system 100 may be a mobile system (such as a mobile phone, a smart phone, a tablet pc (personal computer), a wearable device, a healthcare device, or an Internet of Things (IOT) device).

[0039] Hosts 101, 102, and 103 may control the overall operation of computing system 100. In some embodiments, hosts 101, 102, and 103 may be one of various processors such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), and a data processing unit (DPU). In some embodiments, hosts 101, 102, and 103 may each include a single-core processor or a multi-core processor.

[0040] The plurality of memory devices 111a, 111b, 112a, 112b, 113a, and 113b may be used as a main memory or a system memory of the computing system 100. In some embodiments, the memory devices 111a and 111b may be connected to the host 101; the memory devices 112a and 112b may be connected to the host 102; and the memory devices 113a and 113b may be connected to the host 103. In some embodiments, each of the plurality of memory devices 111a, 111b, 112a, 112b, 113a, and 113b may be a dynamic random access memory (DRAM) device and may have a form factor of a dual in-line memory module (DIMM). However, the embodiment is not limited thereto, and the plurality of memory devices 111a, 111b, 112a, 112b, 113a, and 113b may include a nonvolatile memory such as a flash memory, a phase change RAM (PRAM), a resistive RAM (RRAM), and a magnetic RAM (MRAM).

[0041] The memory devices 111a and 111b may communicate directly with the host 101 through a double data rate (DDR) interface, the memory devices 112a and 112b may communicate directly with the host 102 through a DDR interface, and the memory devices 113a and 113b may communicate directly with the host 103 through a DDR interface. In some embodiments, the hosts 101, 102, and 103 may each include a memory controller configured to control the plurality of memory devices 111a, 111b, 112a, 112b, 113a, and 113b, respectively. However, the embodiments are not limited thereto, and the plurality of memory devices 111a, 111b, 112a, 112b, 113a, and 113b may communicate with each of the hosts 101, 102, and 103 through various interfaces.

[0042] The plurality of CXL memory devices 130, 140, and 150 may include CXL memory controllers 131, 141, and 151 (e.g., CXL memory controller 1 131, CXL memory controller 2 141, and CXL memory controller 3 151), respectively, and non-volatile memories (NVM) 1 132, NVM 2 142, and NVM 3 152. For example, under the control of the hosts 101, 102, and 103, each of the CXL memory controllers 131, 141, and 151 may store data in each of the non-volatile memories 132, 142, and 152, or may transmit data stored in each of the non-volatile memories 132, 142, and 152 to the hosts 101, 102, and 103. In some embodiments, the non-volatile memories 132, 142, and 152 may be, but are not limited to, NAND flash memories.

[0043] In some embodiments, hosts 101, 102, and 103 and CXL storage devices 130, 140, and 150 may be configured to share the same interface with each other. For example, hosts 101, 102, and 103 and CXL storage devices 130, 140, and 150 may communicate with each other via a compute fast link (CXL) interface (CXL IF) 120. In some embodiments, CXL interface 120 may represent a dynamic protocol multiplexing of dynamic protocols supporting coherency, memory access, and input / output protocols (IO protocols) to enable low latency and high bandwidth links for various connections between accelerators, memory devices, or various electronic devices.

[0044] Figure 2 For detailed explanation Figure 1 An exemplary diagram of components of a host and a CXL storage device.

[0045] Figure 21 and CXL storage device 130 ("CXL SD 1"). The description of host 101 is also applicable to hosts 102 and 103 ( Figure 1 ), and the description of CXL storage device 130 is also applicable to CXL storage devices 140 and 150 ( Figure 1 ). Therefore, the description of host 101 and CXL storage device 130 replaces the description of hosts 102 and 103 and CXL storage devices 140 and 150.

[0046] In one embodiment, the host 101 and the CXL storage device 130 communicate with each other through the CXL interface 120. However, the embodiment is not limited thereto, and the host 101 and the CXL storage device 130 may communicate with each other based on various computing interfaces such as the GEN-Z protocol, the NVLink protocol, the Cache Coherent Interconnect for Accelerators (CCIX) protocol, and the Open Coherent Accelerator Processor Interface (Open CAPI) protocol.

[0047] Reference Figure 2 , the CXL interface 120 may include a lower protocol "CXL.io", and may include "CXL.cache" and "CXL.mem". The CXL.io protocol is a PCIe transaction layer, and may be used in the computing system 100 for device discovery, interrupt management, provision of access through registers, initialization processing, signal error processing, etc. When an accelerator (e.g., a GPU or a field programmable gate array (FPGA)) accesses the host memory 101c, the CXL.cache protocol may be used. When the host 101 accesses the dedicated memory of the accelerator or the buffer memory (BFM 1) 133 of the CXL memory device 130, the CXL.mem protocol may be used.

[0048] In some embodiments, the host 101 and the CXL storage device 130 may communicate with each other using CXL.io (I / O protocol). CXL.io may have a non-uniform I / O protocol based on PCIe. The host 101 and the CXL storage device 130 may use user CXL.io to send and receive various types of information including user data (UD) 132a.

[0049] The host 101 may include a host processor 101b, a host memory 101c, and a CXL host interface (CXL_H I / F) circuit 101a. The host processor 101b may control the operation of the host 101 as a whole. In some embodiments, the host processor 101b may be one of a plurality of modules provided in an application processor (AP), and the application processor may be implemented as a system on chip (SOC).

[0050] The host memory 101c is a working memory, and may store commands, programs, data, etc. required for the operation of the host processor 101b. In one embodiment, the host memory 101c may be used as a buffer memory for temporarily storing data to be transmitted to or from the CXL storage device 130. If the host processor 101b is implemented as an AP, the host memory 101c may be an embedded memory provided in the AP, or may be a non-volatile memory or a memory module placed outside the AP.

[0051] According to some embodiments, the host processor 101b and the host memory 101c may be implemented as separate semiconductor chips. In some embodiments, the host processor 101b and the host memory 101c may be integrated on the same semiconductor chip.

[0052] The CXL host interface circuit 101a may communicate with the CXL storage device 130 via the CXL interface 120. Specifically, the CXL host interface circuit 101a may communicate with the CXL storage device 130 via a CXL switch (eg, CXL switch 1) 120a included in the CXL interface 120. Figure 3 The CXL switch 120a is described in detail.

[0053] The CXL memory device 130 may include a CXL memory controller 131, a buffer memory 133, and a non-volatile memory 132. The CXL memory controller 131 may include a CXL memory interface (CXL_S I / F) circuit 131a, a processor 131b, a RAM 131c, a flash translation layer (FTL) 131d, an error correction code (ECC) engine 131e, and a buffer memory interface circuit 131f.

[0054] The CXL storage interface circuit 131a may be connected to the CXL switch 120a. The CXL storage interface circuit 131a may communicate with the host 101 or other CXL storage devices 140 and 150 through the CXL switch 120a.

[0055] The processor 131 b may be configured to control the overall operation of the CXL memory controller 131. The RAM 131 c may be used as a working memory or a buffer memory of the CXL memory controller 131.

[0056] The FTL 131d may perform various management operations to efficiently use the nonvolatile memory 132. In one embodiment, the FTL 131d may perform address conversion between a logical block address managed by the host 101 and a physical block address used in the nonvolatile memory 132 based on mapping data or a mapping table. The FTL 131d may perform a bad block management operation on the nonvolatile memory 132. The FTL 131d may perform a wear leveling operation on a nonvolatile memory (NVM). The FTL 131d may also perform a garbage collection operation on the nonvolatile memory 132.

[0057] In some embodiments, the FTL 131d may be implemented based on software, hardware, firmware, or a combination thereof. When the FTL 131d is implemented in the form of software or firmware, program codes associated with the FTL 131d may be stored in the RAM 131c and driven by the processor 131b. If the FTL 131d is implemented as hardware, a hardware configuration configured to perform the above-described various management operations may be implemented in the CXL storage controller 131.

[0058] The ECC engine 131e may perform error detection and correction functions on data stored in the nonvolatile memory 132. For example, the ECC engine 131e may generate parity bits for user data 132a to be stored in the nonvolatile memory 132, and the parity bits thus generated may be stored together with the user data 132a in the nonvolatile memory 132. When the user data 132a is read from the nonvolatile memory 132, the ECC engine 131e may detect and correct errors of the user data 132a using the parity bits read from the nonvolatile memory 132 together with the read user data 132a.

[0059] The buffer memory interface circuit 131f may control the buffer memory 133 so that data is stored in or read from the buffer memory 133. In some embodiments, the buffer memory interface circuit 131f may be implemented to comply with a standard such as a DDR interface and a low power double data rate interface (LPDDR) interface.

[0060] The buffer memory 133 may store data or output stored data under the control of the CXL memory controller 131. In addition, the buffer memory 133 may store various types of information required for the operation of the CXL memory device 130. For example, the buffer memory 133 may include a shared memory. In some embodiments, the buffer memory 133 may be a high-speed memory such as a DRAM.

[0061] The shared memory ("shared memory 1") 133a may store data collected by the CXL storage controller 131 monitoring the state of itself (i.e., the CXL storage device 130) (e.g., hardware state and software state). The hardware state may include remaining capacity, the number of bad blocks, temperature, life span, etc. The software state may include busyness, the amount of commands (or requests) received from the host 101, a command pattern (or request pattern) frequently requested from the host 101, a data pattern requested from the host, etc.

[0062] In one embodiment, the shared memory 133a may include information about the degradation degree of the nonvolatile memory 132. For example, the CXL memory controller 131 may check the degradation degree of the nonvolatile memory 132 and update the information about the degradation degree of the nonvolatile memory 132 to the shared memory 133a.

[0063] Other devices connected to the CXL storage device 130 through the CXL interface 120 in the computing system 100 may access the shared memory 133 a of the CXL storage device 130 . For example, the CXL storage controller 131 may access the shared memory 143 a ( Figure 3 ), and the non-volatile memory 142 ( Figure 3 Similarly, the host 101 can access the shared memory 133a of the CXL storage device 130 through the CXL switch 120a. When the CXL storage devices 130, 140, and 150 are connected through the CXL switch ( Figure 3 When the CXL switch 1 120a and the CXL switch 2 2120b are connected, each of the CXL storage devices 130, 140 and 150 includes a shared memory 133a, 143a and 153a ( Figure 3 In this way, information about the degradation degree of the non-volatile memory of any one CXL memory device can be shared with other CXL memory devices via the CXL interface 120 .

[0064] Although the shared memory 133a is Figure 2 133a is shown as being placed in the buffer memory 133, but the embodiment is not limited thereto. In some embodiments, the shared memory 133a may be placed outside the buffer memory 133 to be accessible by the CXL memory controller 131. That is, the shared memory 133a may not store data temporarily stored in the buffer memory 133, but may store data that is not temporarily stored inside the CXL memory device 130 (e.g., inside the CXL memory controller 131) for the operation of the CXL memory device 130.

[0065] Figure 2 The buffer memory 133 is shown to be placed between the CXL memory controller 131 and the nonvolatile memory 132 outside the CXL memory controller 131 , but the embodiment is not limited thereto. In some embodiments, the buffer memory 133 may be a configuration provided inside the CXL memory controller 131 .

[0066] The NAND interface circuit 133b may control the nonvolatile memory 132 so that data is stored in or read from the nonvolatile memory 132. In some embodiments, the NAND interface circuit 133b may be implemented to comply with a standard such as a switching interface or an open NAND flash interface (ONFI).

[0067] For example, if the nonvolatile memory 132 includes multiple NAND flash memory devices and the NAND interface circuit 133b is implemented based on a switching interface, the NAND interface circuit 133b can communicate with the multiple NAND flash memory devices through multiple channels, and the multiple NAND flash memory devices can be connected to the multiple channels through a multi-channel and multi-way structure.

[0068] In some embodiments, the NAND interface circuit 133b may transmit a chip enable signal ( / CE), a command latch enable signal (CLE), an address latch enable signal (ALE), a read enable signal ( / RE), and a write enable signal ( / WE) to each of the plurality of NAND flash memory devices through each of the plurality of channels. In one embodiment, each of the plurality of NAND flash memory devices and the NAND interface circuit 133b may transmit and receive a data signal DQ and a data strobe signal DQS through each of the plurality of channels.

[0069] The NAND interface circuit 133b Figure 2 In one embodiment, if the buffer memory 133 is included in the CXL memory controller 131 , the NAND interface circuit 133 b may be placed inside the CXL memory controller 131 and outside the buffer memory 133 .

[0070] The nonvolatile memory 132 may store or output user data 132a under the control of the CXL storage controller 131. In one embodiment, the nonvolatile memory 132 may store or output mapping data (MD) 132b under the control of the CXL storage controller 131. In some embodiments, the mapping data 132b stored in the nonvolatile memory 132 may include mapping information corresponding to the entire user data 132a stored in the nonvolatile memory 132. In some embodiments, as another embodiment, the mapping data 132b related to some of the mapping information of the user data 132a stored in the nonvolatile memory 132 may be included in the buffer memory 133.

[0071] Figure 3 It is used to explain Figure 1 An exemplary diagram of a computing system.

[0072] Reference Figure 3 , the CXL interface 120 may include a CXL switch 120a (“CXL switch 1”) and a CXL switch 120b (“CXL switch 2”). The CXL storage device 130 may be connected to (or communicate with) the hosts 101, 102, and 103 via the CXL switch 120a. The CXL storage devices 140 and 150 may be connected to (or communicate with) the hosts 101, 102, and 103 via the CXL switches 120a and 120b.

[0073] That is, the CXL switch 120 a may be configured to arbitrate communications between the hosts 101, 102, and 103 and the CXL storage devices 130, 140, and 150. For example, when the hosts 101, 102, and 103 and the CXL storage devices 130, 140, and 150 communicate with each other, the CXL switch 120 a may be configured to transmit information (such as requests, data, responses, or signals transmitted from the hosts 101, 102, and 103 or the CXL storage devices 130, 140, and 150) to the CXL storage devices 130, 140, and 150 or the hosts 101, 102, and 103.

[0074] In one embodiment, the CXL switch 120 b may be configured to arbitrate communications between the hosts 101, 102, and 103 and the CXL storage devices 140 and 150. In one embodiment, when the hosts 101, 102, and 103 and the CXL storage devices 140 and 150 communicate with each other, the CXL switch 120 b may be configured to send information (such as a request, data, response, or signal sent from the hosts 101, 102, and 103 or the CXL storage devices 140 and 150) to the CXL storage devices 140 and 150 or the hosts 101, 102, and 103. In an embodiment, the CXL storage device 130 may not be connected to the CXL switch 120 b, and thus, the CXL storage device 130 may not be connected to the hosts 101, 102, and 103 through the CXL switch 120 b.

[0075] According to some embodiments, the CXL switch (included in the CXL interface 120) may have a hierarchical structure. In one embodiment, the CXL switch 120a may be an upper switch, and the CXL switch 120b may be a lower switch. In one embodiment, a plurality of CXL storage devices 130, 140, and 150 may be grouped according to whether they are connected to each other through a single CXL switch. In one embodiment, the CXL storage devices 130, 140, and 150 (connected to each other through the CXL switch 120a) may form one group G1, and the CXL storage devices 140 and 150 (connected to each other through the CXL switch 120b) may form another group G2. In one embodiment, because the CXL switch 120b is a lower-level switch than the CXL switch 120a, the group G2 may be a lower-level group than the group G1.

[0076] Among the CXL storage devices included in the upper group, a CXL storage device that is not connected to the lower switch may not be included in the lower group. In one embodiment, the CXL storage device 130 may not be connected to the CXL switch 120b, and thus may not be included in the group G2 corresponding to the lower level of the group G1. In an embodiment, the CXL storage devices 140 and 150 included in the same lower group G2 may communicate with each other through the CXL switch 120b. When the CXL storage device 130 communicates with the CXL storage devices 140 and 150 (included in the group G2), the CXL storage device 130 may communicate with the CXL storage devices 140 and 150 through both the CXL switch 120a and the CXL switch 120b.

[0077] In some embodiments, the CXL memory devices 130, 140, and 150 may communicate with each other using CXL.mem (memory access protocol). CXL.mem may be a memory access protocol that supports memory access. The CXL memory device 130 may use CXL.mem to access the shared memory 143a of the CXL memory device 140. Similarly, the CXL memory device 140 may use CXL.mem to access the shared memory 133a of the CXL memory device 130 or the shared memory 153a of the CXL memory device 150.

[0078] According to an embodiment, the hosts 101, 102, and 103 and each memory (e.g., the buffer memories 133, 143, and 153 or the shared memories 133a, 143a, and 153a) of the CXL storage devices 130, 140, and 150 may communicate with each other using CXL.mem. For example, the hosts 101, 102, and 103 may use CXL.mem to access the shared memories 133a, 143a, and 153a of each of the CXL storage devices 130, 140, and 150. In addition, each of the CXL storage controllers 131, 141, and 151 may send data stored in each of the buffer memories 133, 143, and 153 to each of the hosts 101, 102, and 103 through CXL.mem.

[0079] In some embodiments, the buffer memory 133, 143, and 153 of each of the CXL storage devices 130, 140, and 150 may be divided into one or more regions. For example, each of the CXL storage controllers 131, 141, and 151 divides the storage space of each of the buffer memories 133, 143, and 153 into one or more regions, and may provide them to each of the hosts 101, 102, and 103. In this case, each of the hosts 101, 102, and 103 may recognize different regions within one buffer memory as independent storage spaces. For example, the hosts 101, 102, and 103 may recognize regions ("region 1", "region 2", and "region 3") of the buffer memory 133 of the CXL storage device 130 as independent storage spaces.

[0080] In some embodiments, shared memory 133a, 143a, and 153a ("shared memory 1", "shared memory 2", and "shared memory 3", respectively) of each of CXL storage devices 130, 140, and 150 may be included in any one of a plurality of regions, and a single region may be allocated to the shared memory. For example, Figure 3As shown in , the shared memory 133a may be included in a region ("region 2") of the buffer memory 133. In some embodiments, the entire region of the buffer memory 133 (all of "region 1", "region 2" and "region 3") may be allocated to the shared memory 133a.

[0081] In some embodiments, one host may access multiple regions. For example, host 101 may access regions (e.g., “region 1” and “region 2”) of CXL storage device 130 simultaneously or with a time lag. In one embodiment, host 101 may access a region (e.g., “region 3”) of CXL storage device 130 and a region (e.g., “region 1”) of CXL storage device 140 simultaneously or with a time lag.

[0082] Furthermore, in some embodiments, multiple hosts 101, 102, and 103 may access a region in a buffer memory at the same time. In one embodiment, host 101 and host 102 may access a region (e.g., "region 3") of CXL storage device 130 at the same time or substantially at the same time. In this way, when multiple hosts access any region of a CXL storage device at the same time or substantially at the same time, the workload is concentrated on the CXL storage device, and the life of the CXL storage device may be significantly reduced.

[0083] Figure 4 The operation of a computing system according to some embodiments is shown. Figure 4 Show Figure 4 The following will refer to the operation of the computing system. Figure 4 and Figure 5 Although the case where the host 101 sends a write command to the CXL storage device 140 will be described below as an example, the following description is also applicable to the case where any one of the other hosts 102 and 103 sends a write command to any one of the CXL storage devices 130, 140, and 150.

[0084] Reference Figure 4 and Figure 5 In operation S100, the host 101 may issue a write command for writing write data into the CXL storage device 140 through the CXL host interface 120. The write command may be sent to the CXL switch 120a, and the CXL switch 120a may send the write command to the CXL switch 120b. The CXL switch 120b may send the write command to the CXL storage device 140 as a target of the write command.

[0085] Next, in operations S101, S102, and S103, in response to receiving a write command from the CXL switch 120 b (or based on receiving a write command from the CXL switch 121 b), the CXL storage controller 141 of the CXL storage device 140 may check the degradation degree of the non-volatile memory 142 through the shared memory 143 a, and may check the degradation degree of the non-volatile memory 152 through the shared memory 153 a. In one embodiment, the CXL storage controller 141 may access the shared memory 153 a of the CXL storage device 150 through the CXL switch 120 b to obtain information on the degradation degree of the non-volatile memory 152.

[0086] Next, in operation S104, the CXL storage controller 141 may compare the degradation degree of the nonvolatile memory 142 with the degradation degree of the nonvolatile memory 152. In response to the fact that the degradation degree of the nonvolatile memory 142 is not higher than the degradation degree of the nonvolatile memory 152 (or based on the recognition that the degradation degree of the nonvolatile memory 142 is not higher than the degradation degree of the nonvolatile memory 152) (S104-No), the CXL storage controller 141 may control the write data to be written on the nonvolatile memory 142 (operation S105). Alternatively, in response to the fact that the degradation degree of the nonvolatile memory 142 is higher than the degradation degree of the nonvolatile memory 152 (or based on the recognition that the degradation degree of the nonvolatile memory 142 is higher than the degradation degree of the nonvolatile memory 152) (S104-Yes), the CXL storage controller 141 may transmit a request for transmitting a write command to the CXL storage device 150 to the host 101 through the CXL switch 120b and the CXL switch 120a (S106).

[0087] Next, in operations S107, S108, and S109, the host 101 may send a write command to the CXL storage device 150 through the CXL switches 120a and 120b in response to receiving the request (or based on the received request). After receiving the write command from the CXL switch 120b, the CXL storage controller 151 may write the write data on the nonvolatile memory 152. According to an embodiment, the write data to be sent from the host 101 to the CXL storage device 150 may be sent to the CXL storage device 150 together with the write command, or may be sent to the CXL storage device 150 at a time interval after the write command is sent from the host 101 to the CXL storage device 150.

[0088] In this manner, after receiving a write command from the host 101, the CXL memory controller 141 of the CXL memory device 140 checks the degradation degree of the nonvolatile memory 152 of the other CXL memory devices (e.g., the CXL memory device 150) included in the group G2 corresponding to the lowest level group among the groups G1 and G2 to which the CXL memory controller 141 belongs. In a case where the degradation degree of the nonvolatile memory 142 controlled by the CXL memory controller 141 is high and the degradation degree of the nonvolatile memory (e.g., the nonvolatile memory 152) of the other CXL memory devices (e.g., the CXL memory device 150) is low, the CXL memory controller 141 may request the host 101 to send a write command to the other CXL memory devices (e.g., the CXL memory device 150).

[0089] In some embodiments, the CXL storage controller 141 of the CXL storage device 140 may request the host 101 to send a write command to other CXL storage devices (e.g., the CXL storage device 130), which are not included in the group G2 corresponding to the lowest level group among the groups G1 and G2 to which the CXL storage controller 141 belongs, but the CXL storage device 130 may include a shared memory.

[0090] For example, when the CXL storage device 130 includes the shared memory 133 a, the CXL storage controller 141 may access the shared memory 133 a through the CXL switches 120 a and 120 b, and check the degradation degree of the nonvolatile memory 132. Therefore, the CXL storage controller 141 may request the host 101 to send a write command to the CXL storage device 130 based on recognizing that the degradation degree of the nonvolatile memory 132 is lower than that of the nonvolatile memory 142.

[0091] Furthermore, in some embodiments, when the degradation degree of the nonvolatile memory 142 is high and the CXL storage controller 141 may not process a write command received from the host 101, the CXL storage controller 141 checks the degradation degree of the nonvolatile memory 152 through the shared memory 153a, checks the degradation degree of the nonvolatile memory 132 through the shared memory 133a, and then compares the two degradation degrees, and may request the host 101 to send a write command to a CXL storage device including a nonvolatile memory having a lower degradation degree.

[0092] In this way, a CXL memory device (receiving a write command from the host) can actively process a command received from the host by checking the degradation degree of other CXL memory devices via the CXL interface and the shared memory.

[0093] Figure 6 and Figure 7 The operation of a computing system according to some embodiments is shown. Figure 8 Show Figure 6 and Figure 7 The following will refer to the operation of the computing system. Figures 6 to 8 The operation of a computing system according to some embodiments is described.

[0094] Reference Figures 6 to 8 , operations S200 to S205 and Figure 4 Operations S100 to S105 are the same as those of the nonvolatile memory 142 and thus will be omitted for convenience of explanation. On the other hand, in operation S206, in response to the fact that the degradation degree of the nonvolatile memory 142 is higher than the degradation degree of the nonvolatile memory 152 (or based on the recognition that the degradation degree of the nonvolatile memory 142 is higher than the degradation degree of the nonvolatile memory 152) (S204-Yes), the CXL storage controller 141 may transmit a signal (signal 1) S1 to the CXL storage device 150 through the switch CXL switch 120b. The signal S1 may include a write command received by the CXL storage controller 141 from the host 101, and a host buffer address of the host 101 requesting the write command. The host buffer address may be received by the CXL storage controller 141 from the host 101 together with the write command.

[0095] In some embodiments, the CXL storage controller 141 may access the shared memory 153 a of the CXL storage device 150 through the CXL switch 120 b , and the CXL storage controller 141 may send the signal S1 to the CXL storage device 150 in a manner of updating the signal S1 to the shared memory 153 a .

[0096] Next, through operations S207 and S208, the CXL storage controller 151 may receive the signal S1 through the CXL switch 120b and receive write data from the host 101 based on the host buffer address of the request write command. Subsequently, in operation S209, the CXL storage controller 151 may write the write data on the nonvolatile memory 152 based on the host buffer address.

[0097] Next, in operation S210, after executing the write command received from the CXL memory controller 141, the CXL memory controller 151 may transmit a command response signal notifying completion of the write command to the CXL memory device 140 that transmitted the write command to the CXL memory controller 151. Thereafter, in operations S211 and S212, the CXL memory controller 141 receives the command response signal through the CXL switch 120 b, and may transmit the command response signal notifying completion of the write command requested by the host 101 to the host 101 that first transmitted the write command to the CXL memory controller 141 through the CXL switches 120 b and 120 a. In operation S213, the host 101 may receive the command response signal from the CXL memory device 140 through the CXL switch 120 a.

[0098] In this manner, the host 101 may receive a write command response signal from the CXL memory device 140 to which the host 101 first sent the write command, rather than from the CXL memory device 150 that executed the write command.

[0099] Fig. 9 and Fig.10 The operation of a computing system according to some embodiments is shown. Fig.11 Show Fig. 9 and Fig.10 The following will refer to the operation of the computing system. Figures 9 to 11 The operation of a computing system according to some embodiments is described.

[0100] Reference Figures 9 to 11 In operation S300, the host 101 may use the CXL host interface circuit 101a ( Figure 3 140. The read command may be sent to CXL switch 120a, and CXL switch 120a may send the read command to CXL switch 120b. CXL switch 120b may send the read command to CXL storage device 140, which is the target of the read command.

[0101] Next, in operations S301 and S302, the CXL storage controller 141 of the CXL storage device 140 receives a read command from the CXL switch 120 b and may determine whether the data requested to be read by the host 101 (hereinafter, defined as target data) is stored in the nonvolatile memory 142. In the case that the target data is stored in the nonvolatile memory 142 (S302, “Yes”), the CXL storage controller 141 may read the target data from the nonvolatile memory 142 (S303). Subsequently, in operation S304, the CXL storage controller 141 may send the read target data to the host 101 through the CXL switches 120 b and 120 a.

[0102] On the other hand, if the target data is stored in the nonvolatile memory 132 (operation S302, “No”), the CXL storage controller 141 may determine whether the target data is stored in the nonvolatile memory 152 in operation S305. In this way, in a case where the target data is not stored in the nonvolatile memory 142 controlled by the CXL storage controller 141, the CXL storage controller 141 may check whether the target data is stored in the nonvolatile memory 152 of other CXL storage devices (e.g., the CXL storage device 150) included in the group G2 corresponding to the lowest level group among the groups G1 and G2 to which the CXL storage controller 141 belongs. However, the embodiment is not limited thereto, and the CXL storage controller 141 may check whether the target data is stored in other CXL storage devices (e.g., the CXL storage device 130 including the shared memory 133a) that are not included in the group G2 corresponding to the lowest level group among the groups G1 and G2 to which the CXL storage controller 141 belongs but include a shared memory.

[0103] In this manner, in some embodiments, the host 101 may send a read command to the CXL memory device 140, but the target data of the read command may be stored in a CXL memory device other than the CXL memory device 140. Figure 4 and Figure 5 Described embodiments or references Figures 6 to 8 In the described embodiment, although the host 101 sends a write command to the CXL storage device 140 , due to high degradation of the nonvolatile memory 142 (included in the CXL storage device 140 ), the nonvolatile memory 152 of the CXL storage device 150 connected to the CXL storage device 140 through the CXL switch 120 b , rather than the nonvolatile memory 142 , may execute the write command, and thus target data may be stored in the nonvolatile memory 152 of the CXL storage device 150 .

[0104] However, the embodiment is not limited thereto. For example, in some embodiments, write data may be stored in the nonvolatile memory 142 in response to (or based on) a write request of the host 101 to the CXL storage device 140. However, in the case where the host 101 sends a read command for write data to the CXL storage device 140, the read request of the host 101 is immediately concentrated on the CXL storage device 140, and latency may increase. In an embodiment, the CXL storage controller 141 may store a portion of the data requested to be read by the host in the buffer memory 143, and may temporarily store the remaining portion of the data requested to be read by the host in the buffer memory 153 of the CXL storage device 150 through the CXL switch 120b. In the case where the CXL storage controller 141 receives a read request for data stored in the CXL storage device 150 from the host 101, the CXL storage controller 151 may be controlled to execute the read request in response to the fact that the storage device 140 did not process the read request (or based on recognizing that the storage device 140 did not process the read request).

[0105] Subsequently, in operation S306, when the target data is stored in the nonvolatile memory 152 (S305, "Yes"), the CXL storage controller 141 may transmit a signal S2 to the CXL storage device 150 through the CXL switch 120b. The signal S2 may include a read command received by the CXL storage controller 141 from the host 101 and a buffer address (host buffer address) of the host 101 requesting the read command. The host buffer address may be received by the CXL storage controller 141 from the host 101 together with the read command.

[0106] In some embodiments, the CXL storage controller 141 may access the shared memory 153 a of the CXL storage device 150 through the CXL switch 120 b , and may send the signal S2 to the CXL storage device 150 in a manner of updating the signal S2 to the shared memory 153 a .

[0107] Next, through operations S307, S308, and S309, the CXL storage controller 151 may receive the signal S2 through the CXL switch 120b, read the target data stored in the nonvolatile memory 152 based on the host buffer address of the request read command, and send the read data to the host 101 through the CXL switch 120b and the CXL switch 120a. Next, in operation S310, the host 101 may receive the data read from the CXL switch 120a.

[0108] Next, in operation S311, after executing the read command received from the CXL memory controller 141, the CXL memory controller 151 may transmit a command response signal notifying completion of the read command to the CXL memory device 140 that transmitted the read command to the CXL memory controller 151. Thereafter, in operations S312 and S313, the CXL memory controller 141 (of the CXL SD 2 140) receives the command response signal through the CXL switch 120b, and may transmit the command response signal notifying completion of the read command requested by the host 101 to the host 101 that first transmitted the read command to the CXL memory controller 141 through the CXL switches 120a and 120b.

[0109] In this manner, the host 101 may receive the read command response signal ( S314 ) from the CXL memory device 140 that first receives the read command from the host 101 , rather than from the CXL memory device 150 that executes the read command.

[0110] Fig.12 A computing system according to some other embodiments is shown. Hereinafter, a repeated description of the previous embodiments will not be provided, and the differences will be mainly described.

[0111] Reference Fig.12 , the plurality of CXL storage devices 130, 140, and 150 may support (or provide) namespaces and zoned namespaces (ZNS). When the namespace function is used, a storage device as one physical device may be divided into a plurality of logical partitions (i.e., namespaces), and data may be managed based on the namespaces. When the ZNS function is used, a single namespace may be additionally divided into a plurality of partitions, and data may be managed based on the namespaces and partitions. Within a single CXL storage device, both a plurality of namespaces and partitions are included within the same physical device, and each namespace and each partition may be used as a separate storage space.

[0112] like Fig.12 As shown in , each of the CXL storage devices 130, 140, and 150 may include multiple partitions. For example, the non-volatile memory 132 of the CXL storage device 130 may include multiple partitions (“Partition 1”, “Partition 2”, “Partition 3”, . . . , “Partition 1”), the non-volatile memory 142 of the CXL storage device 140 may include multiple partitions (“Partition 1”, “Partition 2”, “Partition 3”, . . . , “Partition m”), and the non-volatile memory 152 of the CXL storage device 150 may include multiple partitions (“Partition 1”, “Partition 2”, “Partition 3”, . . . , “Partition n”), where l, m, and n are integers greater than 1.

[0113] In some embodiments, hosts 101, 102, and 103 may request partition allocation (partition request) for each of CXL storage devices 130, 140, and 150. Hosts 101, 102, and 103 may store data in at least one partition allocated from CXL storage devices 130, 140, and 150 or read data stored in the allocated partition.

[0114] Fig.13 Show Fig.12 The operation of a computing system. Fig.14 Show Fig.13 The following will refer to the operation of the computing system. Fig.13 and Fig.14 Operation of a computing system according to some embodiments is described. Although a case where the host 101 sends a partition allocation request to the CXL storage device 140 instead of the host 101 will be described as an example, the following description is also applicable to a case where any one of the other hosts 101, 102, and 103 sends a partition allocation request to any one of the CXL storage devices 130, 140, and 150.

[0115] Reference Fig.13 and Fig.14 In operation S400, the host 101 may use the CXL host interface circuit 101a ( Figure 3 140) issues an allocation request (partition request) for at least one partition among the partitions included in the non-volatile memory 142 to the CXL storage device 140. The partition allocation request may be sent to the CXL switch 120a, and the CXL switch 120a may send the partition allocation request to the CXL switch 120b. The CXL switch 120b may send the partition allocation request to the CXL storage device 140 that is the target of the partition allocation request.

[0116] Next, in operations S401, S402, and S403, in response to (or based on) receiving a partition assignment request from the CXL switch 120b, the CXL storage controller 141 of the CXL storage device 140 may check the degradation degree of the non-volatile memory 142 through the shared memory 143a, and may check the degradation degree of the non-volatile memory 152 through the shared memory 153a. In an embodiment, the CXL storage controller 141 may access the shared memory 153a of the CXL storage device 150 through the CXL switch 120b to obtain information on the degradation degree of the non-volatile memory 152.

[0117] Next, in operation S404, the CXL storage controller 141 may compare the degradation degree of the nonvolatile memory 142 with the degradation degree of the nonvolatile memory 152. In response to the fact that the degradation degree of the nonvolatile memory 142 is not higher than the degradation degree of the nonvolatile memory 152 (or based on the recognition that the degradation degree of the nonvolatile memory 142 is not higher than the degradation degree of the nonvolatile memory 152) (S404-No), the CXL storage controller 141 may allocate at least one or more partitions among the partitions included in the nonvolatile memory 142 to the host 101 (S405). In one embodiment, in response to the degradation degree of the nonvolatile memory 142 being higher than the degradation degree of the nonvolatile memory 152 (or based on recognizing that the degradation degree of the nonvolatile memory 142 is higher than the degradation degree of the nonvolatile memory 152 ) ( S404 —Yes), the CXL storage controller 141 may send a request for sending a partition allocation request to the CXL storage device 150 to the host 101 through the CXL switch 120 b and the CXL switch 120 a ( S406 ).

[0118] Next, in operation S407 and operation S408, the host 101 may send a partition allocation request to the CXL storage device 150 through the CXL switches 120a and 120b in response to (or based on) receiving the aforementioned request. In operation S409, after receiving the partition allocation request from the CXL switch 120b, the CXL storage controller 151 may allocate at least one or more partitions among the partitions included in the non-volatile memory 152 to the host 101.

[0119] In this manner, the CXL storage controller 141 of the CXL storage device 140 that has received the partition assignment request from the host 101 may check the degradation degree of the nonvolatile memory 152 of the other CXL storage devices (e.g., the CXL storage device 150) included in the group G2 corresponding to the lowest level group among the groups G1 and G2 to which the CXL storage controller 141 belongs. In a case where the degradation degree of the nonvolatile memory 142 controlled by the CXL storage controller 141 (of the CXL storage device 140) is high and the degradation degree of the nonvolatile memory 152 of the other CXL storage devices (e.g., the CXL storage device 150) is low, the CXL storage controller 141 may request the host 101 to send the partition assignment request to the other CXL storage devices (e.g., the CXL storage device 150).

[0120] In some embodiments, the CXL storage controller 141 of the CXL storage device 140 may request the host 101 to allocate a partition allocation request to other CXL storage devices (e.g., the CXL storage device 130 including the shared memory 133 a ) that are not included in the group G2 corresponding to the lowest level group among the groups G1 and G2 to which the CXL storage controller 141 belongs but include a shared memory.

[0121] In one embodiment, when the CXL storage device 130 includes the shared memory 133 a, the CXL storage controller 141 may access the shared memory 133 a through the CXL switch 120 b and the CXL switch 120 a, and check the degradation level of the non-volatile memory 132. Therefore, in response to a situation where the degradation level of the non-volatile memory 142 is higher than the degradation level of the non-volatile memory 132 (or based on recognizing that the degradation level of the non-volatile memory 142 is higher than the degradation level of the non-volatile memory 132), the CXL storage controller 141 may request the host 101 to send a partition allocation request to the CXL storage device 130.

[0122] Furthermore, in some embodiments, in the case where the degradation degree of the non-volatile memory 142 is high and cannot process a partition allocation request received from the host 101, the CXL storage controller 141 may check the degradation degree of the non-volatile memory 152 through the shared memory 153a and check the degradation degree of the non-volatile memory 132 through the shared memory 133a, and then compare the two, and may request the host 101 to send a partition allocation request to a CXL storage device including a non-volatile memory having a low degradation degree.

[0123] However, whether the CXL storage device receiving the partition allocation request from the host 101 allocates the partition included in the nonvolatile memory controlled by the CXL storage device to the host 101, or whether to control the allocation of the partition included in the nonvolatile memory of other CXL storage devices connected through the CXL interface to the host 101 is not limited to the result of comparing the degradation degrees of the two nonvolatile memories. In some embodiments, the CXL storage controller of the CXL storage device receiving the partition allocation request from the host 101 may compare the degradation degree of the partition included in the nonvolatile memory controlled by the CXL storage controller of the CXL storage device (e.g., the degree to which the partition included in the nonvolatile memory of a specific CXL storage device is allocated to the host, etc.) with the degradation degree of the partition included in other CXL storage devices connected through the CXL interface, and may control the CXL storage device having a relatively low degradation degree of the partition to execute the partition allocation request of the host 101.

[0124] Fig.15A computing system according to some other embodiments is shown. Hereinafter, a repeated description of the previous embodiments will not be provided, and the differences will be mainly described.

[0125] Reference Fig.15 In the computing system 100B, the host 101 may further include a baseboard management controller (BMC) 101d and an auxiliary power supply 101e. In addition, the CXL storage device 130 and the CXL storage device 140 may further include a microcontroller 134 (MCU1) and a microcontroller 144 (MCU2), respectively.

[0126] The BMC 101d may be configured to manage internal components of a storage system including the CXL storage devices 130, 140, and 150. In some embodiments, the BMC 101d may program a plurality of CXL storage devices (including the CXL storage devices 130, 140, and 150) in the storage system and set the plurality of CXL storage devices and the CXL interface 120 according to instructions given by an administrator of the computing system 100, thereby setting a boot and control path. The BMC 101d may use sensors to monitor a physical state of a server corresponding to the host 101. For example, the BMC 101d may check hardware health information and power consumption information (such as connection status, lifespan, temperature, and log information of a plurality of CXL storage devices (including the CXL storage devices 130, 140, and 150) in the storage system).

[0127] The auxiliary power supply 101e may supply power to the MCUs 134 and 144. Each of the MCUs 134 and 144 is supplied with a voltage from the auxiliary power supply 101e and may operate separately from each of the CXL memory devices 130, 140, and 150. For example, even when the CXL memory devices 130, 140, and 150 are powered off, the MCUs 134 and 144 are powered by the auxiliary power supply 101e and remain operable. The MCUs 134 and 144 may each include a memory 134a and 144a. The memories 134a and 144a may be DRAM, SRAM, FRAM, etc., respectively.

[0128] The MCUs 134 and 144 may communicate with the BMC 101d independently. That is, the MCUs 134 and 144 may send and receive signals independently of the BMC 101d without the control of the host processor 101b. The path through which the host processor 101b sends and receives signals to and from the CXL storage controllers 131 and 141 may be referred to as "in-band". The path through which the BMC 101d sends and receives signals independently of the MCUs 134 and 144 may be referred to as "out-of-band". In some embodiments, in the case where the host processor 101b and the CXL storage controllers 131 and 141 send and receive signals on the in-band path, the host processor 101b and the CXL storage controllers 131 and 141 may communicate with each other through the CXL interface. In the case where the BMC 101d and the MCUs 134 and 144 transmit and receive signals on an out-of-band path, the BMC 101d and the MCUs 134 and 144 may not communicate with each other through a CXL interface. However, the embodiment is not limited thereto. Both the in-band path and the out-of-band path may be connected through a CXL interface.

[0129] Fig.16 and Fig.17 Show Fig.15 The operation of a computing system. Fig.18 Show Fig.15 The following will refer to the operation of the computing system. Figures 16 to 18 The operation of a computing system according to some embodiments is described.

[0130] Reference Figures 16 to 18 In operation S500, the host 101 may use the CXL host interface circuit 101a ( Figure 3 1 ) issues a write command and write data to the CXL storage device 130. The write command may be sent to a CXL switch within the CXL interface 120, and the CXL interface 120 may send the write command to the CXL storage controller 131 of the CXL storage device 130 that is the target of the write command.

[0131] Next, in operations S501, S502, and S503, in response to (or based on) receiving a write command from the CXL interface 120, the CXL memory controller 131 of the CXL memory device 130 may check the degradation degree of the non-volatile memory 132 through the shared memory 133a, and check the degradation degree of the non-volatile memory 142 through the shared memory 143a. In an embodiment, the CXL memory controller 131 may access the shared memory 143a of the CXL memory device 140 through the CXL interface 120 to obtain information on the degradation degree of the non-volatile memory 142.

[0132] Next, in operation S504, the CXL storage controller 131 may compare the degradation degree of the nonvolatile memory 132 with the degradation degree of the nonvolatile memory 142. In response to the fact that the degradation degree of the nonvolatile memory 132 is not higher than the degradation degree of the nonvolatile memory 142 (or based on the recognition that the degradation degree of the nonvolatile memory 132 is not higher than the degradation degree of the nonvolatile memory 142) (S504, "No"), the CXL storage controller 131 may control the write data to be written on the nonvolatile memory 132 (S505). Optionally, in operation S506 , in response to the fact that the degradation degree of the nonvolatile memory 132 is higher than the degradation degree of the nonvolatile memory 142 (or based on recognizing that the degradation degree of the nonvolatile memory 132 is higher than the degradation degree of the nonvolatile memory 142 ) ( S504 , “Yes”), the CXL storage controller 131 may send a write command to the CXL storage device 140 through the CXL interface 120 .

[0133] In addition, the CXL storage controller 131 may transmit the write data to the CXL storage device 140 based on a peer-to-peer (P2P) method without the control of the host processor 101 b. For example, in operation S507, the CXL storage controller 131 may transmit the write data to the MCU 134. In some embodiments, the CXL storage controller 131 may temporarily store the write data in the buffer memory 133 before transmitting the write data to the MCU 134, and then transmit the write data temporarily stored in the buffer memory 133 to the MCU 134.

[0134] In some embodiments, after the CXL storage controller 131 initially stores write data in the nonvolatile memory 132 according to a write command, when the degradation degree of the nonvolatile memory 132 worsens, the CXL storage controller 131 may read the write data from the nonvolatile memory 132 and send it to the MCU 134 to move the write data to the nonvolatile memory 142.

[0135] Next, in operations S508 and S509, the MCU 134 may receive the write data and transmit the received write data to the BMC 101d. In an embodiment, the MCU 134 may transmit the write data to the BMC 101d through an out-of-band path without the control of the host processor 101b. Fig.16 It is shown that the MCU 134 sends the write data to the BMC 101d without passing through the CXL interface 120, but the embodiment is not limited thereto. In some embodiments, the MCU 134 may send the write data to the BMC 101d through the CXL interface 120.

[0136] Next, in operations S510 and S511, the BMC 101d may receive the write data and transmit the received write data to the MCU 144. In one embodiment, the transmission of the write data from the BMC 101d to the MCU 144 is the same as the transmission of the write data from the MCU 134 to the BMC 101d.

[0137] Next, the MCU 134 may transmit the received write data to the CXL memory controller 141 , and the CXL memory controller 141 may transmit the received write data to the nonvolatile memory 142 through operations S512 to S514 .

[0138] In this manner, in some embodiments, the CXL memory controller 131 may transmit write data to the CXL memory device 140 based on the P2P method without control of the host processor 101 b , thereby managing the degree of degradation of the nonvolatile memory 132 included in the CXL memory device 130 .

[0139] Subsequently, in operation S515, after executing the write command received from the CXL memory controller 131, the CXL memory controller 141 may transmit a command response signal notifying completion of the write command to the CXL memory device 130 that transmitted the write command to the CXL memory controller 141. Thereafter, in operations S516 and S517, the CXL memory controller 131 receives the command response signal through the CXL interface 120, and may transmit the command response signal notifying completion of the write command requested by the host 101 to the host 101 that first transmitted the write command to the CXL memory controller 131 through the CXL interface 120. Therefore, in operation S518, the host 101 may finally receive the command response signal through the CXL interface 120.

[0140] In this manner, the host 101 may receive a write command response signal from the CXL memory device 130 to which the host 101 first sent the write command, rather than from the CXL memory device 140 that executed the write command.

[0141] Fig.19 A computing system according to some other embodiments is shown. Fig. 20 It is used to describe in detail Fig. 20 An exemplary diagram of components of a host and a CXL memory device. Fig.21 Show Fig.19 The following will refer to Figures 19 to 21 A computing system according to some embodiments is described. Hereinafter, a repeated description of the previous embodiments will not be provided, and the differences will be mainly described.

[0142] First refer to Fig.19 and Fig. 20 ,and Figure 1 and Figure 2 Differently, the computing system 100C may include a CXL memory device 160. A plurality of CXL memory devices 130, 140 and the CXL memory device 160 may constitute a memory system 100SC. The CXL memory device 160 may include a CXL memory controller 161 and a volatile memory (VM) 162. The host 101 and the CXL memory device 160 may communicate with each other using CXL.mem. The host 101 and the CXL memory device 160 may send and receive various types of information (including user data 162c) to each other using CXL.mem. The CXL memory controller 161 may include a CXL memory interface (CXL_M I / F) circuit 161a, a processor 161b, a memory manager 161c, and a memory interface circuit 161d.

[0143] The CXL memory interface circuit 161a may be connected to the CXL switch 120a. The CXL memory interface circuit 161a may communicate with the host 101 or the CXL memory devices 130 and 140 ( Fig.19 shown in) communication.

[0144] The processor 161b may be configured to control the overall operation of the CXL memory controller 161. The memory manager 161c may be configured to manage the buffer memory (buffer memory (BFM) 4) 162b. The CXL memory interface circuit 161a may control the volatile memory 162 so that data is stored in or read from the volatile memory 162. In some embodiments, the CXL memory interface circuit 161a may be implemented to comply with a standard such as a DDR interface and an LPDDR interface.

[0145] The volatile memory 162 may include a shared memory (shared memory 4) 162a and a buffer memory 162b. In addition, the volatile memory 162 is configured by a DRAM or the like, and may store user data 162c. The shared memory 162a may store data obtained by monitoring and collecting the state of the volatile memory 162 by the CXL memory controller 161. For example, the shared memory 162a may include information on the degree of degradation of the volatile memory 162. In the computing system 100C, other devices connected to the CXL memory device 160 through the CXL interface 120 may access the shared memory 162a of the CXL memory device 160. In addition, the CXL memory device 160 may access other devices connected through the CXL interface 120 (e.g., the corresponding shared memories 133a and 143a ( Fig.21 shown in )).

[0146] Reference Fig.21 , the CXL storage device (“CXL SD 2”) 140 and the CXL memory device (“CXL MD”) 160 may be connected together through the CXL switch 120 b, and the CXL storage device 140 and the CXL memory device 160 may access each of the shared memories 143 a and 162 a through the CXL switch 120 b. Therefore, in a case where the host 101 sends a command related to the operation of the non-volatile memory 142 to the CXL storage device 140 and the CXL memory controller 141 does not process the command on the CXL storage device 140, the CXL storage controller 141 may send the command to the CXL memory device 160 connected through the CXL switch 120 b, and the CXL memory controller 161 may be controlled to execute the command.

[0147] In one embodiment, in the case where the host 101 sends a command related to the operation of the volatile memory 162 to the CXL memory device 160 and the CXL memory controller 161 does not process the command on the CXL memory device 160, the CXL memory controller 161 may send the command to one of the CXL memory devices 130 and 140 connected through the CXL interface 120, and the CXL memory controllers 131 and 141 that received the command may be controlled to execute the command.

[0148] Fig. 22 A data center is shown in which a computing system according to some embodiments is applied.

[0149] In some embodiments, the computing system described above with reference to the drawings may be included as an application server 50_1 and / or a storage server 60_1 in a data center 1. In addition, the storage system applied to the disclosed embodiments may be applied to each of the application server 50_1 and / or the storage server 60_1.

[0150] The data center 1 may collect various data and provide services, and may be referred to as a "data storage center". For example, the data center 1 may be used as a system for search engine and database operations, or a computing system used by a company (such as a bank) or a government agency. Fig. 22 As shown in , the data center 1 may include application servers 50_1 to 50_n and storage servers 60_1 to 60_m (m and n are integers greater than 1). The number n of application servers 50_1 to 50_n and the number m of storage servers 60_1 to 60_m may be selected differently according to embodiments, and the number n of application servers 50_1 to 50_n may be different from the number m of storage servers 60_1 to 60_m.

[0151] The application servers 50_1 to 50_n may include at least one of processors 51_1 to 51_n, memories 52_1 to 52_n, switches 53_1 to 53_n, network interface controllers (NICs) 54_1 to 54_n, and storage devices 55_1 to 55_n. The processors 51_1 to 51_n may control the overall operation of the application servers 50_1 to 50_n, and may access the memories 52_1 to 52_n to execute instructions and / or data loaded into the memories 52_1 to 52_n. As non-limiting examples, the memories 52_1 to 52_n may include double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVM DIMM).

[0152] According to the embodiment, the number of processors and the number of memories included in the application servers 50_1 to 50_n may be selected differently. In some embodiments, the processors 51_1 to 51_n and the memories 52_1 to 52_n may provide a processor-memory pair. In some embodiments, the number of processors 51_1 to 51_n and the memories 52_1 to 52_n may be different from each other. The processors 51_1 to 51_n may include a single-core processor or a multi-core processor. In some embodiments, as shown by Fig. 22 As indicated by the dotted lines in FIG. 1 , the storage devices 55_1 to 55_n may be omitted in the application servers 50_1 to 50_n. The number of storage devices 55_1 to 55_n included in the application servers 50_1 to 50_n may be selected differently according to embodiments. The processors 51_1 to 51_n, the memories 52_1 to 52_n, the switches 53_1 to 53_n, the NICs 54_1 to 54_n, and / or the storage devices 55_1 to 55_n may communicate with each other through the CXL interfaces and CXL switches described above with reference to the drawings.

[0153] The storage servers 60_1 to 60_m may include at least one of processors 61_1 to 61_m, memories 62_1 to 62_m, switches 63_1 to 63_m, NICs 64_1 to 64_n, and storage devices 65_1 to 65_m. The processors 61_1 to 61_m and memories 62_1 to 62_m may operate in a manner similar to the processors 51_1 to 51_n and memories 52_1 to 52_n of the above-mentioned application servers 50_1 to 50_n.

[0154] The application servers 50_1 to 50_n and the storage servers 60_1 to 60_m can communicate with each other through a network. In some embodiments, the network 70 can be implemented using a fiber channel (FC), Ethernet, etc. FC can be a medium for relatively high-speed data transmission, and an optical switch that provides high performance / high availability can be used. Depending on the access method of the network 70, the storage servers 60_1 to 60_m can be provided as a file storage device, a block storage device, or an object storage device.

[0155] In some embodiments, the network 70 may be a storage-only network such as a storage area network (SAN). For example, the SAN may utilize an FC network and may be an FC-SAN implemented according to the FC protocol (FCP). Alternatively, the SAN may be an IP-SAN implemented using a TCP / IP network and according to the SCSI or Internet SCSI (iSCSI) protocols over TCP / IP. In some embodiments, the network 70 may be a general-purpose network such as a TCP / IP network. For example, the network 70 may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), and NVMe over fabric (NVMe-oF).

[0156] Hereinafter, although the application server 50_1 and the storage server 60_1 will be mainly described, the description of the application server 50_1 is also applicable to other application servers (eg, 50_n), and the description of the storage server 60_1 is also applicable to other storage servers (eg, 60_m).

[0157] The application server 50_1 may store data requested to be stored by a user or client in one of the storage servers 60_1 to 60_m through the network 70. In addition, the application server 50_1 may obtain data requested to be read by a user or client from one of the storage servers 60_1 to 60_m through the network 70. For example, the application server 50_1 may be implemented by a network server, a database management system (DBMS), etc.

[0158] The application server 50_1 may access the memory 52_n and / or the storage device 55_n included in other application servers 50_n through the network 70, and / or may access the memory 62_1 to 62_m and / or the storage device 65_1 to 65_m included in the storage servers 60_1 to 60_m through the network 70. Therefore, the application server 50_1 performs various operations on the data stored in the application servers 50_1 to 50_n and / or the storage servers 60_1 to 60_m. For example, the application server 50_1 may execute instructions for moving or copying data between the application servers 50_1 to 50_n and / or the storage servers 60_1 to 60_m. In an embodiment, data may be moved to the memory 52_1 to 52_n of the application servers 50_1 to 50_n through the memory 62_1 to 62_m of the storage servers 60_1 to 60_m or directly from the storage devices 65_1 to 65_m of the storage servers 60_1 to 60_m. In some embodiments, data moving over network 70 may be encrypted data for security or privacy.

[0159] In the storage server 60_1, the interface IF may provide a physical connection between the processor 61_1 and the controller CTRL and a physical connection between the NIC 64_1 and the controller CTRL. For example, the interface IF may be implemented in a direct attached storage (DAS) type that directly connects the storage device 65_1 using a dedicated cable. In addition, for example, the interface IF may be implemented in various interface types (such as, Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Minicomputer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVM Express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) Card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS) and Compact Flash (CF) Card Interface).

[0160] In the storage server 60_1 , the switch 63_1 may selectively connect the processor 61_1 and the storage device 65_1 , or selectively connect the NIC 64_1 and the storage device 65_1 , under the control of the processor 61_1 .

[0161] In some embodiments, the NIC 64_1 may include a network interface card, a network adapter, etc. The NIC 54_1 may be connected to the network 70 through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC 54_1 may include an internal memory, a DSP, a host bus interface, etc., and may be connected to the processor 61_1 and / or the switch 63_1, etc. through the host bus interface. In some embodiments, the NIC 64_1 may be integrated with at least one of the processor 61_1, the switch 63_1, and the storage device 65_1.

[0162] In the application servers 50_1 to 50_n or the storage servers 60_1 to 60_m, the processors 51_1 to 51_m and 61_1 to 61_n may send commands to the storage devices 55_1 to 55_n and 65_1 to 65_m or the memories 52_1 to 52_n and 62_1 to 62_m to program or read data. In an embodiment, the data may be data after error correction by an error correction code (ECC) engine. The data may be data that has undergone a data bus conversion (DBI) or a data mask (DM) process, and may include cyclic redundancy code (CRC) information. The data may be data that is encrypted for security or privacy.

[0163] In response to (or based on) a read command received from the processors 51_1 to 51_m and 61_1 to 61_n, the storage devices 55_1 to 55_n and 65_1 to 65_m may send a control signal and a command / address signal to a non-volatile memory device (e.g., a NAND flash memory device) NVM. Thus, when data is read from the non-volatile memory device NVM, a read enable signal is input to the data output control signal and may be used to output data to the DQ bus. The read enable signal may be used to generate a data strobe signal. The command and address signals may be latched according to the rising edge or falling edge of the write enable signal.

[0164] The controller CTRL may generally control the operation of the storage device 65_1. In one embodiment, the controller CTRL may include a static random access memory (SRAM). The controller CTRL may write data on the nonvolatile memory device NVM in response to (or based on) a write command, or may read data from the nonvolatile memory device NVM in response to (or based on) a read command. For example, a write command and / or a read command may be generated based on a request provided from a host (e.g., a processor 61_1 in a storage server 60_1, a processor 61_m in another storage server 60_m, or processors 51_1 to 51_n in application servers 50_1 to 50_n). The buffer BUF may temporarily store (buffer) data to be written to the nonvolatile memory device NVM or data read from the nonvolatile memory device NVM. In some embodiments, the buffer BUF may include a DRAM. In addition, the buffer BUF may store metadata, and the metadata may refer to user data or data generated by the controller CTRL to manage the nonvolatile memory device NVM. The storage device 65_1 may include a security element (SE) for security or privacy.

[0165] Although the disclosure has been particularly shown and described with reference to the disclosed exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims. The exemplary embodiments should be considered in a descriptive sense only and not for purposes of limitation.

Claims

1. A storage system, comprising: a first computing fast link storage device configured to be connected to a host through a computing fast link interface including a first computing fast link switch and a second computing fast link switch; as well as A second computing fast link storage device is configured to be connected to the host through a computing fast link interface, Wherein, the first computing fast link storage device comprises: a first computing fast link storage controller; a first non-volatile memory controlled by a first computing fast link storage controller; and a first shared memory including information about a first degradation degree of the first non-volatile memory, Wherein, the second computing fast link storage device comprises: a second computing fast link storage controller; a second non-volatile memory controlled by a second computing fast link storage controller; and a second shared memory including information about a second degree of degradation of the second non-volatile memory, the second shared memory being accessible by the first computing fast link storage controller through the first computing fast link switch, and Wherein, the first computing fast link storage controller is configured as: receiving a command from a host related to an operation of the first non-volatile memory, and Based on identifying that the first degradation degree is higher than the second degradation degree, the second computing fast link storage controller is controlled to execute the command instead of the first computing fast link storage controller executing the command.

2. The storage system according to claim 1, wherein: The first computing fast link storage controller is configured to request the host to send the command to the second computing fast link storage device based on identifying that the first degradation level is higher than the second degradation level.

3. The storage system according to claim 1, wherein: The first computing fast link storage controller is configured to: based on identifying that the first degradation degree is higher than the second degradation degree, send the command to the second computing fast link storage device through a first signal, and The first signal includes a buffer address of a host sending the command.

4. The storage system according to claim 3, wherein: The command includes a write command, and Wherein, the second computing fast link storage device is configured to receive write data from the host based on a buffer address of the host sending the write command.

5. The storage system according to claim 4, wherein: The second computing fast link storage controller is configured to execute a write command and transmit a command response signal notifying completion of the write command requested by the host to the first computing fast link storage device.

6. The storage system according to claim 5, wherein: The host is configured to send a read command to the first computing fast link storage device, The first computing fast link storage controller is configured to: based on the read command, send the read command to the second computing fast link storage device through the second signal, and The second signal includes a buffer address of a host sending a read command.

7. The storage system according to any one of claims 1 to 6, further comprising: A third computing fast link storage device is configured to be connected to the host through a second computing fast link switch, Wherein, the third computing fast link storage device comprises: A third computing fast link storage controller; a third non-volatile memory controlled by a third computing fast link storage controller; and a third shared memory including information about a third degradation degree of the third non-volatile memory, the third shared memory being accessible by the first computing fast link storage controller through the first computing fast link switch and the second computing fast link switch, and Wherein, the third computing fast link storage device is not connected to the host through the first computing fast link switch.

8. A storage system comprising: A first computing fast link storage device configured to be connected to a host via a computing fast link interface; as well as A second computing fast link storage device is configured to be connected to the host through a computing fast link interface, Wherein, the first computing fast link storage device comprises: a first computing fast link storage controller; a first non-volatile memory controlled by a first computing fast link storage controller; and a first shared memory including information about a first degradation degree of the first non-volatile memory, Wherein, the second computing fast link storage device comprises: a second computing fast link storage controller; a second non-volatile memory controlled by a second computing fast link storage controller; and a second shared memory including information about a second degradation degree of the second non-volatile memory, the second shared memory being accessible by the first computing fast link storage controller through a computing fast link interface, and Wherein, the first computing fast link storage controller is configured as: receiving a command related to the operation of the first non-volatile memory from a host, and Based on recognizing that the command is not processed in the first computing fast link storage device, controlling the second computing fast link storage controller to execute the command.

9. The storage system according to claim 8, wherein: The command includes a write command, and The first computing fast link storage controller is configured to: receive a write command, and based on identifying that the first degradation degree is higher than the second degradation degree, control the second computing fast link storage controller to write the data requested by the host into the second non-volatile memory.

10. The storage system according to claim 9, wherein: The commands also include a read command, The first computing fast link storage controller is configured to: based on the read command, send the read command to the second computing fast link storage device through the first signal, and The first signal includes a buffer address of a host requesting a read command.

11. The storage system according to claim 8, wherein: The commands include read commands, The data requested to be read by the host is stored in the first non-volatile memory. Wherein, the first computing fast link storage device comprises a first buffer memory, Wherein, the second computing fast link storage device comprises a second buffer memory, and Wherein, the first computing fast link storage controller is configured as: storing first data in the first buffer memory, the first data being a part of the data requested to be read by the host, and Second data is stored in the second buffer memory, the second data being a remaining portion of the data requested to be read by the host.

12. The storage system according to claim 11, wherein: The first computing fast link storage controller is configured to: based on the read command, send a read command to the second computing fast link storage device through a first signal, and The first signal includes a buffer address of a host requesting a read command.

13. The storage system according to claim 12, wherein: The second computing quick link storage controller is configured to transmit the second data stored in the second buffer memory to the host based on the buffer address of the host requesting the read command and the read command.

14. The storage system according to any one of claims 8 to 13, wherein: The host includes a host processor, a baseboard management controller, and an auxiliary power supply. The first computing fast link storage device includes: a first microcontroller configured to independently communicate with a baseboard management controller without control of a host processor, The second computing fast link storage device includes: a second microcontroller configured to independently communicate with the baseboard management controller without the control of the host processor, and The auxiliary power supply is configured to supply power to each of the first microcontroller and the second microcontroller.

15. The storage system according to claim 14, wherein: The commands include write commands, wherein the host processor is configured to send a write command and write data to the first computing fast link storage controller, and The first computing fast link storage controller is configured to: receive a write command, and send the write command to the second computing fast link storage device based on identifying that the first degradation level is higher than the second degradation level.

16. The storage system according to claim 15, wherein: The first computing fast link storage controller is configured to: receive the write data and, based on identifying that the first degradation level is higher than the second degradation level, send the write data to the first microcontroller, and The first microcontroller is configured to send the received write data to the baseboard management controller.

17. The storage system according to claim 16, wherein: The baseboard management controller is configured to send the received write data to the second microcontroller, wherein the second microcontroller is configured to send the received write data to the second computing fast link storage controller, and The second computing fast link storage controller is configured to receive a write command and write data, and write the write data on the second non-volatile memory.

18. A computing system comprising: Host; as well as A storage system includes a first computing fast link storage device and a second computing fast link storage device, wherein the first computing fast link storage device and the second computing fast link storage device are configured to be connected to a host through a computing fast link interface, Wherein, the first computing fast link storage device comprises: a first computing fast link storage controller; a first non-volatile memory controlled by a first computing fast link storage controller; and a first shared memory including information about a first degradation degree of the first non-volatile memory, Wherein, the second computing fast link storage device comprises: a second computing fast link storage controller; a second non-volatile memory controlled by a second computing fast link storage controller; and a second shared memory including information about a second degradation degree of the second non-volatile memory, the second shared memory being accessible by the first computing fast link storage controller through a computing fast link interface, and Wherein, the first computing fast link storage controller is configured as: receiving a command related to the operation of the first non-volatile memory from a host, and Based on identifying that the first degradation degree is higher than the second degradation degree, the second computing fast link storage controller is controlled to execute the command instead of the first computing fast link storage controller executing the command.

19. The computing system of claim 18, wherein: The first non-volatile memory includes a first partition namespace, the first partition namespace includes a plurality of first partitions, The second non-volatile memory includes a second partition namespace, the second partition namespace includes a plurality of second partitions, wherein the command comprises a partition allocation request of the host for at least one of the plurality of first partitions, and The first computing fast link storage controller is further configured to: based on identifying that the first degradation degree is higher than the second degradation degree, send a first request for sending a partition allocation request to the second computing fast link storage device to the host.

20. The computing system of claim 19, wherein: The host is configured to: send a partition allocation request to a second computing fast link storage device based on a first request received from the first computing fast link storage device, and The second computing fast link storage controller is configured to: allocate at least one partition of the plurality of second partitions to the host based on the partition allocation request.

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