Data synchronization method, chip and sound vibration system

Abstract

This application provides a data synchronization method, a chip, and a vibration-following-the-tone system. The data synchronization method includes: receiving a node input signal based on a first clock signal; outputting a node output signal based on a second clock signal; determining whether a synchronization signal is valid during the output of the node output signal; if the synchronization signal is valid, preparing to output the next node output signal; if the synchronization signal is invalid, continuing to output the node output signal if the node output signal has not been completed, until the node output signal is completed or the synchronization signal is valid; if the node output signal is completed, continuing to output a compensation signal until the synchronization signal is valid. This application achieves synchronization between the node output signal and the node input signal without the need for a phase-locked loop circuit, which helps to reduce the circuit area and manufacturing cost of the driver chip.

Description

Technical Field

[0001] This application relates to the field of data conversion technology, specifically to a data synchronization method, a chip, and a vibration system that follows the sound. Background Technology

[0002] For application circuits of devices such as motors or speakers, it is necessary to convert digital signals into analog signals to drive the load. Therefore, it is required to ensure the synchronization of digital signals and analog signals to avoid data loss.

[0003] In some implementation scenarios, phase-locked loop (PLL) circuits can be used to ensure that the update clocks of digital signals and analog signals are from the same clock source, thereby guaranteeing the synchronization of digital signals and analog signals.

[0004] However, to achieve synchronization between digital and analog signals using this technology, a phase-locked loop circuit needs to be set in the corresponding driver chip (such as a motor driver chip or an audio driver chip), which leads to an increase in the area of ​​the driver chip and an increase in the cost of a single chip. Summary of the Invention

[0005] This application provides a data synchronization method, a chip, and a sound-following vibration system to solve the above-mentioned technical problems.

[0006] In a first aspect, this application provides a data synchronization method, comprising: receiving a node input signal based on a first clock signal; outputting a node output signal based on a second clock signal; determining whether a synchronization signal is valid during the output of the node output signal; when the synchronization signal is valid, preparing to output the next node output signal; when the synchronization signal is invalid, continuing to output the node output signal if the node output signal has not been completely output, until the node output signal is completely output or the synchronization signal is valid; if the node output signal is completely output, continuing to output a compensation signal until the synchronization signal is valid.

[0007] In some embodiments, the node input signal is received once every preset number of first clock signal cycles, and the node output signal is output once in each cycle of the synchronization signal; wherein the first clock signal and the second clock signal are signals from different sources and / or different phases, and the average period of the synchronization signal is equal to the preset number of first clock signal cycles.

[0008] In some embodiments, the node input signal is received based on a first clock signal and a data input clock, and the node input signal is received once in each cycle of the data input clock; wherein the first clock signal and the second clock signal are signals from different sources and / or different phases, and the average period of the synchronization signal is equal to the period of the data input clock.

[0009] In some embodiments, the synchronization signal includes a synchronization pulse signal. The step of determining whether the synchronization signal is valid during the output of the node output signal includes: determining whether a synchronization signal pulse has arrived during the output of the node output signal; when the synchronization signal pulse arrives, preparing to output the next node output signal; if the synchronization signal pulse has not arrived, and the node output signal has not been fully output, continuing to output the node output signal until the node output signal is fully output or the synchronization pulse signal arrives; if the node output signal is fully output, continuing to output a compensation signal until the synchronization pulse signal arrives.

[0010] In some embodiments, the data synchronization method further includes: during the output of the node output signal, counting the period of the second clock signal to obtain a counting result; when the synchronization signal is valid, changing the counting result to a second preset value; when the synchronization signal is invalid, determining whether the counting result has reached a first preset value; if the counting result has reached the first preset value, maintaining the counting result at the first preset value until the synchronization signal is valid.

[0011] In some embodiments, after the counting result changes to a second preset value, the next node output signal is output after a preset number of second clock signal cycles.

[0012] In some embodiments, the second preset value is the next count value after the first preset value.

[0013] In some embodiments, the synchronization signal is generated based on the data input clock and a second clock signal, and each period of the synchronization signal is an integer multiple of the period of the second clock signal.

[0014] Secondly, this application provides a chip for performing the data synchronization method of the first aspect.

[0015] In some embodiments, the chip includes: a storage module configured to receive a node input signal based on a first clock signal; a digital-to-analog converter configured to output a node output signal based on a second clock signal; and a synchronization determination module configured to determine whether a synchronization signal is valid during the output of the node output signal; if the synchronization signal is valid, prepare to output the next node output signal; if the synchronization signal is invalid, maintain the output of the node output signal until the synchronization signal is valid.

[0016] In some embodiments, the synchronization determination module includes: a counting unit configured to count the period of a second clock signal to obtain a counting result; a first execution unit configured to determine whether the synchronization signal is valid, and when the synchronization signal is valid, change the counting result to a second preset value; and a second execution unit configured to determine whether the counting result reaches a first preset value when the synchronization signal is invalid, and if the counting result reaches the first preset value, maintain the counting result at the first preset value until the synchronization signal is valid.

[0017] Thirdly, this application provides a sound-following vibration system, comprising: a processor configured to output audio data and vibration waveform data; an audio driver chip configured to receive audio data and generate an audio analog signal based on the audio data; a vibration motor driver chip configured to receive vibration waveform data and generate a vibration analog signal based on the vibration waveform data; an audio player configured to receive the audio analog signal and play music based on the audio analog signal; and a vibration motor configured to receive the vibration analog signal and vibrate based on the vibration analog signal; wherein the audio driver chip and / or the vibration motor driver chip executes a data synchronization method as exemplified in the first aspect to synchronize the audio data and the audio analog signal, and / or synchronize the vibration waveform data and the vibration analog signal.

[0018] This application receives node input signals based on a first clock signal and outputs node output signals based on a second clock signal. During the output of the node output signal, if the synchronization signal is valid (e.g., a rising edge or falling edge arrives), the system prepares to output the next node output signal. If the synchronization signal is invalid and the node output signal is not fully output, the system continues to output the node output signal until it is fully output or the synchronization signal becomes valid. If the synchronization signal is invalid and the node output signal is fully output, the system continues to output a compensation signal until the synchronization signal becomes valid, ensuring that the node output signal is output once per cycle of the synchronization signal. Since the average period of the synchronization signal in this embodiment is equal to the period of the data input clock, the receiving frequency of the node input signal and the output frequency of the node output signal are comparable. Furthermore, since the first clock signal and the second clock signal can be signals from different sources and / or different phases, synchronization between the node output signal and the node input signal can be achieved without the need for a phase-locked loop circuit, which helps reduce the circuit area and manufacturing cost of the driver chip. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of data synchronization in related technologies;

[0021] Figure 2 This is a flowchart illustrating a data synchronization method provided in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the relevant signals provided in the embodiments of this application;

[0023] Figure 4 This is another schematic diagram of the relevant signals provided in the embodiments of this application;

[0024] Figure 5 This is a schematic diagram of a synchronization signal, a data input clock, and a second clock signal provided in an embodiment of this application;

[0025] Figure 6 This is another schematic diagram of the synchronization signal, data input clock, and second clock signal provided in the embodiments of this application;

[0026] Figure 7 This is a schematic diagram of a flow chart of the output signal of the output node provided in the embodiments of this application;

[0027] Figure 8 This is another schematic diagram of the relevant signals provided in the embodiments of this application;

[0028] Figure 9 This is a schematic diagram of a chip provided in an embodiment of this application;

[0029] Figure 10 This is another schematic diagram of the chip provided in the embodiments of this application;

[0030] Figure 11 This is a schematic diagram of a sound-following vibration system provided in the embodiments of this application.

[0031] The system includes 10 FIFO storage modules, 20 digital-to-analog converter modules, 30 timing modules, 40 synchronization judgment modules, 50 OSC clock modules, 100 processors, 200 audio driver chips, 300 motor driver chips, 400 audio players, and 500 vibration motors. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more described features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0034] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0035] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0036] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0037] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should be considered for specifying significant digits and employing a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this application are approximate values, in specific embodiments, such numerical values ​​are set as precisely as feasible.

[0038] For each patent, patent application, patent application publication, and other material such as articles, books, specifications, publications, and documents referenced in this application, the entire contents of that application are incorporated herein by reference, except for historical application documents that are inconsistent with or conflict with the content of this application, and documents that limit the broadest scope of the claims of this application (currently or subsequently appended to this application). It should be noted that if there are any inconsistencies or conflicts between the descriptions, definitions, and / or terminology used in the supplementary materials of this application and the examples in this application, the descriptions, definitions, and / or terminology used in this application shall prevail.

[0039] In some implementation scenarios, phase-locked loop (PLL) circuits can be used to ensure that the update clock frequencies of digital and analog signals share the same clock source, thereby guaranteeing the synchronization of digital and analog signals. See also... Figure 1 , Figure 1 The diagram illustrates a data synchronization method in related technologies. The data synchronization circuit includes a First-In-First-Out (FIFO) memory and a Phase-Locked Loop (PLL) circuit. Node data is stored in the FIFO memory via a bus according to the input clock. Simultaneously, the PLL circuit obtains the output clock by multiplying the input clock. The node data in the FIFO outputs an output signal of the corresponding frequency according to the output clock. Since the input clock and output clock are associated based on the PLL and share the same clock source, the synchronization between the input and output signals can be guaranteed.

[0040] However, to achieve synchronization between input and output signals using this technology, a phase-locked loop circuit needs to be set in the corresponding chip (such as a motor driver chip or an audio driver chip), which leads to an increase in the area of ​​the driver chip and an increase in the cost of a single chip.

[0041] Therefore, this application provides a data synchronization method, a chip, and a sound-following vibration system, which will be described in detail below.

[0042] First, refer to Figure 2 , Figure 2 A flowchart of a data synchronization method in an embodiment of this application is shown, wherein the data synchronization method includes steps S201 to S203.

[0043] Step S201: Receive node input signals based on the first clock signal.

[0044] In some embodiments, the node input signal can be input to the memory via a bus based on a first clock signal and a data input clock, thereby completing the node input signal reception process.

[0045] Generally, the first clock signal and the data input clock are from the same source, meaning that the first clock signal and the data input clock can be generated based on the same crystal oscillator circuit. For example, the bus can be an I2C bus, an I2S bus, an SPI bus, a CAN bus, or an SSP bus, and the memory can be a synchronous first-in-first-out (FIFO) memory or an asynchronous FIFO memory.

[0046] Specifically, the node input signal is received once per cycle of the data input clock. Taking the I2S bus using the standard IIS mode to transmit node input signals as an example, the input frequency of the node input signal is 48kHz, the data length of each node input signal is 32 bits, that is, the period of the data input clock is 1 / 48000 seconds, and the node input signal is received once every 1 / 48000 seconds. Furthermore, the frequency of the first clock signal is 32 * 48kHz = 1.536mHz. Taking the I2S bus using the standard TMD mode to transmit node input signals as an example, the input frequency of the node input signal is 48kHz, the data length of each node input signal is 64 bits, that is, the period of the data input clock is 1 / 48000 seconds, and the node input signal is received once every 1 / 48000 seconds. Furthermore, the frequency of the first clock signal is 64 * 48kHz = 3.072mHz.

[0047] In some embodiments, the node input signal can be received once every preset number of first clock signal cycles. For example, when the memory receives the node input signal, the memory counts the first clock signal. When the count reaches a set value (e.g., from 0 to 31), it indicates that a node input signal with a data length of 32 bits has been received. The memory then resets the count and begins receiving the next node input signal, and so on, in a cyclical manner. In one example, if the data length of each node input signal is 32 bits and the frequency of the first clock signal is 1.536 MHz, then the fixed duration is 1 / 1.536 MHz * 32 = 1 / 48000 seconds.

[0048] Step S202: Output the node output signal based on the second clock signal (on-chip OSC).

[0049] It should be noted that since the node input signal is received once in each cycle of the data input clock, after the Nth node input signal is received, the memory has already written the complete N-1th node input signal. Therefore, after the Nth node input signal is received (for example, after a preset number of second clock signal cycles), the circuit (e.g., a digital-to-analog converter) can start outputting the Nmth node output signal based on the second clock signal and the synchronization signal according to the Nmth node input signal received in the memory, where m is a positive integer greater than or equal to 1.

[0050] Generally, the second clock signal and the synchronization signal are clock signals from the same source, and the second clock signal and the synchronization signal can be generated based on the same crystal oscillator circuit.

[0051] Specifically, the node output signal can be generated based on a second clock signal that is from a different source and / or in a different phase from the first clock signal. In other words, there is no need to set up a phase-locked loop (PLL) circuit to generate the second clock signal based on the first clock signal, or no need to set up a PLL circuit to generate the second clock signal based on the data input clock. In one example, the first clock signal can be generated based on a crystal oscillator circuit, while the second clock signal is generated based on another crystal oscillator circuit.

[0052] In some embodiments, the ideal frequency of the second clock signal may be different from the frequency of the first clock signal. For example, taking the I2S bus using the standard IIS mode to transmit node input signals as an example, the input frequency of the node input signal is 48kHz, the data length of each node input signal is 32 bits, the frequency of the first clock signal is 32*48kHz=1.536mHz, the output frequency of the node output signal is also 48kHz, and the ideal data length of each node output signal is 128 bits. Then the ideal frequency of the second clock signal is 128*48kHz=6.144mHz.

[0053] In some embodiments, the ideal frequency of the second clock signal may be equal to the frequency of the first clock signal.

[0054] It should be noted that in the specific circuit implementation, the actual frequency of the second clock signal deviates from the ideal frequency. This deviation will cause the node output signal and the node input signal to be input and output asynchronously. Moreover, as time goes on, the synchronization error between the node output signal and the node input signal caused by this frequency deviation becomes larger and larger. Therefore, a synchronization signal is needed to correct the synchronization between the node output signal and the node input signal.

[0055] Step S203: During the output process of the node output signal, determine whether the synchronization signal is valid.

[0056] It should be noted that determining whether a synchronization signal is valid can refer to determining whether the rising edge or falling edge of the synchronization signal has arrived. For example, an edge trigger can be used to determine whether the rising edge or falling edge of the synchronization signal has arrived. When the rising edge / falling edge of the synchronization signal arrives, it indicates that the synchronization signal is valid.

[0057] Specifically, when the synchronization signal is invalid, if the node output signal has not been completed, the node output signal continues to be output until the node output signal is completed or the synchronization signal is valid. If the node output signal is completed, the compensation signal (such as a high-level signal, a low-level signal, or an alternating high-low level AC signal) continues to be output until the synchronization signal is valid. When the synchronization signal is valid, the node output signal can be prepared to be output for the next time, so that the node output signal is output once in each cycle of the synchronization signal.

[0058] In some embodiments, see Figure 3 , Figure 3 A schematic diagram of the relevant signals in an embodiment of this application is shown. During the output signal of the (N-1)th node, the output signal of the (N-1)th node has been completed before the synchronization signal is valid. Therefore, a compensation signal that remains at a low level is output until the synchronization signal is valid. When the synchronization signal is valid, the output of the current output signal of the (N-1)th node is immediately stopped, and the output of the Nth node signal is immediately started according to the input signal of the Nth node received by the memory.

[0059] In some embodiments, see Figure 4 , Figure 4Another schematic diagram of the relevant signals in the embodiment of this application is shown. During the process of outputting the N-1th node signal, the N-1th node output signal has been completed before the synchronization signal is valid. Therefore, a compensation signal that remains high is output until the synchronization signal is valid. After the synchronization signal is valid, the current N-1th node output signal continues to be output for a preset number (e.g., 3) cycles of the second clock signal. After the preset number of cycles of the second clock signal, the Nth node output signal is started to be output according to the Nth node input signal received by the memory.

[0060] It is understood that the accompanying drawings of this application are provided as an example with a preset quantity of 3, and do not constitute a limitation on this embodiment. In specific applications, the preset quantity can be set to any positive integer or 0.

[0061] This embodiment receives the node input signal based on a first clock signal and outputs the node output signal based on a second clock signal. During the output of the node output signal, if the synchronization signal is valid (e.g., a rising edge or falling edge arrives), the system prepares to output the next node output signal. If the synchronization signal is invalid and the node output signal is not fully output, the system continues to output the node output signal until it is fully output or the synchronization signal becomes valid. If the synchronization signal is invalid and the node output signal is fully output, the system continues to output a compensation signal until the synchronization signal becomes valid, ensuring that the node output signal is output once per cycle of the synchronization signal. Since the cycle of the synchronization signal in this embodiment is equal to the cycle of the data input clock, the receiving frequency of the node input signal and the output frequency of the node output signal are comparable. Furthermore, since the first clock signal and the second clock signal can be signals from different sources and / or different phases, synchronization between the node output signal and the node input signal can be achieved without a phase-locked loop circuit, which helps reduce the circuit area and manufacturing cost of the driver chip.

[0062] In some embodiments, such as an embodiment where the node input signal is received once every preset number of first clock signal periods, the average period of the synchronization signal is equal to the preset number of first clock signal periods.

[0063] In some embodiments, such as for a node input signal based on the first clock signal and a data input clock received, the average period of the synchronization signal is equal to the period of the data input clock.

[0064] In some embodiments, the synchronization signal includes a synchronization pulse signal. The step of determining whether the synchronization signal is valid during the output of the node output signal includes: determining whether a pulse of the synchronization pulse signal has arrived during the output of the node output signal; when a pulse of the synchronization pulse signal arrives, preparing to output the next node output signal; if a pulse of the synchronization pulse signal has not arrived, and the node output signal has not been completely output, continuing to output the node output signal until the node output signal is completely output or a pulse of the synchronization pulse signal arrives; if the node output signal is completely output, continuing to output a compensation signal until a pulse of the synchronization pulse signal arrives.

[0065] For example, taking the I2S bus using the standard IIS mode to transmit node input signals as an example, the period of the data input clock is 1 / 48000 seconds. If the first pulse period of the synchronization pulse signal is 1.2 / 48000 seconds, the second pulse period is 0.8 / 48000 seconds, the third pulse period is 0.9 / 48000 seconds, and the fourth pulse period is 1.1 / 48000 seconds, it can be seen that the average period of the synchronization pulse signal over these four pulse periods is also 1 / 48000 seconds. Therefore, from an overall perspective, the average period of the synchronization pulse signal is equal to the period of the data input clock. That is, the input frequency of the node input signal is comparable to the output frequency of the node output signal. This can ultimately prevent the input frequency of the node input signal from exceeding the output frequency of the node output signal, which would lead to an increasing amount of data stored in the memory and cause data overflow. Meanwhile, since the first clock signal and the second clock signal in this embodiment can be signals from different sources and / or different phases, the synchronization between the node output signal and the node input signal can be achieved without setting up a phase-locked loop circuit, which is beneficial to reduce the circuit area of ​​the driver chip and the manufacturing cost of a single chip.

[0066] In some embodiments, the synchronization signal is generated based on the data input clock and a second clock signal, and each pulse period of the synchronization signal is an integer multiple of the period of the second clock signal. See also Figure 5 , Figure 5 The diagram illustrates a synchronization signal, a data input clock, and a second clock signal in an embodiment of this application. After the first rising edge of the data input clock arrives, and the rising edge of the second clock signal arrives, the synchronization signal generating circuit outputs a first pulse. The pulse period of the first pulse is 13 cycles of the second clock signal. After the second rising edge of the data input clock arrives, and the rising edge of the second clock signal arrives, the synchronization signal generating circuit (e.g., a pulse generator) outputs a second pulse. The pulse period of the second pulse is 12 cycles of the second clock signal.

[0067] As can be seen, since the pulse of the synchronization signal can only be output after the rising edge of the data input clock and the second clock signal are valid, the pulse of the synchronization signal is actually controlled by the data input clock. Furthermore, each period of the synchronization signal can be made to be an integer multiple of the period of the second clock signal, so that the average period of the synchronization signal is equal to the period of the data input clock. Thus, the average period of each output of the node output signal is equal to the period of the data input clock, and the duration of each output is an integer multiple of the period of the second clock signal.

[0068] In some embodiments, the synchronization signal generating circuit that outputs the synchronization signal may include digital circuits composed of flip-flops, pulse generators, logic gate circuits, etc.

[0069] In some embodiments, the synchronization signal may also be generated based on the delayed data input clock and a second clock signal, for example, see [reference needed]. Figure 6 , Figure 6 This illustration shows another schematic diagram of the synchronization signal, data input clock, and second clock signal in an embodiment of this application. The delayed data input clock has the same period as the original data input clock, which also makes the average period of the synchronization signal equal to the period of the data input clock.

[0070] In some embodiments, see Figure 7 , Figure 7 The diagram illustrates a flow chart of the output signal of the output node in an embodiment of this application. The data synchronization method further includes steps S701 to S704.

[0071] Step S701: During the output process of the node output signal, the period of the second clock signal is counted to obtain the counting result.

[0072] Step S702: When the synchronization signal is invalid, determine whether the counting result has reached the first preset value.

[0073] Step S703: If the counting result reaches the first preset value, the counting result is kept at the first preset value until the synchronization signal is valid.

[0074] Step S704: When the synchronization signal is valid, change the counting result to the second preset value.

[0075] It should be noted that the change of the counter's count result to the second preset value indicates that it is ready to output the next node output signal. Therefore, when the synchronization signal is valid, after changing the count result to the second preset value, regardless of whether the counter's count result reaches the first preset value, it is ready to output the next node output signal. This is equivalent to shortening the output duration of the node output signal by one or more cycles of the second clock signal. Conversely, when the synchronization signal is invalid, if the counter's count result reaches the first preset value, the count result is maintained at the first preset value until the synchronization signal is valid. During the process of maintaining the count result at the first preset value, a low-level compensation signal is output, which is equivalent to extending the output duration of the node output signal by the number of cycles of the second clock signal during the process of maintaining the count result at the first preset value.

[0076] As can be seen, this embodiment can shorten the output duration of the node output signal and extend the output duration of the node output signal by counting the period of the second clock signal and combining the control logic of whether the synchronization signal is valid and whether the counting result reaches the first preset value. Ultimately, the output frequency of the node output signal is comparable to the input frequency of the node input signal, thereby avoiding the phenomenon of memory data overflow.

[0077] In some embodiments, after the counting result changes to a second preset value, the next node output signal is output after a preset number of second clock signal cycles. See also Figure 8 , Figure 8 A schematic diagram of the relevant signals in an embodiment of this application is shown, wherein after the counting result changes to the second preset value, the next node output signal is output after an interval of 3 cycles of the second clock signal.

[0078] It should be noted that the accompanying drawings of this application use a preset number of second clock signals with a period of 3 as an example, which does not constitute a limitation on this embodiment; in specific applications, the preset number of second clock signals can be spaced out as 0, 1, 2 or even more second clock signals.

[0079] In some embodiments, the second preset value is the next count value after the first preset value, see reference. Figure 8Taking a forward cyclic counting from 0, 1, 2...127 as an example, when the count result is 0, the next count value is 1; when the count result is 125, the next count value is 126; and when the count result is 127, the next count value is 0. If the first preset value is 124, then the second preset value is 125. During the output of the (N-1)th node output signal, the count result is 123 when the synchronization signal is valid, and changes to 125 after the synchronization signal is valid. During the output of the (N-2)th node output signal, the count result remains at 124 when the synchronization signal is valid, and changes to 125 after the synchronization signal is valid. After the count result changes to 125, the count result changes to 0 after 3 cycles of the second clock signal. Therefore, in some embodiments, the node output signal can be output starting each time the count result is 0.

[0080] In other embodiments, taking the negative cyclic counting of count results 127, 126, 125...0 as an example, when the count result is 127, the next count result is 126; when the count result is 4, the next count result is 3; when the count result is 0, the next count result is 127. If the first preset value is 4, then the second preset value is 3. Combined with the embodiment where the next node output signal is output after the count result changes to the second preset value and the interval is 3 cycles of the second clock signal, that is, in some embodiments, the node output signal can be output every time the count result is 0.

[0081] It is understood that the above embodiments are illustrated by taking integer counting as an example and do not constitute a limitation on this embodiment. In some embodiments, the counting results can also be counted sequentially by a set code. For example, they can be counted sequentially in the manner of odd numbers 1, 3, 5...127, or in the manner of even numbers 0, 2, 4, 6...126.

[0082] It is worth noting that the above content regarding the data synchronization method is intended to clearly illustrate the implementation and verification process of this application. Those skilled in the art can also make equivalent modifications under the guidance of this application. For example, the delayed data input clock can be used as a synchronization signal for the output node output signal, thus making the average period of the synchronization signal equal to the period of the data input clock.

[0083] To better implement the data synchronization method in the embodiments of this application, another embodiment of this application provides a chip for executing the data synchronization method as described in any of the above embodiments. For example, the chip can be a motor driver chip or an audio driver chip. Since the chip in the embodiments of this application has all the beneficial effects of the data synchronization method described above, it will not be elaborated further here.

[0084] See Figure 9 , Figure 9 The diagram illustrates a module of a chip in an embodiment of this application. The chip includes a storage module 10, a digital-to-analog converter module 20, and a synchronization judgment module 40. The storage module 10 receives node input signals based on a first clock signal and a data input clock. Simultaneously, the storage module 10 outputs node output signals based on a second clock signal generated by the OSC clock module 30. The digital-to-analog converter module 20 outputs a PWM signal based on the node output signals. The synchronization judgment module 40 determines whether a synchronization signal (e.g., whether a pulse has arrived) is valid during the output of the node output signals. If the synchronization signal is valid, it prepares to output the next node output signal; if the synchronization signal is invalid, and the node output signal has not been fully output, it continues to output the node output signal until the node output signal is fully output or the synchronization signal is valid. If the node output signal is fully output, it continues to output a compensation signal until the synchronization signal is valid.

[0085] In some embodiments, see Figure 10 The diagram shows another module of the chip in this embodiment of the application. The synchronization judgment module 40 includes a counting unit 41, a first execution unit 42, and a second execution unit 43. The counting unit 41 is configured to count the period of the second clock signal to obtain a counting result. The counting result is used to output a PWM signal according to the node output signal. The first execution unit 42 is configured to determine whether the synchronization signal is valid. When the synchronization signal is valid, the counting result is changed to a second preset value. The second execution unit 43 is configured to determine whether the counting result has reached a first preset value when the synchronization signal is invalid. If the counting result has reached the first preset value, the counting result is kept at the first preset value until the synchronization signal is valid.

[0086] It should be noted that, Figure 9 or Figure 10The modules shown can be implemented in various ways. For example, in some embodiments, the device and its modules can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the methods and systems described above can be implemented using computer-executable instructions and / or included in processor control code.

[0087] The chip and its module provided in this embodiment can be implemented not only by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic circuits and transistors, or programmable hardware devices such as field-programmable gate arrays and programmable logic devices, but also by a combination of the above hardware circuits and software (e.g., firmware).

[0088] It should be noted that the above description of the device and its modules is for convenience only and should not be construed as limiting this application to the scope of the embodiments described. It is understood that those skilled in the art, after understanding the principle of the system, may arbitrarily combine the various modules or construct subsystems connected to other modules without departing from this principle. For example, Figure 9 or Figure 10 The digital-to-analog conversion module 20 and the synchronization judgment module 40 disclosed herein can be different modules in a system, or a single module can implement the functions of two or more of the above modules.

[0089] To better implement the chip in the embodiments of this application, another embodiment of this application also provides a sound-following vibration system based on the chip. (See attached document.) Figure 11 , Figure 11 A schematic diagram of a sound-following vibration system according to an embodiment of this application is shown. The sound-following vibration system includes: a processor 100 configured to output audio data and vibration waveform data; an audio driver chip 200 configured to receive audio data and generate an audio analog signal based on the audio data; a vibration motor driver chip 300 configured to receive vibration waveform data and generate a vibration analog signal based on the vibration waveform data; an audio player 400 configured to receive the audio analog signal and play music based on the audio analog signal; and a vibration motor 500 configured to receive the vibration analog signal and vibrate based on the vibration analog signal.

[0090] The audio driver chip 200 and / or vibration motor driver chip 300 in the sound-following vibration system provided in this embodiment can execute the data synchronization method as described in any of the above embodiments. Therefore, they can synchronize audio data and audio analog signals, and / or synchronize vibration waveform data and vibration analog signals, avoiding the loss of audio data and vibration waveform data. Since the driver chip in the sound-following vibration system of this application embodiment is equipped with the data synchronization method of the above embodiments, it has all the beneficial effects of the above data synchronization method, which will not be repeated here.

[0091] In some embodiments, the processor uses the same protocol to transmit audio data and vibration waveform data. For example, taking the I2S protocol to transmit audio data and vibration waveform data, the left channel of the I2S bus can be used to transmit audio data to the audio driver chip, while the right channel transmits vibration waveform data to the motor driver chip. This allows the audio data and vibration waveform data to be transmitted synchronously, enabling the audio player and motor to work synchronously to better achieve the sound-following vibration effect and ultimately avoid the phenomenon of asynchrony between audio signals and vibration signals.

[0092] To better implement the sound-following vibration system in the embodiments of this application, another embodiment of this application provides an electronic device, which may be, but is not limited to, a car, a smart wearable device, a mobile terminal, or a smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and point-of-sales terminals (POS). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0093] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0094] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0095] The data synchronization method, driving chip, and sound-following vibration system provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A data synchronization method, characterized in that, include: The input signal of the receiving node is based on the first clock signal; The output node outputs a signal based on the second clock signal; During the output process of the node's output signal, it is determined whether the synchronization signal is valid; When the synchronization signal is valid, prepare to output the next node output signal; If the synchronization signal is invalid, and the node output signal has not been completed, the node output signal will continue to be output until the node output signal is completed or the synchronization signal is valid; if the node output signal is completed, the compensation signal will continue to be output until the synchronization signal is valid.

2. The data synchronization method as described in claim 1, characterized in that, The node input signal is received once every preset number of first clock signal cycles; Wherein, the first clock signal and the second clock signal are signals from different sources and / or different phases, and the average period of the synchronization signal is equal to the period of the preset number of first clock signals.

3. The data synchronization method as described in claim 1, characterized in that, The node input signal is received based on the first clock signal and the data input clock, and the node input signal is received once in each cycle of the data input clock. The first clock signal and the second clock signal are signals from different sources and / or different phases, and the average period of the synchronization signal is equal to the period of the data input clock.

4. The data synchronization method as described in claim 2 or 3, characterized in that, The synchronization signal includes a synchronization pulse signal, and the step of determining whether the synchronization signal is valid during the output process of the node output signal includes: During the output process of the node's output signal, it is determined whether the pulse of the synchronization signal has arrived; When the pulse of the synchronization pulse signal arrives, prepare to output the next node output signal; If the node output signal has not been completed before the pulse of the synchronization pulse signal arrives, the node output signal continues to be output until the node output signal is completed or the pulse of the synchronization pulse signal arrives; if the node output signal has been completed, the compensation signal continues to be output until the pulse of the synchronization pulse signal arrives.

5. The data synchronization method as described in claim 1, characterized in that, The method further includes: During the output process of the node output signal, the period of the second clock signal is counted to obtain a counting result; When the synchronization signal is valid, the counting result is changed to a second preset value; When the synchronization signal is invalid, determine whether the counting result has reached a first preset value. If the counting result has reached the first preset value, keep the counting result at the first preset value until the synchronization signal is valid.

6. The data synchronization method as described in claim 5, characterized in that, After the counting result changes to the second preset value, after a preset number of cycles of the second clock signal, the next node output signal is output.

7. The data synchronization method as described in claim 5, characterized in that, The second preset value is the next count value after the first preset value.

8. The data synchronization method as described in claim 4, characterized in that, The synchronization signal is generated based on the second clock signal, and each period of the synchronization signal is an integer multiple of the period of the second clock signal.

9. A chip, characterized in that, The chip is used to perform the data synchronization method as described in any one of claims 1 to 8.

10. The chip as described in claim 9, characterized in that, The chip includes: The storage module is configured to receive node input signals based on a first clock signal; The digital-to-analog converter module is configured to output a signal based on the second clock signal output node; The synchronization judgment module is configured to, during the output of the node output signal, determine whether the synchronization signal is valid; when the synchronization signal is valid, prepare to output the next node output signal; when the synchronization signal is invalid, if the node output signal has not been completely output, continue to output the node output signal until the node output signal is completely output or the synchronization signal is valid; if the node output signal is completely output, continue to output a compensation signal until the synchronization signal is valid.

11. The chip as described in claim 10, characterized in that, The synchronization determination module includes: The counting unit is configured to count the period of the second clock signal to obtain a counting result; The first execution unit is configured to determine whether the synchronization signal is valid, and when the synchronization signal is valid, change the counting result to a second preset value. The second execution unit is configured to, when the synchronization signal is invalid, determine whether the counting result has reached a first preset value; if the counting result has reached the first preset value, maintain the counting result at the first preset value until the synchronization signal is valid.

12. A sound-following vibration system, characterized in that, include: The processor is configured to output audio data and vibration waveform data; An audio driver chip is configured to receive the audio data and generate an analog audio signal based on the audio data; A vibration motor driver chip is configured to receive the vibration waveform data and generate a vibration analog signal based on the vibration waveform data; An audio player is configured to receive the analog audio signal and play music based on the analog audio signal; A vibration motor is configured to receive the vibration simulation signal and vibrate based on the vibration simulation signal; The audio driver chip and / or the vibration motor driver chip perform the data synchronization method as described in any one of claims 1 to 8.

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