Connection relationship establishment method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a connection relation establishing method and device, a storage medium and electronic device.The method comprises the steps that target combinational logic with the fan-out number meeting a preset condition is determined, and a start register, a first end point register set and a logic gate in a combinational logic path corresponding to the target combinational logic are determined; copying the start register and the logic gate to obtain a first copy register and a first copy logic gate; and establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and a first endpoint register of the first endpoint register set.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip design, and specifically, to a method and device for establishing a connection relationship, a storage medium, and an electronic device. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the feature size of semiconductor manufacturing technology has been gradually reduced, the integration of chips has been greatly increased, and the chip structure has become increasingly complex. In current chip design, the increase in the number of logic gates and the reduction in chip size require chip designers to save area and maximize the number of logic in a limited area. If you cannot plan in advance and take corresponding measures to design from the beginning of the design, many difficult problems may arise during the back-end design of the chip, such as timing violations caused by the scattered placement of registers or excessive insertion of buffers to fix the register-to-register / ICGs enable timing. In IC design, high fan-out is a common problem. Excessive fan-out is a common type of situation that easily causes timing violations. Excessive fan-out will significantly deteriorate the jump of the connection point. Especially when processing clock and reset signals. These signals usually need to drive multiple logic gates, resulting in a high fan-out number. It may cause signal quality degradation, increase delay, cause offset violations, and affect the normal operation of the chip.

[0003] Regarding the related technology, in integrated circuit design, high fan-out combinational logic causes timing violations, and no effective solution has been proposed yet.

[0004] Therefore, it is necessary to improve the related technology to overcome the above-mentioned defects in the related technology. Summary of the invention

[0005] The embodiments of the present application provide a method and device for establishing a connection relationship, a storage medium, and an electronic device to at least solve the problem of timing violations caused by high fan-out combinational logic in integrated circuit design in the related art.

[0006] According to one embodiment of the present application, a method for establishing a connection relationship is provided, including: determining a target combinational logic whose fan-out number meets a preset condition, and determining a starting register, a first end register set, and a logic gate in a combinational logic path corresponding to the target combinational logic; copying the starting register and the logic gate to obtain a first copy register and a first copy logic gate; establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and the first end register of the first end register set.

[0007] In an exemplary embodiment, establishing a first connection relationship between the first copy register and the first copy logic gate includes: determining a third connection relationship between the start register and the logic gate; and establishing a first connection relationship between the first copy register and the first copy logic gate according to the third connection relationship.

[0008] In an exemplary embodiment, after establishing a first connection relationship between the first copy register and the first copy logic gate according to the third connection relationship, the method further includes: determining whether there are other logic gates in the combinational logic path, wherein the other logic gates are logic gates of the previous stage of the logic gate, and the other logic gates are not copied; in the case of determining that the other logic gates exist in the combinational logic path, determining a fourth connection relationship between the logic gate and the other logic gates; and establishing a fifth connection relationship between the first copy logic gate and the other logic gates according to the fourth connection relationship.

[0009] In an exemplary embodiment, before or after establishing the second connection relationship between the first copy logic gate and the first destination register of the first destination register set, the method further includes: when there are multiple first copy logic gates, determining a sixth connection relationship between the pairwise logic gates; and establishing a seventh connection relationship between the pairwise first copy logic gates according to the sixth connection relationship between the pairwise logic gates, wherein the pairwise logic gates have a corresponding relationship with the pairwise first copy logic gates.

[0010] In an exemplary embodiment, before establishing a second connection relationship between the first copy logic gate and the first destination register of the first destination register set, the method also includes: determining the number of registers in the first destination register set; and determining the first destination register in the first destination register set according to a preset ratio and the number.

[0011] In an exemplary embodiment, determining the starting register, the first terminal register set, and the logic gate in the combinational logic path corresponding to the target combinational logic includes: determining the area of ​​the chip corresponding to the target combinational logic; when the area is greater than or equal to a preset area, determining the first N levels of logic gates of the first terminal register set, and determining the starting register having a connection relationship with the logic gates of the first N levels, wherein N is a positive integer; when the area is less than the preset area, determining the first M levels of logic gates of the first terminal register set, and determining the starting register having a connection relationship with the logic gates of the first M levels, wherein M is a positive integer less than or equal to N.

[0012] In an exemplary embodiment, after establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and the first terminal register of the first terminal register set, the method further includes: determining whether the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition; if the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition, determining the starting register, the second terminal register set and the logic gate in the updated combinational logic path; copying the starting register and the logic gate in the updated combinational logic path to obtain a second copy register and a second copy logic gate; establishing a connection relationship between the second copy register and the second copy logic gate, and establishing a connection relationship between the second copy logic gate and the second terminal register of the second terminal register set; if the fan-out number of the combinational logic in the updated combinational logic path does not meet the preset condition, stopping updating the combinational logic path.

[0013] According to another embodiment of the present application, a device for establishing a connection relationship is provided, including: a determination module, used to determine a target combinational logic whose fan-out number meets preset conditions, and determine a starting register, a first terminal register set and a logic gate in a combinational logic path corresponding to the target combinational logic; a copy module, used to copy the starting register and the logic gate to obtain a first copy register and a first copy logic gate; an establishment module, used to establish a first connection relationship between the first copy register and the first copy logic gate, and establish a second connection relationship between the first copy logic gate and the first terminal register of the first terminal register set.

[0014] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0015] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0016] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0017] Through the present application, the target combinational logic whose fan-out number meets the preset conditions is determined, and the starting register, the first terminal register set and the logic gate in the combinational logic path corresponding to the target combinational logic are determined; the starting register and the logic gate are copied to obtain the first copy register and the first copy logic gate; a first connection relationship between the first copy register and the first copy logic gate is established, and a second connection relationship between the first copy logic gate and the first terminal register of the first terminal register set is established, that is, in the embodiment of the present application, by copying the starting register and the logic gate in the high fan-out logic combination, and establishing the copied register, logic gate and target terminal register, the fan-out number in the original logic combination is reduced, thereby alleviating the problem of timing violation. Therefore, the problem of timing violation caused by high fan-out combinational logic in integrated circuit design can be solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a hardware structure block diagram of a computer device of a method for establishing a connection relationship in an embodiment of the present application;

[0019] Figure 2 is a flow chart of a method for establishing a connection relationship according to an embodiment of the present application;

[0020] Figure 3 is a flow chart of a method for establishing a connection relationship according to an optional embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a method for establishing a connection relationship according to an embodiment of the present application;

[0022] Figure 5 It is a structural block diagram of a device for establishing a connection relationship according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0025] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 FIG. 1 is a hardware structure diagram of a server device of a method for establishing a connection relationship in an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1Only one is shown in the figure) processor 102 (processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0026] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for establishing the connection relationship in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0027] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0028] In this embodiment, a method for establishing a connection relationship is provided. Figure 2 is a flow chart of a method for establishing a connection relationship according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0029] Step S202, determining a target combinational logic whose fan-out number meets a preset condition, and determining a starting register, a first end register set, and a logic gate in a combinational logic path corresponding to the target combinational logic;

[0030] Step S204, copying the starting register and the logic gate to obtain a first copy register and a first copy logic gate;

[0031] Step S206: establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and the first destination register of the first destination register set.

[0032] It should be noted that the “first duplicate logic gate” refers to a logic gate duplicated from an original high fan-out logic gate; and the “first duplicate register” refers to a register duplicated from an original high fan-out register.

[0033] Through the above steps, the target combinational logic whose fan-out number meets the preset conditions is determined, and the starting register, the first terminal register set and the logic gate in the combinational logic path corresponding to the target combinational logic are determined; the starting register and the logic gate are copied to obtain the first copy register and the first copy logic gate; a first connection relationship between the first copy register and the first copy logic gate is established, and a second connection relationship between the first copy logic gate and the first terminal register of the first terminal register set is established, that is, in the embodiment of the present application, by copying the starting register and the logic gate in the high fan-out logic combination, and establishing the copied register, logic gate and target terminal register, the fan-out number in the original logic combination is reduced, thereby alleviating the problem of timing violation. Therefore, the problem of timing violation caused by high fan-out combinational logic in integrated circuit design can be solved.

[0034] The execution subject of the above steps may be a computer terminal, etc., but is not limited thereto.

[0035] Optionally, the "establishing a first connection relationship between the first copy register and the first copy logic gate" in the above step S206 can be implemented in the following way: determining a third connection relationship between the starting register and the logic gate; and establishing a first connection relationship between the first copy register and the first copy logic gate according to the third connection relationship.

[0036] That is to say, in the embodiment of the present application, the connection relationship between the first copy register and the first copy logic gate is established by copying the connection relationship between the starting register and the logic gate. For example, when the starting register 1 is directly connected to the logic gate 1, a direct connection relationship between the copy register 1 and the copy logic gate 1 is established; when the starting register 1 and the logic gate 1 are connected based on the logic gate 2, a connection relationship between the copy register 1 and the copy logic gate 2, and a connection relationship between the copy logic gate 2 and the copy logic gate 1 are established; however, when the copy logic gate 2 does not exist, a connection relationship between the copy register 1 and the logic gate 2, and a connection relationship between the logic gate 2 and the copy logic gate 1 are established.

[0037] The embodiment of the present application analyzes and understands the propagation of signals in the original design, especially the load and delay problems of signals under high fan-out conditions, and then specifically copies registers and logic gates and reestablishes the connection relationship between them to disperse the load, reduce delays, improve signal quality and improve timing performance. This method can not only solve the direct problems caused by high fan-out, such as timing violations and congestion, but also optimize the overall layout and performance of the circuit to a certain extent, reduce the difficulty and time of subsequent layout and wiring, and improve the efficiency and reliability of chip design.

[0038] Optionally, after establishing the first connection relationship between the first copy register and the first copy logic gate according to the third connection relationship, the following steps need to be performed: determining whether there are other logic gates in the combinational logic path, wherein the other logic gates are logic gates of the previous stage of the logic gate, and the other logic gates are not copied; when it is determined that the other logic gates exist in the combinational logic path, determining a fourth connection relationship between the logic gate and the other logic gates; and establishing a fifth connection relationship between the first copy logic gate and the other logic gates according to the fourth connection relationship.

[0039] In the embodiment of the present application, it is also necessary to identify whether there are other uncopied previous-stage logic gates in the original combinational logic path in addition to the logic gates that have been identified and planned to be copied. Once the existence of uncopied previous-stage logic gates is identified, it is necessary to analyze the connection relationship between the other logic gates and the target logic gate. Since the connection relationship between the other logic gates and the target logic gate involves the direction of the signal flow, the conditions for data transmission, etc., it must be accurately copied when copying the connection relationship.

[0040] Based on the original logic relationship, a new connection relationship between the copied logic gates and the uncopied logic gates is established. This new relationship should fully reflect and maintain the original logic function and data flow, ensuring that the copied path is functionally equivalent to the original path, while solving the high fan-out problem.

[0041] That is to say, in the embodiment of the present application, when copying registers and logic gates, the entire logic path can be fully processed, including identifying and optimizing all related logic gates to achieve timing convergence, reduce congestion and improve signal integrity. This method improves the accuracy and efficiency of solving timing problems in the synthesis stage, and avoids the additional area consumption and debugging work caused by blindly copying logic units. By combining algorithmic analysis and manual instructions, designers can optimize the design more flexibly and controllably, especially when dealing with high fan-out problems. This method provides a more sophisticated solution.

[0042] Optionally, before or after establishing the second connection relationship between the first copy logic gate and the first destination register of the first destination register set, the following scheme needs to be executed: when the number of the first copy logic gates is multiple, determine the sixth connection relationship between the pairwise logic gates; establish the seventh connection relationship between the pairwise first copy logic gates based on the sixth connection relationship between the pairwise logic gates, wherein the pairwise logic gates have a corresponding relationship with the pairwise first copy logic gates.

[0043] In an embodiment of the present application, for logic gates with high fan-out, it may be necessary to copy multiple logic gates to distribute the load, thereby reducing the fan-out of each logic gate and improving the driving capability and timing performance of the signal. The "sixth connection relationship" is used to indicate the connection method between the original logic gates. After copying the logic gates, it is first necessary to determine the connection relationship between the original logic gates, such as how they are connected through signal lines (nets), the order and direction of the connection, and any possible combinational logic relationships. The "seventh connection relationship" refers to the new connection relationship established between the copied logic gates. Determining the seventh connection relationship based on the sixth connection relationship means determining how to connect the copied logic gates based on the connection relationship between the original logic gates to maintain the consistency of the circuit function while optimizing the timing path and fan-out.

[0044] Through the embodiments of the present application, for each logic gate in the original circuit, there are one or more duplicated logic gates corresponding thereto, and the connection relationship between them is also kept consistent through the conversion from the "sixth connection relationship" to the "seventh connection relationship". This correspondence helps to ensure that the duplication operation does not change the basic function of the circuit, while being able to effectively disperse the load and optimize the timing. That is, by intelligently duplicating the logic gates and re-establishing the connection between them, the circuit performance is optimized. This method not only solves the high fan-out problem, but also maintains the integrity of the circuit function, and is an effective means to improve reliability and performance in design. In actual operation, specific functions of EDA tools, such as logic duplication, fan-out analysis, timing checking, etc., can also be used, combined with design rule checking (DRC) and layout and wiring (routing) strategies, to achieve circuit design optimization.

[0045] In an exemplary embodiment, before establishing a second connection relationship between the first copy logic gate and the first destination register of the first destination register set, the method also includes: determining the number of registers in the first destination register set; and determining the first destination register in the first destination register set according to a preset ratio and the number.

[0046] It should be noted that the above-mentioned "first destination register set" includes all target registers in the high fan-out problem, that is, those registers that need to be optimized or may cause timing problems. The above-mentioned "preset ratio" can be an empirical value or can be based on specific design rules or goals (such as one-half).

[0047] Based on this preset ratio and the number of registers calculated previously, the algorithm will select a certain number of registers for optimization operations, such as duplication or reconfiguration. The number of registers selected is based on a certain ratio of the total number of registers in the set to ensure that the optimization is both effective and not excessive, avoiding unnecessary increases in area and power consumption.

[0048] The embodiment of the present application solves the high fan-out timing problem through quantitative analysis (determining the number of registers) and intelligent decision-making (selecting the registers that need to be optimized according to a preset ratio). It combines automation and empirical rules to improve design efficiency and reduce manual intervention while ensuring design quality, thereby achieving the best design effect within limited resources and time.

[0049] Through the parameter of "preset ratio", the scope and effect of optimization are balanced, avoiding the waste of resources caused by blind copying. Instead, the registers on the critical path are processed in a targeted manner, thereby achieving the goal of both solving the problem and controlling costs.

[0050] In an exemplary embodiment, determining the starting register, the first terminal register set, and the logic gate in the combinational logic path corresponding to the target combinational logic includes: determining the area of ​​the chip corresponding to the target combinational logic; when the area is greater than or equal to a preset area, determining the first N levels of logic gates of the first terminal register set, and determining the starting register having a connection relationship with the logic gates of the first N levels, wherein N is a positive integer; when the area is less than the preset area, determining the first M levels of logic gates of the first terminal register set, and determining the starting register having a connection relationship with the logic gates of the first M levels, wherein M is a positive integer less than or equal to N.

[0051] That is, according to the different chip areas, the depth of the target combinational logic path analysis is dynamically adjusted to optimize the processing of registers and logic gates in the design. The details are as follows:

[0052] The depth of the register to be copied is determined based on whether the chip area exceeds a preset threshold (preset area). The setting of the preset area is usually based on empirical data in chip design, which reflects that the optimization strategy for the logic path may need to be adjusted under different area conditions.

[0053] When the area is greater than or equal to the preset area, there is more area to carry the duplicated logic gates. Therefore, the algorithm determines the first N levels of logic gates of the first destination register set and the starting registers associated with these logic gates. Here N is a positive integer.

[0054] When the area is smaller than the preset area, that is, the chip area is smaller, it may mean a more compact design, so there is not much area to carry the duplicated logic gates. At this time, the algorithm will determine the first M-level logic gates of the first terminal register set and the corresponding starting registers, where M≤N. That is, in the case of a smaller area, the optimization strategy may focus more on local optimization to avoid unnecessary resource consumption.

[0055] The embodiments of the present application distinguish different chip areas and adopt different depths of analysis and optimization strategies. The present invention embodies flexibility and intelligence in chip design. When the area is large, in-depth analysis can more comprehensively identify and optimize potential problem points, such as high fan-out, congestion or timing violations. When the area is small, more emphasis is placed on local optimization to avoid unnecessary resource consumption.

[0056] In an exemplary embodiment, after establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and the first terminal register of the first terminal register set, the method further includes: determining whether the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition; if the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition, determining the starting register, the second terminal register set and the logic gate in the updated combinational logic path; copying the starting register and the logic gate in the updated combinational logic path to obtain a second copy register and a second copy logic gate; establishing a connection relationship between the second copy register and the second copy logic gate, and establishing a connection relationship between the second copy logic gate and the second terminal register of the second terminal register set; if the fan-out number of the combinational logic in the updated combinational logic path does not meet the preset condition, stopping updating the combinational logic path.

[0057] That is to say, after establishing the first connection relationship between the first copy register and the first copy logic gate, the inventive method will further check whether the fan-out number of the combinational logic in the updated path meets the preset conditions. The above preset conditions refer to the threshold value of the fan-out number to ensure the driving capability and integrity of the signal. If the fan-out number in the updated combinational logic path meets the preset conditions, it is necessary to determine the starting register, the second end register set and the logic gate in the path again. The above "second end register set" refers to the object to be processed in the next round after the first round of optimization. Copy the determined starting register and logic gate to obtain the second copy register and the second copy logic gate, and establish a connection relationship between them, as well as a connection relationship with the second end register set. This process of copying and connecting is carried out under the premise of ensuring that the fan-out number is controlled within a reasonable range, so as to gradually optimize the entire chip design.

[0058] If the fan-out number in a combinatorial logic path does not meet the preset conditions after a certain update, further updates to this path are stopped. This avoids unnecessary resource consumption and increased design complexity.

[0059] Through the iterative approach in the embodiments of the present application, the impact of high fan-out on chip design can be gradually reduced, signal quality can be improved, timing violations can be reduced, and power consumption and area can be controlled at the same time.

[0060] Obviously, the above-described embodiments are only embodiments of a part of the present invention, rather than all embodiments. In order to better understand the method for establishing the above connection relationship, the above process is described below in conjunction with an embodiment, but it is not intended to limit the technical solution of the embodiment of the present invention, specifically:

[0061] In an alternative embodiment, Figure 3 : is a flow chart of a method for establishing a connection relationship according to an optional embodiment of the present invention, and the specific steps are as follows:

[0062] Step S301: write RTL code;

[0063] Step S302: compile RTL code;

[0064] Step S303: Use the PT / DC tool to find a combinational logic with a fan-out number that is too large (i.e., the fan-out number is greater than or equal to n, where n is the engineer's experience value), and use this combinational logic to find the starting points of all paths passing through this combinational logic.

[0065] like Figure 4 Register A, register B, and register C in.

[0066] Step S304: Copy the found starting point register.

[0067] And connect all related nets to the starting point, such as Figure 4 Register A_rep and register C_rep in , and connect the points related to A_rep / C_rep with lines;

[0068] Step S305: Check and copy the intermediate logic.

[0069] Check the combinational logic between the start point and the end point, and copy the combinational logic found with too large fanout; Figure 4 The combinational logic F / G in, and the replicated combinational logic F_rep / G_rep.

[0070] Step S306: Find the copied intermediate logic and reconnect it to the copied starting point.

[0071] like Figure 4 The points related to F_rep / G_rep are connected by lines.

[0072] Step S307: insert chip test (Design for Testability, referred to as DFT);

[0073] Step S308: incremental compilation;

[0074] Step S309: Completed.

[0075] The embodiment of the present application, based on the existing EDA tool method, uses register replication and logic replication methods to fundamentally solve the high fan-out problem commonly seen in chip design. Compared with the traditional method of solving the high fan-out problem by modifying the code or inserting a buffer, this method has greatly improved reliability and controllability. And by trying to reasonably replicate key registers, there will not be too many replicated registers and an increase in area due to too much replicated logic; the present application can also greatly help the timing convergence caused by high fan-out, while solving the possible congestion problem, saving area and winding resources, and reducing the debugging time of the back-end engineer for the EDA tool.

[0076] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0077] In the present embodiment, a device for establishing a connection relationship is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0078] Figure 5 is a structural block diagram of a device for establishing a connection relationship according to an embodiment of the present application, such as Figure 5 As shown, the device comprises:

[0079] A determination module 52, configured to determine a target combinational logic whose fan-out number meets a preset condition, and to determine a start register, a first end register set, and a logic gate in a combinational logic path corresponding to the target combinational logic;

[0080] A copy module 54, used for copying the starting register and the logic gate to obtain a first copy register and a first copy logic gate;

[0081] The establishing module 56 is used to establish a first connection relationship between the first copy register and the first copy logic gate, and to establish a second connection relationship between the first copy logic gate and a first destination register of the first destination register set.

[0082] Through the above-mentioned device, the target combinational logic whose fan-out number meets the preset conditions is determined, and the starting register, the first terminal register set and the logic gate in the combinational logic path corresponding to the target combinational logic are determined; the starting register and the logic gate are copied to obtain the first copy register and the first copy logic gate; a first connection relationship between the first copy register and the first copy logic gate is established, and a second connection relationship between the first copy logic gate and the first terminal register of the first terminal register set is established, that is, in the embodiment of the present application, by copying the starting register and the logic gate in the high fan-out logic combination, and establishing the copied register, logic gate and target terminal register, the fan-out number in the original logic combination is reduced, thereby alleviating the problem of timing violation. Therefore, the problem of timing violation caused by high fan-out combinational logic in integrated circuit design can be solved.

[0083] In an exemplary embodiment, the establishing module 56 is used to determine a third connection relationship between the start register and the logic gate; and establish a first connection relationship between the first copy register and the first copy logic gate according to the third connection relationship.

[0084] In an exemplary embodiment, a module 56 is established to determine whether there are other logic gates in the combinational logic path, wherein the other logic gates are logic gates of the previous stage of the logic gate and the other logic gates are not copied; when it is determined that the other logic gates exist in the combinational logic path, a fourth connection relationship between the logic gate and the other logic gates is determined; and a fifth connection relationship between the first copied logic gate and the other logic gates is established based on the fourth connection relationship.

[0085] In an exemplary embodiment, a module 56 is established to determine a sixth connection relationship between the pairwise logic gates when there are multiple first replicated logic gates; and a seventh connection relationship between the pairwise first replicated logic gates is established based on the sixth connection relationship between the pairwise logic gates, wherein the pairwise logic gates correspond to the pairwise first replicated logic gates.

[0086] In an exemplary embodiment, the determination module 52 is configured to determine the number of registers in the first destination register set; and determine the first destination register in the first destination register set according to a preset ratio and the number.

[0087] In an exemplary embodiment, the determination module 52 is used to determine the area of ​​the chip corresponding to the target combinational logic; when the area is greater than or equal to the preset area, determine the logic gates of the first N levels of the first endpoint register set, and determine the starting point register that has a connection relationship with the logic gates of the first N levels, wherein N is a positive integer; when the area is less than the preset area, determine the logic gates of the first M levels of the first endpoint register set, and determine the starting point register that has a connection relationship with the logic gates of the first M levels, wherein M is a positive integer less than or equal to N.

[0088] In an exemplary embodiment, the determination module 52 is used to determine whether the fan-out number of the combinatorial logic in the updated combinatorial logic path meets the preset condition; if the fan-out number of the combinatorial logic in the updated combinatorial logic path meets the preset condition, determine the starting register, the second terminal register set and the logic gate in the updated combinatorial logic path; copy the starting register and the logic gate in the updated combinatorial logic path to obtain a second copy register and a second copy logic gate; establish a connection relationship between the second copy register and the second copy logic gate, and establish a connection relationship between the second copy logic gate and the second terminal register of the second terminal register set; if the fan-out number of the combinatorial logic in the updated combinatorial logic path does not meet the preset condition, stop updating the combinatorial logic path.

[0089] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0090] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0091] Optionally, the computer readable storage medium is configured to execute the following steps when executed:

[0092] Step S1, determining a target combinational logic whose fan-out number meets a preset condition, and determining a starting register, a first end register set, and a logic gate in a combinational logic path corresponding to the target combinational logic;

[0093] Step S2, copying the starting register and the logic gate to obtain a first copy register and a first copy logic gate;

[0094] Step S3: establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and the first destination register of the first destination register set.

[0095] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0096] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0097] Optionally, the electronic device is configured to perform the following steps when in operation:

[0098] Step S1, determining a target combinational logic whose fan-out number meets a preset condition, and determining a starting register, a first end register set, and a logic gate in a combinational logic path corresponding to the target combinational logic;

[0099] Step S2, copying the starting register and the logic gate to obtain a first copy register and a first copy logic gate;

[0100] Step S3: establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and the first destination register of the first destination register set.

[0101] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0102] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0103] Optionally, the computer program product is configured to perform the following steps when executed:

[0104] Step S1, determining a target combinational logic whose fan-out number meets a preset condition, and determining a starting register, a first end register set, and a logic gate in a combinational logic path corresponding to the target combinational logic;

[0105] Step S2, copying the starting register and the logic gate to obtain a first copy register and a first copy logic gate;

[0106] Step S3: establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and the first destination register of the first destination register set.

[0107] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0108] An embodiment of the present application also provides a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0109] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0110] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0111] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for establishing a connection relationship, characterized in that: include: Determine a target combinational logic whose fan-out number meets a preset condition, and determine a starting register, a first end register set, and a logic gate in a combinational logic path corresponding to the target combinational logic; Copying the starting register and the logic gate to obtain a first copy register and a first copy logic gate; A first connection relationship between the first copy register and the first copy logic gate is established, and a second connection relationship between the first copy logic gate and a first destination register of the first destination register set is established.

2. The method according to claim 1, characterized in that Establishing a first connection relationship between the first replica register and the first replica logic gate includes: Determining a third connection relationship between the start register and the logic gate; A first connection relationship between the first replica register and the first replica logic gate is established according to the third connection relationship.

3. The method according to claim 2, characterized in that After establishing a first connection relationship between the first copy register and the first copy logic gate according to the third connection relationship, the method further includes: Determine whether there are other logic gates in the combinational logic path, wherein the other logic gates are logic gates of a previous stage of the logic gate and the other logic gates are not copied; In the case where it is determined that the other logic gate exists in the combinational logic path, determining a fourth connection relationship between the logic gate and the other logic gates; A fifth connection relationship between the first duplicate logic gate and the other logic gates is established according to the fourth connection relationship.

4. The method according to claim 1, characterized in that Before or after establishing a second connection relationship between the first replica logic gate and the first destination register of the first destination register set, the method further includes: When there are multiple first duplicate logic gates, determining a sixth connection relationship between any two of the logic gates; A seventh connection relationship between the pairwise first replicated logic gates is established based on the sixth connection relationship between the pairwise logic gates, wherein the pairwise logic gates correspond to the pairwise first replicated logic gates.

5. The method according to claim 1, characterized in that Before establishing a second connection relationship between the first copy logic gate and the first destination register of the first destination register set, the method further includes: determining the number of registers in the first endpoint register set; The first destination register is determined in the first destination register set according to a preset ratio and the quantity.

6. The method according to claim 1, characterized in that Determining a starting register, a first end register set, and a logic gate in a combinational logic path corresponding to the target combinational logic includes: Determining the area of ​​a chip corresponding to the target combinational logic; When the area is greater than or equal to the preset area, determining the first N levels of logic gates of the first end register set, and determining the starting point registers having a connection relationship with the first N levels of logic gates, wherein N is a positive integer; When the area is smaller than the preset area, the first M logic gates of the first endpoint register set are determined, and the starting point registers connected to the first M logic gates are determined, where M is a positive integer less than or equal to N.

7. The method according to claim 1, characterized in that After establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and a first destination register of the first destination register set, the method further includes: Determining whether the fan-out number of the combinational logic in the updated combinational logic path meets the preset condition; When the fan-out number of the combinatorial logic in the updated combinatorial logic path meets the preset condition, determining the starting register, the second end register set and the logic gate in the updated combinatorial logic path; Copying the starting register and the logic gate in the updated combinational logic path to obtain a second copy register and a second copy logic gate; Establishing a connection relationship between the second copy register and the second copy logic gate, and establishing a connection relationship between the second copy logic gate and a second destination register of the second destination register set; When the fan-out number of the combinatorial logic in the updated combinatorial logic path does not meet the preset condition, the updating of the combinatorial logic path is stopped.

8. A device for establishing a connection relationship, characterized in that: include: A determination module, used to determine a target combinational logic whose fan-out number meets a preset condition, and to determine a starting register, a first end register set, and a logic gate in a combinational logic path corresponding to the target combinational logic; A copy module, used for copying the starting register and the logic gate to obtain a first copy register and a first copy logic gate; An establishing module is used to establish a first connection relationship between the first copy register and the first copy logic gate, and to establish a second connection relationship between the first copy logic gate and a first destination register of the first destination register set.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

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