Display driving method, display driving circuit, display panel

Abstract

The application discloses a display driving method, a display driving circuit and a display panel. The display driving method comprises the following steps: obtaining a low-brush display area; performing frequency reduction processing on a first clock signal corresponding to the low-brush display area to obtain a second clock signal according to the low-brush display area; and controlling a pixel driving unit corresponding to the low-brush display area to generate a corresponding pixel driving signal according to a gate scanning signal and the second clock signal, and setting the frequency of the second clock signal to be greater than or equal to the frequency of the pixel driving signal. Therefore, the power consumption of the low-brush display area is reduced when the display picture is displayed in the refresh rate partition mode, the power consumption benefit in the partition refresh application scenario is improved, and the purpose of reducing the display power consumption is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, in particular to a display driving method, a display driving circuit and a display panel. BACKGROUND

[0002] With the improvement of people's living standards, electronic products play an important role in people's lives, and display panels are important components of electronic products, so the demand for display panels is increasing.

[0003] Now the ordinary display effect can not meet the quality of people's life, people's demand for high refresh rate display panel is also more and more big, however, the power consumption of high refresh rate display panel is also high, which has a negative effect on the use time of electronic products, which is not conducive to reducing the power consumption of display terminal. SUMMARY

[0004] In view of the above problems, the present application provides a display driving method, a display driving circuit and a display panel, aiming to provide a partition refresh scheme to solve the problem of single display of the current full-screen refresh display, which is not conducive to reducing power consumption.

[0005] The first aspect of the embodiment of the present application provides a display driving method, which comprises:

[0006] obtaining a low refresh display area;

[0007] performing frequency reduction processing on a first clock signal corresponding to the low refresh display area to obtain a second clock signal according to the low refresh display area;

[0008] controlling a pixel driving unit corresponding to the low refresh display area to generate a corresponding pixel driving signal according to a gate scanning signal and the second clock signal;

[0009] wherein the frequency of the second clock signal is greater than or equal to the frequency of the pixel driving signal.

[0010] In some embodiments, the rising edge or falling edge of the second clock signal is consistent with the rising edge of the pixel driving signal.

[0011] In some embodiments, the rising edge or falling edge of the second clock signal is consistent with the falling edge of the pixel driving signal.

[0012] In some embodiments, the second clock signal is obtained by performing frequency reduction processing on the first clock signal corresponding to the low refresh display area according to the low refresh display area, comprising:

[0013] pulling the level of the first clock signal low in the case that the pixel driving signal is low.

[0014] In some embodiments, the display driving method further comprises:

[0015] generating a corresponding partition enabling signal according to the low-brush display area, to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal.

[0016] The second aspect of the embodiments of the present application further provides a display driving circuit, comprising a plurality of pixel driving units and a master control circuit, wherein the master control circuit is configured to execute the display driving method as described in any one of the above embodiments.

[0017] The plurality of pixel driving units are configured to drive a plurality of display pixels to light up respectively.

[0018] In some embodiments, the display driving circuit further comprises a plurality of scan driving modules, and a plurality of gate scan lines are connected to the plurality of scan driving modules respectively.

[0019] The scan driving modules are controlled by the master control circuit to provide gate scan signals for the plurality of gate scan lines, and the plurality of pixel driving units are connected to corresponding gate scan lines respectively.

[0020] Each of the pixel driving units is configured to drive the corresponding display pixel to light up according to the received gate scan signal and data signal.

[0021] In some embodiments, the pixel driving unit comprises a first driving transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, and a storage capacitor.

[0022] The first end of the second switch transistor is configured to receive a display data signal, and the control end of the second switch transistor is configured to receive a first data control signal.

[0023] The control end of the fourth switch transistor is configured to receive a first scan control signal, and the control end of the third switch transistor is configured to receive a second scan control signal.

[0024] The control end of the fifth switch transistor and the control end of the sixth switch transistor are connected together and configured to receive a light-emitting control signal.

[0025] The control end of the seventh switch transistor and the control end of the eighth switch transistor are connected together and configured to receive a second data control signal.

[0026] The first end of the fifth switch tube is connected with the first end of the storage capacitor, the second end of the second switch tube, the second end of the fifth switch tube and the first end of the first drive tube are connected, the second end of the storage capacitor, the control end of the first drive tube and the first end of the third switch tube are connected, the second end of the third switch tube, the first end of the fourth switch tube, the second end of the first drive tube, the first end of the sixth switch tube and the first end of the eighth switch tube are connected, the second end of the fourth switch tube is connected with a first reference signal end, the second end of the sixth switch tube and the first end of the seventh switch tube are connected with the positive electrode of a display pixel, the negative electrode of the display pixel is connected with a reference ground, the second end of the seventh switch tube is connected with a second reference signal end, and the second end of the eighth switch tube is connected with a third reference signal end.

[0027] In some embodiments, the second switch tube, the seventh switch tube, the eighth switch tube, the fifth switch tube and the sixth switch tube are P-type MOS tubes; and the third switch tube and the fourth switch tube are N-type MOS tubes.

[0028] The third aspect of the embodiments of the present application further provides a display panel, which comprises the display driving circuit according to any one of the above embodiments.

[0029] The embodiments of the present application have the following beneficial effects: by obtaining a low-brushing display area, a second clock signal is obtained by performing frequency reduction processing on a first clock signal corresponding to the low-brushing display area according to the low-brushing display area; a pixel driving unit corresponding to the low-brushing display area is controlled to generate a corresponding pixel driving signal according to a gate scanning signal and the second clock signal, and the frequency of the second clock signal is set to be greater than or equal to the frequency of the pixel driving signal, so that the power consumption of the low-brushing display area is reduced when the display picture is displayed in a refresh rate partition manner, the power consumption benefit in the partition refresh application scenario is improved, and the purpose of reducing display power consumption is achieved.

[0030] The above description is only a summary of the technical solutions of the present application, in order to enable the technical means of the present application to be implemented according to the content of the description, and in order to enable the above and other purposes, characteristics and advantages of the present application to be more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0031] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are intended to further assist in understanding the preferred embodiments, and are not intended to limit the application thereto. Moreover, like reference numerals denote like parts throughout the several views in the drawings. In the drawings:

[0032] Figure 1The first schematic diagram of the display driving method provided by the embodiment of the present application is shown in FIG. 1.

[0033] Figure 2a The first waveform schematic diagram of the second clock signal SCK2 and the pixel driving signal SCAN provided by the embodiment of the present application is shown in FIG. 2.

[0034] Figure 2b The second waveform schematic diagram of the second clock signal SCK2 and the pixel driving signal SCAN provided by the embodiment of the present application is shown in FIG. 3.

[0035] Figure 3a The third waveform schematic diagram of the second clock signal SCK2 and the pixel driving signal SCAN provided by the embodiment of the present application is shown in FIG. 4.

[0036] Figure 3b The fourth waveform schematic diagram of the second clock signal SCK2 and the pixel driving signal SCAN provided by the embodiment of the present application is shown in FIG. 5.

[0037] Figure 4 The effect schematic diagram before the clock signal is reduced in frequency provided by the embodiment of the present application is shown in FIG. 6.

[0038] Figure 5 The effect schematic diagram after the clock signal is reduced in frequency provided by the embodiment of the present application is shown in FIG. 7.

[0039] Figure 6 The second schematic diagram of the display driving method provided by the embodiment of the present application is shown in FIG. 8.

[0040] Figure 7 The schematic diagram of the display driving circuit provided by the embodiment of the present application is shown in FIG. 9.

[0041] Figure 8 The schematic diagram of the pixel driving unit provided by the embodiment of the present application is shown in FIG. 10.

[0042] Figure 9 The schematic diagram of the partition enabling signal provided by the embodiment of the present application is shown in FIG. 11. DETAILED DESCRIPTION

[0043] The embodiments of the technical solutions of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and therefore only serve as examples, but cannot limit the protection scope of the present application.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above description of drawings are intended to cover non-exclusive inclusion.

[0045] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise explicitly and specifically limited.

[0046] In this paper, the phrase "embodiment" means that the specific features, structures or properties described in conjunction with the embodiment can be included in at least one embodiment of the present application. The phrase is not necessarily referring to the same embodiment at various places in the specification, nor is it an independent or alternative embodiment that is not mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0047] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are in an "or" relationship.

[0048] In the description of the embodiments of the present application, the term "multiple frames" refers to two or more (including two).

[0049] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the embodiments of the present application.

[0050] In the related art, when the display panel display is partitioned and refreshed, in the case that the refresh rate of each display area is different, the low refresh display area is usually not supported for frequency reduction processing, for example, in the application scenario of upper, middle and lower display refresh rate of 1HZ-120HZ-1HZ, the frequency reduction measure is not supported in the upper and lower 1HZ refresh area, and the 1HZ display area needs to keep the same behavior as the GOA signal of the 120HZ area. Therefore, there is a problem that the power consumption benefit is small in the common scenario of partitioned refresh 1HZ-120HZ-1HZ.

[0051] To solve the above technical problems, the display driving method provided in the embodiments of the present application comprises steps S100-S300. Figure 1 The display driving method provided in the embodiments of the present application comprises steps S100-S300.

[0052] In step S100, a low-refresh display region is acquired.

[0053] In the embodiments, the low-refresh display region refers to a region in the display panel that displays at a low refresh rate. When displaying a picture, the display panel can display some regions at a low refresh rate according to user demand or picture display requirement. For example, the display refresh rate of a region that only needs to display text can be reduced to reduce display power consumption.

[0054] In some embodiments, the picture refresh rate of the low-refresh display region can be less than 30 Hz.

[0055] In some embodiments, the picture refresh rate of the low-refresh display region can be 1 Hz.

[0056] In step S200, a second clock signal is obtained by frequency-reducing a first clock signal corresponding to the low-refresh display region according to the low-refresh display region.

[0057] In the embodiments, when the partition refresh function of the display panel is enabled, the refresh frequencies of the display pictures of different regions can be inconsistent. For example, the refresh frequencies of the display pictures of the upper, middle and lower regions of the display panel are 1 Hz, 120 Hz and 1 Hz respectively. However, all the pixel driving units still receive a clock signal with the highest frequency, for example, a clock signal with a frequency of 120 Hz. Therefore, using a higher clock signal frequency in the low-refresh display region can cause energy waste. Therefore, the first clock signal received by the pixel driving unit in the low-refresh display region is frequency-reduced to obtain a low-frequency second clock signal. The frequency of the pixel driving signal is related to the refresh rate of the display region. For example, the refresh rate of the display region is equal to the frequency of the pixel driving signal. Since the frequency of the second clock signal is greater than or equal to the frequency of the pixel driving signal, the picture display in the low-refresh display region is not affected, the normal signal output of the pixel driving unit is not affected, and the power consumption benefit of the display panel under the partition refresh can be greatly improved.

[0058] In step S300, the pixel driving unit corresponding to the low-refresh display region generates a corresponding pixel driving signal according to the gate scanning signal and the second clock signal.

[0059] In the embodiment, the display panel includes a plurality of display pixels, the plurality of display pixels can be arranged in an array, each display pixel is driven by a corresponding pixel driving unit, the pixel driving unit can generate a corresponding pixel driving signal according to a received gate scanning signal and a second clock signal, so as to drive the display pixel in the low brush display area to light up. In the high brush display area, the pixel driving unit can generate a corresponding pixel driving signal according to a received gate scanning signal and a first clock signal, so as to drive the display pixel in the high brush display area to light up. When the plurality of display pixels in the high brush display area and the low brush display area are driven to light up, the corresponding pictures can be displayed.

[0060] In some embodiments, the host circuit can control the pixel driving unit to generate a pixel driving signal with a low duty cycle according to the low brush display area, so as to reduce the refresh rate of the display picture in the low brush display area.

[0061] In some embodiments, the frequency reduction processing in step S200 can be to reduce the duty cycle of the first clock signal, so as to obtain a second clock signal with a low duty cycle. For example, in the case that the display picture refresh frequency is 1 Hz, the frequency of the first clock signal is 120 Hz, and then the second clock signal with a frequency of 30 Hz or 1 Hz can be obtained by frequency reduction processing on the first clock signal. Since the frequency of the second clock signal with a frequency of 30 Hz is greater than the current display picture refresh frequency, and the frequency of the second clock signal with a frequency of 1 Hz is equal to the current display picture refresh frequency, at this time, the picture display in the low brush display area will not be affected, the normal signal output of the pixel driving unit will not be affected, and the power consumption benefit of the display panel under partition refresh can be greatly improved.

[0062] In some embodiments, the rising edge or the falling edge of the second clock signal is consistent with the rising edge of the pixel driving signal.

[0063] In the embodiment, the gray scale of the display pixel is related to the light-up time of the display pixel, and the light-up time of the display pixel is related to the duty cycle of the pixel driving signal, that is, the time of the pixel driving signal being at a high level in each display period. The rising edge of the second clock signal is the interval in which the second clock signal is converted from a low level to a high level, and the falling edge of the second clock signal is the interval in which the second clock signal is converted from a high level to a low level. Since there is a level mutation between the rising edge and the falling edge of the second clock signal, by setting the rising edge or the falling edge of the second clock signal to be consistent with the rising edge of the pixel driving signal, the display integrity of the pixel driving signal SCAN in each display period can be ensured, and the problem of picture display distortion caused by refresh rate switching or frequency switching of the clock signal can be avoided.

[0064] Referring to Figure 2aAs shown, by setting the rising edge of the second clock signal SCK2 to be consistent with the rising edge of the pixel driving signal SCAN, the display integrity of the pixel driving signal SCAN in each display period can be ensured, and the problem of picture display distortion caused by refresh rate switching or frequency switching of the clock signal can be avoided.

[0065] In some embodiments, referring to Figure 2b As shown, by setting the falling edge of the second clock signal SCK2 to be consistent with the rising edge of the pixel driving signal SCAN, the display integrity of the pixel driving signal SCAN in each display period can be ensured, and the problem of picture display distortion caused by refresh rate switching or frequency switching of the clock signal can be avoided.

[0066] In some embodiments, the rising edge or the falling edge of the second clock signal SCK2 is consistent with the falling edge of the pixel driving signal.

[0067] In the embodiment, the gray scale of the display pixel is related to the lighting time of the display pixel, and the lighting time of the display pixel is related to the duty cycle of the pixel driving signal, i.e., the time of the pixel driving signal being at high level in each display period. Referring to Figure 3a As shown, by setting the rising edge of the second clock signal SCK2 to be consistent with the falling edge of the pixel driving signal SCAN, the display integrity of the pixel driving signal SCAN in each display period can be ensured, and the problem of picture display distortion caused by refresh rate switching or frequency switching of the clock signal can be avoided.

[0068] In some embodiments, referring to Figure 3b As shown, by setting the falling edge of the second clock signal SCK2 to be consistent with the falling edge of the pixel driving signal SCAN, the display integrity of the pixel driving signal SCAN in each display period can be ensured, and the problem of picture display distortion caused by refresh rate switching or frequency switching of the clock signal can be avoided.

[0069] In some embodiments, in step S200, the second clock signal is obtained by performing frequency reduction processing on the first clock signal corresponding to the low-refresh display area according to the low-refresh display area, including: lowering the level of the first clock signal in the case that the pixel driving signal is at low level.

[0070] In this embodiment, when the duty cycle of the pixel driving signal output by the pixel driving unit corresponding to the low refresh rate display area decreases, it indicates that the low refresh rate display area of ​​the display panel has adopted a low refresh rate display. Thus, the first clock signal can be down-clocked by matching the first clock signal with the pixel driving signal. That is, when the pixel driving signal is low, the level of the first clock signal is pulled low, and when the pixel driving signal is high, the level of the first clock signal is pulled high. In this way, it can be ensured that the waveform of the first clock signal is consistent with the waveform of the pixel driving signal, which can reduce the power consumption of the first clock signal without affecting the display of the screen on the display panel.

[0071] In some embodiments, with the partition refresh function of the display panel enabled, the following description is based on a screen resolution of 1316*2832.

[0072] In practical applications, the high refresh rate display area can be determined by the start and end coordinates. Among related technologies, such as... Figure 4 As shown, the timing behavior of the GOA signal in the 1Hz area of ​​the display panel is consistent with the timing behavior of the GOA signal in the middle 120Hz area of ​​the display panel. As a result, in common scenarios, when the refresh rates of the display screens in the upper, middle and lower areas of the display panel are 120Hz, 1Hz and 1Hz respectively, the power consumption gain is not significant.

[0073] like Figure 4 With partition refresh enabled, the refresh rates of the top, middle, and bottom areas of the display panel are 120Hz-1Hz-1Hz respectively. In channel 1, a high-level partition enable signal VFE indicates a high refresh rate display area, and a low-level partition enable signal VFE indicates a low refresh rate display area. Channel 2 uses the SINP1 signal, and channel 3 uses the clock signal SCKIP1. Figure 4 Only clock signal SCK1P1 is captured. Clock signals SCK2P1, SCK3P1, and SCK4P1 behave identically to clock signal SCK1P1, all being the clock for SINP1, with all four channels acting as source signals. (Combined with...) Figure 4 As can be seen, in the first frame of the display, the source signal, clock signal SCK1P1, and partition enable signal VFE are all working normally, and the display in this frame is refreshed to full screen. In the next frame of the display, the partition enable signal VFE and the source signal are at a high level in lines 1-960, the partition enable signal VFE and the source signal are at a high refresh rate of 120Hz in lines 1-960, and the partition enable signal VFE and the source signal are at a low refresh rate of 1Hz in lines 961-2832. However, in the 1Hz range, the clock signal SCK1P1 is still working normally in the low refresh rate display area.

[0074] likeFigure 5 As shown in the first frame of the display picture, the source signal source, the clock signal SCK1P1 and the partition enable signal VFE are all in normal operation, and the full screen of the frame of the display picture is refreshed; in the next frame of the display picture, the partition enable signal VFE and the source signal source are high in the 1-960th row, the partition enable signal VFE and the source signal source are 120HZ in the 1-960th row, the partition enable signal VFE and the source signal source are 1HZ in the 961-2832th row, but in the 1HZ area, the clock signal SCK1P1 in the 961-2832th row in the low refresh display area is pulled low to the level of the clock signal SCK1P1, and the level of the source signal source is not affected.

[0075] Table 1:

[0076]

[0077] The power consumption of the scheme 1 in Table 1 is obtained by executing the display driving method in the embodiment of the present application, the power consumption of the scheme 2 in Table 1 is obtained by executing the traditional display driving method, VDD1, VDDD / DVDD, VCI, AVDD and VGL represent the power consumption of the corresponding node, DDIC-SUM represents the total power consumption, digital-SUM represents the total power consumption of the digital signal, and analog-SUM represents the total power consumption of the analog signal. As shown in Table 1, by Figure 5 In the low refresh display area, the level of the clock signal SCK1P1 is pulled low, so that the GOA part power consumption benefit is obvious, and the power consumption benefit is about 14mW. By analogy, the waveform diagram of SCK2P1, SCK3P1 and SCK4P1 is the same as that of SCK1P1 Figure 1 Therefore, if the four clock signals SCK1P1, SCK2P1, SCK3P1 and SCK4P1 of SCANP1 are pulled to the PVGL_N level for frequency reduction (60HZ / 30HZ / 10HZ, the same applies) below the partition end coordinate under the partition refresh, this measure can effectively reduce the GOA power consumption under the partition refresh.

[0078] In some embodiments, as shown in FIG. 4, Figure 6 As shown in the first frame of the display picture, the source signal source, the clock signal SCK1P1 and the partition enable signal VFE are all in normal operation, and the full screen of the frame of the display picture is refreshed; in the next frame of the display picture, the partition enable signal VFE and the source signal source are high in the 1-960th row, the partition enable signal VFE and the source signal source are 120HZ in the 1-960th row, the partition enable signal VFE and the source signal source are 1HZ in the 961-2832th row, but in the 1HZ area, the clock signal SCK1P1 in the 961-2832th row in the low refresh display area is pulled low to the level of the clock signal SCK1P1, and the level of the source signal source is not affected.

[0079] In the embodiment, the scanning area requiring to reduce the display refresh rate is determined by the low-brush display area, and a corresponding partition enabling signal is generated, which is used to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal, so as to reduce the on-off duty cycle of the pixels in the corresponding area, thereby realizing the partition display of the display panel and reducing the display refresh rate in the low-brush display area.

[0080] In some embodiments, in combination with Figure 7 As shown, the partition enabling signal can also be processed with AND logic with the scan driving signal output by the scan driving module 520, so as to adjust the duty cycle of the scan driving signal output to the gate scan line 501, so as to achieve the purpose of controlling the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal, and realize the partition refresh display of the display panel.

[0081] In some embodiments, the host circuit 510 can provide a corresponding partition scan signal for the scan driving module 520 according to the content to be displayed on the display panel, so as to adjust the refresh rate of the corresponding display picture. For example, according to the coordinates and refresh rate requirements of the display picture, the refresh rate of the display picture is set according to the frequency distribution such as 60hz-120hz-60hz, 30hz-120hz-30hz, 1hz-120hz-1hz, etc. Specifically, in the implementation of the function of displaying different refresh rates in multiple areas of the mobile phone, if the mobile phone simultaneously watches a video (which requires high refresh rate display) and reads text (which requires low refresh rate display), the refresh rate of the text display area in the display picture is set to a low refresh rate (for example, 1Hz, 30Hz, etc.), so as to reduce the power consumption of the display panel without affecting the display effect.

[0082] The embodiment of the present application also provides a display driving circuit, which is shown in Figure 7 As shown, the display driving circuit in the embodiment of the present application includes a plurality of pixel driving units 530 and a host circuit 510, the host circuit 510 is used to execute the display driving method in any of the above embodiments, and the plurality of pixel driving units 530 are used to respectively drive a plurality of display pixels to light up.

[0083] In the embodiment, the display panel includes a plurality of display pixels, the plurality of display pixels can be arranged in an array, each display pixel is driven by a corresponding pixel driving unit 530, the pixel driving unit 530 can generate a pixel driving signal according to the received gate scan signal, so as to drive the corresponding display pixel to light up, and the plurality of display pixels can display a corresponding picture when driven to light up. The host circuit 510 can control the corresponding pixel driving unit 530 to generate a pixel driving signal with a low duty cycle according to the low-brush display area, so as to reduce the refresh rate of the display picture in the low-brush display area.

[0084] In some embodiments, in combination with Figure 7 As shown in FIG. 5, the display driving circuit further includes a plurality of scan driving modules 520, and the plurality of gate scan lines 501 are connected to the plurality of scan driving modules 520 respectively; the scan driving modules 520 are controlled by the master circuit 510 to provide gate scan signals for the plurality of gate scan lines 501, and the plurality of pixel driving units 530 are connected to the corresponding gate scan lines 501 respectively; each pixel driving unit 530 is configured to drive the corresponding display pixel to light up according to the received gate scan signal and data signal.

[0085] In this embodiment, in combination with Figure 7 As shown in FIG. 5, the display panel can include N+1 rows of display pixels, each row of display pixels corresponds to a gate scan line 501, and each gate scan line 501 is connected to a corresponding scan driving module 520. The master circuit 510 can provide a partition scan signal for the corresponding scan driving module 520, so as to adjust the display refresh rate of the display area of the display panel. As shown in FIG. 5, the master circuit 510 provides a partition enable signal SWN for the Nth scan driving module 520, and the master circuit 510 provides a partition enable signal SWN+1 for the N+1th scan driving module 520. The N+1 scan driving modules 520 provide gate scan signals for the plurality of gate scan lines 501 according to the corresponding partition enable signals. Figure 7

[0086] In some embodiments, as shown in FIG. 5, the pixel driving unit 530 includes a first driving transistor T1, a second switch transistor T2, a third switch transistor T3, a fourth switch transistor T4, a fifth switch transistor T5, a sixth switch transistor T6, and a storage capacitor Cst. Figure 8

[0087] In this embodiment, the first end of the second switch transistor T2 is configured to receive a display data signal, and the control end of the second switch transistor T2 is configured to receive a first data control signal Data; the control end of the fourth switch transistor T4 is configured to receive a first scan control signal SN1, and the control end of the third switch transistor T3 is configured to receive a second scan control signal SN2. In some embodiments, the second scan control signal SN2 can be provided by a level conversion circuit composed of the seventeenth switch transistor T17 and the eighteenth switch transistor T18, and the partition enable signal VFE can be output to the control end of the third switch transistor T3 as the second scan control signal SN2 via the output end GOUT of the level conversion circuit, so as to realize the partition refresh control of the pixel driving unit 530.

[0088] ​​The control terminal of the fifth switch tube T5 and the control terminal of the sixth switch tube T6 are connected in common for receiving a light emission control signal EM; the control terminal of the seventh switch tube T7 and the control terminal of the eighth switch tube T8 are connected in common for receiving a second data control signal SP2. The first terminal of the fifth switch tube T5 and the first terminal of the storage capacitor Cst are connected in common to a first power supply terminal ELVDD; the second terminal of the second switch tube T2, the second terminal of the fifth switch tube T5 and the first terminal of the first drive tube T1 are connected in common; the second terminal of the storage capacitor Cst, the control terminal of the first drive tube T1 and the first terminal of the third switch tube T3 are connected in common; the second terminal of the third switch tube T3, the first terminal of the fourth switch tube T4, the second terminal of the first drive tube T1, the first terminal of the sixth switch tube T6 and the first terminal of the eighth switch tube T8 are connected in common; the second terminal of the fourth switch tube T4 is connected to a first reference signal terminal Vrefn1; the second terminal of the sixth switch tube T6 and the first terminal of the seventh switch tube T7 are connected in common to the positive electrode of a display pixel; the negative electrode of the display pixel is connected to a reference ground; the second terminal of the seventh switch tube T7 is connected to a second reference signal terminal Vrefn2; and the second terminal of the eighth switch tube T8 is connected to a third reference signal terminal Vrefp.

[0089] In some embodiments, the second switch tube T2, the seventh switch tube T7, the eighth switch tube T8, the fifth switch tube T5 and the sixth switch tube T6 are P-type MOS tubes; and the third switch tube T3 and the fourth switch tube T4 are N-type MOS tubes.

[0090] In some embodiments, the master control circuit 510 is further configured to perform the step S400 in the above-described embodiments, and the master control circuit 510 generates a corresponding partition enable signal according to a low-brush display region, and controls a corresponding pixel driving unit to reduce the duty cycle of a pixel driving signal by the partition enable signal, so as to reduce the switching duty cycle of the pixels in the corresponding region.

[0091] In some embodiments, the display driving circuit is configured to drive a display panel, and the display panel can include a plurality of partition refresh regions. The master control circuit 510 in the display driving circuit can provide a plurality of partition enable signals to pixel driving units in the plurality of partition refresh regions, so as to adjust the refresh rate in each partition refresh region and realize the partition refresh function of the display panel.

[0092] Referring to Figure 9 As shown in the figure, the display driving circuit can include four partition refresh regions, and the partition refresh function of the display panel in the embodiment can be controlled by four partition enable signals VFE (VFE_1, VFE_2, VFE_3, VFE_4), wherein each partition enable signal VFE can drive 16 rows of display pixels, and one cycle of the four partition enable signals VFE is 64 rows. In combination with Figure 9As shown, the refresh rate of the display pixels in the 1st-16th rows (1-16H) is controlled by the first partition enable signal VFE_1, the refresh rate of the display pixels in the 17th-32nd rows is controlled by the second partition enable signal VFE_2, the refresh rate of the display pixels in the 33rd-48th rows (33-48H) is controlled by the third partition enable signal VFE_3, the refresh rate of the display pixels in the 49th-64th rows is controlled by the fourth partition enable signal VFE_4, the refresh rate of the display pixels in the 65th-84th rows is controlled by the first partition enable signal VFE_1, and so on.

[0093] In some embodiments, the output end GOUT of the level conversion circuit is connected to the third switch tube T3, the high level of the partition enable signal VFE is PVGH_N, and the low level of the partition enable signal VFE is PVGL_N, as shown in the following figure. Figure 8 The output of the partition enable signal VFE can directly act on the gate of the third switch tube T3. If the voltage of the partition enable signal VFE is PVGL_N, the voltage acting on the third switch tube T3 is always negative, the third switch tube T3 can be an NMOS, so the third switch tube T3 is always closed, and the voltage of the storage capacitor Cst remains unchanged (equivalent to the 1Hz region in 1Hz-120Hz-1Hz). If the voltage of the partition enable signal VFE is PVGH_N, there is basically no difference from the ordinary display driving circuit, and it works normally (equivalent to the 120HZ region in 1-120-1).

[0094] The embodiment of the present application also provides a display panel, which comprises the display driving circuit according to any one of the above embodiments.

[0095] In the embodiment, the display panel comprises a display panel and a display driving circuit, the display panel comprises a plurality of display pixels, each display pixel comprises at least one display pixel, and the display pixel can emit a corresponding color when lit, for example, the display pixel can emit one of red light, blue light or green light, and three colors of display pixels can constitute a display pixel. By obtaining a low-brushing display area, a pixel driving unit corresponding to the low-brushing display area is controlled to generate a corresponding pixel driving signal, and then a first clock signal received by the pixel driving unit corresponding to the low-brushing display area is subjected to frequency reduction processing to obtain a second clock signal, so that the frequency of the second clock signal is greater than or equal to the frequency of the pixel driving signal, thereby reducing the power consumption of the low-brushing display area when the display picture is refreshed and displayed in a partitioned manner, improving the power consumption benefit in the partitioned refresh application scenario, and achieving the purpose of reducing display power consumption.

[0096] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is taken as an example for description, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. In addition, the specific names of each functional unit and module are only for easy distinction, and do not limit the protection scope of the present application. The specific working process of the units and modules in the system can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0097] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0098] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the electronic device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0099] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0100] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of software functional unit.

[0101] The above examples are only used to illustrate the technical solutions of the present application, but not limit the same; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A display driving method, characterized in that, The display driving method includes: Obtain the low refresh rate display area; The second clock signal is obtained by downclocking the first clock signal corresponding to the low refresh rate display area based on the low refresh rate display area. The pixel driving unit corresponding to the low refresh rate display area generates a corresponding pixel driving signal based on the gate scan signal and the second clock signal; Wherein, the frequency of the second clock signal is greater than or equal to the frequency of the pixel driving signal; The pixel driving unit includes: a first driving transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventeenth switching transistor, and an eighteenth switching transistor, as well as a storage capacitor; The first terminal of the second switching transistor is used to receive display data signals, and the control terminal of the second switching transistor is used to receive first data control signals; The control terminal of the fourth switch is used to receive the first scan control signal, and the control terminal of the third switch is used to receive the second scan control signal; the partition enable signal outputs the second scan control signal to the control terminal of the third switch via a level conversion circuit composed of the seventeenth and eighteenth switches; the first scan control signal is configured as the gate scan signal; The control terminals of the fifth and sixth switching transistors are connected together to receive a light emission control signal; the light emission control signal is configured as the second clock signal. The control terminal of the seventh switch is connected to the control terminal of the eighth switch, and is used to receive the second data control signal; The first end of the fifth switch and the first end of the storage capacitor are connected to the first power supply terminal. The second ends of the second switch, the second end of the fifth switch, and the first end of the first driving transistor are connected together. The second end of the storage capacitor, the control terminal of the first driving transistor, and the first end of the third switch are connected together. The second ends of the third switch, the first ends of the fourth switch, the second ends of the first driving transistor, the first ends of the sixth switch, and the first ends of the eighth switch are connected together. The second end of the fourth switch is connected to the first reference signal terminal. The second ends of the sixth switch and the first ends of the seventh switch are connected to the positive terminal of the display pixel. The negative terminal of the display pixel is connected to the reference ground. The second end of the seventh switch is connected to the second reference signal terminal. The second end of the eighth switch is connected to the third reference signal terminal.

2. The display driving method according to claim 1, characterized in that, The rising edge or falling edge of the second clock signal coincides with the rising edge of the pixel drive signal.

3. The display driving method according to claim 1, characterized in that, The rising or falling edge of the second clock signal coincides with the falling edge of the pixel drive signal.

4. The display driving method according to claim 1, characterized in that, The step of downclocking the first clock signal corresponding to the low refresh rate display area to obtain the second clock signal based on the low refresh rate display area includes: When the pixel drive signal is low, the level of the first clock signal is pulled low.

5. The display driving method according to claim 1, characterized in that, The display driving method further includes: A corresponding partition enable signal is generated based on the low refresh rate display area to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal.

6. A display driving circuit, characterized in that, The display driving circuit includes multiple pixel driving units and a main control circuit, wherein the main control circuit is used to execute the display driving method as described in any one of claims 1-5; The plurality of pixel driving units are used to drive the plurality of display pixels to light up respectively.

7. The display driving circuit according to claim 6, characterized in that, The display driving circuit also includes multiple scan driving modules, and multiple gate scan lines are respectively connected to multiple scan driving modules; The scanning drive module is controlled by the main control circuit to provide gate scan signals to multiple gate scan lines, and the multiple pixel drive units are respectively connected to the corresponding gate scan lines; Each pixel driving unit is used to drive the corresponding display pixel to light up according to the received gate scan signal and data signal.

8. The display driving circuit according to claim 6, characterized in that, The second, seventh, eighth, fifth, and sixth switching transistors are P-type MOS transistors; the third and fourth switching transistors are N-type MOS transistors.

9. A display panel, characterized in that, The display panel includes the display driving circuit as described in any one of claims 6 to 8.

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