Semiconductor processing equipment

Abstract

A semiconductor processing apparatus includes: a light generator configured to output extreme ultraviolet (EUV) light having an EUV band; a mask stage configured to place a mask reflecting the EUV light output from the light generator; a light receiving optical unit including a plurality of mirrors generating output light by reflecting the EUV light reflected from the mask, at least one of the plurality of mirrors including a mirror body and a reflective layer attached to a surface of the mirror body; a power supply configured to apply a bias voltage to the reflective layer; and a substrate table configured to place a substrate from which the optical radiation is to be output.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0092345 filed in the Korean Intellectual Property Office on July 17, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to the field of semiconductor processing, and more particularly, to a semiconductor processing device with improved semiconductor processing yield. Background Art

[0004] Semiconductor processing includes light processing, etching processing, deposition processing, etc. for forming multiple layers on a substrate, wherein multiple patterns can be formed on multiple corresponding layers. As the line width and spacing of multiple patterns are gradually refined, a lithography process using relatively short-wavelength light (e.g., extreme ultraviolet (EUV) light) has been proposed. Semiconductor processing equipment that performs a lithography process using EUV light may include multiple mirrors that reflect EUV light. However, when EUV light is radiated only on a local area of ​​at least one of the multiple mirrors, deformation may occur in the mirror, which may reduce the yield of the lithography process. Summary of the invention

[0005] Generally, in some aspects, the present disclosure relates to a semiconductor processing device that improves the yield of semiconductor processing, such that a graphene layer capable of reducing temperature imbalance can be formed according to a pattern of EUV light radiated in at least one of a plurality of mirrors included in the semiconductor processing device that performs a lithography process using EUV light.

[0006] According to some aspects of the present disclosure, a semiconductor processing device includes: an illumination unit (light generator) configured to output EUV light having an EUV band; a mask stage on which a mask reflecting the EUV light output from the illumination unit is placed; a light receiving optical unit (optical light receiver) including a plurality of mirrors generating output light by reflecting the EUV light reflected from the mask, at least one of the plurality of mirrors including a mirror body and a reflective layer attached to a surface of the mirror body; a power supply configured to apply a bias voltage to the reflective layer; and a substrate stage on which a substrate irradiated with the output light is placed. In some embodiments, the reflective layer includes a plurality of silicon layers, a plurality of molybdenum layers alternately stacked with the plurality of silicon layers, and at least one graphene layer, wherein the graphene layer includes a base region having graphene and a plurality of pads attached to the base region to which the bias voltage is applied.

[0007] According to some aspects of the present disclosure, a semiconductor processing device includes: a mask stage on which a mask is placed; a substrate stage on which a substrate is placed; an illumination unit (light generator) configured to output EUV light having an EUV band to the mask; and a light receiving optical unit (optical light receiver) including a plurality of mirrors that reflect EUV light reflected from the mask and enable the EUV light to be incident on the substrate, at least one of the plurality of mirrors including a mirror body and a reflective layer attached to a surface of the mirror body. In some embodiments, the reflective layer includes a plurality of silicon layers, a plurality of molybdenum layers alternately stacked with the plurality of silicon layers, and at least one graphene layer.

[0008] According to some aspects of the present disclosure, a semiconductor processing device includes: an illumination unit (light generator) configured to output EUV light; a mask stage on which a mask that reflects EUV light output from the illumination unit is placed; a substrate stage on which a substrate that receives EUV light reflected from the mask is placed; and a light receiving optical unit (optical light receiver) disposed between the mask stage and the substrate stage and including a plurality of mirrors that reflect EUV light reflected from the mask. In some embodiments, at least one of the plurality of mirrors includes a mirror body and a reflective layer attached to a surface of the mirror body; and the reflective layer includes a plurality of first layers, a plurality of second layers, and at least one third layer. In some embodiments, the plurality of first layers, the plurality of second layers, and the third layer are formed of different materials, the plurality of first layers and the plurality of second layers are alternately stacked, wherein the thickness of the third layer is less than the thickness of each of the plurality of first layers and the plurality of second layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a schematic diagram of an exemplary semiconductor processing apparatus according to some embodiments.

[0011] Figure 2 is a diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments.

[0012] Figure 3A and Figure 3B is a diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments.

[0013] Figure 4 is a schematic diagram illustrating an exemplary mirror included in a semiconductor processing apparatus according to some embodiments.

[0014] Figures 5 to 9 is a schematic diagram illustrating an exemplary stacked structure of a reflective layer included in a mirror in a semiconductor processing apparatus according to some embodiments.

[0015] FIG. 10A to FIG. 10C is a schematic diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments.

[0016] Fig.11 is a schematic diagram of an exemplary semiconductor processing apparatus according to some embodiments.

[0017] Figures 12 to 15 is a schematic diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments.

[0018] Figures 16 to 20 is a schematic diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments.

[0019] Fig.21 and Fig. 22 is a schematic diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments.

[0020] Fig.23 is a schematic diagram illustrating an exemplary stacked structure of a reflective layer included in a mirror in a semiconductor processing apparatus according to some embodiments.

[0021] Fig.24 and Fig.25 is a schematic diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a schematic diagram illustrating an exemplary semiconductor processing apparatus according to some embodiments. Figure 1 In the figure, an exemplary semiconductor processing equipment 100 includes a device for performing a photolithography process, and may include an illumination unit (light generator) 110, an optical illumination unit (light generator) 120, a mask stage 130, a light receiving optical unit (optical light receiver) 140, a wafer stage 150 and a controller 160.

[0024] The lighting unit 110 may be configured to generate and emit EUV light with high energy density in a wavelength range of several nanometers to tens of nanometers. In some embodiments, the lighting unit 110 may generate and output EUV light with high energy density in the 13.5nm band, and may include a plasma-based light source or a synchrotron radiation light source. For example, the light source included in the lighting unit 110 may output EUV light using plasma. The light source radiates high-power laser light to a droplet formed of one of materials such as tin, lithium, and xenon, and may operate according to a laser-generated plasma (LPP) method for generating plasma, according to a discharge-generated plasma (DPP) method, or according to a master oscillator power amplifier (MOPA) method. The high-power laser collides with the droplets supplied by the droplet supply unit to form plasma, so the lighting unit 110 may include an irradiation mirror and a collector for re-concentrating the EUV light formed by the plasma. The collector is configured to act as a reflector and may be arranged close to the droplet to increase the re-condensation efficiency. The energy density of the EUV light output from the lighting unit 110 may be increased by the lighting mirror and the collector.

[0025] The optical illumination unit 120 may include a plurality of mirrors. In the exemplary semiconductor processing apparatus 100, the optical illumination unit 120 may include two or three mirrors. However, the number of mirrors included in the optical illumination unit 120 is not necessarily limited to two or three. The optical illumination unit 120 may be configured to transmit EUV light emitted from the illumination unit 110 toward the mask stage 130. Here, the EUV light emitted from the illumination unit 110 may be reflected by the mirror included in the optical illumination unit 120 and may be incident on a mask 135 disposed on the mask stage 130. In some embodiments, the mask 135 may be a reflective mask including a reflective region and a non-reflective region and / or an intermediate reflective region. In some embodiments, the mask 135 may include a reflective multilayer film for reflecting extreme ultraviolet light on a substrate formed of a low thermal expansion coefficient material (LTEM) such as quartz, and an absorption layer pattern formed on the reflective multilayer film, etc. In some embodiments, the reflective multilayer film may have a structure in which layers formed of different materials are stacked. In some embodiments, the absorption layer may be formed of TaN, TaNO, TaBO, Ni, Au, Ag, C, Te, Pt, Pd, Cr, etc. However, the material of the absorption layer is not limited to the above materials, and a portion of the absorption layer may correspond to the above non-reflection area and / or the intermediate reflection area.

[0026] The mask 135 may reflect EUV light incident through the optical illumination unit 120 and make it incident to the light receiving optical unit 140. The light receiving optical unit 140 may be configured as an imaging optical system disposed between the mask stage 130 and the wafer stage 150. In some embodiments, the EUV light passing through the optical illumination unit 120 may be structured according to a pattern formed by a reflective multilayer film and an absorption layer on a substrate in the mask 135 and may be incident to the light receiving optical unit 140.

[0027] The EUV light may be structured to include at least second-order diffraction light based on the pattern on the mask 135. The structured EUV light is incident on the light receiving optical unit 140 while retaining information in the form of a pattern included in the mask 135, and may be irradiated to the wafer 155 placed on the wafer stage 150 through the light receiving optical unit 140, thereby forming an image corresponding to the shape of the pattern included in the mask 135. In some embodiments, the structured EUV light is irradiated on a photoresist layer applied on the wafer 155, and a predetermined pattern may be formed on the photoresist layer. However, according to some embodiments, the structured EUV light passing through the light receiving optical unit 140 may be incident on a processing target other than the wafer 155.

[0028] The EUV light reflected by the mask 135 and passing through the light receiving optical unit 140 may be incident at a predetermined slope relative to the upper surface of the wafer 155. In some embodiments, the light receiving optical unit 140 may adjust the propagation path of the EUV light so that the EUV light is incident on the upper surface of the wafer 155 at an incident angle of about 6 degrees.

[0029] The mask 135 may be disposed on the mask stage 130, and the wafer 155 may be disposed on the wafer stage 150. In some embodiments, the mask stage 130 and the wafer stage 150 may be controlled by a controller 160. In an initial state where the mask 135 and the wafer 155 are disposed on the mask stage 130 and the wafer stage 150, respectively, when the upper surface of each of the mask 135 and the wafer 155 is defined as an xy plane, each of the mask stage 130 and the wafer stage 150 may be moved by the controller 160. In some embodiments, the controller 160 may be configured to rotate each of the mask stage 130 and the wafer stage 150 based on the z axis on the xy plane, or may rotate based on any axis of the xy plane on the yz plane or the xz plane. Through the movement of the mask stage 130 and / or the wafer stage 150 described above, the mask 135 and / or the wafer 155 may be moved or rotated in a three-dimensional space along the x-axis, the y-axis, and the z-axis.

[0030] The light receiving optical unit 140 may include a plurality of mirrors. Each of the plurality of mirrors included in the light receiving optical unit 140 may include a mirror body and a reflective layer attached to a surface of the mirror body. As described above, the EUV light that passes through the optical illumination unit 120 and is reflected by the mask 135 is structured and enters the light receiving optical unit 140, and each of the plurality of mirrors may reflect the structured EUV light.

[0031] Since EUV light is structured and incident on at least one of the plurality of mirrors during the exemplary process, the EUV light may be incident on only a partial area. Therefore, the temperature may rise only in some areas irradiated by the EUV light, and the characteristics of the EUV light reflected from the mirror may be unexpectedly changed due to physical deformation occurring in the mirror.

[0032] In some embodiments, to reduce the temperature imbalance as described above, the reflective layer may include at least one graphene layer. In some embodiments, the reflective layer may include a plurality of silicon layers, a plurality of molybdenum layers alternately stacked with the plurality of silicon layers, and at least one graphene layer. Here, the position where the graphene layer is disposed and the number of the graphene layers may be changed differently according to the embodiment.

[0033] The graphene layer may have a relatively high thermal conductivity compared to the silicon layer and the molybdenum layer. When the structured EUV light is radiated only on a portion of the reflective layer included in the mirror, the temperature increase due to the irradiation of the EUV light may be easily transferred to the entire area of ​​the reflective layer, and the temperature imbalance of the mirror may be reduced.

[0034] In some embodiments, the graphene layer may include a base region formed of graphene and a plurality of pads attached to the base region. The plurality of pads may be connected to a power source or the like included in the controller 160. The power source refers to a pattern of structured EUV light, so that only those areas in the mirror that are not irradiated by EUV light during processing are selectively heated. A voltage may be applied to some selected pads of the plurality of pads. Therefore, temperature imbalance according to the position of the mirror may be effectively resolved, and the yield of the processing may be improved.

[0035] Figure 2 is a diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments. Figure 2 , a semiconductor processing apparatus 200 according to some embodiments may include a light receiving optical unit (optical light receiver) 210, a mask stage 220, a wafer stage 230, a controller 240, etc. A mask 225 may be disposed on the mask stage 220, and a wafer 235 may be disposed on the wafer stage 230.

[0036] The light receiving optical unit 210 includes a plurality of mirrors 211 to 216 configured to reflect EUV light reflected from the mask 225, and the EUV light reflected by the plurality of mirrors 211 to 216 may be incident on the wafer 235. The controller 240 may be configured to operate the semiconductor processing apparatus 200 by adjusting the positions and postures of the plurality of mirrors 211 to 216 and the mask stage 220 and the wafer stage 230 so that the EUV light reflected from the mask 225 is incident on the wafer 235.

[0037] Each of the plurality of mirrors 211 to 216 may include a mirror body and a reflective layer disposed on a surface of the mirror body. The reflective layer may be a layer formed on the surface of the mirror body to increase the reflectivity of extreme ultraviolet light in each of the plurality of mirrors 211 to 216, and in some embodiments, may include a plurality of first layers and a plurality of second layers formed of different materials and alternately stacked. The first layer and the second layer are formed of materials having different refractive indices, and in some embodiments, the first layer may be formed of silicon and the second layer may be formed of molybdenum.

[0038] exist Figure 2 In the embodiment of the present invention, at least some of the plurality of mirrors 211 to 216 may have different sizes. In at least one of the plurality of mirrors 211 to 216, EUV light may be reflected after being irradiated on only a partial area of ​​the mirror, and may not be reflected onto a front surface of the mirror. Therefore, the temperature of the partial area irradiated by EUV light may be higher than the temperature of the remaining area to which EUV light is not irradiated. The shape of the mirror may be deformed due to the temperature difference, and undesirable aberrations may occur in the EUV light reflected from the mirror, and as a result, the yield of semiconductor processing performed in the semiconductor processing apparatus 200 may be reduced.

[0039] In some embodiments, in the reflective layer included in at least one of the plurality of mirrors 211 to 216 expected to be deformed due to the temperature difference, at least one third layer formed of a material different from the first layer and the second layer may be added. In some embodiments, the third layer may be formed of a material having a thickness smaller than that of each of the first layer and the second layer and having a higher thermal conductivity than the material constituting the first layer and the second layer. Therefore, the thermal conductivity of the entire reflective layer may be improved by the third layer, and the temperature difference appearing in the mirror may be significantly reduced. In some embodiments, the third layer may be formed of graphene having high thermal conductivity.

[0040] When the graphene layer is included in the reflective layer, even if the extreme ultraviolet light is radiated and reflected only on a portion of the mirror, the heat generated by the EUV light radiated on the partial area of ​​the mirror can be effectively transferred to the front surface of the mirror. Therefore, the temperature imbalance caused by the extreme ultraviolet light radiating only on a portion of the mirror can be reduced, and as a result, the deformation of the mirror can be effectively reduced.

[0041] In some embodiments, the graphene layer included in the reflective layer may include a base region formed of graphene and a plurality of pads attached to the base region. A power source is connected to the plurality of pads, and the power source may include a power circuit configured to output a bias voltage and may be included in the controller 240.

[0042] When a bias voltage is supplied to some selected pads among a plurality of pads, heat may be generated by the resistance component of the base region between the selected pads. In some embodiments, the heat generated by the bias voltage may be generated only in a partial region defined between the selected pads rather than in the entire base region. Therefore, considering the pattern of EUV light radiated to the mirror, the region in the graphene layer included in the reflective layer of the mirror that is not directly irradiated by the EUV light may be preheated by the bias voltage, and as a result, the temperature imbalance may be effectively reduced, and deformation of the mirror may be prevented.

[0043] Figure 3A and Figure 3B is a diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments. Figure 3A and Figure 3B In FIG. 1 , a pattern of EUV light 300 output by an illumination unit (light generator) is included in a semiconductor processing device, and an aberration 320 appears in a mirror 310 during semiconductor processing. Figure 3A and Figure 3B As shown, EUV light 300 output by the illumination unit may have a predetermined pattern on a plane perpendicular to the optical axis, wherein the EUV light may be radiated only on a partial area of ​​the mirror 310. Since the EUV light is radiated only on a portion of the mirror 310, the temperature of some areas radiated by the EUV light may be higher than the temperature of other areas. Therefore, the shape of the mirror 310 may be physically deformed, and aberration 320 may occur in the mirror 310, such as Figure 3A and Figure 3B Due to aberration 320 generated in mirror 310, the yield of an exemplary semiconductor process may be reduced.

[0044] In some embodiments, by adding a graphene layer to a reflective layer disposed on a surface of the mirror 310, aberration 320 generated in the mirror 310 due to unbalanced EUV radiation can be significantly reduced. Thus, a reduction in the yield of semiconductor processing can be prevented.

[0045] Figure 4 FIG. 1 is a diagram simply showing an exemplary mirror included in a semiconductor processing device according to some embodiments. Figure 4, a mirror 400 included in a semiconductor processing apparatus according to some embodiments may include a mirror body 410 and a reflective layer 420 disposed on a surface of the mirror body 410. The reflective layer 420 is disposed on a surface on which EUV light is radiated from the mirror body 410 and then reflected. In some embodiments, the reflective layer 420 may include a plurality of layers.

[0046] exist Figure 4 , the mirror 400 may be one of a plurality of mirrors included in a light receiving optical unit disposed on a path where EUV light reflected from a mask advances to a wafer. The reflective layer 420 may be attached to a surface of the mirror body 410 to improve the reflectivity of EUV light, and may include a plurality of silicon layers, a plurality of molybdenum layers, and at least one graphene layer. In some embodiments, the plurality of silicon layers and the plurality of molybdenum layers included in the reflective layer 420 are alternately stacked, and several tens (e.g., 40 to 50) Mo / Si layer pairs having one silicon layer and one molybdenum layer may be included in the reflective layer 420.

[0047] Figures 5 to 9 is a schematic diagram showing an exemplary stacking structure of a reflective layer included in a mirror in a semiconductor processing device according to some embodiments. Figure 5 In the embodiment, the reflective layer 420 may include a plurality of silicon layers 421, a plurality of molybdenum layers 422, and a graphene layer 423. In some embodiments, the upper surface of the graphene layer 423 contacts the lower surface of the silicon layer 421, and the lower surface of the graphene layer 423 may contact the upper surface of the molybdenum layer 422. The graphene layer 423 may be disposed between the silicon layer 421 located at the top of the plurality of silicon layers 421 and the molybdenum layer 422 located at the top of the plurality of molybdenum layers 422.

[0048] The thickness of the graphene layer 423 may be less than the thickness of the silicon layer 421 and the thickness of the molybdenum layer 422. In some embodiments, the sum of the thicknesses of the silicon layer 421 and the molybdenum layer 422 adjacent to each other in the stacking direction may have a value close to half of 13.5 nm (the wavelength band of EUV light). In some embodiments, the sum of the thicknesses of one silicon layer 421 and one molybdenum layer 422 in contact with each other may be 6.5 nm to 7.5 nm, and the thickness of the graphene layer 423 may be 0.2 nm to 0.5 nm.

[0049] In some embodiments, the molybdenum disilicide (MoSi 2 ) can also be disposed between the silicon layer 421 and the molybdenum layer 422 adjacent to each other in the stacking direction. The heating layer can be a layer intentionally inserted between the silicon layer 421 and the molybdenum layer 422 by a deposition process or the like. Therefore, the reflection efficiency of the reflective layer 420 can be improved by adding the heating layer.

[0050] The thickness of the heating layer may be smaller than the corresponding thicknesses of the silicon layer 421 and the molybdenum layer 422. In some embodiments, when the heating layer is added, the sum of the thicknesses of the silicon layer 421 and the molybdenum layer 422 adjacent to each other in the stacking direction and the heating layer therebetween may have a value close to half of 13.5 nm (the wavelength band of EUV light).

[0051] exist Figure 6 , the reflective layer 420A may include a plurality of silicon layers 421, a plurality of molybdenum layers 422, and a graphene layer 423. In some embodiments, the lower surface of the graphene layer 423 contacts the upper surface of the uppermost silicon layer 421, and the upper surface of the graphene layer 423 is exposed to the outside and may directly receive EUV light. In some embodiments, the graphene layer 423 may be disposed on the lowermost side of the reflective layer 420A, wherein one surface of the graphene layer 423 may contact the surface of the mirror body.

[0052] exist Figure 6 In addition to the arrangement of the graphene layer 423, other characteristics can be similar to those described above with reference to Figure 5 Those described. In some embodiments, the sum of the thicknesses of one silicon layer 421 and one molybdenum layer 422 that are in contact with each other in the stacking direction may have a value close to half of 13.5 nm (the wavelength band of EUV light). In addition, the thickness of the graphene layer 423 may be smaller than the thickness of the silicon layer 421 and the thickness of the molybdenum layer 422. In some embodiments, a heating layer formed of a material having a high heating characteristic (such as molybdenum disilicide) may be additionally provided between the silicon layer 421 and the molybdenum layer 422.

[0053] exist Figure 7 In some embodiments, the reflective layer 420B may include a plurality of silicon layers 421, a plurality of molybdenum layers 422, and a graphene layer 423. In some embodiments, the upper surface of the graphene layer 423 may contact the lower surface of the uppermost molybdenum layer 422, wherein the graphene layer 423 may be disposed below the silicon layer 421 and the molybdenum layer 422 disposed on the top. In some embodiments, other characteristics except the arrangement of the graphene layer 423 may be similar to those described above with reference to Figure 5 Those described.

[0054] exist Figures 5 to 7 In FIG. 4 , the reflective layers 420 , 420A, and 420B are shown as including only one graphene layer 423 , but in some embodiments, two or more graphene layers 423 and 424 may be disposed on the reflective layer 420C. Figure 8In the embodiment, among the plurality of silicon layers 421 and the plurality of molybdenum layers 422 included in the reflective layer 420C, the first graphene layer 423 may be disposed between the uppermost silicon layer 421 and the uppermost molybdenum layer 422. In some embodiments, the second graphene layer 424 may be disposed below the uppermost molybdenum layer 422. In some embodiments, the number of graphene layers 423 and 424 is not necessarily limited to two, and the number of graphene layers 423 and 424 may be three or more. In some embodiments, the positions where the graphene layers 423 and 424 are inserted are not limited to Figures 5 to 8 The exemplary embodiments are shown and may be selected in various ways.

[0055] exist Fig. 9 , the reflective layer 420D may include a plurality of silicon layers 421, a plurality of molybdenum layers 422, graphene layers 423 and 424, and metal layers 425 and 426. The stacking order of the plurality of silicon layers 421, the plurality of molybdenum layers 422, and the graphene layers 423 and 424 may be similar to that described above with reference to Figure 8 In some embodiments, the reflective layer 420D may further include a first metal layer 425 and a second metal layer 426. Each of the first metal layer 425 and the second metal layer 426 may be a layer configured to increase the reflectivity of the reflective layer 420D. In some embodiments, the silicon layer 421 is disposed on the first metal layer 425 and the molybdenum layer 422 is disposed below. The molybdenum layer 422 may be disposed above the second metal layer 426 and the silicon layer 421 may be disposed below.

[0056] In some embodiments, each of the first metal layer 425 and the second metal layer 426 may be multiple. For example, the first metal layer 425 is disposed between the silicon layer 421 and the molybdenum layer 422 in the stacking direction, and the second metal layer 426 may be disposed between the molybdenum layer 422 and the silicon layer 421 in the stacking direction. The first metal layer 425 may be formed of yttrium or niobium. The second metal layer 426 may be formed of ruthenium.

[0057] In some embodiments, the first graphene layer 423 is disposed between the first metal layer 425 and the molybdenum layer 422, and the second graphene layer 424 may be disposed between the second metal layer 426 and the silicon layer 421. For example, like the first graphene layer 423 and the second graphene layer 424, the thickness of each of the first metal layer 425 and the second metal layer 426 may be smaller than the thickness of each of the silicon layer 421 and the molybdenum layer 422.

[0058] FIG. 10A to FIG. 10C is a schematic diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments. FIG. 10A to FIG. 10C An equivalent thermal circuit may be provided to describe the thermal conductivity characteristics of a reflective layer attached to a mirror in a semiconductor processing device according to some embodiments. FIG. 10A to FIG. 10CIn FIG. 4 , thermal resistances R1-R4 representing thermal conductivity characteristics are shown. For ease of explanation, it is assumed that the thickness and length of the silicon layer 421 and the molybdenum layer 422 are FIG. 10A to FIG. 10C The same in each of them.

[0059] Fig. 10A It can be an equivalent thermal circuit of a reflective layer including only the silicon layer 421 and the molybdenum layer 422. Fig. 10A The thermal resistance R of the reflective layer including only the silicon layer 421 and the molybdenum layer 422 is tot1 It may be defined as in the following Equation 1. In Equation 1, Ksi and Kmo are thermal conductivities of silicon and molybdenum, respectively, A is the thickness of the silicon layer and the molybdenum layer, and L may be the length of the silicon layer and the molybdenum layer.

[0060]

[0061] Fig. 10B It can be an equivalent thermal circuit of a reflective layer including a silicon layer 421, a molybdenum layer 422 and a graphene layer 423. Fig. 10B The thermal resistance R of the reflective layer including the silicon layer 421, the molybdenum layer 422 and the graphene layer 423 is tot2 It may be defined as in the following Equation 2. For convenience of explanation, it is assumed that the thickness of the graphene layer 423 is 1 / 10 of the thickness of each of the silicon layer 421 and the molybdenum layer 422 .

[0062] In Equation 2, Kg may be the thermal conductivity of graphene.

[0063]

[0064] In some embodiments, the thermal conductivity of graphene can be about 38 times that of silicon and about 35 times that of molybdenum. Fig. 10B The thermal resistance R of the reflective layer of the embodiment shown in FIG. tot2 Can be less than according to Fig. 10A The thermal resistance R of the reflective layer of the embodiment shown in FIG. tot1 By inserting the graphene layer 423, the thermal conductivity of the reflective layer can be improved. When EUV light is radiated only on a partial area of ​​the mirror including the reflective layer, deformation due to temperature imbalance of the mirror can be significantly reduced, and the occurrence of aberration of the mirror is effectively suppressed.

[0065] Fig. 10C It may be an equivalent thermal circuit of a reflective layer including a silicon layer 421, a molybdenum layer 422, and a plurality of graphene layers 423 and 424. Fig. 10C The thermal resistance R of the reflective layer including the silicon layer 421, the molybdenum layer 422 and the graphene layers 423 and 424 is tot3It may be defined as in the following Equation 3. For ease of description, it is assumed that the thickness of each of the graphene layers 423 and 424 is 1 / 10 of the thickness of each of the silicon layer 421 and the molybdenum layer 422 .

[0066]

[0067] exist Fig. 10C The thermal resistance R of the reflective layer tot3 Can be less than according to Fig. 10A The thermal resistance R of the reflective layer of the embodiment shown in FIG. tot1 and according to Fig. 10B The thermal resistance R of the reflective layer of the embodiment shown in FIG. tot2 When EUV light is irradiated onto only a portion of the mirror including the reflective layer, deformation due to temperature imbalance of the mirror can be significantly reduced, and the occurrence of aberration of the mirror can be effectively suppressed.

[0068] Fig.11 is a schematic diagram of an exemplary semiconductor processing apparatus according to some embodiments. Fig.11 In the semiconductor processing device 500, the reflective layer attached to the mirror includes a graphene layer 510, and the graphene layer 510 may include a base region 511 containing graphene and a plurality of pads 512 and 513 attached to the base region 511. The plurality of pads 512 and 513 are formed of a metal material and may be arranged along an edge of the base region 511. In some embodiments, the plurality of pads 512 and 513 may be attached to a position other than the edge of the base region 511.

[0069] The plurality of pads 512 and 513 may include a first pad 512 and a second pad 513. The first pad 512 may be connected to a first switch circuit 521 through a plurality of first wires 501, and the second pad 513 may be connected to a second switch circuit 522 through a plurality of second wires 502. The first switch circuit 521 and the second switch circuit 522 may provide a power supply 520 together with a power supply circuit 523.

[0070] The first switch circuit 521 may be configured to select one of the plurality of first conductive lines 501 to determine a first selected pad among the first pads 512. In some embodiments, the second switch circuit 522 may be configured to select one of the plurality of second conductive lines 502 to determine a second selected pad among the second pads 513. The first switch circuit 521 includes a first multiplexer, and the second switch circuit 522 may include a second multiplexer.

[0071] When the first selection pad and the second selection pad are determined, the power supply circuit 523 may be configured to output a predetermined bias voltage. Therefore, heat may be generated by the bias voltage in a partial selection area defined between the first selection pad and the second selection pad in the base area 511. In some embodiments, by selecting a selection area to which a bias voltage output from the power supply circuit 523 is applied, the first switch circuit 521 and the second switch circuit 522 are selected, and the temperature of the selected area as a part of the base area 511 may be increased. Therefore, while radiating EUV light having a predetermined pattern, a bias voltage is applied by selecting an area in the mirror including a reflective layer that is not radiated by EUV light, thereby effectively solving the temperature imbalance of the mirror including the reflective layer.

[0072] Figures 12 to 15 is a schematic diagram illustrating an exemplary operation of a semiconductor processing device according to some embodiments. Figures 12 to 15 The semiconductor processing apparatus 500 described may be similar to the one previously described with reference to Fig.11 In some embodiments, the semiconductor processing device 500 may include: a graphene layer 510 including a base region 511 having graphene and a plurality of pads 512 and 513 formed of a conductive material such as metal; and a power supply 520. The graphene layer 510 may be included in a reflective layer attached to a surface of a mirror reflecting EUV light.

[0073] exist Fig.12 , a first selection pad 512A may be determined among the first pads 512 by the first switch circuit 521, and a second selection pad 513A may be determined among the second pads 513 by the first switch circuit 522. A bias voltage output from the power supply circuit 523 is applied to the first selection pad 512A and the second selection pad 513A, and heat may be generated in a selection area 516A which is a part of the base area 511. The selection area 516A may be selected as an area to which EUV light is not radiated from a mirror to which a reflective layer including a graphene layer 510 is attached. By determining an area not radiated by EUV light as the selection area 516A and applying a bias voltage to generate heat, the yield of semiconductor processing using extreme ultraviolet light may be improved by reducing temperature imbalance in all areas of the mirror and suppressing the occurrence of aberrations due to temperature imbalance.

[0074] exist Fig.13In the embodiment, the first selection pad 512B in the first pad 512 is determined by the first switch circuit 521, and the second selection pad 513B in the second pad 513 is determined by the first switch circuit 522. The bias voltage output from the power supply circuit 523 is applied to the first selection pad 512B and the second selection pad 513B. Therefore, heat can be generated in the selection area 516B which is a part of the base area 511. In some embodiments, the selection area 516B may be different from the selection area 516A. In some embodiments, the selection areas 516A and 516B may be adjusted in consideration of the pattern of EUV light radiated to the mirror. By pre-applying the bias voltage to the selection areas 516A and 516B before radiating EUV light, or by applying the bias voltage to the selection areas 516A and 516B while radiating EUV light, the temperature imbalance in all areas of the mirror can be significantly reduced, and the occurrence of aberrations can be suppressed.

[0075] In some embodiments, the area of ​​the selected region where heat is generated by the bias voltage can be adjusted by adjusting the time for which the bias voltage is applied. Fig.14 In the embodiment, the first selection pad 512B and the second selection pad 513B can be arranged according to the reference Fig.13 The embodiment described above is determined in the same manner. Fig.14 , the bias voltage output from the power supply circuit 523 may be applied to the first selection pad 512B and the second selection pad 513B for a relatively longer time. Therefore, the selection area in which heat is generated by the bias voltage may extend from the first selection area 516B1 to the second selection area 516B2 as the time of applying the bias voltage elapses. However, in some embodiments, the temperature of the second selection area 516B2 may be relatively lower than the temperature of the first selection area 516B1. As described above, in some embodiments, the temperature of the selected area may be controlled by adjusting the time of applying the bias voltage, the amplitude of the bias voltage, etc. While radiating EUV light, the temperature difference of the area of ​​the mirror may be reduced, and the occurrence of aberrations may be significantly reduced.

[0076] In some embodiments, according to the position, area, etc. of the selected region, in order to increase the temperature by applying a bias voltage, at least one of the first switch circuit 521 and the second switch circuit 522 may select two or more selection pads. Fig.15 , unlike the first switch circuit 521 which selects one first selection pad 512C, the second switch circuit 522 can select three second selection pads 513C, 513D, and 513E. Therefore, in the base region 511, the bias voltage is simultaneously applied to all three selection regions 516C, 516D, and 516E. Heat can be simultaneously generated in the selected regions 516C, 516D, and 516E.

[0077] exist Fig.15In the embodiment, in a mirror to which a reflective layer including a graphene layer 510 is attached, a light irradiation region 519 may be selected. EUV light irradiated to the light irradiation region 519 may be reflected to the next mirror or wafer, so that only the temperature of the light irradiation region 519 may be locally increased.

[0078] exist Fig.15 In the embodiment, by applying a bias voltage between the first selection pad 512C and the plurality of second selection pads 513C, 513D, and 513E, the temperature of the region other than the light irradiation region 519 can be increased. By suppressing the temperature imbalance of the mirror and minimizing the occurrence of aberrations, the yield of semiconductor processing can be stably maintained using EUV light.

[0079] Figures 16 to 20 is a schematic diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments.

[0080] exist Fig.16 and Fig.17 In the semiconductor processing device 600, the reflective layer attached to the mirror may include a graphene layer 610, and the graphene layer 610 may include a base region 611 containing graphene and a plurality of pads 612, 613, 614, and 615 attached to the base region 611. The plurality of pads 612, 613, 614, and 615 may be formed of a conductive material. The plurality of pads 612, 613, 614, and 615 may be divided into a first pad 612, a second pad 613, a third pad 614, and a fourth pad 615. In some embodiments, the first pad 612 is a pad arranged along the left edge of the base region 611, and the second pad 613 may be a pad arranged along the right edge of the base region 611. In some embodiments, the third pad 614 is a pad arranged along the upper edge of the base region 611, and the fourth pad 615 may be a pad arranged along the lower edge of the base region 611.

[0081] exist Fig.16 and Fig.17 , the power supply 620 includes a first switch circuit 621, a second switch circuit 622, a first power supply circuit 623, a third switch circuit 624, a fourth switch circuit 625, and a second power supply circuit 626. The first switch circuit 621 is connected between the first pad 612 and the first power supply circuit 623, and the second switch circuit 622 can be connected between the second pad 613 and the first power supply circuit 623. In some embodiments, the third switch circuit 624 is connected between the third pad 614 and the second power supply circuit 626, and the fourth switch circuit 625 can be connected between the fourth pad 615 and the second power supply circuit 626. Therefore, each of the plurality of pads 612, 613, 614, and 615 can be commonly connected to two of the first switch circuit 621, the second switch circuit 622, the third switch circuit 624, and the fourth switch circuit 625.

[0082] exist Fig.16 and Fig.17 In the embodiment, by differently setting the time when the first power supply circuit 623 and the second power supply circuit 626 output the bias voltage, the temperature of the first point P1 to the third point P3 can be differently controlled. Fig.16 , the first switch circuit 621 may be configured to select the first selection pad 612A from the first pad 612, and the second switch circuit 622 may be configured to select the second selection pad 613A from the second pad 613. Each of the third switch circuit 624 and the fourth switch circuit 625 may be turned off so that the selection pad among the third pad 614 and the fourth pad 615 may not be selected. The first bias voltage output from the first power supply circuit 623 may be applied to the first selection area 616 between the first selection pad 612A and the second selection pad 613A. Therefore, the temperatures of the first point P1 and the second point P2 included in the first selection area 616 may also be increased.

[0083] exist Fig.17 , the first switch circuit 621 and the second switch circuit 622 are turned off, the third switch circuit 624 may be configured to select the first selection pad 614A from the third pad 614, and the fourth switch circuit 625 may be configured to select the second selection pad 615A from the fourth pad 615. Therefore, the second bias voltage output from the second power supply circuit 626 is applied to the second selection region 618, and the temperatures of the second point P2 and the third point P3 may increase.

[0084] The light irradiation area 619 where EUV light is irradiated to the mirror to which the reflective layer including the graphene layer 610 is attached can be as follows: Fig.17 To increase the temperature of the region other than the light irradiation region 619, as shown in FIG. Fig.16 and Fig.17 As described, the bias voltage is applied to the first selection area 616 and the second selection area 618 in sequence, and the temperature imbalance of the mirror can be resolved.

[0085] Figures 18 to 20 It is shown in Fig.16 and Fig.17 A timing diagram of an exemplary operation of a semiconductor processing device 600 is shown in FIG. Fig.18 is a diagram showing an exemplary operation of the first power supply circuit 623 and the resulting change in the temperature of the base region 611. Fig.18 In the embodiment, between the first time point t1 and the second time point t2, the first bias voltage VB may be applied to the first selection region 616. Therefore, the temperature of the first point P1 included in the first selection region 616 may rise to the first temperature T1.

[0086] Fig.19is a diagram showing an exemplary operation of the second power supply circuit 626 and a temperature change of the base area 611 according to the operation. Fig.19 , between the third time point t3 and the fourth time point t4, the second bias voltage VB may be applied to the second selection region 618. Therefore, the temperature of the third point P3 included in the second selection region 618 may be increased to the first temperature T1. The second bias voltage VB outputted from the second power supply circuit 626 may have the same level as the first bias voltage VB outputted from the first power supply circuit 623.

[0087] Reference Fig.16 and Fig.17 , Fig.18 The exemplary operations shown in Fig.19 The exemplary operations shown in can be performed continuously. Fig. 20 In the embodiment, the first bias voltage VB is applied to the first selection region 616 between the first time point t1 and the second time point t2, and the second bias voltage VB may be applied to the second selection region 618 between the third time point t3 and the fourth time point t4.

[0088] The temperature of the second point P2 overlapping the first selection area 616 and the second selection area 618 is increased to the first temperature T1 at the second time point t2, and from the third time point t3, the temperature can be increased again by the second bias voltage to reach the second temperature T2. As described above, in the semiconductor processing equipment 600, the time when each of the first power supply circuit 623 and the second power supply circuit 626 applies the bias voltage is controlled, and the temperatures of the points P1-P3 defined in the base area 611 can be set differently.

[0089] Fig.21 and Fig. 22 is a schematic diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments. Fig.21 and Fig. 22 The configuration of the semiconductor processing equipment 600 may be the same as that described above. Fig.16 and Fig.17 However, in Fig.21 and Fig. 22 In order to increase the temperature of the area other than the light irradiation area 619, the bias voltage may be applied to the first selection pad 612A, the second selection pad 613A, the third selection pad 614A, and the fourth selection pad 615A at the same time. In some embodiments, each of the first power supply circuit 623 and the second power supply circuit 626 may be configured to output the bias voltage VB during the time from the first time point t1 to the second time point t2, such as Fig. 22Therefore, the bias voltage is simultaneously applied to the first selection pad 612A, the second selection pad 613A, the third selection pad 614A, and the fourth selection pad 615A, and the temperatures of the first selection area 616 and the second selection area 618 may be increased.

[0090] Fig. 22 The temperature graph of FIG. 61 shows a graph showing the temperatures of a first point P1 included in the first selection area 616, a second point P2 overlapping the first selection area 616 and the second selection area 618, and a third point P3 included in the second selection area 618. The temperatures of the first point P1 and the third point P3 may be increased to the first temperature T1 by the bias voltage. In some embodiments, the temperature of the second point P2 overlapping both the first selection area 616 and the second selection area 618 may be increased to the second temperature T2 by the bias voltage outputted from each of the first power supply circuit 623 and the second power supply circuit 626.

[0091] Fig.23 is a schematic diagram showing an exemplary stacking structure of a reflective layer included in a mirror in a semiconductor processing device according to some embodiments. Fig.23 In the embodiment, the reflective layer 700 included in the mirror may include a plurality of silicon layers 710, a plurality of molybdenum layers 720, and a plurality of graphene layers 730 and 740. Figures 5 to 9 The arrangement and thickness of the multiple silicon layers 710, the multiple molybdenum layers 720, and the multiple graphene layers 730 and 740 can be understood by referring to the description.

[0092] exist Fig.23 In the embodiment, the first graphene layer 730 may include a base region 731 formed of graphene and a plurality of pads 732 attached to the base region 731. In some embodiments, the second graphene layer 740 may further include a base region 741 and a plurality of pads 742. Fig.23 As shown, the position where the plurality of pads 732 are attached to the base region 731 in the first graphene layer 730 may be different from the position where the plurality of pads 742 are attached to the base region 741 in the second graphene layer 740. The plurality of pads 732 included in the first graphene layer 730 and the plurality of pads 742 included in the second graphene layer 740 may be connected to different power supplies. Therefore, in the first graphene layer 730, a selected region where a bias voltage is applied and heat is generated may be determined to be a position different from that of a selected region where heat is generated by applying a bias voltage in the second graphene layer 740, and to have a different shape, etc. According to the position and area of ​​the light irradiation region where EUV light is irradiated to the mirror to which the reflective layer 700 is attached, by appropriately selecting a selected region in each of the first graphene layer 730 and the second graphene layer 740, the temperature imbalance of the mirror may be significantly reduced, and the generation of aberrations may be suppressed.

[0093] Fig.24 and Fig.25 is a schematic diagram illustrating an exemplary operation of a semiconductor processing apparatus according to some embodiments. Fig.24 , the first graphene layer 730 is connected to the first power source 750. The first graphene layer 730 includes a base region 731 and a plurality of pads 732 and 733, and the first power source 750 may include a first switch circuit 751, a second switch circuit 752, and a power circuit 753. The first switch circuit 751 is connected to the plurality of first pads 732 through the plurality of first wires 701, and the second switch circuit 752 may be connected to the plurality of second pads 733 through the plurality of second wires 702.

[0094] exist Fig.25 , the second graphene layer 740 may be connected to the second power source 760. In some embodiments, the second graphene layer 740 includes a base region 741 and a plurality of pads 742 and 743, and the second power source 760 may include a first switch circuit 761, a second switch circuit 762, and a power circuit 763. The first switch circuit 761 is connected to the plurality of first pads 742 through the plurality of first wires 703, and the second switch circuit 762 is connected to the plurality of second pads 743 through the plurality of second wires 704.

[0095] exist Fig.24 and Fig.25 , positions at which the plurality of pads 732 and 733 are disposed in the first graphene layer 730 and positions at which the plurality of pads 742 and 743 are disposed in the second graphene layer 740 may be different from each other. Therefore, a selected area in which heat is generated in the first graphene layer 730 by the first power source 750 may be disposed differently from a selected area in which heat is generated in the second graphene layer 740 by the second power source 760. By differently disposing and combining the selected area of ​​the first graphene layer 730 and the selected area of ​​the second graphene layer 740, in the mirror to which the reflective layer 700 is attached, the temperature of an area other than a light irradiation area to which EUV light is irradiated may be effectively increased. Therefore, temperature imbalance occurring while EUV light is irradiated to the mirror to which the reflective layer 700 is attached and aberration caused thereby may be suppressed, and the yield of semiconductor processing using extreme ultraviolet light may be stably managed.

[0096] As described above, according to some embodiments, the reflective layer included in at least one of the plurality of mirrors included in the semiconductor processing equipment may include a graphene layer. The graphene layer has a relatively high thermal conductivity compared to other layers included in the reflective layer, and therefore, the temperature imbalance generated in the mirror may be alleviated by the graphene layer. In addition, according to some embodiments, by applying a voltage to the graphene layer to increase the temperature of at least a portion of the graphene layer, the temperature imbalance generated in the mirror may be reduced and the yield of semiconductor processing may be improved.

[0097] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of the claimed protection. Certain features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially required in this way, in some cases, one or more features from a combination may be removed from the combination, and the combination may point to a variant of a sub-combination or a sub-combination.

Claims

1. A semiconductor processing device comprising: a light generator configured to output extreme ultraviolet light having an extreme ultraviolet band; a mask stage configured to place a mask configured to reflect the extreme ultraviolet light output from the light generator; an optical light receiver comprising a plurality of mirrors configured to generate output light by reflecting the extreme ultraviolet light reflected from the mask, at least one of the plurality of mirrors comprising a mirror body and a reflective layer attached to a surface of the mirror body; a power supply configured to apply a bias voltage to the reflective layer; as well as a substrate stage configured to place a substrate to be irradiated with the output light, The reflective layer includes a plurality of silicon layers, a plurality of molybdenum layers alternately stacked with the plurality of silicon layers, and at least one graphene layer, and Wherein, the at least one graphene layer comprises: a base region including graphene, and A plurality of pads are attached to the base region and are configured such that the bias voltage can be applied to the plurality of pads.

2. The semiconductor processing equipment according to claim 1, wherein: The plurality of pads are arranged along an edge of the base region.

3. The semiconductor processing equipment according to claim 1, wherein: The power supply comprises: a first power supply circuit configured to output a first bias voltage, a first switch circuit connected between a first pad of the plurality of pads and the first power supply circuit, and A second switch circuit is connected between a second pad of the plurality of pads and the first power supply circuit, the second pad being different from the first pad.

4. The semiconductor processing equipment according to claim 3, in, The first switching circuit includes a first multiplexer, and Wherein, the second switch circuit includes a second multiplexer.

5. The semiconductor processing equipment according to claim 3, in, The first switch circuit is configured to determine a first selection pad among the first pads, The second switch circuit is configured to determine a second selection pad among the second pads, and The first power supply circuit is configured to apply the first bias voltage to the first selection pad and the second selection pad.

6. The semiconductor processing equipment according to claim 5, wherein: The first switch circuit and the second switch circuit are configured to determine the first selection pad and the second selection pad based on a position and an area of ​​a radiation region in which the extreme ultraviolet light is radiated in at least one mirror among the plurality of mirrors.

7. The semiconductor processing equipment according to claim 3, wherein: The power supply also includes: a second power supply circuit configured to output a second bias voltage, a third switch circuit connected between a third pad among the plurality of pads and the second power supply circuit, and A fourth switch circuit is connected between a fourth pad among the plurality of pads and the second power supply circuit, the fourth pad being different from the third pad.

8. The semiconductor processing equipment according to claim 7, in, The first switch circuit is configured to determine a first selection pad among the first pads, The second switch circuit is configured to determine a second selection pad among the second pads, The third switch circuit is configured to determine a third selection pad among the third pads, and The second switch circuit is configured to determine a fourth selection pad among the fourth pads, wherein the first power supply circuit is configured to apply a first bias voltage to the first selection pad and the second selection pad in a first time period, and The second power supply circuit is configured to apply a second bias voltage to the third selection pad and the fourth selection pad in a second time period after the first time period.

9. A semiconductor processing device comprising: a mask stage configured to place a mask; a substrate stage configured to place a substrate; a light generator configured to output extreme ultraviolet light having an extreme ultraviolet band to the mask; as well as an optical light receiver comprising a plurality of mirrors configured to reflect the extreme ultraviolet light reflected from the mask and allow the extreme ultraviolet light to be incident on the substrate, at least one of the plurality of mirrors comprising a mirror body and a reflective layer attached to a surface of the mirror body, The reflective layer includes a plurality of silicon layers, a plurality of molybdenum layers alternately stacked with the plurality of silicon layers, and at least one graphene layer.

10. The semiconductor processing equipment according to claim 9, wherein: The graphene layer has a thickness smaller than a thickness of each of the plurality of silicon layers and the plurality of molybdenum layers.

11. The semiconductor processing equipment according to claim 9, wherein: The reflective layer further includes a plurality of metal layers disposed between the plurality of silicon layers and the plurality of molybdenum layers.

12. The semiconductor processing equipment according to claim 11, wherein: The plurality of metal layers include: at least one first metal layer comprising yttrium or niobium, and At least one second metal layer includes ruthenium.

13. The semiconductor processing equipment according to claim 11, in, The graphene layer comprises a first surface and a second surface parallel to the first surface, wherein the first surface is in contact with one of the plurality of silicon layers and the plurality of molybdenum layers, and Wherein, the second surface contacts at least one of the plurality of metal layers.

14. The semiconductor processing equipment according to claim 9, in, The graphene layer comprises a first surface and a second surface parallel to the first surface, wherein the first surface is in contact with one of the plurality of silicon layers, and Wherein, the second surface is in contact with one of the plurality of molybdenum layers.

15. The semiconductor processing equipment according to claim 9, in, The graphene layer comprises a first surface and a second surface parallel to the first surface, wherein the first surface is an outwardly exposed surface, and The second surface contacts one of the plurality of silicon layers and the plurality of molybdenum layers.

16. The semiconductor processing equipment according to claim 9, in, The graphene layer comprises a first surface and a second surface parallel to the first surface, wherein the first surface is in contact with one of the plurality of silicon layers and the plurality of molybdenum layers, and The second surface is in contact with a surface of the mirror body.

17. The semiconductor processing equipment according to claim 9, in, The graphene layer includes a first graphene layer and a second graphene layer, wherein each of the first graphene layer and the second graphene layer comprises a first surface and a second surface parallel to the first surface, wherein, in each of the first graphene layer and the second graphene layer, the first surface is located farther away from the mirror body than the second surface, wherein the first surface of the first graphene layer contacts a first silicon layer among the plurality of silicon layers, and Wherein, the second surface of the first graphene layer contacts the first molybdenum layer among the multiple molybdenum layers.

18. The semiconductor processing equipment according to claim 17, in, The first surface of the second graphene layer is in contact with a second molybdenum layer of the plurality of molybdenum layers, wherein the second surface of the second graphene layer contacts the second silicon layer of the plurality of silicon layers, and Wherein, the first molybdenum layer and the second molybdenum layer are the same molybdenum layer.

19. A semiconductor processing device comprising: a light generator configured to output extreme ultraviolet light; a mask stage configured to place a mask configured to reflect the extreme ultraviolet light output from the light generator; a substrate stage configured to place a substrate, the substrate configured to receive the extreme ultraviolet light reflected from the mask; as well as an optical light receiver disposed between the mask stage and the substrate stage and including a plurality of mirrors that reflect the extreme ultraviolet light reflected from the mask, wherein at least one of the plurality of mirrors comprises a mirror body and a reflective layer attached to a surface of the mirror body, The reflective layer includes a plurality of first layers, a plurality of second layers and at least one third layer. wherein the plurality of first layers have a first material, the plurality of second layers have a second material, and the third layer has a third material, wherein the first material, the second material and the third material are different from each other, wherein the plurality of first layers and the plurality of second layers are stacked alternately, and The thickness of the third layer is smaller than the thickness of each of the plurality of first layers and the plurality of second layers.

20. The semiconductor processing equipment according to claim 19, wherein: The thermal conductivity of the material constituting the third layer is higher than the thermal conductivity of the material constituting the plurality of first layers and the thermal conductivity of the material constituting the plurality of second layers.

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