VMID voltage generator with low standby power consumption

Abstract

The invention discloses a VMID voltage generator with low standby power consumption, which is applied to a driver IC and provides VMID voltage for the driver IC. The VMID voltage generator comprises a VMID voltage generation circuit with high power consumption and a VMID voltage generation circuit with ultra-low power consumption. The high-power-consumption VMID voltage generation circuit is composed of high-power-consumption electronic components. The ultra-low power consumption VMID voltage generation circuit is composed of an ultra-low power consumption electronic component. When the driver IC operates in a normal mode, the high-power-consumption VMID voltage generation circuit is turned on, the ultra-low-power-consumption VMID voltage generation circuit is turned off, and the VMID voltage is generated by the high-power-consumption VMID voltage generation circuit. When the driver IC is operated in a standby mode, the high-power-consumption VMID voltage generation circuit is turned off, the ultra-low-power-consumption VMID voltage generation circuit is turned on, and the VMID voltage is generated by the ultra-low-power-consumption VMID voltage generation circuit. Therefore, when the driver IC is standby, the VMID voltage generating circuit with ultra-low power consumption is selected to provide the VMID voltage, so that the standby power consumption of the driver IC can be greatly reduced.

Description

[0001] This application is a divisional application of the invention patent application with application number 202411460134.1. The filing date of the original application is October 18, 2024. Technical Field

[0002] The invention relates to a VMID voltage generator, in particular to a VMID voltage generator with ultra-low power consumption in a standby state. Background Art

[0003] Figure 1 Figure 2 is a schematic diagram of the driver circuit architecture and its voltage range. Figure 1 As shown, the driver IC 100 can also be a source driver IC applied to a liquid crystal panel, and its main structure includes a positive voltage operational amplifier (POP) 11 and a negative voltage operational amplifier (NOP) 12. The positive voltage operational amplifier 11 generates a voltage between VMID and AVDD for use by the subsequent liquid crystal panel, while the negative voltage operational amplifier 12 generates a voltage between 0V and VMID for use by the subsequent liquid crystal panel. Different grayscales can be displayed when the voltage across the liquid crystal on the panel is different.

[0004] In the source driver IC application of small and medium-sized LCD panels, since the liquid crystal flip voltage is within 6V, the AVDD application will be within 12V for the full positive half-voltage LCD panel architecture, and VMID is a voltage between 0V and AVDD. For example, VMID can be a median voltage equal to or close to AVDD / 2. Different from the source driver IC of large-sized LCD panels that use high-voltage electronic components (such as 32V), the source driver IC of small and medium-sized LCD panels uses medium-voltage electronic components (such as 6V) for circuit design.

[0005] In the source driver IC of small and medium-sized LCD panels, a VMID voltage generator is usually required inside the IC to generate the VMID voltage. Figure 2 FIG. 1 is a schematic diagram of a conventional VMID voltage generator. Figure 2 As shown, the VMID voltage generator 200 includes a bandgap reference circuit 21 and an operational amplifier 22. The bandgap reference circuit 21 provides a reference voltage and a reference current to the operational amplifier 22, and the operational amplifier 22 generates a VMID voltage and provides a thrust to drive the VMID voltage according to the reference voltage and the reference current.

[0006] The operation modes of the source driver IC include a normal mode and a standby mode. In the normal mode, the source driver IC will turn on most of the internal circuits, and the turned-on circuits include the VMID voltage generator 200. The turned-on VMID voltage generator 200 will normally provide the VMID voltage. In the standby mode, the source driver IC will turn off most of the internal circuits to reduce power consumption. However, due to the problem of the withstand voltage of electronic components, the source driver IC still needs to continue to provide the VMID voltage. Therefore, in the past, when the source driver IC operates in the standby mode, it is still necessary to provide the VMID voltage through the VMID voltage generator 20.

[0007] In addition, taking the actual circuit design as an example, when the bandgap reference circuit 21 and the operational amplifier 22 are turned on and operated in normal mode, the bandgap reference circuit 21 consumes about 50uA and the operational amplifier 22 consumes about 450uA, so the total power consumption is 500uA; when the bandgap reference circuit 21 and the operational amplifier 22 are turned on and operated in standby mode, the power consumption of the bandgap reference circuit 21 can be reduced to 20uA and the power consumption of the operational amplifier 22 can be reduced to 80uA, so the total power consumption is reduced to 100uA.

[0008] Therefore, those familiar with the field of electronic circuit technology should understand that the traditional bandgap reference circuit 21 and the operational amplifier 22 are composed of circuit components with high power consumption. Even if operating in standby mode, as long as the bandgap reference circuit 21 and the operational amplifier 22 are turned on, the VMID voltage generator 200 will have a lot of power consumption (for example, the total power consumption in standby mode is still 100uA), making it difficult for the LCD panel or the source driver IC to further reduce power consumption in standby mode. Summary of the invention

[0009] In the past, when the driver IC was operating in standby mode, the bandgap reference circuit and operational amplifier in the traditional VMID voltage generator were used to generate the VMID voltage. However, the bandgap reference circuit and operational amplifier are composed of high-power electronic components. Therefore, the driver IC still consumes a lot of power in standby mode. In view of this, the present invention adds an ultra-low power VMID voltage generating circuit in the VMID voltage generator. When the driver IC is operating in standby mode, the bandgap reference circuit and operational amplifier are turned off, and the ultra-low power VMID voltage generating circuit is turned on to select the ultra-low power VMID voltage generating circuit to provide the VMID voltage. Since the ultra-low power VMID voltage generating circuit consumes very low power when operating, it can greatly reduce the power consumption of the driver IC in standby mode.

[0010] In order to achieve the above-mentioned purpose, the present invention provides a VMID voltage generator with low standby power consumption, characterized in that the VMID voltage generator is applied to a driver IC to provide a VMID voltage to the driver IC, and the VMID voltage generator includes: a high-power VMID voltage generating circuit, which is composed of high-power electronic components; and an ultra-low-power VMID voltage generating circuit, which is composed of ultra-low-power electronic components, wherein the output of the high-power VMID voltage generating circuit and the output of the ultra-low-power VMID voltage generating circuit are connected to an output node, and the output node generates a VMID voltage; wherein, when the driver IC operates in a normal mode, the high-power VMID voltage generating circuit is turned on, the ultra-low-power VMID voltage generating circuit is turned off, and the VMID voltage is generated by the high-power VMID voltage generating circuit; when the driver IC operates in a standby mode, the high-power VMID voltage generating circuit is turned off, and the ultra-low-power VMID voltage generating circuit is turned on, and the VMID voltage is generated by the ultra-low-power VMID voltage generating circuit.

[0011] Preferably, the ultra-low power consumption VMID voltage generating circuit comprises: a first resistor, one end of which is connected to a voltage source and the other end is connected to an output node; and a second resistor, one end of which is connected to the output node and the other end is grounded; wherein the VMID voltage is generated on the output node through voltage division of the first resistor and the second resistor.

[0012] Preferably, the VMID voltage is set to a predetermined value, and the sizes of the first resistor and the second resistor are adjusted according to the predetermined value of the VMID voltage.

[0013] Preferably, the ultra-low power consumption VMID voltage generating circuit comprises: a first resistor, one end of which is connected to a voltage source and the other end is connected to a first node; a second resistor, one end of which is connected to the first node and the other end is grounded; a first transistor, which is an NMOS transistor, whose drain is connected to the voltage source, the gate is connected to the first node and the source is connected to the output node; and a second transistor, which is a PMOS transistor, whose drain is grounded, the gate is connected to the first node and the source is connected to the output node; wherein a first voltage is generated on the first node, and the VMID voltage is between VA+VTH_P1 and VA-VTH_N1, VA is the first voltage, VTH_N1 is the threshold voltage of the first transistor, and VTH_P1 is the threshold voltage of the second transistor.

[0014] Preferably, the VMID voltage is set to a predetermined value, and the sizes of the first resistor and the second resistor are adjusted according to the predetermined value of the VMID voltage.

[0015] Preferably, the ultra-low power consumption VMID voltage generating circuit comprises: a first resistor, one end of which is connected to a voltage source and the other end of which is connected to a first node; a second resistor, one end of which is connected to a second node and the other end of which is grounded; a third resistor connected between the first node and the second node; a first transistor, which is an NMOS transistor, whose drain is connected to a voltage source, whose gate is connected to the first node and whose source is connected to an output node; and a second transistor, which is a PMOS transistor, whose drain is grounded, whose gate is connected to the second node and whose source is connected to the output node; wherein a first voltage is generated at the first node and a second voltage is generated at the second node; wherein the VMID voltage is set to a predetermined value, and the VMID voltage is embedded near the predetermined value by setting the magnitudes of the first voltage and the second voltage; wherein the first voltage is set to be close to and lower than VMID+VGS_N1, and the second voltage is set to be close to and higher than VMID-VGS_P1, VGS_N1 is the VGS voltage of the first transistor, and VGS_P1 is the VGS voltage of the second transistor.

[0016] Preferably, the predetermined values ​​of the first voltage, the second voltage and the VMID voltage are set by adjusting the values ​​of the first resistor, the second resistor and the third resistor.

[0017] Preferably, the ultra-low power consumption VMID voltage generating circuit comprises: a first resistor, one end of which is connected to a voltage source and the other end of which is connected to a first node; a second resistor, one end of which is connected to a second node and the other end of which is grounded; a first transistor, which is an NMOS transistor, whose drain is connected to a voltage source, whose gate is connected to a first node and whose source is connected to an output node; a second transistor, which is a PMOS transistor, whose drain is grounded, whose gate is connected to a second node and whose source is connected to an output node; a third transistor, which is an NMOS transistor, whose drain and gate are connected to a first node and whose source is connected to a third node; a fourth transistor, which is a PMOS transistor, whose drain and gate are connected to a second node and whose source is connected to a third node; wherein a first voltage is generated at the first node, a second voltage is generated at the second node, and a third voltage is generated at the third node; wherein a VGS voltage of the third transistor is designed to be equal to a VGS voltage of the fourth transistor; wherein a predetermined value is set for the VMID voltage, the predetermined value is set to be equal to the third voltage, and the VMID voltage is embedded near the predetermined value.

[0018] Preferably, the VGS voltage of the third transistor is set to be lower than the VGS voltage of the first transistor, and the VGS voltage of the fourth transistor is set to be lower than the VGS voltage of the second transistor.

[0019] Preferably, the first voltage, the second voltage and the third voltage are set by adjusting the sizes of the first resistor and the second resistor.

[0020] Preferably, the high power consumption VMID voltage generating circuit comprises: a bandgap reference circuit for providing a reference voltage and a reference current; and an operational amplifier, wherein the input end of the operational amplifier is connected to the bandgap reference circuit and the output end is connected to the output node; wherein the operational amplifier generates a VMID voltage at the output node and provides a thrust to drive the VMID voltage based on the reference voltage and the reference current. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the driver's circuit architecture and its voltage range.

[0022] Figure 2 FIG. 4 is a schematic diagram of a conventional VMID voltage generator.

[0023] Figure 3 FIG. 4 is a schematic diagram of the structure of the VMID voltage generator of the present invention.

[0024] Figure 4 FIG. 4 is a circuit operation diagram of the VMID voltage generator of the present invention in a normal mode.

[0025] Figure 5 FIG. 4 is a circuit operation diagram of the VMID voltage generator of the present invention in the standby mode.

[0026] Figure 6 This is an ultra-low power consumption VMID voltage generating circuit according to the first embodiment of the present invention.

[0027] Figure 7 This is an ultra-low power consumption VMID voltage generating circuit according to the first embodiment of the present invention.

[0028] Figure 8 This is an ultra-low power consumption VMID voltage generating circuit according to the first embodiment of the present invention.

[0029] Fig. 9 This is an ultra-low power consumption VMID voltage generating circuit according to the first embodiment of the present invention.

[0030] Description of Reference Numerals

[0031] 100: Driver IC

[0032] 11: Positive voltage operational amplifier

[0033] 12: Negative voltage operational amplifier

[0034] 200: VMID voltage generator

[0035] 21: Bandgap reference circuit

[0036] 22: Operational Amplifier

[0037] 300: VMID voltage generator

[0038] 30: High power consumption VMID voltage generation circuit

[0039] 301: Output node

[0040] 40: Ultra-low power consumption VMID voltage generation circuit

[0041] 401: First Node

[0042] 402: Second Node

[0043] 403: Third Node

[0044] 41: Ultra-low power consumption VMID voltage generation circuit

[0045] 42: Ultra-low power consumption VMID voltage generation circuit

[0046] 43: Ultra-low power consumption VMID voltage generation circuit

[0047] 44: Ultra-low power consumption VMID voltage generation circuit

[0048] R1: First resistor

[0049] R2: Second resistor

[0050] R3: The third resistor

[0051] N1: First transistor

[0052] P1: Second transistor

[0053] N2: The third transistor

[0054] P2: The fourth transistor DETAILED DESCRIPTION

[0055] In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the present application is further described in detail below in conjunction with drawings and specific implementation methods.

[0056] See also Figure 3 FIG. 1 is a schematic diagram of the structure of the VMID voltage generator of the present invention. Figure 3As shown, the VMID voltage generator 300 of the present invention is applied in a driver IC, which is a source driver IC or a driver IC that requires a VMID voltage as an operating voltage. The VMID voltage generator 300 includes a high-power VMID voltage generating circuit 30 and an ultra-low-power VMID voltage generating circuit 40. The output of the high-power VMID voltage generating circuit 30 and the output of the ultra-low-power VMID voltage generating circuit 40 are connected to an output node 301, and a VMID voltage is generated on the output node 301. AVDD is a voltage source, and the VMID voltage can also be called a median voltage.

[0057] like Figure 4 As shown, when the driver IC operates in normal mode, the driver IC turns on the high-power VMID voltage generating circuit 30 and turns off the ultra-low-power VMID voltage generating circuit 40, and the VMID voltage is generated by the high-power VMID voltage generating circuit 30. Specifically, the high-power VMID voltage generating circuit 30 of the present invention still uses the traditional bandgap reference circuit 21 and operational amplifier 22 for circuit design. The input end of the operational amplifier 22 is connected to the bandgap reference circuit 21, and the output end is connected to the output node 301. When the high-power VMID voltage generating circuit 30 is turned on, the bandgap reference circuit 21 provides a reference voltage and a reference current to the operational amplifier 22, and the operational amplifier 22 generates a VMID voltage on the output node 301 and provides a thrust to drive the VMID voltage according to the reference voltage and the reference current. When the bandgap reference circuit 21 and the operational amplifier 22 are turned on and operated in a normal mode, the bandgap reference circuit 21 consumes about 50uA, and the operational amplifier 22 consumes about 450uA. The total power consumption of the high-power VMID voltage generating circuit 30 is 500uA.

[0058] In addition, such as Figure 5 As shown, when the driver IC enters the standby mode, the driver IC turns off the high-power VMID voltage generating circuit 30 and turns on the ultra-low-power VMID voltage generating circuit 40. The VMID voltage is generated by the ultra-low-power VMID voltage generating circuit 40. Therefore, when the driver IC is in the standby mode, the ultra-low-power VMID voltage generating circuit 40 is selected to provide the VMID voltage, which can not only solve the problem of the withstand voltage of the electronic components, but also enable the driver IC in the standby mode to further effectively reduce the power consumption. Preferably, through appropriate circuit design, the total power consumption of the ultra-low-power VMID voltage generating circuit 40 is limited to a predetermined value, such as within 10uA. As for the circuit structure of the ultra-low-power VMID voltage generating circuit 40, it will be explained in detail later.

[0059] Furthermore, in actual circuit design, the driver IC can decide to turn on or off the high-power VMID voltage generating circuit 30 and the ultra-low-power VMID voltage generating circuit 40 by controlling a selector connected between AVDD, the high-power VMID voltage generating circuit 30, and the ultra-low-power VMID voltage generating circuit 40. For example, when the driver IC operates in a normal mode, the control selector is turned on by connecting the line between AVDD and the VMID voltage generating circuit 30 and disconnecting the line between AVDD and the ultra-low-power VMID voltage generating circuit 40, thereby turning on the high-power VMID voltage generating circuit 30 and turning off the ultra-low-power VMID voltage generating circuit 40; or, when the driver IC operates in a standby mode, the control selector is turned off by disconnecting the line between AVDD and the VMID voltage generating circuit 30 and connecting the line between AVDD and the ultra-low-power VMID voltage generating circuit 40, thereby turning off the high-power VMID voltage generating circuit 30 and turning on the ultra-low-power VMID voltage generating circuit 40.

[0060] See also Figure 6 This is an ultra-low power consumption VMID voltage generating circuit according to the first embodiment of the present invention. Figure 6 As shown, the ultra-low power consumption VMID voltage generating circuit 41 of the first embodiment includes a first resistor R1 and a second resistor R2. One end of the first resistor R1 is connected to AVDD and the other end is connected to the output node 301. One end of the second resistor R2 is connected to the output node 301 and the other end is grounded. The VMID voltage is generated on the output node 301.

[0061] In this embodiment, the VMID voltage is obtained by voltage division using resistors R1 and R2, VMID=AVDD*R2 / (R1+R2), and the power consumption is AVDD / (R1+R2).

[0062] In the present invention, the VMID voltage is set to a predetermined value, and the sizes of the resistors R1 and R2 can be adjusted according to the predetermined value of the VMID voltage. If the predetermined value of the VMID voltage is set to AVDD / 2, R1=R2=R X , the VMID voltage will be AVDD / 2, and the power consumption will be AVDD / 2R X . Taking a specific example as an explanation, AVDD = 10V, R1 and R2 are both designed to be 5MΩ, then VMID = 10V / 2 = 5V, and the power consumption is 10V / (5MΩ+5MΩ) = 10uA. In this way, the VMID voltage can be easily obtained through simple resistor voltage division, and through the appropriate design of the resistance size of R1 and R2, ultra-low power consumption (such as 10uA) can be achieved, so the power consumption of the driver IC standby can be greatly reduced.

[0063] In the present invention, setting the first resistor R1 equal to the second resistor R2 is only a specific embodiment. In actual application, the first resistor R1 may not be equal to the second resistor R2.

[0064] Furthermore, in each embodiment of the present invention, the VMID voltage is preset to AVDD / 2, which is only an example listed for the convenience of explanation. In actual circuit application, the preset value of the VMID voltage may also be changed accordingly according to the requirements of the driver IC.

[0065] See also Figure 7 This is an ultra-low power consumption VMID voltage generating circuit according to the second embodiment of the present invention. Figure 7 As shown, compared with the ultra-low power VMID voltage generating circuit 41 of the first embodiment, the ultra-low power VMID voltage generating circuit 42 of the second embodiment further includes a first transistor N1 and a second transistor P1. The first transistor N1 is an NMOS transistor, and the second transistor P1 is a PMOS transistor.

[0066] One end of the first resistor R1 is connected to AVDD and the other end is connected to the first node 401. One end of the second resistor R2 is connected to the first node 401 and the other end is grounded. The drain of the first transistor N1 is connected to AVDD, the gate is connected to the first node 401 and the source is connected to the output node 301. The drain of the second transistor P1 is grounded, the gate is connected to the first node 401 and the source is connected to the output node 301. A first voltage VA is generated on the first node 401, and a VMID voltage is generated on the output node 301. The first voltage VA = AVDD*R2 / (R1+R2). If R1 = R2 = R X , the first voltage VA will be AVDD / 2, and the power consumption will be AVDD / 2R X .

[0067] During the operation of the ultra-low power consumption VMID voltage generation circuit 42, when the VMID voltage is pulled down below the first voltage VA minus the threshold voltage VTH of the first transistor N1, i.e., VMID < VA - VTH_N1, the first transistor N1 will conduct. The conducting first transistor N1 will pull up the VMID voltage, and after pulling up the VMID voltage by a predetermined voltage value (such as the threshold voltage VTH_N1), the first transistor N1 will be turned off, and the VMID voltage will be in a steady state. Conversely, when the VMID voltage is pulled up above the first voltage VA plus the threshold voltage VTH of the second transistor P1 (i.e., VMID > VA + VTH_P1), the second transistor P1 will conduct. The conducting second transistor P1 will pull down the VMID voltage, and after pulling down the VMID voltage by a predetermined voltage value (such as the threshold voltage VTH_P1), the second transistor P1 will be turned off, and the VMID voltage will be in a steady state. In the steady state, the VMID voltage will be between VA + VTH_P1 and VA - VTH_N1. Similarly, if it is designed that R1 = R2 = R X , the VMID voltage will be between AVDD / 2 + VTH_P1 and AVDD / 2 - VTH_N1.

[0068] Therefore, compared with the ultra-low power consumption VMID voltage generation circuit 41 of the first embodiment, the ultra-low power consumption VMID voltage generation circuit 42 of the second embodiment can increase the driving ability of the VMID voltage and still maintain an ultra-low power consumption state during standby by adding two MOS transistors. For example, if it is designed that R1 = R2 = R X , the power consumption will still be maintained at AVDD / 2R X .

[0069] Please refer to Figure 8 the ultra-low power consumption VMID voltage generation circuit of the third embodiment of the present invention. As Figure 8 shown, compared with the ultra-low power consumption VMID voltage generation circuit 42 of the second embodiment, the ultra-low power consumption VMID voltage generation circuit 43 of the third embodiment further includes a third resistor R3. The third resistor R3 is used to separate the gate of the first transistor N1 and the gate of the second transistor P1 that were originally connected together.

[0070] One end of the first resistor R1 is connected to AVDD and the other end is connected to the first node 401. One end of the second resistor R2 is connected to the second node 402 and the other end is grounded. The third resistor R3 is connected between the first node 401 and the second node 402. The drain of the first transistor N1 is connected to AVDD, the gate is connected to the first node 401, and the source is connected to the output node 301. The drain of the second transistor P1 is grounded, the gate is connected to the second node 402, and the source is connected to the output node 301. A first voltage VA is generated at the first node 401, a second voltage VB is generated at the second node 402, and a VMID voltage is generated at the output node 301.

[0071] In this embodiment, by adjusting the sizes of the first resistor R1, the second resistor R2, and the third resistor R3, the first voltage VA is set close to and lower than VMID+VGS_N1, and the second voltage VB is set close to and higher than VMID-VGS_P1. VGS_N1 is the VGS voltage of the first transistor N1, and VGS_P1 is the VGS voltage of the second transistor P1. Through the setting of the first voltage VA and the second voltage VB, during the operation of the ultra-low power consumption VMID voltage generating circuit 43, the first transistor N1 and the second transistor P1 will not be turned on at the same time.

[0072] Furthermore, since the first voltage VA is set close to and lower than VMID+VGS_N1, when the VMID voltage is slightly pulled down, the first transistor N1 will be slightly turned on, and the slightly turned on first transistor N1 will pull the slightly pulled down VMID back to the original predetermined value (such as AVDD / 2), and after VMID is pulled back to the original predetermined value, the first transistor N1 is turned off; or, since the second voltage VB is set close to and higher than VMID-VGS_P1, when the VMID voltage is slightly pulled up, the second transistor P1 will be slightly turned on, and the slightly turned on second transistor P1 will pull VMID back to the original predetermined value (such as AVDD / 2), and after VMID is pulled back to the original predetermined value, the second transistor P1 is turned off.

[0073] Compared to the second embodiment, the VMID voltage is floating and is between a larger voltage range, such as between AVDD / 2+VTH and AVDD / 2-VTH. In the third embodiment, the VMID voltage will be clamped around a predetermined value (such as AVDD / 2). Thus, clamping the VMID voltage around a predetermined value can increase the stability of the power supply.

[0074] In a specific example, the total resistance R of the first resistor R1, the second resistor R2 and the third resistor R3 is T Can also be set equal to 2R X , such as R T =2R X, the total power consumption of the low power VMID voltage generating circuit 43 can still maintain AVDD / 2R X .

[0075] See also Fig. 9 This is an ultra-low power consumption VMID voltage generating circuit according to the fourth embodiment of the present invention. Fig. 9 As shown, compared with the ultra-low power consumption VMID voltage generating circuit 43 of the third embodiment, the ultra-low power consumption VMID voltage generating circuit 44 of the fourth embodiment uses two diode-connected transistors N2 and P2 to replace the third resistor R3.

[0076] One end of the first resistor R1 is connected to AVDD and the other end is connected to the first node 401. One end of the second resistor R2 is connected to the second node 402 and the other end is grounded. The drain of the first transistor N1 is connected to AVDD, the gate is connected to the first node 401, and the source is connected to the output node 301. The drain of the second transistor P1 is grounded, the gate is connected to the second node 402, and the source is connected to the output node 301. The drain and gate of the third transistor N2 are connected to the first node 401 and the source is connected to the third node 403. The drain and gate of the fourth transistor P2 are connected to the second node 402 and the source is connected to the third node 403. A first voltage VA is generated at the first node 401, a second voltage VB is generated at the second node 402, a third voltage VC is generated at the third node 403, and a VMID voltage is generated at the output node 301.

[0077] Preferably, the VGS of the third transistor N2 is designed to be equal to the VGS of the fourth transistor P2, and the predetermined value of the VMID voltage will be set equal to the third voltage VC. If R1=R2, and the VGS of the third transistor N2 is designed to be the same as the VGS of the fourth transistor P2, so that the third voltage VC is equal to AVDD / 2, then when the ultra-low power consumption VMID voltage generating circuit 44 operates, the VMID voltage will be close to AVDD / 2. In addition, in the specific example, the total resistance R of the first resistor R1 and the second resistor R2 is T Can also be set equal to 2R X , such as R T =2R X , the total power consumption of the ultra-low power VMID voltage generating circuit 44 is (AVDD-2VGS) / 2R X .

[0078] Preferably, the VGS of the third transistor N2 is set smaller than the VGS of the first transistor N1, and the VGS of the fourth transistor P2 is set smaller than the VGS of the second transistor P1, so that during the operation of the ultra-low power consumption VMID voltage generating circuit 43, the first transistor N1 and the second transistor P1 are not turned on at the same time.

[0079] When the VTH of NMOS (such as the threshold voltage VTH of the first transistor N1 and the third transistor N2) increases or decreases due to process drift, since VMID=VC+VGS_N2-VGS_N1, the VMID voltage will still be equal to the third voltage VC and will not be affected by the process drift of the VTH of NMOS. Similarly, when the VTH of PMOS (such as the threshold voltage VTH of the second transistor P1 and the fourth transistor P2) increases or decreases due to process drift, since VMID=VC-VGS_P2+VGS_P1, the VMID voltage will still be equal to the third voltage VC and will not be affected by the process drift of the VTH of PMOS.

[0080] Therefore, by adding the third transistor N2 and the fourth transistor P2, the ultra-low power consumption VMID voltage generating circuit 44 has a better ability to resist process drift, so as to provide a more accurate and predetermined VMID voltage.

[0081] The above is only a preferred specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can make equivalent substitutions or changes within the technical scope disclosed in the present application according to the technical solution and application concept of the present application, which should be covered by the protection scope of the present application.

Claims

1. A VMID voltage generator with low standby power consumption, characterized in that: The VMID voltage generator is applied to a driver IC to provide a VMID voltage to the driver IC. The VMID voltage generator includes: Ultra-low power VMID voltage generation circuit, including: a first resistor, one end of which is connected to the voltage source and the other end of which is connected to the first node; a second resistor having one end connected to the second node and the other end connected to the ground; A first transistor is an NMOS transistor, a drain of which is connected to the voltage source, a gate of which is connected to the first node, and a source of which is connected to the output node; The second transistor is a PMOS transistor, with a drain connected to the ground, a gate connected to the second node, and a source connected to the output node; A third transistor is an NMOS transistor, a drain and a gate of which are connected to the first node and a source of which is connected to a third node; and a fourth transistor, which is a PMOS transistor, a drain and a gate of which are connected to the second node and a source of which is connected to the third node; A first voltage is generated on the first node, a second voltage is generated on the second node, and a third voltage is generated on the third node; The VGS voltage of the third transistor is designed to be equal to the VGS voltage of the fourth transistor; The VMID voltage is set to a predetermined value, which is set equal to the third voltage, and the VMID voltage will be embedded to near the predetermined value.

2. The VMID voltage generator with low standby power consumption as claimed in claim 1, characterized in that: The VGS voltage of the third transistor is set to be lower than the VGS voltage of the first transistor, and the VGS voltage of the fourth transistor is set to be lower than the VGS voltage of the second transistor.

3. The VMID voltage generator with low standby power consumption as claimed in claim 2, wherein: The first voltage, the second voltage and the third voltage are set by adjusting the magnitudes of the first resistor and the second resistor.

4. The VMID voltage generator with low standby power consumption as claimed in claim 1, wherein: It also includes a high-power VMID voltage generating circuit composed of high-power electronic components, and the output of the high-power VMID voltage generating circuit is connected to the output node; wherein, when the driver IC operates in normal mode, the high-power VMID voltage generating circuit is turned on, the ultra-low-power VMID voltage generating circuit is turned off, and the VMID voltage is generated by the high-power VMID voltage generating circuit; when the driver IC operates in standby mode, the high-power VMID voltage generating circuit is turned off, and the ultra-low-power VMID voltage generating circuit is turned on, and the VMID voltage is generated by the ultra-low-power VMID voltage generating circuit.

5. The VMID voltage generator with low standby power consumption as claimed in claim 4, characterized in that: The high power consumption VMID voltage generating circuit comprises: A bandgap reference circuit for providing a reference voltage and a reference current; and an operational amplifier, wherein an input terminal of the operational amplifier is connected to the bandgap reference circuit and an output terminal of the operational amplifier is connected to the output node; The operational amplifier generates the VMID voltage at the output node, and provides a thrust to drive the VMID voltage according to the reference voltage and the reference current.

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