Three-phase four-level neutral-point clamped inverter and neutral-point voltage balance control method

Abstract

The invention discloses a three-phase four-level neutral-point-clamped inverter and a neutral-point voltage balance control method.The three-phase four-level neutral-point-clamped inverter comprises a direct-current power source, three direct-current bus capacitors connected in series and twelve switch tubes, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube and the sixth switch tube form a chopping unit, and the chopping unit is connected with the direct-current power source. The seventh switch tube to the twelfth switch tube form a three-phase bridge arm circuit, the three direct-current bus capacitors connected in series are connected with the chopping unit, the chopping unit is further connected with the input end of the three-phase bridge arm circuit, and the midpoint of each bridge arm of the three-phase bridge arm circuit is connected with a three-phase alternating-current end. The three-phase four-level neutral point clamped inverter has the advantages of low cost, simple control and high reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of midpoint clamped inverters, and in particular to a three-phase four-level midpoint clamped inverter and a midpoint voltage balance control method. Background Art

[0002] Neutral Point Clamped (NPC) inverter is a multi-level inverter topology widely used in medium voltage systems such as renewable energy power generation, electric vehicles, rail transit, and motor drives. Compared with three-level NPC inverters, four-level inverters have lower total harmonic distortion and better electromagnetic compatibility performance; compared with five-level NPC inverters, four-level inverters have fewer electrolytic capacitors and power devices, and have greater advantages in cost, loss, and size. Therefore, four-level inverters are competitive in industrial applications.

[0003] In the existing four-level neutral-point clamped inverter topology, at least 18 power switches are used in three phases, resulting in high cost, complex control and reduced reliability. In recent years, multi-level topologies with reduced number of switching devices have the characteristics of lower cost and higher reliability, becoming a new development trend.

[0004] Neutral voltage imbalance has always been a common problem of four-level neutral-point clamped inverter topology. The neutral voltage balance control strategy can ensure uniform stress distribution of power devices, reduce the harmonic content in the output voltage, improve the quality of voltage waveform, thereby reducing interference to the power grid or load, improving the power quality of the system, and meeting the higher requirements of modern power systems and industrial applications for power quality. Therefore, it is necessary to provide a low-cost, high-reliability four-level neutral-point clamped inverter and its neutral voltage balance control strategy. Summary of the invention

[0005] The present invention aims to solve the technical problems in the related art at least to a certain extent. To this end, the first object of the present invention is to provide a three-phase four-level neutral point clamped inverter, which has the advantages of low cost, simple control and high reliability.

[0006] A second object of the present invention is to provide a midpoint voltage balance control method.

[0007] A third object of the present invention is to provide a computer-readable storage medium.

[0008] A fourth object of the present invention is to provide an electronic device.

[0009] To achieve the above object, the present invention is implemented through the following technical solutions:

[0010] A three-phase four-level midpoint clamped inverter comprises: a DC power supply, three DC bus capacitors connected in series and twelve switch tubes, wherein the first to sixth switch tubes constitute a chopper unit, the seventh to twelfth switch tubes constitute a three-phase bridge arm circuit, the three DC bus capacitors connected in series are connected to the chopper unit, the chopper unit is also connected to the input end of the three-phase bridge arm circuit, and the midpoints of the bridge arms of the three-phase bridge arm circuit are respectively connected to the three-phase AC ends.

[0011] Preferably, the twelve switch tubes are all MOS tubes.

[0012] Preferably, the source of the first switch tube and the drain of the second switch tube are connected and have a first node, the source of the second switch tube and the drain of the fifth switch tube are connected and have a second node, the source of the fifth switch tube and the drain of the sixth switch tube are connected and have a third node; the source of the third switch tube and the drain of the fourth switch tube are both connected to the second node, the drain of the first switch tube is connected to the positive end of the first DC bus capacitor and the positive end of the DC power supply, the source of the sixth switch tube is connected to the negative end of the third DC bus capacitor and the negative end of the DC power supply, and the drain of the third switch tube and the source of the fourth switch tube are respectively connected to the positive and negative ends of the second DC bus capacitor.

[0013] Preferably, in the three-phase bridge arm circuit, the source of the upper half bridge arm switch tube of each phase is connected to the drain of the corresponding lower half bridge arm switch tube, the drain of the upper half bridge arm switch tube of each phase is connected to the first node, and the source of the lower half bridge arm switch tube of each phase is connected to the third node.

[0014] To achieve the above object, the second aspect of the present invention provides a midpoint voltage balance control method, which is applied to the above three-phase four-level midpoint clamped inverter, and the method comprises:

[0015] Acquire multiple switch combinations of a three-phase four-level neutral point clamped inverter, and divide the multiple switch combinations into four vectors;

[0016] Based on multiple switch combinations in four vectors, the space vector distribution of the three-phase four-level neutral point clamped inverter is obtained;

[0017] Based on the space vector distribution, the second DC bus capacitor voltage balance control and the first DC bus capacitor voltage and the third DC bus capacitor voltage dynamic balance control are implemented to achieve midpoint voltage balance control.

[0018] Preferably, the space vector distribution includes six sectors.

[0019] Preferably, realizing the second DC bus capacitor voltage balance control based on the space vector distribution includes:

[0020] For each sector, determining at least one switch combination in which the second DC bus capacitor is in a charging state, and determining at least one switch combination in which the second DC bus capacitor is in a discharging state;

[0021] The action time of the first vector of the corresponding sector is obtained by adjusting the action time of at least one switch combination when the first adjustment factor and the second DC bus capacitor are in a charging state, and the action time of the second vector of the corresponding sector is obtained by adjusting the action time of at least one switch combination when the first adjustment factor and the second DC bus capacitor are in a discharging state, so that the three-phase four-level neutral point clamped inverter is acted on based on the adjusted action time of the first vector and the action time of the second vector to achieve voltage balance control of the second DC bus capacitor.

[0022] Preferably, dynamically balancing the first DC bus capacitor voltage and the third DC bus capacitor voltage includes:

[0023] For each sector, determining at least one switch combination in which the first DC bus capacitor or the third DC bus capacitor is in a charging state, and determining at least one switch combination in which the first DC bus capacitor or the third DC bus capacitor is in a discharging state;

[0024] The action time of the corresponding sector charging vector is obtained by adjusting the second adjustment factor and the action time of at least one switch combination when the first DC bus capacitor is in a charging state, or the action time of at least one switch combination when the third DC bus capacitor is in a discharging state; and

[0025] The action time of the corresponding sector discharge vector is obtained by adjusting the second adjustment factor and the action time of at least one switch combination when the first DC bus capacitor is in a discharging state, or the action time of at least one switch combination when the third DC bus capacitor is in a charging state;

[0026] The three-phase four-level neutral point clamped inverter is acted on based on the adjusted action time of the charging vector and the action time of the discharging vector to achieve dynamic balance control of the first DC bus capacitor voltage and the third DC bus capacitor voltage.

[0027] To achieve the above object, the third aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the above-mentioned midpoint voltage balance control method is implemented.

[0028] To achieve the above objectives, the fourth aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the above-mentioned midpoint voltage balance control method is implemented.

[0029] The present invention has at least the following technical effects:

[0030] The present invention provides a three-phase four-level midpoint clamped inverter, comprising a DC power supply, three DC bus capacitors connected in series and twelve switch tubes, wherein the first to sixth switch tubes constitute a chopper unit, the seventh to twelfth switch tubes constitute a three-phase bridge arm circuit, the three DC bus capacitors connected in series are connected to the chopper unit, the chopper unit is connected to the input end of the three-phase bridge arm circuit, and the midpoints of each bridge arm of the three-phase bridge arm circuit are respectively connected to the three-phase AC end. The three-phase four-level midpoint clamped inverter has fewer switch devices and has the advantages of low cost, simple control and high reliability. In addition, the present invention also provides a midpoint voltage balance control method, which adopts a simplified space vector distributed modulation technology to realize voltage balance control of each DC bus capacitor, and further realizes midpoint voltage balance of the three-phase four-level midpoint clamped inverter.

[0031] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The figure is a schematic structural diagram of a three-phase four-level neutral-point clamped inverter according to an embodiment of the present invention.

[0033] Figure 2 Flow chart of a midpoint voltage balancing control method according to an embodiment of the present invention.

[0034] FIG. 3 is an equivalent circuit diagram of six switch combinations according to an embodiment of the present invention.

[0035] Figure 4 4 is a space vector distribution diagram of a three-phase four-level neutral point clamped inverter according to an embodiment of the present invention.

[0036] Figure 5 4 is a schematic diagram of a capacitor voltage balance control principle according to an embodiment of the present invention.

[0037] FIG. 6( a ) is a simulation diagram of a DC bus capacitor voltage according to an embodiment of the present invention.

[0038] FIG6( b ) is a simulation diagram of phase voltage and phase current according to an embodiment of the present invention.

[0039] FIG6( c ) is a simulation diagram of the phase current FFT according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The present embodiment is described in detail below, and examples of the embodiment are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0041] The three-phase four-level neutral point clamped inverter and the neutral point voltage balance control method of this embodiment are described below with reference to the accompanying drawings.

[0042] Figure 1 FIG. 1 is a schematic diagram of the structure of a three-phase four-level neutral point clamped inverter according to an embodiment of the present invention. Figure 1 As shown, the three-phase four-level midpoint clamped inverter includes a DC power supply, three DC bus capacitors C1-C3 connected in series, and twelve switch tubes S1-S 12 Among them, the twelve switch tubes are all MOS (metal oxide semiconductor field effect transistor) tubes, and of course they can also be IGBT (insulated gate bipolar transistor) or SiC (silicon carbide) devices. The first switch tube S1 to the sixth switch tube S6 constitute a chopper unit, and the seventh switch tube S7 to the twelfth switch tube S 12 A three-phase bridge arm circuit is formed, three series-connected DC bus capacitors are connected to the chopper unit, the chopper unit is also connected to the input end of the three-phase bridge arm circuit, and the midpoints of each bridge arm of the three-phase bridge arm circuit are respectively connected to the three-phase AC ends of phase A, phase B and phase C.

[0043] Specifically, the source of the first switch tube S1 and the drain of the second switch tube S2 are connected and have a first node, the source of the second switch tube S2 and the drain of the fifth switch tube S5 are connected and have a second node, the source of the fifth switch tube S5 and the drain of the sixth switch tube S6 are connected and have a third node; the source of the third switch tube S3 and the drain of the fourth switch tube S4 are both connected to the second node, the drain of the first switch tube S1 is connected to the positive end of the first DC bus capacitor C1 and the positive end of the DC power supply, the source of the sixth switch tube S6 is connected to the negative end of the third DC bus capacitor C3 and the negative end of the DC power supply, and the drain of the third switch tube S3 and the source of the fourth switch tube S4 are respectively connected to the positive and negative ends of the second DC bus capacitor C2.

[0044] In the three-phase bridge arm circuit, the source of each phase upper half bridge arm switch tube is connected to the drain of the corresponding lower half bridge arm switch tube. 11 The drains of the lower half bridge arm switches of each phase are connected to the first node, such as S8, S 10 , S 12 The sources of are connected to the third node.

[0045] In this embodiment, the three-phase bridge arm circuits share a chopper unit, and different switch combinations can generate 0, Udc / 3, 2U dc / 3 and U dc Four levels, U dc The three-phase four-level midpoint clamped inverter proposed in this embodiment has only 12 power switch tubes and can output four levels, with fewer switch devices, and has the advantages of low cost, simple control and high reliability.

[0046] Figure 2 FIG. 1 is a flow chart of a midpoint voltage balance control method according to an embodiment of the present invention. Figure 2 As shown, the method includes:

[0047] S101: Acquire multiple switch combinations of a three-phase four-level neutral-point clamped inverter, and divide the multiple switch combinations into four vectors.

[0048] S102: Obtaining a space vector distribution of a three-phase four-level neutral point clamped inverter based on a plurality of switch combinations in four vectors.

[0049] S103: Implementing balanced control of the second DC bus capacitor voltage and dynamic balanced control of the first DC bus capacitor voltage and the third DC bus capacitor voltage based on the space vector distribution, so as to implement balanced control of the midpoint voltage.

[0050] In this embodiment, all switch states of the three-phase four-level neutral point clamped inverter topology are shown in Table 1, wherein the switch combination indicates that the corresponding switch is turned on, and four vectors, namely, vector 0 to vector 4, are divided according to multiple switch combinations.

[0051] Table 1 Switching state table of three-phase four-level neutral point clamped inverter topology

[0052]

[0053]

[0054] Figure 3 is an equivalent circuit diagram of six switch combinations, which are described in detail as follows:

[0055] As shown in FIG. 3( a ), the second switch tube S2 , the fourth switch tube S4 , the fifth switch tube S5 , the seventh switch tube S7 , and the tenth switch tube S 10 and the twelfth switch tube S 12 The first DC bus capacitor C1, the second DC bus capacitor C2 and the third DC bus capacitor C3 are not affected.

[0056] As shown in FIG. 3( b ), the second switch tube S2, the fourth switch tube S4, the sixth switch tube S6, the seventh switch tube S7, the tenth switch tube S 10and the twelfth switch tube S 12 The first DC bus capacitor C1 and the second DC bus capacitor C2 are charged, and the third DC bus capacitor C3 is discharged when the midpoint current flows out; when the midpoint current flows in, the first DC bus capacitor C1 and the second DC bus capacitor C2 are discharged, and the third DC bus capacitor C3 is charged.

[0057] As shown in FIG. 3( c ), the first switch tube S1 , the third switch tube S3 , the fifth switch tube S5 , the seventh switch tube S7 , the tenth switch tube S 10 and the twelfth switch tube S 12 The first DC bus capacitor C1 is turned on to obtain a vector switch state 322. When the midpoint current flows out, the second DC bus capacitor C2 and the third DC bus capacitor C3 are charged, and the first DC bus capacitor C1 is discharged; when the midpoint current flows in, the second DC bus capacitor C2 and the third DC bus capacitor C3 are discharged, and the first DC bus capacitor C1 is charged.

[0058] As shown in FIG. 3( d ), the second switch tube S2 , the third switch tube S3 , the sixth switch tube S6 , the seventh switch tube S7 , and the tenth switch tube S 10 and the twelfth switch tube S 12 The second DC bus capacitor C2 and the third DC bus capacitor C3 are turned on to obtain the 2-vector switch state 200. When the midpoint current flows out, the second DC bus capacitor C2 and the third DC bus capacitor C3 are discharged, and the first DC bus capacitor C1 is charged; when the midpoint current flows in, the second DC bus capacitor C2 and the third DC bus capacitor C3 are charged, and the first DC bus capacitor C1 is discharged.

[0059] As shown in FIG. 3( e ), the first switch tube S1 , the fourth switch tube S4 , the fifth switch tube S5 , the seventh switch tube S7 , and the tenth switch tube S 10 and the twelfth switch tube S 12 The first DC bus capacitor C1 and the second DC bus capacitor C2 are turned on to obtain the 2-vector switch state 311. When the midpoint current flows out, the first DC bus capacitor C1 and the second DC bus capacitor C2 are discharged, and the third DC bus capacitor C3 is charged; when the midpoint current flows in, the first DC bus capacitor C1 and the second DC bus capacitor C2 are charged, and the third DC bus capacitor C3 is discharged.

[0060] As shown in FIG. 3( f ), the first switch tube S1, the sixth switch tube S6, the seventh switch tube S7, the tenth switch tube S 10 and the twelfth switch tube S 12 The three-vector switch state 300 is obtained. No matter the midpoint current flows in or out, the first DC bus capacitor C1, the second DC bus capacitor C2 and the third DC bus capacitor C3 are not affected.

[0061] Figure 4The space vector distribution of the three-phase four-level neutral point clamped inverter is shown in Figure 1. The space vector distribution includes six sectors. Figure 3(a)-3(f) From the analysis, it can be seen that the first DC bus capacitor C1 to the third DC bus capacitor C3 are charged and discharged only under the 1 vector and the 2 vector, and the 0 vector and the 3 vector have no effect on the neutral point current.

[0062] Based on this, the second DC bus capacitor voltage balance control is implemented based on the space vector distribution, including: for each sector, determining at least one switch combination in which the second DC bus capacitor C2 is in a charging state, and determining at least one switch combination in which the second DC bus capacitor C2 is in a discharging state; adjusting the action time of the first vector of the corresponding sector, i.e., vector 1, through the first adjustment factor k and the action time of at least one switch combination in which the second DC bus capacitor C2 is in a charging state, and adjusting the action time of the second vector of the corresponding sector, i.e., vector 2, through the first adjustment factor k and the action time of at least one switch combination in which the second DC bus capacitor C2 is in a discharging state, so as to act on the three-phase four-level neutral point clamped inverter based on the adjusted action time of the first vector and the action time of the second vector, so as to implement the second DC bus capacitor voltage balance control.

[0063] Taking sector I as an example, the second DC bus capacitor C2 is charged in the switching states 100, 110, 322 and 332, and discharged in the switching states 200, 220, 311 and 331. To this end, the first adjustment factor k is introduced to redistribute the action time of the 1 vector and the 2 vector, thereby adjusting the charging and discharging time of the second DC bus capacitor C2. The action time of the 1 vector and the 2 vector after allocation is shown in formula (1):

[0064]

[0065] Among them, T 1矢量 , T 2矢量 Respectively represent the action time of vector 1 and vector 2, T 100 , T 110 , T 322 , T 332 , T 200 , T 220 , T 311 , T 331 They respectively represent the action time of the switch states 100, 110, 322, 332, 200, 220, 311 and 331. The voltage balance control of the second DC bus capacitor can be achieved by applying the adjusted action time of vector 1 and vector 2 to the three-phase four-level neutral point clamped inverter.

[0066] For sector II, the second DC bus capacitor C2 is charged in switching states 110, 010, 332 and 232, and discharged in switching states 220, 020, 331 and 131. To this end, the first adjustment factor k can be introduced to redistribute the action time of the 1 vector and the 2 vector of sector II, thereby adjusting the charging and discharging time of the second DC bus capacitor C2.

[0067] In one embodiment of the present invention, dynamically balancing the first DC bus capacitor voltage and the third DC bus capacitor voltage includes:

[0068] For each sector, at least one switch combination in which the first DC bus capacitor C1 or the third DC bus capacitor C3 is in a charging state is determined, and at least one switch combination in which the first DC bus capacitor C1 or the third DC bus capacitor C3 is in a discharging state is determined; the action time of the charging vector of the corresponding sector is adjusted by the second adjustment factor s and the action time of at least one switch combination in which the first DC bus capacitor C1 is in a charging state, or the action time of at least one switch combination in which the third DC bus capacitor C3 is in a discharging state; and the action time of the discharge vector of the corresponding sector is adjusted by the second adjustment factor s and the action time of at least one switch combination in which the first DC bus capacitor C1 is in a discharging state, or the action time of at least one switch combination in which the third DC bus capacitor C3 is in a charging state; the three-phase four-level neutral point clamped inverter is acted on based on the adjusted action time of the charging vector and the action time of the discharge vector to achieve dynamic balance control of the voltage of the first DC bus capacitor and the voltage of the third DC bus capacitor.

[0069] Under ideal conditions, the charging and discharging currents of the first DC bus capacitor C1 and the third DC bus capacitor C3 are the same and can maintain balance. However, in actual conditions, factors such as capacitance value, internal resistance of electrolytic capacitors, and capacitor voltage oscillation frequency need to be considered, and appropriate control is still required. It should be noted that the three DC bus capacitors are all electrolytic capacitors.

[0070] Taking sector I as an example, the first DC bus capacitor C1 is charged in switch states 100, 110, 200 and 220, and discharged in switch states 322, 332, 311 and 331; the third DC bus capacitor C3 is discharged in switch states 100, 110, 200 and 220, and charged in switch states 322, 332, 311 and 331. In order to keep the upper and lower capacitors, i.e., the capacitor voltages of C1 and C3, a second adjustment factor s is introduced to allocate the action time of these switch redundant states, i.e., the charging vector and the discharging vector. The action time of the allocated charging vector and the discharging vector is shown in formula (2):

[0071]

[0072] Among them, T1 and T2 are the action time of the charging vector and the discharge vector respectively. Applying the adjusted action time of the charging vector and the action time of the discharge vector to the three-phase four-level midpoint clamped inverter can realize dynamic balance control of the first DC bus capacitor voltage and the third DC bus capacitor voltage, realize three-capacitor balance control, and realize midpoint voltage balance control of the three-phase four-level midpoint clamped inverter.

[0073] Figure 5 The capacitor voltage balance control principle is given. The voltage U between the first DC bus capacitor C1 and the third DC bus capacitor C3 is C1 and U C3 The deviation is used as the input of the PI (proportional integral) controller to control the second adjustment factor s in real time to maintain the dynamic balance of the upper and lower capacitor voltages. C2 and U dc The deviation of / 3 is used as the input of the PI controller to maintain the first adjustment factor k near 1 / 2, thereby achieving balanced control of the second DC bus capacitor C2.

[0074] In order to demonstrate the feasibility of the three-phase four-level neutral point clamped inverter topology, a simulation model was built according to the simulation parameters in Table 2. The simulation results are shown in Figure 6(a)-6(c) shown.

[0075] Table 2 Simulation model parameters

[0076]

[0077] In the simulation, the initial voltage of the three DC bus capacitors is 400V. As can be seen from Figure 6(a), when the traditional carrier stacking modulation technology is used, the first DC bus capacitor C1 and the third DC bus capacitor C3 are continuously charged, and the second DC bus capacitor C2 is continuously discharged, and the three DC bus capacitors cannot achieve self-balancing. When the capacitor voltage balance control algorithm is added at t=1s, the voltage of the three DC bus capacitors reaches U dc / 3, achieving dynamic balance. Figure 6(b) shows the simulation results of phase voltage and phase current. The phase voltage contains 0, U dc / 3, 2U dc / 3 and U dc Figure 6(c) shows the simulation result of phase current FFT (Fast Fourier Transform), and the total harmonic distortion of the current is 2.34%. The simulation results prove the feasibility of the three-phase four-level neutral point clamped inverter topology of this embodiment.

[0078] Furthermore, the present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned midpoint voltage balance control method is implemented.

[0079] Furthermore, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the above-mentioned midpoint voltage balance control method is implemented.

[0080] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0081] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A three-phase four-level neutral point clamped inverter, characterized in that: include: A DC power supply, three DC bus capacitors connected in series and twelve switch tubes, wherein the first to sixth switch tubes constitute a chopper unit, the seventh to twelfth switch tubes constitute a three-phase bridge arm circuit, the three DC bus capacitors connected in series are connected to the chopper unit, the chopper unit is also connected to the input end of the three-phase bridge arm circuit, and the midpoints of the bridge arms of the three-phase bridge arm circuit are respectively connected to the three-phase AC ends.

2. The three-phase four-level neutral point clamped inverter according to claim 1, characterized in that: All twelve switch tubes are MOS tubes.

3. The three-phase four-level neutral point clamped inverter according to claim 2, characterized in that: The source of the first switch tube is connected to the drain of the second switch tube and has a first node, the source of the second switch tube is connected to the drain of the fifth switch tube and has a second node, the source of the fifth switch tube is connected to the drain of the sixth switch tube and has a third node; the source of the third switch tube and the drain of the fourth switch tube are both connected to the second node, the drain of the first switch tube is connected to the positive end of the first DC bus capacitor and the positive end of the DC power supply, the source of the sixth switch tube is connected to the negative end of the third DC bus capacitor and the negative end of the DC power supply, and the drain of the third switch tube and the source of the fourth switch tube are respectively connected to the positive and negative ends of the second DC bus capacitor.

4. The three-phase four-level neutral point clamped inverter according to claim 3, characterized in that: In the three-phase bridge arm circuit, the source of the upper half bridge arm switch tube of each phase is connected to the drain of the corresponding lower half bridge arm switch tube, the drain of the upper half bridge arm switch tube of each phase is connected to the first node, and the source of the lower half bridge arm switch tube of each phase is connected to the third node.

5. A midpoint voltage balance control method, characterized in that: Applied to a three-phase four-level neutral point clamped inverter according to any one of claims 1 to 4, the method comprises: Acquire multiple switch combinations of a three-phase four-level neutral point clamped inverter, and divide the multiple switch combinations into four vectors; Based on multiple switch combinations in four vectors, the space vector distribution of the three-phase four-level neutral point clamped inverter is obtained; Based on the space vector distribution, the second DC bus capacitor voltage balance control and the first DC bus capacitor voltage and the third DC bus capacitor voltage dynamic balance control are implemented to achieve midpoint voltage balance control.

6. The midpoint voltage balance control method according to claim 5, characterized in that: The space vector distribution includes six sectors.

7. The midpoint voltage balance control method according to claim 6, characterized in that: A second DC bus capacitor voltage balance control is implemented based on the space vector distribution, including: For each sector, determining at least one switch combination in which the second DC bus capacitor is in a charging state, and determining at least one switch combination in which the second DC bus capacitor is in a discharging state; The action time of the first vector of the corresponding sector is obtained by adjusting the action time of at least one switch combination when the first adjustment factor and the second DC bus capacitor are in a charging state, and the action time of the second vector of the corresponding sector is obtained by adjusting the action time of at least one switch combination when the first adjustment factor and the second DC bus capacitor are in a discharging state, so that the three-phase four-level neutral point clamped inverter is acted on based on the adjusted action time of the first vector and the action time of the second vector to achieve voltage balance control of the second DC bus capacitor.

8. The midpoint voltage balance control method according to claim 7, characterized in that: Dynamically balancing the voltage of the first DC bus capacitor and the voltage of the third DC bus capacitor includes: For each sector, determining at least one switch combination in which the first DC bus capacitor or the third DC bus capacitor is in a charging state, and determining at least one switch combination in which the first DC bus capacitor or the third DC bus capacitor is in a discharging state; The action time of the corresponding sector charging vector is obtained by adjusting the second adjustment factor and the action time of at least one switch combination when the first DC bus capacitor is in a charging state, or the action time of at least one switch combination when the third DC bus capacitor is in a discharging state; and The action time of the corresponding sector discharge vector is obtained by adjusting the second adjustment factor and the action time of at least one switch combination when the first DC bus capacitor is in a discharging state, or the action time of at least one switch combination when the third DC bus capacitor is in a charging state; The three-phase four-level neutral point clamped inverter is acted on based on the adjusted action time of the charging vector and the action time of the discharging vector to achieve dynamic balance control of the first DC bus capacitor voltage and the third DC bus capacitor voltage.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the midpoint voltage balancing control method according to any one of claims 5 to 8 is implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the midpoint voltage balance control method according to any one of claims 5 to 8 is implemented.

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