Pin multiplexing circuit and electronic device

Abstract

The present invention provides a pin multiplexing circuit and electronic equipment, and relates to the field of computer technology. The circuit includes: a time-sharing control circuit and at least one signal synthesis circuit, wherein: at least one signal synthesis circuit is respectively connected to at least one output end of the time-sharing control circuit, and the output end of each signal synthesis circuit is connected to the target pin of a CPLD chip; the time-sharing control circuit is used to sequentially generate a time-sharing trigger signal corresponding to each signal synthesis circuit; each signal synthesis circuit is used to synthesize two received signals to be synthesized into one time-sharing multiplexing signal based on the time-sharing trigger signal; the time-sharing control circuit is also used to sequentially combine all time-sharing multiplexing signals based on all time-sharing trigger signals to obtain one pin multiplexing signal, and send the pin multiplexing signal to the target pin of the CPLD chip. The present invention can realize that multiple signals to be synthesized share one target pin of the CPLD chip, and greatly improve the I / O resource utilization rate of the CPLD chip.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a pin multiplexing circuit and electronic equipment. Background Art

[0002] As the functions of servers and other devices continue to increase, the information that the devices need to obtain continues to increase, and the I / O (Input / Output) resources used are gradually increasing, and the cost is rising. Therefore, how to improve the I / O resource utilization of CPLD (Complex Programmable Logic Device) chips has become a difficult point.

[0003] In the prior art, logic control circuits, software or multi-level chips are generally used to implement pin multiplexing of CPLD chips to improve I / O resource utilization of CPLD chips, but the design process is cumbersome, the control process is complex, and the cost is high. Summary of the invention

[0004] The present invention provides a pin multiplexing circuit and an electronic device, which are used to solve the defects of the prior art that the design process of pin multiplexing is cumbersome, the control process is complex, and the cost is high.

[0005] The present invention provides a pin multiplexing circuit, comprising: a time-sharing control circuit and at least one signal synthesis circuit, wherein:

[0006] The at least one signal synthesis circuit is respectively connected to at least one output end of the time-sharing control circuit, and the output end of each signal synthesis circuit is connected to the target pin of the CPLD chip;

[0007] The time-sharing control circuit is used to sequentially generate time-sharing trigger signals corresponding to each of the signal synthesis circuits; each of the signal synthesis circuits is used to synthesize the two received signals to be synthesized into one time-sharing multiplexed signal based on the time-sharing trigger signal; the time-sharing control circuit is also used to sequentially combine all time-sharing multiplexed signals based on all time-sharing trigger signals to obtain one pin multiplexing signal, and send the pin multiplexing signal to the target pin of the CPLD chip.

[0008] According to the pin multiplexing circuit provided by the present invention, when the number of paths of the signals to be synthesized is equal to two, the time-sharing control circuit is used to generate a time-sharing trigger signal corresponding to a complete cycle; the signal synthesis circuit is used to alternately output the two received signals to be synthesized based on the duty cycle of the time-sharing trigger signal, so as to synthesize the two signals to be synthesized into one time-sharing multiplexed signal;

[0009] When the number of signals to be synthesized is greater than two, the time-sharing control circuit is used to segment the complete cycle and sequentially generate time-sharing trigger signals corresponding to each segment; whether each time-sharing trigger signal is received or not is used to control the working state of the corresponding signal synthesis circuit; each signal synthesis circuit is used to, when receiving a time-sharing trigger signal, alternately output the two received signals to be synthesized within the working period corresponding to the time-sharing trigger signal based on the duty cycle of the time-sharing trigger signal, so as to synthesize the two signals to be synthesized into one time-sharing multiplexed signal.

[0010] According to the pin multiplexing circuit provided by the present invention, when the time-sharing control circuit only includes a first switching control circuit, the output end of the first switching control circuit is respectively connected to a first power supply and a first input end of the signal synthesis circuit; the first switching control circuit is used to generate a time-sharing trigger signal corresponding to the signal synthesis circuit.

[0011] According to the pin multiplexing circuit provided by the present invention, when the time-sharing control circuit includes at least two first switching control circuits and at least one second switching control circuit, the output end of the previous second switching control circuit is connected to the first power supply and the power supply end of the next second switching control circuit, the output end of the last second switching control circuit is connected to the first power supply and the power supply end of each of the first switching control circuits, and the output end of each of the first switching control circuits is connected to the first power supply and the first input end of the corresponding signal synthesis circuit; the previous second switching control circuit is used to generate a selection signal for the next second switching control circuit, and the selection signal is used to switch the working state of the next second switching control circuit or the working state of the next first switching control circuit; each of the first switching control circuits is used to generate a time-sharing trigger signal of the corresponding signal synthesis circuit based on the received selection signal.

[0012] According to the pin multiplexing circuit provided by the present invention, the first switching control circuit includes a voltage comparator including a voltage comparator, an RC circuit and a voltage divider circuit, wherein:

[0013] The positive input terminal of the voltage comparator is connected to the first terminal of the voltage divider circuit, the negative input terminal of the voltage comparator is connected to the first terminal of the RC circuit, the output terminal of the voltage comparator is connected to the second terminal of the RC circuit, the third terminal of the voltage divider circuit and the first power supply, and the output terminal of the voltage comparator serves as the output terminal of the first switching control circuit, and the second terminal of the voltage divider circuit is connected to the first power supply;

[0014] The voltage divider circuit is used to divide the output voltage of the first power supply to obtain a positive voltage divider that meets the target duty cycle; the RC circuit is used to generate a negative voltage; and the voltage comparator is used to generate the time-sharing trigger signal based on the comparison result between the negative voltage and the positive voltage divider.

[0015] According to the pin multiplexing circuit provided by the present invention, the voltage dividing circuit comprises a first voltage dividing resistor, a second voltage dividing resistor and a third voltage dividing resistor, wherein:

[0016] The first end of the first voltage-dividing resistor is connected to the first end of the second voltage-dividing resistor and the first end of the third voltage-dividing resistor, and is connected to the positive input end of the voltage comparator as the first end of the voltage-dividing circuit. The second end of the first voltage-dividing resistor is connected to the first power supply as the second end of the voltage-dividing circuit. The second end of the second voltage-dividing resistor is connected to the output end of the voltage comparator as the third end of the voltage-dividing circuit. The second end of the third voltage-dividing resistor is grounded.

[0017] According to the pin multiplexing circuit provided by the present invention, the second switching control circuit includes a third switching control circuit and a switch circuit, wherein:

[0018] The internal circuit structure of the third switching control circuit is the same as that of the first switching control circuit, the output end of the third switching control circuit is connected to the first input end of the switch circuit, the first output end of the switch circuit is connected to the power supply end of the first third switching control circuit of the next stage or the power supply end of the first first switching control circuit, the second output end of the switch circuit is connected to the power supply end of the second third switching control circuit of the next stage or the power supply end of the second first switching control circuit, and the first output end and the second output end of the switch circuit are both used as the output end of the second switching control circuit;

[0019] The third switching control circuit is used to generate a switching control signal corresponding to the switching circuit; the first output end of the switching circuit is used to generate a first selection signal among the selection signals based on the switching control signal, and the second output end of the switching circuit is used to generate a second selection signal among the selection signals based on the switching control signal, and the first selection signal and the second selection signal have opposite polarities.

[0020] According to the pin multiplexing circuit provided by the present invention, the signal synthesis circuit includes a first control circuit and a second control circuit, wherein:

[0021] The first end of the first control circuit is connected to the first end of the second control circuit, and both are used to receive the time-sharing trigger signal sent by the first switching control circuit; the second end of the first control circuit is used to receive the first signal to be synthesized; the third end of the first control circuit is connected to the output end of the second control circuit and serves as the output end of the signal synthesis circuit;

[0022] The second end of the second control circuit is used to receive the second signal to be synthesized, and the third end of the second control circuit is connected to the first power supply and serves as the fourth input end of the signal synthesis circuit;

[0023] The first control circuit is used to output a first time-sharing signal corresponding to the first signal to be synthesized in the first period of the working cycle of the segment where the time-sharing trigger signal is located; the second control circuit is used to output a second time-sharing signal corresponding to the second signal to be synthesized in the second period of the working cycle of the segment where the time-sharing trigger signal is located; the first time-sharing signal and the second time-sharing signal are output alternately to obtain a time-sharing multiplexed signal; the sum of the first period and the second period is equal to the working period.

[0024] According to the pin multiplexing circuit provided by the present invention, the second control circuit includes a MOS transistor Q2, a MOS transistor Q3 and a pull-up resistor, wherein:

[0025] The gate of the MOS transistor Q2 serves as the first end of the second control circuit, the source of the MOS transistor Q2 is grounded, the drain of the MOS transistor Q2 is connected to the first end of the pull-up resistor and the gate of the MOS transistor Q3, and the second end of the pull-up resistor serves as the third end of the second control circuit; the source of the MOS transistor Q3 serves as the second end of the second control circuit, and the drain of the MOS transistor Q3 serves as the output end of the second control circuit;

[0026] The time-sharing trigger signal is also used to control the on-off state of the MOS tube Q2, and the drain of the MOS tube Q2 is used to output a first square wave signal generated based on the time-sharing trigger signal; the first square wave signal is used to control the on-off state of the MOS tube Q3, and the drain of the MOS tube Q3 is used to output a second time-sharing signal generated based on the on-off state of the MOS tube Q3 and the second signal to be synthesized.

[0027] The present invention also provides an electronic device, comprising a CPLD chip and a pin multiplexing circuit as described in any one of the above items.

[0028] The pin multiplexing circuit and electronic device provided by the present invention have a pin multiplexing circuit in which a time-sharing control circuit sequentially generates a time-sharing trigger signal corresponding to each signal synthesis circuit, and each signal synthesis circuit synthesizes two received signals to be synthesized into a time-sharing multiplexing signal according to the corresponding time-sharing trigger signal, and sequentially combines all time-sharing multiplexing signals according to all the time-sharing trigger signals generated in sequence to obtain a pin multiplexing signal, and sends the pin multiplexing signal to the target pin of the CPLD chip. In the present invention, multiple signals to be synthesized are synthesized into a pin multiplexing signal, and through time-sharing multiplexing of the target pin of the CPLD chip, multiple signals to be synthesized share one target pin, which greatly improves the I / O resource utilization rate of the CPLD chip, and the circuit is simple, the control process is simple, and the demand for pin multiplexing can be achieved at a relatively low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 It is a connection diagram of a pin multiplexing circuit provided in an embodiment of the present invention.

[0031] Figure 2 It is a schematic diagram of the generation process of the pin multiplexing signal provided by an embodiment of the present invention.

[0032] Figure 3 This is one of the structural schematic diagrams of the pin multiplexing circuit provided in an embodiment of the present invention.

[0033] Figure 4 It is a structural schematic diagram of a first switching control circuit provided by an embodiment of the present invention.

[0034] Figure 5 This is the second structural schematic diagram of the pin multiplexing circuit provided in an embodiment of the present invention.

[0035] Figure 6 4 is a connection diagram of a second switching control circuit provided in an embodiment of the present invention.

[0036] Figure 7 This is one of the structural schematic diagrams of the switch circuit provided by the embodiment of the present invention.

[0037] Figure 8 This is the second structural schematic diagram of the switch circuit provided in the embodiment of the present invention.

[0038] Fig. 9It is a structural schematic diagram of a signal synthesis circuit provided by an embodiment of the present invention.

[0039] Fig.10 This is one of the schematic diagrams of the composition of the pin multiplexing signal provided by the embodiment of the present invention.

[0040] Fig.11 This is the second schematic diagram of the composition of the pin multiplexing signal provided in the embodiment of the present invention.

[0041] Reference numerals:

[0042] 110: time-sharing control circuit; 111: first switching control circuit; 1111: voltage comparator; 1112: RC circuit; 1113: voltage divider circuit; 112: second switching control circuit; 1121: third switching control circuit; 1122: switch circuit; 113: first voltage comparator; 114: second voltage comparator; 120: signal synthesis circuit; 121: second control circuit; 200: CPLD chip. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] In view of the problems in the prior art that the design process of pin multiplexing is cumbersome, the control process is complex, and the cost is high, an embodiment of the present invention provides a pin multiplexing circuit. Figure 1 is a connection diagram of a pin multiplexing circuit provided in an embodiment of the present invention, such as Figure 1 As shown, the pin multiplexing circuit includes: a time-sharing control circuit 110 and at least one signal synthesis circuit 120.

[0045] The at least one signal synthesis circuit 120 is respectively connected to at least one output end of the time-sharing control circuit 110 , and the output end of each signal synthesis circuit 120 is connected to a target pin of the CPLD chip 200 .

[0046] The time-sharing control circuit 110 is used to sequentially generate time-sharing trigger signals corresponding to each of the signal synthesis circuits 120; each of the signal synthesis circuits 120 is used to synthesize the two received signals to be synthesized into one time-sharing multiplexed signal based on the time-sharing trigger signal; the time-sharing control circuit 110 is also used to sequentially combine all time-sharing multiplexed signals based on all time-sharing trigger signals to obtain one pin multiplexing signal, and send the pin multiplexing signal to the target pin of the CPLD chip 200.

[0047] It should be noted that the time-sharing trigger signal is a square wave signal with a periodic level change, and the level change of the time-sharing trigger signal controls the signal output by the signal synthesis circuit 120. For example, when the time-sharing trigger signal is a high-level signal, the control signal synthesis circuit 120 outputs one of the signals to be synthesized, and when the time-sharing trigger signal is a low-level signal, the control signal synthesis circuit 120 outputs the other signal to be synthesized, and the two signals to be synthesized are synthesized into one time-sharing multiplexed signal by alternately outputting the two signals to be synthesized.

[0048] It should be noted that the two signals to be synthesized by each signal synthesis circuit 120 can be signals carrying information or empty signals, but at least one of the two signals to be synthesized is a signal carrying information, that is, each signal synthesis circuit 120 can receive one signal carrying information and the other signal to be synthesized is an empty signal, and synthesize the signal carrying information and the empty signal into a time-division multiplexed signal, or each signal synthesis circuit 120 can receive two signals carrying information and synthesize the two signals carrying information into a time-division multiplexed signal.

[0049] It should be noted that the signal carrying information may be a single signal with a single waveform or a signal with a periodically changing waveform. For example, the signal carrying information may be a module status signal or a fan speed signal, etc., and the embodiments of the present invention are not limited to this.

[0050] Furthermore, when the number of paths of the signals to be synthesized is equal to two, the time-sharing control circuit is used to generate a time-sharing trigger signal corresponding to a complete cycle; the signal synthesis circuit is used to alternately output the two received signals to be synthesized based on the duty cycle of the time-sharing trigger signal, so as to synthesize the two signals to be synthesized into one time-sharing multiplexed signal;

[0051] When the number of signals to be synthesized is greater than two, the time-sharing control circuit is used to segment the complete cycle and sequentially generate time-sharing trigger signals corresponding to each segment; whether each time-sharing trigger signal is received or not is used to control the working state of the corresponding signal synthesis circuit; each signal synthesis circuit is used to, when receiving a time-sharing trigger signal, alternately output the two received signals to be synthesized within the working period corresponding to the time-sharing trigger signal based on the duty cycle of the time-sharing trigger signal, so as to synthesize the two signals to be synthesized into one time-sharing multiplexed signal.

[0052] Specifically, if only two signals to be synthesized need to be synthesized, only one time-sharing control circuit and one signal synthesis circuit are needed. The time-sharing control circuit can generate a time-sharing trigger signal corresponding to a complete cycle. There is a level change in the time-sharing trigger signal. For example, when the duty cycle of the time-sharing trigger signal is 50%, the time-sharing trigger signal is a high-level signal in the first half of the complete cycle and a low-level signal in the second half. When the time-sharing trigger signal is a high-level signal, the signal synthesis circuit can output one signal to be synthesized, and when the time-sharing trigger signal is a low-level signal, the signal synthesis circuit can output another signal to be synthesized. Based on this, within a complete cycle, the alternating output of the two signals to be synthesized can be regarded as synthesizing the two signals to be synthesized into a time-sharing multiplexed signal for output.

[0053] If the number of signals to be synthesized is greater than two, a time-sharing control circuit and at least two signal synthesis circuits are required. According to the number of signal synthesis circuits, the time-sharing control circuit can segment the complete cycle. In the working cycle corresponding to the segment, the corresponding signal synthesis circuit is controlled to be in working state, so that all signal synthesis circuits form a sequence and are in working state in sequence. In the working cycle of the segment corresponding to the signal synthesis circuit, the time-sharing control circuit can send the time-sharing trigger signal to the corresponding signal synthesis circuit. The signal synthesis circuit can output the two signals to be synthesized received by itself alternately according to the duty cycle of the time-sharing trigger signal, so as to synthesize the two signals to be synthesized into one time-sharing multiplexing signal. Based on this, in a complete cycle, all time-sharing multiplexing signals are output in sequence according to the working cycle corresponding to each segment, so as to realize the synthesis of more than two signals to be synthesized into one pin multiplexing signal.

[0054] For example, Figure 2 FIG. 1 is a schematic diagram of a generation flow of a pin multiplexing signal provided by an embodiment of the present invention, such as Figure 2As shown, taking the pin multiplexing circuit including two signal synthesis circuits 120, the signal synthesis circuit 120A receives the signal 1 to be synthesized and the signal 2 to be synthesized, the signal synthesis circuit 120B receives the signal 3 to be synthesized and the signal 4 to be synthesized, and the duty cycle of the time-sharing trigger signal is 50% as an example, the two output ends of the time-sharing control circuit 110 are respectively connected to the signal synthesis circuit 120A and the signal synthesis circuit 120B, the time-sharing control circuit 110 generates the time-sharing trigger signal 1 corresponding to the signal synthesis circuit 120A in the first half cycle, and generates the time-sharing trigger signal 2 corresponding to the signal synthesis circuit 120B in the second half cycle. In the first half cycle, since the duty cycle of the time-sharing trigger signal 1 is 50%, after the time-sharing trigger signal 1 acts on the signal synthesis circuit 120A, the signal synthesis circuit 120A synthesizes the to-be-synthesized signal 1 and the to-be-synthesized signal 2 into a time-sharing multiplexing signal 1, and the to-be-synthesized signal 1 and the to-be-synthesized signal 2 are alternately output in the time-sharing multiplexing signal 1, that is, in the first half cycle, the to-be-synthesized signal 1 and the to-be-synthesized signal 2 each occupy a quarter cycle. In the second half cycle, since the duty cycle of the time-sharing trigger signal 2 is 50%, after the time-sharing trigger signal 2 acts on the signal synthesis circuit 120B, the signal synthesis circuit 120B synthesizes the to-be-synthesized signal 3 and the to-be-synthesized signal 4 into a time-sharing multiplexing signal 2, and the to-be-synthesized signal 3 and the to-be-synthesized signal 4 are alternately output in the time-sharing multiplexing signal 2, that is, in the second half cycle, the to-be-synthesized signal 3 and the to-be-synthesized signal 4 each occupy a quarter cycle. The time-division multiplexing signal 1 synthesized in the first half cycle and the time-division multiplexing signal 2 synthesized in the second half cycle form a pin multiplexing signal. In a complete cycle, the pin multiplexing signal sequentially outputs the signal to be synthesized 1, the signal to be synthesized 2, the signal to be synthesized 3 and the signal to be synthesized 4, and outputs them in a cycle.

[0055] It should be noted that the final synthesized pin multiplexing signal is transmitted on a hardware line.

[0056] In the pin multiplexing circuit provided by the embodiment of the present invention, the time-sharing control circuit 110 sequentially generates the time-sharing trigger signals corresponding to each signal synthesis circuit 120 in the pin multiplexing circuit. Each signal synthesis circuit 120 synthesizes the two received signals to be synthesized into one time-sharing multiplexing signal according to the corresponding time-sharing trigger signal. The two signals to be synthesized are alternately combined in the time-sharing multiplexing signal. According to all the time-sharing trigger signals generated in sequence, all the time-sharing multiplexing signals are sequentially combined to obtain one pin multiplexing signal, and the pin multiplexing signal is sent to the target pin of the CPLD chip 200. In the embodiment of the present invention, multiple signals to be synthesized are synthesized into one pin multiplexing signal, that is, multiple signals to be synthesized are alternately output through the pin multiplexing signal. Through the time-sharing multiplexing of the target pin of the CPLD chip 200, multiple signals to be synthesized share one target pin, which greatly improves the I / O resource utilization rate of the CPLD chip 200. The circuit is simple, the control process is simple, and the demand for pin multiplexing can be achieved at a low cost.

[0057] Further, in the case where the time-sharing control circuit 110 only includes the first switching control circuit 111, the output end of the first switching control circuit 111 is respectively connected to the first power supply VCC and the first input end of the signal synthesis circuit 120; the first switching control circuit 111 is used to generate a time-sharing trigger signal corresponding to the signal synthesis circuit 120.

[0058] Specifically, Figure 3 FIG. 1 is one of the structural diagrams of the pin multiplexing circuit provided in an embodiment of the present invention. Figure 3 As shown, when the time-sharing control circuit 110 includes only one first switching control circuit 111, the pin multiplexing circuit can only synthesize two signals to be synthesized. That is, the first switching control signal is connected to a signal synthesis circuit 120, and generates a time-sharing trigger signal corresponding to the signal synthesis circuit 120. The output switching timing of the two signals to be synthesized is controlled by the time-sharing trigger signal. Since the time-sharing trigger signal is a periodically changing square wave, that is, the time-sharing trigger signal includes an alternating high-level signal and a low-level signal, the signal synthesis circuit 120 alternately outputs the two signals to be synthesized, thereby realizing the synthesis of the two signals to be synthesized. For example, in the first half of the cycle, the time-sharing trigger signal is a high-level signal, which can control the signal synthesis circuit 120 to output one of the signals to be synthesized, and in the second half of the cycle, the time-sharing trigger signal is a low-level signal, which can control the signal synthesis circuit 120 to output the other signal to be synthesized. By alternating the output of the two signals to be synthesized in different time periods, the two signals to be synthesized are synthesized into a time-sharing multiplexed signal. Since only one time-division multiplexing signal is generated, the time-division multiplexing signal is the pin multiplexing signal.

[0059] Further, Figure 4is a schematic diagram of the structure of a first switching control circuit provided by an embodiment of the present invention, such as Figure 4 As shown, the first switching control circuit 111 includes a voltage comparator 1111, an RC circuit 1112 and a voltage divider circuit 1113, wherein:

[0060] The positive input terminal IN+ of the voltage comparator 1111 is connected to the first end of the voltage divider circuit 1113, the negative input terminal IN- of the voltage comparator 1111 is connected to the first end of the RC circuit 1112, the output terminal of the voltage comparator 1111 is connected to the second end of the RC circuit 1112, the third end of the voltage divider circuit 1113 and the first power supply VCC, and the output terminal of the voltage comparator 1111 serves as the output terminal of the first switching control circuit 111, and the second end of the voltage divider circuit 1113 is connected to the first power supply VCC;

[0061] The voltage divider circuit 1113 is used to divide the output voltage of the first power supply VCC to obtain a positive voltage divider that meets the target duty cycle; the RC circuit 1112 is used to generate a negative voltage; and the voltage comparator 1111 is used to generate the time-sharing trigger signal based on the comparison result between the negative voltage and the positive voltage divider.

[0062] The characteristic of the voltage comparator 1111 is that when the voltage of the positive input terminal IN+ is higher than the voltage of the negative input terminal IN-, the voltage comparator 1111 outputs a high level signal. Conversely, when the voltage of the positive input terminal IN+ is lower than the voltage of the negative input terminal IN-, the voltage comparator 1111 outputs a low level signal.

[0063] In the first switching control circuit 111, the characteristics of the voltage comparator 1111 are used to generate a square wave signal with a periodic level change, and then the duty cycle of the square wave signal is adjusted in combination with the charging and discharging time of the RC circuit 1112, so as to obtain a time-sharing trigger signal. When the pin multiplexing circuit is working, the negative voltage of the negative input terminal IN- of the voltage comparator 1111 is relatively low. Since the voltage divider circuit 1113 connected to the positive input terminal IN+ of the voltage comparator 1111 is connected to the first power supply VCC, the positive voltage division of the positive input terminal IN+ of the voltage comparator 1111 is relatively high. Since the output terminal of the voltage comparator 1111 is connected to the first power supply VCC, at this time, the first power supply VCC charges the RC circuit 1112, and the negative voltage of the negative input terminal IN- gradually increases with the increase of the charging time of the RC circuit 1112. In the process where the negative voltage of the negative input terminal IN- is less than the positive voltage division of the positive input terminal IN+, the voltage comparator 1111 outputs a high level signal. Until the negative voltage rises to a value higher than the positive voltage division, the voltage comparator 1111 outputs a low-level signal. At this time, the RC circuit 1112 starts to discharge, and the negative voltage of the negative input terminal IN- gradually decreases as the discharge time of the RC circuit 1112 increases, until the negative voltage decreases to a value lower than the positive voltage division, the voltage comparator 1111 outputs a complete cycle of the time-sharing trigger signal. In this way, a periodically changing time-sharing trigger signal can be obtained.

[0064] Furthermore, if Figure 4 As shown, the voltage divider circuit 1113 includes a first voltage divider resistor R1, a second voltage divider resistor R2 and a third voltage divider resistor R3, wherein:

[0065] The first end of the first voltage-dividing resistor R1 is connected to the first end of the second voltage-dividing resistor R2 and the first end of the third voltage-dividing resistor R3, and is connected to the positive input terminal IN+ of the voltage comparator 1111 as the first end of the voltage-dividing circuit 1113. The second end of the first voltage-dividing resistor R1 is connected to the first power supply VCC as the second end of the voltage-dividing circuit 1113. The second end of the second voltage-dividing resistor R2 is connected to the output terminal of the voltage comparator 1111 as the third end of the voltage-dividing circuit 1113. The second end of the third voltage-dividing resistor R3 is grounded.

[0066] Specifically, in the process of the negative voltage of the negative input terminal IN- being less than the positive voltage division of the positive input terminal IN+, the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 in the voltage-dividing circuit 1113 are connected in parallel and then connected in series with the third voltage-dividing resistor R3. In the process of the negative voltage of the negative input terminal IN- being greater than the positive voltage division of the positive input terminal IN+, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 in the voltage-dividing circuit 1113 are connected in parallel and then connected in series with the first voltage-dividing resistor R1. The corresponding resistance values ​​of the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 in the voltage-dividing circuit 1113 respectively determine the voltage division ratio of the output voltage of the first power supply VCC, thereby determining the magnitude of the positive voltage division. By controlling the magnitude of the positive voltage division, the charging and discharging time of the RC circuit 1112 can be further controlled, thereby controlling the switching timing of the high and low levels in the time-dividing trigger signal, that is, controlling the duty cycle of the time-dividing trigger signal.

[0067] Further, Figure 5 FIG. 2 is a second structural diagram of a pin multiplexing circuit provided in an embodiment of the present invention. Figure 5 As shown, in the case where the time-sharing control circuit 110 includes at least two first switching control circuits 111 and at least one second switching control circuit 112, the output end of the previous second switching control circuit 112 is connected to the first power supply VCC and the power supply end of the next second switching control circuit 112, the output end of the last second switching control circuit 112 is connected to the first power supply VCC and the power supply end of each first switching control circuit 111, and the output end of each first switching control circuit 111 is connected to the first power supply VCC and the first input end of the corresponding signal synthesis circuit 120; the previous second switching control circuit 112 is used to generate a selection signal of the next second switching control circuit 112, and the selection signal is used to switch the working state of the next second switching control circuit 112 or the working state of the next first switching control circuit 111; each first switching control circuit 111 is used to generate a time-sharing trigger signal of the corresponding signal synthesis circuit 120 based on the received selection signal.

[0068] Specifically, since each signal synthesis circuit 120 synthesizes at most two channels of signals to be synthesized, when the number of channels of the signals to be synthesized is greater than two channels, one first switching control circuit 111 generating one time-sharing trigger signal cannot meet the requirement. At this time, at least two first switching control circuits 111 may be included in the time-sharing control circuit 110, each of which generates one time-sharing trigger signal, and each time-sharing trigger signal acts on the corresponding signal synthesis circuit 120. The number of first switching control circuits 111 is equal to the number of signal synthesis circuits 120. When the number of first switching control circuits 111 is m, m signal synthesis circuits 120 can synthesize at most 2m channels of signals to be synthesized, where m is an integer greater than 1.

[0069] In order to control at least two first switching control circuits 111 to generate time-sharing trigger signals respectively in different time periods within a complete cycle, the time-sharing control circuit 110 may further include at least one level of second switching control circuit 112, each second switching circuit of the previous level is connected to at most two second switching control circuits 112 of the next level, and each second switching control circuit 112 of the last level is connected to at most two first switching control circuits 111, so the number of first switching control circuits 111 is at most 2 n , n represents the number of stages of the second switching control circuit 112 included in the time-sharing control circuit 110, and n is a positive integer. The second switching control circuits 112 of all stages can segment a complete cycle, and the second switching control circuit 112 of the previous stage generates a selection signal for the second switching control circuit 112 of the next stage, and the selection signal is also a square wave signal with a periodic level change, so that the working cycle of the second switching control circuit 112 of the next stage is half of the working cycle of the second switching control circuit 112 of the previous stage, and so on, it is obtained that the working cycle of each first switching control circuit 111 is half of the working cycle of the second switching control circuit 112 of the last stage. The selection signal generated by the second switching control circuit 112 of the previous stage is used to control the working state of the second switching control circuit 112 of the next stage or the working state of the first switching control circuit 111 of the next stage. The second switching control circuits 112 of all stages serve as control switches of all first switching control circuits 111, and the control frequency of the second switching control circuits 112 of the same stage remains consistent, controlling each first switching control circuit 111 to generate a time-sharing trigger signal within the corresponding working cycle, so that the corresponding signal synthesis circuit 120 synthesizes two channels of signals to be synthesized. The holding time of each channel of the signals to be synthesized is shown in formula (1), which is:

[0070] ,

[0071] Wherein, T represents a complete cycle, which can be the working cycle of the first-stage second switching control circuit, and t represents the holding time of each to-be-synthesized signal. Each signal synthesis circuit 120 can alternately output the corresponding to-be-synthesized signal within the corresponding working cycle, and the output time of each to-be-synthesized signal is the holding time t.

[0072] Further, Figure 6 is a connection diagram of a second switching control circuit provided by an embodiment of the present invention, such as Figure 6 As shown, the second switching control circuit 112 includes a third switching control circuit 1121 and a switch circuit 1122, wherein:

[0073] The internal circuit structure of the third switching control circuit 1121 is the same as the internal circuit structure of the first switching control circuit 111, the output end of the third switching control circuit 1121 is connected to the first input end of the switch circuit 1122, the first output end of the switch circuit 1122 is connected to the power supply end of the first third switching control circuit 1121 of the next stage or the power supply end of the first first switching control circuit 111, the second output end of the switch circuit 1122 is connected to the power supply end of the second third switching control circuit 1121 of the next stage or the power supply end of the second first switching control circuit 111, and the first output end and the second output end of the switch circuit 1122 are both used as the output end of the second switching control circuit 112;

[0074] The third switching control circuit 1121 is used to generate a switching control signal corresponding to the switching circuit 1122; the first output end of the switching circuit 1122 is used to generate a first selection signal in the selection signal based on the switching control signal, and the second output end of the switching circuit 1122 is used to generate a second selection signal in the selection signal based on the switching control signal, and the first selection signal and the second selection signal have opposite polarity.

[0075] Specifically, the third switching control circuit 1121 included in the second switching control circuit 112 has the same internal circuit structure as the first switching control circuit 111, that is, the third switching control circuit 1121 also includes a voltage comparator 1111, an RC circuit 1112 and a voltage divider circuit 1113, and uses the characteristics of the voltage comparator 1111 to generate a square wave signal with a periodic level change, and then adjusts the duty cycle of the square wave signal in combination with the charge and discharge time of the RC circuit 1112, thereby obtaining a control signal. The control signal is also a square wave signal with a periodic level change. The second switching control circuit 112 of the previous stage can be connected to the two second switching control circuits 112 of the next stage. To ensure that the second switching control circuit 112 or the first switching control circuit 111 of the next stage is effective in different time periods, the control signal can be input into the first input end of the switch circuit 1122. The switch circuit 1122 can generate a selection signal according to the control signal, and the selection signal includes a first selection signal and a second selection signal with opposite polarities. At the same time, the first selection signal and the second selection signal with opposite polarities can control the first third switching control circuit 1121 and the second third switching control circuit 1121 of the next stage to be in different working states, or control the first first switching control circuit 111 and the second first switching control circuit 111 of the next stage to be in different working states, thereby controlling the two second switching control circuits 112 of the next stage to generate new selection signals in different time periods, or controlling the first switching control circuit 111 of the next stage to generate time-sharing trigger signals in different time periods. For example, when the control signal is a high-level signal, the first selection signal outputted from the first output terminal of the switch circuit 1122 is a high-level signal, and the second selection signal outputted from the second output terminal of the switch circuit 1122 is a low-level signal. The first selection signal, which is a high-level signal, can control the first third switching control circuit 1121 of the next stage or the first first switching control circuit 111 of the next stage to be in a working state, and the second selection signal, which is a low-level signal, can control the second third switching control circuit 1121 of the next stage or the second first switching control circuit 111 of the next stage to be in a non-working state. When the control signal is a low-level signal, the first selection signal outputted from the first output terminal of the switch circuit 1122 is a low-level signal, and the second selection signal outputted from the second output terminal of the switch circuit 1122 is a high-level signal. The first selection signal, which is a low-level signal, can control the first third switching control circuit 1121 of the next stage or the first first switching control circuit 111 of the next stage to be in a non-working state, and the second selection signal, which is a high-level signal, can control the second third switching control circuit 1121 of the next stage or the second first switching control circuit 111 of the next stage to be in a working state.

[0076] Optionally, Figure 7 is one of the structural schematic diagrams of the switch circuit provided by the embodiment of the present invention, such as Figure 7As shown, the switch circuit 1122 may include an NMOS (N-Metal-Oxide-Semiconductor) tube N1, an NMOS tube N2 and a first resistor R11, wherein: the gate of the NMOS tube N1 is connected to the gate of the NMOS tube N2 and serves as the first input terminal of the switch circuit 1122, the source of the NMOS tube N1 is connected to the first power supply VCC and serves as the second input terminal of the switch circuit 1122, and the drain of the NMOS tube N1 is connected to the power supply terminal of the first third switching control circuit 1121 of the next stage or the first voltage comparator 113 of the first first switching control circuit 111 and serves as the first output terminal of the switch circuit 1122. The source of the NMOS tube N2 is connected to the first end of the first resistor R11 and the power supply end of the second voltage comparator 114 of the second third switching control circuit 1121 or the second first switching control circuit 111 of the next stage, and serves as the second output end of the switch circuit 1122. The second end of the first resistor R11 is connected to the first power supply VCC and serves as the third input end of the switch circuit 1122. The drain of the NMOS tube N2 is grounded and serves as the fourth input end of the switch circuit 1122.

[0077] like Figure 7As shown, when the control signal input to the first input terminal of the switch circuit 1122 is a high-level signal, the NMOS tube N1 and the NMOS tube N2 are both turned on, and the first selection signal output from the drain of the NMOS tube N1 is a high-level signal, that is, the first power supply VCC supplies power to the power supply terminal of the first third switching control circuit 1121 of the next stage or the first voltage comparator 113 of the first first switching control circuit 111, so that the first third switching control circuit 1121 of the next stage or the first first switching control circuit 111 is in a working state, thereby making the first third switching control circuit 1121 of the next stage continue to generate a control signal, or the first first switching control circuit of the next stage generates a time-sharing trigger signal. After the NMOS tube N2 is turned on, the ground terminal pulls down the voltage of the source of the NMOS tube N2, so that the second selection signal output from the source of the NMOS tube N2 is a low-level signal, so that the first third switching control circuit 1121 of the next stage or the first first switching control circuit 111 is in a non-working state. When the control signal inputted to the first input terminal of the switch circuit 1122 is a low-level signal, both the NMOS transistor N1 and the NMOS transistor N2 are turned off, and the power supply terminal of the first voltage comparator 113 of the first third switching control circuit 1121 or the first first switching control circuit 111 of the next stage is not powered, so that the first third switching control circuit 1121 or the first first switching control circuit 111 of the next stage is in a non-operating state. After the NMOS transistor N2 is turned off, the first power supply VCC supplies power to the power supply terminal of the second voltage comparator 114 of the second third switching control circuit 1121 or the second first switching control circuit 111 of the next stage, so that the second third switching control circuit 1121 or the second first switching control circuit 111 of the next stage is in an operating state, thereby making the second third switching control circuit 1121 of the next stage continue to generate a control signal, or the second first switching control circuit of the next stage generates a time-sharing trigger signal.

[0078] Optionally, Figure 8 FIG. 2 is a second structural diagram of a switch circuit provided in an embodiment of the present invention. Figure 8As shown, the switch circuit 1122 may also include an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, and a second resistor R22, wherein: the gate of the NMOS transistor N3 is connected to the gate of the NMOS transistor N4 and serves as the first input terminal of the switch circuit 1122, the source of the NMOS transistor N3 is connected to the first power supply VCC and serves as the second input terminal of the switch circuit 1122, and the drain of the NMOS transistor N3 serves as the first output terminal of the switch circuit 1122. The source of the NMOS transistor N4 is grounded and serves as the fifth input terminal of the switch circuit 1122, the drain of the NMOS transistor N4 is connected to the first end of the second resistor R22 and the gate of the NMOS transistor N5, the second end of the second resistor R22 is connected to the first power supply VCC and serves as the fourth input terminal of the switch circuit 1122. The source of the NMOS transistor N5 is connected to the first power supply VCC and serves as the third input terminal of the switch circuit 1122, and the drain of the NMOS transistor N5 serves as the second output terminal of the switch circuit 1122.

[0079] like Figure 8As shown, when the control signal input to the first input terminal of the switch circuit 1122 is a high-level signal, both the NMOS transistor N3 and the NMOS transistor N4 are turned on. After the NMOS transistor N3 is turned on, the first selection signal output by the drain of the NMOS transistor N3 is a high-level signal, that is, the first power supply VCC supplies power to the power supply terminal of the first third switching control circuit 1121 of the next stage or the first voltage comparator 113 of the first first switching control circuit 111, so that the first third switching control circuit 1121 of the next stage or the first first switching control circuit 111 is in a working state, thereby making the first third switching control circuit 1121 of the next stage continue to generate a control signal, or the first first switching control circuit of the next stage generates a time-sharing trigger signal. After the NMOS transistor N4 is turned on, the ground terminal pulls down the drain voltage of the NMOS transistor N4, so that the signal input to the gate of the NMOS transistor N5 is a low-level signal, so that the NMOS transistor N5 is turned off, and the power supply end of the second voltage comparator 114 of the second third switching control circuit 1121 or the second first switching control circuit 111 of the next stage is not powered, so that the second third switching control circuit 1121 or the second first switching control circuit 111 of the next stage is in a non-operating state. When the control signal input to the first input end of the switch circuit 1122 is a low-level signal, both the NMOS transistor N3 and the NMOS transistor N4 are turned off. After the NMOS transistor N3 is turned off, the power supply end of the first voltage comparator 113 of the first third switching control circuit 1121 or the first first switching control circuit 111 of the next stage is not powered, so that the first third switching control circuit 1121 or the first first switching control circuit 111 of the next stage is in a non-operating state. After the NMOS tube N4 is turned off, the output voltage of the first power supply VCC acts on the gate of the NMOS tube N5, so that the signal input to the gate of the NMOS tube N5 is a high-level signal, so that the NMOS tube N5 is turned on, and the first power supply VCC supplies power to the power supply end of the second third switching control circuit 1121 of the next stage or the second voltage comparator 114 of the second first switching control circuit 111, so that the second third switching control circuit 1121 of the next stage or the second first switching control circuit 111 is in a working state, thereby making the second third switching control circuit 1121 of the next stage continue to generate a control signal, or the second first switching control circuit of the next stage generates a time-sharing trigger signal.

[0080] It should be noted that, in addition to the above two circuit structures, the switch circuit 1122 may also include other circuit structures, which is not limited in the embodiment of the present invention.

[0081] Furthermore, the signal synthesis circuit includes a first control circuit and a second control circuit, wherein:

[0082] The first end of the first control circuit is connected to the first end of the second control circuit, and both are used to receive the time-sharing trigger signal sent by the first switching control circuit; the second end of the first control circuit is used to receive the first signal to be synthesized; the third end of the first control circuit is connected to the output end of the second control circuit and serves as the output end of the signal synthesis circuit;

[0083] The second end of the second control circuit is used to receive the second signal to be synthesized, and the third end of the second control circuit is connected to the first power supply and serves as the fourth input end of the signal synthesis circuit;

[0084] The first control circuit is used to output a first time-sharing signal corresponding to the first signal to be synthesized in the first period of the working cycle of the segment where the time-sharing trigger signal is located; the second control circuit is used to output a second time-sharing signal corresponding to the second signal to be synthesized in the second period of the working cycle of the segment where the time-sharing trigger signal is located; the first time-sharing signal and the second time-sharing signal are output alternately to obtain a time-sharing multiplexed signal; the sum of the first period and the second period is equal to the working period.

[0085] Specifically, Fig. 9 is a schematic diagram of the structure of a signal synthesis circuit provided by an embodiment of the present invention, such as Fig. 9 As shown, the first control circuit includes a MOS transistor Q1, the gate of the MOS transistor Q1 is connected to the first end of the second control circuit 121 and serves as the first input end of the signal synthesis circuit 120, the gate of the MOS transistor Q1 is used to receive the time-sharing trigger signal sent by the first switching control circuit 111, and the time-sharing trigger signal is used to control the on-off state of the MOS transistor Q1; the source of the MOS transistor Q1 serves as the second input end of the signal synthesis circuit 120, and the source of the MOS transistor Q1 is used to receive the first signal to be synthesized; the drain of the MOS transistor Q1 is connected to the output end of the second control circuit 121 and serves as the output end of the signal synthesis circuit 120, and the drain of the MOS transistor Q1 is used to output a first time-sharing signal generated based on the time-sharing trigger signal and the first signal to be synthesized.

[0086] The second end of the second control circuit 121 serves as the third input end of the signal synthesis circuit 120, and the second end of the second control circuit 121 is used to receive the second signal to be synthesized; the third end of the second control circuit 121 is connected to the first power supply VCC and serves as the fourth input end of the signal synthesis circuit 120; the output end of the second control circuit 121 is used to generate a second time-sharing signal based on the time-sharing trigger signal and the second signal to be synthesized, and the first time-sharing signal and the second time-sharing signal are combined in sequence to obtain a time-sharing multiplexed signal.

[0087] After the signal synthesis circuit 120 receives the time-sharing trigger signal, when the time-sharing trigger signal is a high-level signal, the on-off states corresponding to the MOS tube Q1 and the second control circuit 121 are different, and one of the signals to be synthesized received by the MOS tube Q1 and the second control circuit 121 can be output. After the time-sharing trigger signal is switched to a low-level signal, the on-off states corresponding to the MOS tube Q1 and the second control circuit 121 change, but the on-off states of the two are still different, and the other signal to be synthesized is output.

[0088] For example, taking the MOS tube Q1 as an NMOS tube, after the signal synthesis circuit 120 receives the time-sharing trigger signal, when the time-sharing trigger signal is a high-level signal, that is, in the first half period, the MOS tube Q1 is turned on and the second control circuit 121 is turned off. At this time, the first signal to be synthesized received by the source of the MOS tube Q1 is the first time-sharing signal, and the first time-sharing signal is output; when the time-sharing trigger signal is a low-level signal, that is, in the second half period, the MOS tube Q1 is turned off, the second control circuit 121 is turned on, the second signal to be synthesized received by the second end of the second control circuit 121 is the second time-sharing signal, and the second time-sharing signal is output. The first time-sharing signal in the first half period and the second time-sharing signal in the second half period constitute a time-sharing multiplexed signal.

[0089] Furthermore, if Fig. 9 As shown, the second control circuit 121 includes a MOS transistor Q2, a MOS transistor Q3 and a pull-up resistor R33, wherein:

[0090] The gate of the MOS transistor Q2 serves as the first end of the second control circuit 121, the source of the MOS transistor Q2 is grounded, the drain of the MOS transistor Q2 is connected to the first end of the pull-up resistor R33 and the gate of the MOS transistor Q3, and the second end of the pull-up resistor R33 serves as the third end of the second control circuit 121; the source of the MOS transistor Q3 serves as the second end of the second control circuit 121, and the drain of the MOS transistor Q3 serves as the output end of the second control circuit 121;

[0091] The time-sharing trigger signal is also used to control the on-off state of the MOS tube Q2, and the drain of the MOS tube Q2 is used to output a first square wave signal generated based on the time-sharing trigger signal; the first square wave signal is used to control the on-off state of the MOS tube Q3, and the drain of the MOS tube Q3 is used to output a second time-sharing signal generated based on the on-off state of the MOS tube Q3 and the second signal to be synthesized.

[0092] For example, taking the case where the MOS transistor Q1, the MOS transistor Q2 and the MOS transistor Q3 are all NMOS transistors, when the time-sharing trigger signal is a high-level signal, that is, in the first half period, the MOS transistor Q1 and the MOS transistor Q2 are both turned on. After the MOS transistor Q2 is turned on, the ground terminal connected to the source of the MOS transistor Q2 pulls down the high-level signal, so that the first square wave signal output by the drain of the MOS transistor Q2 is a low-level signal. After the first square wave signal acts on the gate of the MOS transistor Q3, the MOS transistor Q3 is turned off, and then the entire second control circuit 121 is turned off. At this time, the first signal to be synthesized received by the source of the MOS transistor Q1 is the first time-sharing signal, and the first time-sharing signal is output. When the time-sharing trigger signal is a low-level signal, that is, in the second half of the period, both the MOS transistor Q1 and the MOS transistor Q2 are turned off. After the MOS transistor Q2 is turned off, the first power supply VCC connected to the drain of the MOS transistor Q2 pulls up the low-level signal, so that the first square wave signal output by the drain of the MOS transistor Q2 is a high-level signal. After the first square wave signal acts on the gate of the MOS transistor Q3, the MOS transistor Q3 is turned on, and then the entire second control circuit 121 is turned on. At this time, the second signal to be synthesized received by the source of the MOS transistor Q3 is the second time-sharing signal, and the second time-sharing signal is output.

[0093] It should be noted that the first square wave signal has the same frequency and opposite polarity as the time-sharing trigger signal. The two square wave signals with the same frequency and opposite polarity respectively control the output timing of the first signal to be synthesized and the second signal to be synthesized, thereby realizing the synthesis of the first signal to be synthesized and the second signal to be synthesized.

[0094] For example, the pin multiplexing circuit includes a time-sharing control circuit 110 and two signal synthesis circuits 120, and the time-sharing control circuit 110 includes a second switching control circuit 112 and two first switching control circuits 111, and the number of signals to be synthesized is 4, the duty cycle of the selection signal and the time-sharing trigger signal is 50%, and the signals to be synthesized 1 to 4 are all signals carrying information, and the second switching control circuit 112 generates a selection signal. In the first half cycle, the first selection signal in the selection signal is a high-level signal, and the second selection signal is a low-level signal. The first selection signal, which is a high-level signal, can put the first switching control circuit 111 in a working state, and the second selection signal, which is a low-level signal, can put the first switching control circuit 111 in a non-working state. The first switching control circuit 111 can generate a time-sharing trigger signal 1 with a duty cycle of 50%, and the time-sharing trigger signal 1 further divides the first half cycle into a first quarter cycle and a second quarter cycle. In the first quarter cycle, the time-sharing trigger signal 1 is a high-level signal, the MOS transistor Q1 in the signal synthesis circuit 120A is turned on, and the second control circuit 121 is turned off, and the signal 1 to be synthesized received by the source of the MOS transistor Q1 is output. In the second quarter cycle, the time-sharing trigger signal 1 is a low-level signal, the MOS transistor Q1 in the signal synthesis circuit 120A is turned off, the MOS transistor Q2 is turned off, and the MOS transistor Q3 is turned on, so that the second control circuit 121 is turned on, and then the signal 2 to be synthesized received by the source of the MOS transistor Q3 is output. In the second half cycle, the first selection signal in the selection signal is a low-level signal, and the second selection signal is a high-level signal. The second selection signal of the high-level signal can put the first switching control circuit 111 in a working state, and the first selection signal of the low-level signal can put the first switching control circuit 111 in a non-working state. The first switching control circuit 111 can generate a time-sharing trigger signal 2 with a duty cycle of 50%, and the time-sharing trigger signal 2 further divides the second half cycle into a third quarter cycle and a fourth quarter cycle. In the third quarter cycle, the time-sharing trigger signal 2 is a high-level signal, the MOS transistor Q1 in the signal synthesis circuit 120B is turned on, and the second control circuit 121 is turned off, and the signal to be synthesized 3 received by the source of the MOS transistor Q1 is output. In the fourth quarter cycle, the time-sharing trigger signal 2 is a low-level signal, the MOS transistor Q1 in the signal synthesis circuit 120B is turned off, the MOS transistor Q2 is turned off, and the MOS transistor Q3 is turned on, so that the second control circuit 121 is turned on, and then the signal to be synthesized 4 received by the source of the MOS transistor Q3 is output. Fig.10 FIG. 1 is one of the schematic diagrams of the composition of the pin multiplexing signal provided in an embodiment of the present invention, such as Fig.10As shown, the signal to be synthesized 1 and the signal to be synthesized 2 are synthesized into a time-division multiplexing signal 1 in the first half cycle, and the signal to be synthesized 3 and the signal to be synthesized 4 are synthesized into a time-division multiplexing signal 2 in the second half cycle. The time-division multiplexing signal 1 in the first half cycle and the time-division multiplexing signal 2 in the second half cycle are synthesized into a complete cycle of pin multiplexing signal.

[0095] For example, Fig.11 FIG. 2 is a second schematic diagram of the composition of the pin multiplexing signal provided in an embodiment of the present invention. Fig.11 As shown, if the signal to be synthesized 2 is an empty signal, the signal synthesis circuit 120A outputs the signal to be synthesized 1 in the first quarter cycle and outputs the empty signal in the second quarter cycle, and the signal to be synthesized 1 and the empty signal are synthesized into a time-division multiplexing signal 1 in the first half cycle. The signal synthesis circuit 120B outputs the signal to be synthesized 3 in the third quarter cycle and outputs the signal to be synthesized 4 in the fourth quarter cycle, and the signal to be synthesized 3 and the signal to be synthesized 4 are synthesized into a time-division multiplexing signal 2 in the second half cycle, and the time-division multiplexing signal 1 in the first half cycle and the time-division multiplexing signal 2 in the second half cycle are synthesized into a pin multiplexing signal of a complete cycle.

[0096] An embodiment of the present invention further provides an electronic device, comprising a CPLD chip and a pin multiplexing circuit as described in any one of the above items. After generating a pin multiplexing signal, the pin multiplexing circuit outputs it to the target pin of the CPLD chip, and the CPLD chip can accurately analyze the corresponding signal within the corresponding holding time. The CPLD chip can determine the start and end of a cycle through the rising edge signals of adjacent cycles.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pin multiplexing circuit, characterized in that: include: A time-sharing control circuit and at least one signal synthesis circuit, wherein: The at least one signal synthesis circuit is respectively connected to at least one output end of the time-sharing control circuit, and the output end of each signal synthesis circuit is connected to the target pin of the CPLD chip; The time-sharing control circuit is used to sequentially generate time-sharing trigger signals corresponding to each of the signal synthesis circuits; each of the signal synthesis circuits is used to synthesize the two received signals to be synthesized into a time-sharing multiplexed signal based on the time-sharing trigger signal; the time-sharing control circuit is also used to sequentially combine all the time-sharing multiplexed signals based on all the time-sharing trigger signals to obtain a pin multiplexing signal, and send the pin multiplexing signal to the target pin of the CPLD chip; In the case where the time-sharing control circuit includes at least two first switching control circuits and at least one second switching control circuit, the output end of the previous second switching control circuit is connected to the first power supply and the power supply end of the next second switching control circuit, the output end of the last second switching control circuit is connected to the first power supply and the power supply end of each of the first switching control circuits, and the output end of each of the first switching control circuits is connected to the first power supply and the first input end of the corresponding signal synthesis circuit; the previous second switching control circuit is used to generate a selection signal for the next second switching control circuit, and the selection signal is used to switch the working state of the next second switching control circuit or the working state of the next first switching control circuit; each of the first switching control circuits is used to generate a time-sharing trigger signal of the corresponding signal synthesis circuit based on the received selection signal.

2. The pin multiplexing circuit according to claim 1, characterized in that: When the number of paths of the signals to be synthesized is equal to two, the time-sharing control circuit is used to generate a time-sharing trigger signal corresponding to a complete cycle; the signal synthesis circuit is used to alternately output the two received signals to be synthesized based on the duty cycle of the time-sharing trigger signal, so as to synthesize the two signals to be synthesized into one time-sharing multiplexed signal; When the number of signals to be synthesized is greater than two, the time-sharing control circuit is used to segment the complete cycle and sequentially generate time-sharing trigger signals corresponding to each segment; whether each time-sharing trigger signal is received or not is used to control the working state of the corresponding signal synthesis circuit; each signal synthesis circuit is used to, when receiving a time-sharing trigger signal, alternately output the two received signals to be synthesized within the working period corresponding to the time-sharing trigger signal based on the duty cycle of the time-sharing trigger signal, so as to synthesize the two signals to be synthesized into one time-sharing multiplexed signal.

3. The pin multiplexing circuit according to claim 1, characterized in that: In the case where the time-sharing control circuit only includes the first switching control circuit, the output end of the first switching control circuit is respectively connected to the first power supply and the first input end of the signal synthesis circuit; the first switching control circuit is used to generate a time-sharing trigger signal corresponding to the signal synthesis circuit.

4. The pin multiplexing circuit according to claim 1 or 3, characterized in that: The first switching control circuit includes a voltage comparator, an RC circuit and a voltage divider circuit, wherein: The positive input terminal of the voltage comparator is connected to the first terminal of the voltage divider circuit, the negative input terminal of the voltage comparator is connected to the first terminal of the RC circuit, the output terminal of the voltage comparator is connected to the second terminal of the RC circuit, the third terminal of the voltage divider circuit and the first power supply, and the output terminal of the voltage comparator serves as the output terminal of the first switching control circuit, and the second terminal of the voltage divider circuit is connected to the first power supply; The voltage divider circuit is used to divide the output voltage of the first power supply to obtain a positive voltage divider that meets the target duty cycle; the RC circuit is used to generate a negative voltage; and the voltage comparator is used to generate the time-sharing trigger signal based on the comparison result between the negative voltage and the positive voltage divider.

5. The pin multiplexing circuit according to claim 4, characterized in that: The voltage divider circuit comprises a first voltage divider resistor, a second voltage divider resistor and a third voltage divider resistor, wherein: The first end of the first voltage-dividing resistor is connected to the first end of the second voltage-dividing resistor and the first end of the third voltage-dividing resistor, and is connected to the positive input end of the voltage comparator as the first end of the voltage-dividing circuit. The second end of the first voltage-dividing resistor is connected to the first power supply as the second end of the voltage-dividing circuit. The second end of the second voltage-dividing resistor is connected to the output end of the voltage comparator as the third end of the voltage-dividing circuit. The second end of the third voltage-dividing resistor is grounded.

6. The pin multiplexing circuit according to claim 1, characterized in that: The second switching control circuit includes a third switching control circuit and a switch circuit, wherein: The internal circuit structure of the third switching control circuit is the same as that of the first switching control circuit, the output end of the third switching control circuit is connected to the first input end of the switch circuit, the first output end of the switch circuit is connected to the power supply end of the first third switching control circuit of the next stage or the power supply end of the first first switching control circuit, the second output end of the switch circuit is connected to the power supply end of the second third switching control circuit of the next stage or the power supply end of the second first switching control circuit, and the first output end and the second output end of the switch circuit are both used as the output end of the second switching control circuit; The third switching control circuit is used to generate a switching control signal corresponding to the switching circuit; the first output end of the switching circuit is used to generate a first selection signal among the selection signals based on the switching control signal, and the second output end of the switching circuit is used to generate a second selection signal among the selection signals based on the switching control signal, and the first selection signal and the second selection signal have opposite polarities.

7. The pin multiplexing circuit according to claim 1 or 3, characterized in that: The signal synthesis circuit comprises a first control circuit and a second control circuit, wherein: The first end of the first control circuit is connected to the first end of the second control circuit, and both are used to receive the time-sharing trigger signal sent by the first switching control circuit, the second end of the first control circuit is used to receive the first signal to be synthesized, and the third end of the first control circuit is connected to the output end of the second control circuit and serves as the output end of the signal synthesis circuit; The second end of the second control circuit is used to receive the second signal to be synthesized, and the third end of the second control circuit is connected to the first power supply and serves as the fourth input end of the signal synthesis circuit; The first control circuit is used to output a first time-sharing signal corresponding to the first signal to be synthesized in the first period of the working cycle of the segment where the time-sharing trigger signal is located; the second control circuit is used to output a second time-sharing signal corresponding to the second signal to be synthesized in the second period of the working cycle of the segment where the time-sharing trigger signal is located; the first time-sharing signal and the second time-sharing signal are output alternately to obtain a time-sharing multiplexed signal; the sum of the first period and the second period is equal to the working period.

8. The pin multiplexing circuit according to claim 7, characterized in that: The second control circuit comprises a MOS tube (Q2), a MOS tube (Q3) and a pull-up resistor, wherein: The gate of the MOS tube (Q2) serves as the first end of the second control circuit, the source of the MOS tube (Q2) is grounded, the drain of the MOS tube (Q2) is connected to the first end of the pull-up resistor and the gate of the MOS tube (Q3), and the second end of the pull-up resistor serves as the third end of the second control circuit; the source of the MOS tube (Q3) serves as the second end of the second control circuit, and the drain of the MOS tube (Q3) serves as the output end of the second control circuit; The time-sharing trigger signal is also used to control the on-off state of the MOS tube (Q2), and the drain of the MOS tube (Q2) is used to output a first square wave signal generated based on the time-sharing trigger signal; the first square wave signal is used to control the on-off state of the MOS tube (Q3), and the drain of the MOS tube (Q3) is used to output a second time-sharing signal generated based on the on-off state of the MOS tube (Q3) and the second signal to be synthesized.

9. An electronic device comprising a CPLD chip and the pin multiplexing circuit according to any one of claims 1 to 8.

Images