System suitable for receiver to realize ultra-large bandwidth real-time storage playback

Abstract

The invention relates to a system suitable for a receiver to realize ultra-large bandwidth real-time storage and playback, which comprises a down-conversion unit, an up-conversion unit, an ADC (Analog to Digital Converter) unit, a DAC (Digital to Analog Converter) unit, a reference clock unit, a local oscillator unit, an FPGA (Field Programmable Gate Array) signal processing unit, a main control unit and a storage unit, the output end of the local oscillator unit is respectively connected with the down-conversion unit and the up-conversion unit, the output end of the down-conversion unit is connected with the ADC unit, the ADC unit is connected with the FPGA signal processing unit, the DAC unit is connected with the FPGA signal processing unit, the output end of the DAC unit is also connected with the up-conversion unit, and the main control unit is connected with the FPGA signal processing unit. According to the system suitable for the receiver to realize the ultra-large bandwidth real-time storage playback, the ADC with the high sampling rate is adopted, and the system bandwidth can reach 500MHz. The PCIe4.0 high-capacity disk array is adopted, the read-write rate is larger than 6.25 GB / S, and the method has a wide application range.

Description

Technical Field

[0001] The present invention relates to the field of receivers, in particular to the field of ultra-large bandwidth real-time storage and playback of receivers, and specifically refers to a system suitable for realizing ultra-large bandwidth real-time storage and playback of receivers. Background Art

[0002] The ultra-large bandwidth acquisition and playback system can be used in complex electromagnetic environments to record and simulate real electromagnetic environments, and can be widely used in military and civilian fields.

[0003] The ultra-large bandwidth real-time storage and playback system suitable for the receiver proposed in the present invention has an acquisition and playback bandwidth of up to 500MHz. A high-speed communication interface and DMA technology are used in the link to ensure that the data transmission rate meets the system requirements. At the same time, the system is equipped with a large-capacity SSD disk array to solve the problem of insufficient storage space. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a system which is easy to operate, has a high data transmission rate and a wide range of applications and is suitable for receivers to realize ultra-large bandwidth real-time storage and playback.

[0005] In order to achieve the above object, the system of the present invention applicable to a receiver for realizing ultra-large bandwidth real-time storage and playback is as follows:

[0006] The system is suitable for a receiver to realize ultra-large bandwidth real-time storage and playback. Its main characteristics are that the system comprises a down-conversion unit, an up-conversion unit, an ADC unit, a DAC unit, a reference clock unit, a local oscillator unit, an FPGA signal processing unit, a main control unit and a storage unit. The output end of the reference clock unit is respectively connected to the local oscillator unit and the FPGA signal processing unit, the output end of the local oscillator unit is respectively connected to the down-conversion unit and the up-conversion unit, the output end of the down-conversion unit is connected to the ADC unit, the ADC unit is connected to the FPGA signal processing unit, the DAC unit is connected to the FPGA signal processing unit, the output end of the DAC unit is also connected to the up-conversion unit, the main control unit is connected to the FPGA signal processing unit, and the storage unit is connected to the main control unit; the reference clock unit provides a 122.88MHz reference clock to the FPGA unit and the local oscillator unit through a power divider; the down-conversion unit, the ADC unit, the FPGA unit, the main control unit and the storage unit constitute a collection part circuit, and the up-conversion unit, the DAC unit, the FPGA unit, the main control unit and the storage unit constitute a playback part circuit.

[0007] Preferably, the down-conversion unit allows the RF signal to pass through a limiting detection circuit to limit and detect the RF signal power, and after passing through a set of gain adjustment circuits and preliminary signal processing, signals of different frequency bands enter the direct path and the mixing path respectively through the RF switch; the direct path signal directly enters the post-stage ADC input interface after filtering and amplification; the mixing path signal is sent to the mixer for down-conversion after filtering.

[0008] Preferably, the up-conversion unit allows the intermediate frequency signal to enter the mixer and mix with the local oscillator to generate a mixed signal.

[0009] Preferably, the reference clock unit uses a 10 MHz constant temperature crystal oscillator as a clock source, generates a high-precision 122.88 MHz reference clock through a phase-locked loop, and generates a 1.2288 GHz ADC sampling clock after 10 times the frequency.

[0010] Preferably, the local oscillator unit uses 122.88 MHz as a reference clock to generate an adjustable local oscillator clock.

[0011] Preferably, the FPGA signal processing unit transmits data with the ADC unit and the DAC unit via a JESD204B interface, and processes the digital signal at the same time.

[0012] Preferably, the acquisition circuit includes the following processing steps:

[0013] The RF down-conversion unit performs frequency conversion processing on the RF signal to obtain an intermediate frequency signal with an intermediate frequency point of 307.2 MHz and a bandwidth of 500 MHz;

[0014] The FPGA signal processing unit receives the quantized data from the ADC unit for digital processing, and the processed data is transmitted to the main control unit through the PCIe4.0 interface;

[0015] The main control unit uses DMA technology to store downstream data to the SSD disk array.

[0016] Preferably, the playback circuit includes the following processing steps:

[0017] The main control unit reads the IQ data in the disk array and transmits it to the FPGA signal processing unit through DMA technology;

[0018] The FPGA signal processing unit performs digital signal processing on the IQ data and transmits it to the DAC unit through the JESD204B interface;

[0019] The DAC unit performs digital-to-analog conversion to generate an intermediate frequency signal;

[0020] The up-conversion unit up-converts the intermediate frequency signal to generate a radio frequency signal.

[0021] The system for realizing ultra-large bandwidth real-time storage and playback in a receiver of the present invention adopts a high sampling rate ADC, and the system bandwidth can reach 500MHz. The present invention adopts a PCIe4.0 communication interface and DMA transmission technology, and the real-time transmission rate is greater than 6.25GB / S. The present invention adopts a PCIe4.0 large-capacity disk array, and the read and write rate is greater than 6.25GB / S, which has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The present invention is a schematic diagram of the structure of a system suitable for a receiver to implement ultra-large bandwidth real-time storage and playback.

[0023] Figure 2 The present invention is a schematic diagram of DMA transmission of a system suitable for a receiver to implement ultra-large bandwidth real-time storage and playback. DETAILED DESCRIPTION

[0024] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0025] The system for realizing ultra-large bandwidth real-time storage and playback in a receiver of the present invention comprises a down-conversion unit, an up-conversion unit, an ADC unit, a DAC unit, a reference clock unit, a local oscillator unit, an FPGA signal processing unit, a main control unit and a storage unit. The output end of the reference clock unit is respectively connected to the local oscillator unit and the FPGA signal processing unit, the output end of the local oscillator unit is respectively connected to the down-conversion unit and the up-conversion unit, the output end of the down-conversion unit is connected to the ADC unit, the ADC unit is connected to the FPGA signal processing unit, the DAC unit is connected to the FPGA signal processing unit, the output end of the DAC unit is also connected to the up-conversion unit, the main control unit is connected to the FPGA signal processing unit, and the storage unit is connected to the main control unit; the reference clock unit provides a 122.88MHz reference clock to the FPGA unit and the local oscillator unit through a power divider; the down-conversion unit, the ADC unit, the FPGA unit, the main control unit and the storage unit constitute a collection circuit, and the up-conversion unit, the DAC unit, the FPGA unit, the main control unit and the storage unit constitute a playback circuit.

[0026] As a preferred embodiment of the present invention, the down-conversion unit allows the RF signal to pass through a limiting detection circuit to limit and detect the RF signal power, and after passing through a group of gain adjustment circuits and preliminary signal processing, signals of different frequency bands enter the direct path and the mixing path respectively through the RF switch; the direct path signal directly enters the post-stage ADC input interface after filtering and amplification; the mixing path signal is sent to the mixer for down-conversion after filtering.

[0027] As a preferred implementation mode of the present invention, the up-conversion unit allows the intermediate frequency signal to enter the mixer and mix with the local oscillator to generate a mixed signal.

[0028] As a preferred embodiment of the present invention, the reference clock unit uses a 10MHz constant temperature crystal oscillator as a clock source, generates a high-precision 122.88MHz reference clock through a phase-locked loop, and generates a 1.2288GHz ADC sampling clock after 10 times the frequency.

[0029] As a preferred embodiment of the present invention, the local oscillator unit uses 122.88 MHz as a reference clock to generate an adjustable local oscillator clock.

[0030] As a preferred embodiment of the present invention, the FPGA signal processing unit transmits data with the ADC unit and the DAC unit through the JESD204B interface, and processes the digital signal at the same time.

[0031] As a preferred embodiment of the present invention, the acquisition circuit includes the following processing steps:

[0032] The RF down-conversion unit performs frequency conversion processing on the RF signal to obtain an intermediate frequency signal with an intermediate frequency point of 307.2 MHz and a bandwidth of 500 MHz;

[0033] The FPGA signal processing unit receives the quantized data from the ADC unit for digital processing, and the processed data is transmitted to the main control unit through the PCIe4.0 interface;

[0034] The main control unit uses DMA technology to store downstream data to the SSD disk array.

[0035] As a preferred embodiment of the present invention, the playback circuit includes the following processing steps:

[0036] The main control unit reads the IQ data in the disk array and transmits it to the FPGA signal processing unit through DMA technology;

[0037] The FPGA signal processing unit performs digital signal processing on the IQ data and transmits it to the DAC unit through the JESD204B interface;

[0038] The DAC unit performs digital-to-analog conversion to generate an intermediate frequency signal;

[0039] The up-conversion unit up-converts the intermediate frequency signal to generate a radio frequency signal.

[0040] In the specific implementation of the present invention, it is applicable to an ultra-large bandwidth real-time storage and playback system, and its acquisition and playback bandwidth can reach 500MHz. The functional structure of the solution is as follows Figure 2As shown, it consists of two parts: acquisition and playback.

[0041] The acquisition part includes RF down-conversion unit, ADC unit, FPGA unit, main control unit, and storage unit. The ADC sampling rate is 1.2288GHz, and the system frequency point is 307.2MHz, which ensures that the system bandwidth is 500MHz. The ADC and FPGA interface is 4xJESD204B, and its single lane maximum rate can reach 12.5Gbps, ensuring that the ADC quantized data is transmitted to the FPGA in real time. The FPGA unit performs digital processing on the quantized data. The FPGA and the main control unit use the PCIe Gen4 x4 interface to communicate, and its maximum transmission rate can reach 7.877GB / S, which meets the 6.25GB / S transmission rate required for real-time transmission of the system. At the same time, DMA technology is used for memory access control to reduce the CPU burden and further improve the transmission rate. The storage unit uses PCIe4.0 SSD disk array to increase the storage space while meeting the transmission rate requirements. The reference clock unit provides the 122.88MHz reference clock to the FPGA unit and the local oscillator unit through the power divider to achieve the required clock tree design.

[0042] The playback part includes RF up-conversion unit, DAC unit, FPGA unit, main control unit and storage unit. Similarly, the main control unit reads data from the PCIe4.0 SSD hard disk array through DMA technology based on PCIe4.0 bus, and its reading speed can reach 7200MB / S. After digital processing by FPGA, it is transmitted to DAC through JESD204B interface for digital-to-analog conversion, where the frequency point is 307.2MHz and the bandwidth is 500MHz. The intermediate frequency signal is converted into RF signal through digital up-conversion.

[0043] The different functional units are further described below:

[0044] RF down-conversion unit: The RF down-conversion unit is a superheterodyne mixer topology with a frequency of 307.2MHz. The RF signal first passes through a limiter detection circuit to limit and detect the RF signal power, and then passes through a set of gain adjustment circuits, including attenuation, pass-through, and amplification circuits. The attenuation circuit is used by default. After the signal is initially processed, signals of different frequency bands enter the pass-through path and the mixing path respectively through the RF switch. The pass-through path signal is filtered and amplified and directly enters the input interface of the post-stage ADC. The mixing path signal is filtered and sent to the mixer for down-conversion.

[0045] RF up-conversion unit: RF up-conversion adopts superheterodyne mixing topology. The intermediate frequency signal enters the mixer and mixes with the local oscillator to generate a mixed signal. The mixed signal passes through the amplitude control unit to ensure the power dynamic range, power step and power accuracy of the output signal.

[0046] ADC unit: The ADC sampling rate is 1.2288 GHz, its communication interface is 4x JESD204B, and the single lane transmission rate can reach up to 12.5 Gbps.

[0047] DAC unit: The DAC conversion bit width is 16 bits, supports 12.6Gsps RF output, and supports multiple interpolation functions.

[0048] Reference clock unit: The reference unit uses a high-precision 10MHz constant temperature crystal oscillator as the clock source, generates a high-precision 122.88MHz reference clock through a phase-locked loop, and generates a 1.2288GHz ADC sampling clock after 10 times the frequency.

[0049] Local oscillator unit: uses 122.88MHz as the reference clock to generate an adjustable local oscillator clock.

[0050] FPGA signal processing unit: Data is transmitted between the ADC unit and the DAC unit through the JESD204B interface, and digital signals are processed at the same time. PCIe4.0 and DDR4 communication interfaces are established for high-speed data transmission.

[0051] Main control unit: It adopts high-performance HPC, has rich scalability, and can achieve high-speed and large-capacity data transmission.

[0052] Storage unit: The storage unit is a PCIe4.0 interface disk array with a capacity of up to 8TB and a transmission rate of up to 7.877GB / S.

[0053] Acquisition part signal processing flow:

[0054] The RF down-conversion unit performs frequency conversion processing on the RF signal to obtain an intermediate frequency signal with an intermediate frequency point of 307.2 MHz and a bandwidth of 500 MHz;

[0055] The ADC sampling rate can reach 1.2288GHz, ensuring a system bandwidth of 500MHz; the ADC and FPGA use a 4xJESD204B interface, and the single lane rate can reach 12.5Gbps, meeting the system transmission rate requirements;

[0056] The FPGA receives the ADC quantized data and performs digital processing, and the processed data is transmitted to the main control unit through the PCIe4.0 interface;

[0057] The main control unit uses DMA technology to store downstream data to the SSD disk array.

[0058] Playback part of the signal processing flow:

[0059] The main control unit reads the IQ data in the disk array and transmits it to the FPGA through DMA technology;

[0060] The FPGA performs digital signal processing on the IQ data and transmits it to the high-speed DAC via the JESD204B interface;

[0061] High-speed DAC performs digital-to-analog conversion to generate intermediate frequency signals;

[0062] The radio frequency up-conversion unit up-converts the intermediate frequency signal to generate a radio frequency signal.

[0063] For the acquisition part, the RF down-conversion unit mixes the RF signal and converts it to a fixed frequency of 307.2MHz; the ADC sampling rate can reach 1.2288GHz, ensuring the system bandwidth of 500MHz; the ADC and FPGA use a 4x JESD204B interface, and the single lane rate can reach 12.5Gbps, meeting the system transmission rate requirements; the FPGA and the main control unit use a PCIe-based DMA data transmission solution, the FPGA sends the data into the FIFO buffer, the DMA reads the data from the FIFO and transmits it to the PCIe interface inside the FPGA, and the data is sent to the host computer through the PCIe 3.0x16 bus interface. Using high-performance FPGA chips, the maximum data transmission rate will reach 6.6GB / S, meeting the transmission bandwidth required by the system; the FPGA side uses DMA for data transmission, and the PC side needs to install the corresponding driver to cooperate with the FPGA to realize data transmission. The driver provides a device file interface that can be easily accessed using any programming language. The user program can call the device file to interact with the device driver through file I / O, and the device driver moves data through the bus.

[0064] For the playback part, the main control unit reads the IQ data in the disk array and transmits it to the FPGA through DMA technology, which can achieve a maximum transmission rate of 6.6GB / S; the FPGA performs digital signal processing on the IQ data and transmits it to the high-speed DAC through the JESD204B interface; the high-speed ADC performs digital-to-analog conversion on the baseband signal to produce an analog intermediate frequency signal; the intermediate frequency signal is mixed with the local oscillator signal through the RF up-conversion unit to generate an RF signal.

[0065] The innovation of the technical solution of the present invention lies in using a high-speed PCIe transmission interface to process a 500MHz large bandwidth signal. The present invention mentions a DMA processing technology to reduce the workload of the PC end and improve the data stream reading and writing speed.

[0066] With reference to the above process description and illustration, the present invention is fully described.

[0067] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0068] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0069] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0070] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0071] The system for realizing ultra-large bandwidth real-time storage and playback in a receiver of the present invention adopts a high sampling rate ADC, and the system bandwidth can reach 500MHz. The present invention adopts a PCIe4.0 communication interface and DMA transmission technology, and the real-time transmission rate is greater than 6.25GB / S. The present invention adopts a PCIe4.0 large-capacity disk array, and the read and write rate is greater than 6.25GB / S, which has a wide range of applications.

[0072] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system suitable for a receiver to implement ultra-large bandwidth real-time storage and playback, characterized in that: The system comprises a down-conversion unit, an up-conversion unit, an ADC unit, a DAC unit, a reference clock unit, a local oscillator unit, an FPGA signal processing unit, a main control unit and a storage unit. The output end of the reference clock unit is respectively connected to the local oscillator unit and the FPGA signal processing unit, the output end of the local oscillator unit is respectively connected to the down-conversion unit and the up-conversion unit, the output end of the down-conversion unit is connected to the ADC unit, the ADC unit is connected to the FPGA signal processing unit, the DAC unit is connected to the FPGA signal processing unit, the output end of the DAC unit is also connected to the up-conversion unit, the main control unit is connected to the FPGA signal processing unit, and the storage unit is connected to the main control unit; the reference clock unit provides a 122.88MHz reference clock to the FPGA unit and the local oscillator unit through a power divider; the down-conversion unit, the ADC unit, the FPGA unit, the main control unit and the storage unit constitute a collection circuit, and the up-conversion unit, the DAC unit, the FPGA unit, the main control unit and the storage unit constitute a playback circuit.

2. The system for realizing ultra-large bandwidth real-time storage and playback for a receiver according to claim 1, characterized in that: The down-conversion unit allows the radio frequency signal to pass through a limiting detection circuit to limit and detect the radio frequency signal power, and after a set of gain adjustment circuits and preliminary signal processing, signals of different frequency bands enter the direct path and the mixing path respectively through the radio frequency switch; The through-path signal is filtered and amplified before entering the input interface of the subsequent ADC. The signal in the mixing path is filtered and then sent to the mixer for down-conversion.

3. The system for realizing ultra-large bandwidth real-time storage and playback for a receiver according to claim 1, characterized in that: The up-conversion unit allows the intermediate frequency signal to enter the mixer and mix with the local oscillator to generate a mixed signal.

4. The system for implementing ultra-large bandwidth real-time storage and playback in a receiver according to claim 1, characterized in that: The reference clock unit uses a 10MHz constant temperature crystal oscillator as a clock source, generates a high-precision 122.88MHz reference clock through a phase-locked loop, and generates a 1.2288GHz ADC sampling clock after 10 times the frequency.

5. The system for implementing ultra-large bandwidth real-time storage and playback in a receiver according to claim 1, characterized in that: The local oscillator unit uses 122.88 MHz as a reference clock to generate an adjustable local oscillator clock.

6. The system for implementing ultra-large bandwidth real-time storage and playback in a receiver according to claim 1, characterized in that: The FPGA signal processing unit transmits data with the ADC unit and the DAC unit via the JESD204B interface, and processes the digital signal at the same time.

7. The system for implementing ultra-large bandwidth real-time storage and playback in a receiver according to claim 1, characterized in that: The acquisition circuit includes the following processing steps: The RF down-conversion unit performs frequency conversion processing on the RF signal to obtain an intermediate frequency signal with an intermediate frequency point of 307.2 MHz and a bandwidth of 500 MHz; The FPGA signal processing unit receives the quantized data from the ADC unit for digital processing, and the processed data is transmitted to the main control unit through the PCIe4.0 interface; The main control unit uses DMA technology to store downstream data to the SSD disk array.

8. The system for implementing ultra-large bandwidth real-time storage and playback in a receiver according to claim 1, characterized in that: The playback circuit includes the following processing steps: The main control unit reads the IQ data in the disk array and transmits it to the FPGA signal processing unit through DMA technology; The FPGA signal processing unit performs digital signal processing on the IQ data and transmits it to the DAC unit through the JESD204B interface; The DAC unit performs digital-to-analog conversion to generate an intermediate frequency signal; The up-conversion unit up-converts the intermediate frequency signal to generate a radio frequency signal.

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