Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a substrate; forming a first photoresist layer with a storage gate pattern on the substrate; etching the substrate to form a plurality of discrete openings using the first photoresist layer as a mask; forming a storage gate in the openings, a top surface of the storage gate being flush with a top surface of the substrate; forming a select gate layer on the substrate surface and the storage gate surface; forming a second photoresist layer with a select gate pattern on the select gate layer; etching the select gate layer to form a plurality of discrete select gates using the second photoresist layer as a mask. By forming the openings in the substrate and the storage gates in the openings, the storage gates are located in the substrate, and then the select gates are formed on the substrate, so that the select gates and the storage gates have no overlapping area in a projection direction parallel to the substrate, i.e. the select gates and the storage gates have no electrical contact in a pressing process, thereby avoiding crosstalk effect between the storage gates and the select gates, and improving the performance of the memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] A memory cell of a SONOS device is usually composed of a SONOS memory transistor (referred to as memory transistor) and a high-voltage selection transistor (referred to as selection transistor). The memory transistor is used to store data, and the selection transistor is used to complete the selection of data address. Both the two transistors are in the same well region.

[0003] However, in the existing SONOS device, when a memory cell is operated, the word line BL of the memory cell is selected, and the selection gate (SG) of the row is selected by applying voltage, which induces the adjacent memory gate (MG). Similarly, when the memory gate (MG) of the row is selected by applying voltage, the adjacent selection gate (SG) is also induced, resulting in crosstalk effect between the memory gate and the selection gate, which affects the performance of the memory. SUMMARY

[0004] The technical problem solved by the present application is how to improve the performance of the memory.

[0005] To solve the above technical problem, the present application provides a forming method of a semiconductor structure, comprising: providing a substrate; forming a first photoresist layer with a memory gate pattern on the substrate; etching the substrate to form a plurality of discrete openings by taking the first photoresist layer as a mask; forming a memory gate in the openings, the top surface of the memory gate being flush with the top surface of the substrate; forming a selection gate layer on the surface of the substrate and the surface of the memory gate; forming a second photoresist layer with a selection gate pattern on the selection gate layer; etching the selection gate layer to form a plurality of discrete selection gates by taking the second photoresist layer as a mask.

[0006] Optionally, the process of forming the plurality of discrete openings is a dry etching process, and the process parameters of the dry etching process are that the etching gas is one or more of H2, CF4, CHF3, CH2F2, C4F8, and Ar, the flow rate of the etching gas is 30-80 sccm, the source power is 800-1200 W, the bias power is 100-400 W, the etching pressure is 10-50 mTorr, and the etching time is 30-70 s; and the process parameters of etching the substrate are that the pressure of the chamber is 5-15 mT, the source power is 350-1200 W, the bias voltage is 150-600 V, the gas flow rate is 20-200 sccm, and the etching time is 8-60 s.

[0007] Optionally, the method of forming the semiconductor structure further comprises: before the step of forming the select gate layer, forming a storage gate dielectric layer on the opening surface and the substrate surface; and after the step of forming the storage gate, etching and removing the storage gate dielectric layer on the substrate surface to expose the substrate surface, thereby forming a dielectric layer.

[0008] Optionally, the step of forming the storage gate dielectric layer comprises: forming a charge tunneling layer on the opening surface and the substrate surface; forming a charge trapping layer on the surface of the charge tunneling layer; and forming a charge blocking layer on the surface of the charge trapping layer.

[0009] Optionally, the method of forming the semiconductor structure further comprises: before the step of forming the select gate layer, forming a gate oxide layer on the substrate and the storage gate; and after the step of forming the select gate, forming a sidewall on the sidewall of the select gate.

[0010] Optionally, the step of forming the sidewall on the sidewall of the select gate comprises: forming a first silicon oxide layer on the sidewall of the select gate; forming a silicon nitride layer on the surface of the first silicon oxide layer; and forming a second silicon oxide layer on the surface of the silicon nitride layer.

[0011] Optionally, after the step of forming the plurality of discrete select gates, the method further comprises: performing ion implantation on the substrate between the select gates and the storage gate to form source / drain regions.

[0012] Optionally, after the step of forming the source / drain regions, the method further comprises: forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the source / drain regions, the storage gate, and the select gates; and etching the interlayer dielectric layer and the gate oxide layer in sequence to expose the top of the storage gate, the top of the select gate, and the top of the source / drain regions, thereby forming contact holes.

[0013] Optionally, after the step of forming the contact hole, the method further comprises: depositing a metal layer on a bottom surface of the contact hole; and performing an annealing process to react the metal layer with a top surface of the source / drain region, a top surface of the storage gate, and a top surface of the select gate to form a metal silicide layer.

[0014] Accordingly, the present application also provides a semiconductor structure, comprising: a substrate; a plurality of openings separately located in the substrate; a storage gate located in the openings, and a top surface of the storage gate being flush with a top surface of the substrate; and a plurality of select gates separately located on the substrate, the select gates being adjacent to the storage gate in a projection direction perpendicular to the substrate.

[0015] Optionally, the semiconductor structure further comprises: a dielectric layer located on a surface of the openings, the dielectric layer comprising a charge tunneling layer, a charge trapping layer located on a surface of the charge tunneling layer, and a charge blocking layer located on a surface of the charge trapping layer.

[0016] Optionally, the semiconductor structure further comprises: a gate oxide layer located on a bottom surface of the select gate, and a sidewall located on a sidewall surface of the select gate, the sidewall comprising a first silicon oxide layer, a silicon nitride layer located on a surface of the first silicon oxide layer, and a second silicon oxide layer located on a surface of the silicon nitride layer.

[0017] Optionally, the semiconductor structure further comprises: a source / drain region located in the substrate between the select gate and the storage gate.

[0018] Optionally, the semiconductor structure further comprises: a metal silicide layer located on a top surface of the source / drain region, a top surface of the storage gate, and a top surface of the select gate, an interlayer dielectric layer located on the substrate, and a contact hole located in the interlayer dielectric layer.

[0019] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0020] The application forms an opening in a substrate, forms a memory gate in the opening, so that the memory gate is located in the substrate, and then forms a select gate on the substrate, so that the select gate and the memory gate have no overlapping area in the projection direction parallel to the substrate, that is, the select gate and the memory gate have no electrical contact in the pressing process, so as to avoid the crosstalk effect between the memory gate and the select gate, and improve the performance of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a structural schematic diagram of a semiconductor structure;

[0022] Figures 2 to 16 is a schematic diagram of the forming process of the semiconductor structure in an embodiment of the application. DETAILED DESCRIPTION

[0023] It should be noted that the "surface", "upper", in the specification are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0024] Please refer to Figure 1 At present, in the SONOS device, when a memory cell is operated, the word line BL of the memory cell is selected, and the select gate 101 (select gate, SG for short) of the row is selected by pressing, at this time, the adjacent memory gate 102 (memory gate, MG for short) is induced, and the same, when the memory gate 102 (memory gate, MG for short) of the row is selected by pressing, the adjacent select gate 101 (select gate, SG for short) is also induced, resulting in the crosstalk effect between the memory gate 102 and the select gate 101, which affects the performance of the memory.

[0025] In addition, since the memory gate and the select gate are both located on the substrate, the channel length between the source and the drain is the horizontal distance between the source and the drain, if the carrier channel length is to be lengthened, that is, the distance between the source and the drain is to be increased, and then the storage unit area is increased.

[0026] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure and a forming method thereof, wherein a buried storage gate is formed in a substrate, a selection gate is formed on the surface of the substrate, and the selection gate and the storage gate have no overlapping area in the projection direction parallel to the substrate, i.e., the selection gate and the storage gate have no electrical contact during the pressing process, so that the crosstalk effect between the storage gate and the selection gate is avoided, and the performance of the memory is improved.

[0027] To make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0028] Please refer to Figure 2 , a substrate 200 is provided; an isolation region 201 is formed in the substrate 200; and a protective layer 202 is formed on the surface of the substrate 200.

[0029] In the embodiment, the material of the substrate 200 is silicon.

[0030] In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0031] The method for forming the isolation region 201 includes etching the substrate 200 to form a shallow trench, and forming the isolation region 201 in the shallow trench.

[0032] In the embodiment, the material of the isolation region 201 is silicon oxide.

[0033] In the embodiment, the shape of the isolation region 201 is an inverted trapezoid.

[0034] The isolation region 201 is used to avoid electrical crosstalk between adjacent active devices.

[0035] In the embodiment, the method further includes removing the isolation region 201 higher than the surface of the substrate 200 by planarization processing.

[0036] In the embodiment, the planarization processing adopts a chemical mechanical polishing process.

[0037] In the embodiment, by adjusting the process parameters of the chemical mechanical polishing, the isolation region 201 higher than the surface of the substrate 200 can be removed and stopped at the surface flush with the substrate 200 in the polishing process.

[0038] In other embodiments, the thickness of the isolation region 201 higher than the surface of the substrate 200 is 0 angstrom to 80 angstrom.

[0039] In the embodiment, the material of the protective layer 202 is silicon oxide or silicon oxynitride.

[0040] In the embodiment, the thickness of the protective layer 202 ranges from 30 angstroms to 50 angstroms.

[0041] In some embodiments, the protective layer 202 is a single layer or a multi-layer stack.

[0042] When the protective layer 202 is a single layer, the material of the protective layer 202 is silicon nitride.

[0043] When the protective layer 202 is a multi-layer stack, the material of the protective layer 202 is a combination of one or more of silicon nitride, silicon oxide, and carbon-rich silicon nitride.

[0044] The protective layer 202 is used to protect the surface of the substrate 200 from damage during the subsequent process of forming the openings 203.

[0045] As can be seen, by forming the protective layer 202 on the substrate 200, the substrate 200 is protected from damage during the subsequent etching process of forming the openings 203, thereby ensuring the integrity of the substrate 200.

[0046] Please refer to Figure 3 A first photoresist layer having a pattern of storage gates 205 is formed on the substrate 200; and the substrate 200 is etched using the first photoresist layer as a mask to form a plurality of discrete openings 203.

[0047] In the embodiment, the process of forming the plurality of discrete openings 203 is a dry etching process, and the process parameters of the dry etching process are as follows: the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8, and Ar, the gas flow rate of the etching gas is 30-80 sccm, the source power is 800-1200 W, the bias power is 100-400 W, the etching pressure is 10-50 mTorr, and the etching time is 30-70 seconds; and the process parameters of etching the substrate 200 are as follows: the pressure in the chamber is 5-15 mT, the source power is 350-1200 W, the bias voltage is 150-600 V, the gas flow rate is 20-200 sccm, and the etching time is 8-60 seconds.

[0048] Please refer to Figure 4 A storage gate 205 dielectric layer is formed on the surface of the openings 203 and the surface of the substrate 200

[0049] The step of forming the storage gate dielectric layer includes: forming a charge tunneling layer (not shown in the figure) on the surface of the opening 203 and the surface of the substrate 200; forming a charge trapping layer (not shown in the figure) on the surface of the charge tunneling layer; and forming a charge blocking layer (not shown in the figure) on the surface of the charge trapping layer.

[0050] In the embodiment, the storage gate dielectric layer is in an "ONO" structure, i.e., a "sandwich structure" formed by silicon oxide, silicon nitride and silicon oxide.

[0051] Please refer to Figure 5 The storage gate layer 2051 is formed in the opening 203 and on the surface of the substrate 200.

[0052] In the embodiment, the material of the storage gate layer 2051 is single crystal silicon or polycrystalline silicon.

[0053] Please refer to Figure 6 The storage gate layer 2051 is subjected to a planarization process to form a storage gate 205, and the top surface of the storage gate 205 is flush with the top surface of the substrate 200.

[0054] After the storage gate 205 is formed, the storage gate dielectric layer on the surface of the substrate 200 is etched to expose the surface of the substrate 200, thereby forming a dielectric layer 204.

[0055] In the embodiment, after the storage gate 205 is formed, the method further includes: forming a gate oxide layer 206 on the substrate 200 and on the storage gate 205.

[0056] In the above scheme, the storage gate 205 is located in the substrate 200, so that the distance of the channel between the source and the drain is increased from the horizontal distance to the sum of the length of the storage gate 205 in the substrate 200 and the width of the select gate 207, so that the carrier channel length is lengthened without changing the distance between the source and the drain in the horizontal direction, thereby reducing the storage cell area and improving the performance of the memory.

[0057] Please refer to Figure 7 The select gate layer 2071 is formed on the surface of the gate oxide layer 206.

[0058] In the embodiment, the material of the gate oxide layer 206 is silicon oxide.

[0059] Please refer to Figure 8 A second photoresist layer with a select gate 207 pattern is formed on the select gate layer 2071; and the select gate layer 2071 is etched to form a plurality of discrete select gates 207 by taking the second photoresist layer as a mask.

[0060] In the above scheme, an opening 203 is formed in the substrate 200, and a storage gate 205 is formed in the opening 203, so that the storage gate 205 is located in the substrate 200, and then a select gate 207 is formed on the substrate 200, so that the select gate 207 and the storage gate 205 have no overlapping area in the projection direction parallel to the substrate 200, that is, the select gate 207 and the storage gate 205 have no electrical contact during the pressurization process, thereby avoiding the crosstalk effect between the storage gate 205 and the select gate 207, and improving the performance of the memory.

[0061] Please refer to Figure 9 After the step of forming the select gate 207 , a spacer 2072 is formed on the sidewall of the select gate 207 .

[0062] The step of forming the sidewall spacer 2072 on the sidewall of the select gate 207 includes: forming a first silicon oxide layer on the sidewall of the select gate 207; forming a silicon nitride layer on the surface of the first silicon oxide layer; and forming a second silicon oxide layer on the surface of the silicon nitride layer.

[0063] Please refer to Figure 10 , an interlayer dielectric layer 2073 is formed on the substrate 200 , and the interlayer dielectric layer 2073 covers the source / drain regions 2074 , the storage gate 205 and the select gate 207 .

[0064] After the step of forming a plurality of discrete selection gates 207 , the method further includes: performing ion implantation on the substrate 200 between the selection gates 207 and the storage gates 205 to form source / drain regions 2074 .

[0065] Please refer to Figure 11 as well as Figure 12 , Figure 11 It is a top view. Figure 11 Only the substrate 200, the storage gate 205 and the select gate 207 are shown. Figure 12 It is along Figure 11 In the cross-sectional view along the AA1 direction, the interlayer dielectric layer 2073 and the gate oxide layer 206 are sequentially etched until the top of the source / drain region 2074 is exposed, thereby forming a first contact hole (not shown in the figure).

[0066] After the step of forming the first contact hole, it also includes: depositing a first metal layer (not shown in the figure) on the bottom surface of the first contact hole; performing an annealing process to allow the first metal layer to react with the top surface of the source / drain region 2074 to form a first metal silicide layer 2081.

[0067] The process of etching the interlayer dielectric layer 2073 is dry etching, and the process parameters of the dry etching include: the pressure of the chamber is 20 mT to 100 mT, the source power is 500 W to 2800 W, the bias power is 30 W to 2800 W, the gas flow is 20 sccm to 200 sccm, and the etching time is 8 s to 20 s.

[0068] After the step of forming the first contact hole, the method further includes: forming a first metal layer (not shown in the figure) at the bottom of the first contact hole; and performing an annealing process to react the first metal layer with the top surface of the source / drain region 2074 to form a first metal silicide layer 2081.

[0069] After forming the first metal silicide layer 2081, the method further includes: filling the first contact hole with a conductive material to form a first conductive plug 208.

[0070] In this embodiment, the first conductive plug 208 is formed by a chemical vapor deposition process or a physical vapor deposition process.

[0071] In this embodiment, the material of the first conductive plug 208 is copper, aluminum, or tungsten.

[0072] In this embodiment, the method of forming the first metal layer is a chemical vapor deposition process, the material of the first metal layer is nickel-platinum alloy, titanium, or cobalt, and the thickness of the first metal layer ranges from 80 angstroms to 130 angstroms.

[0073] In this embodiment, the step of performing an annealing process includes: performing a first sub-annealing process on the first metal layer and the top surface of part of the source / drain region 2074 to react the first metal layer with the top surface of part of the source / drain region 2074 to form a high-resistance metal silicide layer (not shown in the figure); and performing a second sub-annealing process on the high-resistance metal silicide layer to cause phase transition reaction of the high-resistance metal silicide layer to form the first metal silicide layer 2081.

[0074] In this embodiment, the first sub-annealing process uses a rapid thermal annealing furnace, and the process parameters of the first sub-annealing process are: the annealing temperature is 200°C to 350°C, and the annealing time is 15 seconds to 45 seconds.

[0075] In this embodiment, the second sub-annealing process uses a rapid thermal annealing furnace, and the process parameters of the second sub-annealing process are: the annealing temperature is 300°C to 600°C, and the annealing time is 15 seconds to 45 seconds.

[0076] In this embodiment, after the first sub-annealing process, the method further includes: removing the first metal layer that has not reacted with silicon by wet etching to prevent bridge connection from causing circuit short circuit.

[0077] The temperature of the first sub-annealing process is less than the temperature of the second sub-annealing process. In the first sub-annealing process, the annealing temperature is 200-350°C, and the first metal layer only reacts with the top surface of part of the source / drain region 2074102 to form a high-resistance metal silicide layer. If the annealing temperature is outside the range of 200-350°C, the reaction between the first metal layer and the top surface of part of the source / drain region 2074102 will be incomplete or excessive.

[0078] In the second sub-annealing process, the annealing temperature is 300-600°C, which converts the high-resistance metal silicide layer into a low-resistance metal silicide layer. If the annealing temperature is outside the range of 300-600°C, the high-resistance metal silicide layer will not be completely converted into a low-resistance metal silicide layer.

[0079] In the above scheme, the first metal silicide layer 2081 is formed by two annealing processes, which avoids the problem of short circuit caused by generating a low-resistance metal silicide layer by only one annealing process. Specifically, the process temperature in the first annealing process is very high. In such a high-temperature environment, silicon can diffuse along the grain boundaries of the first metal silicide layer 2081, causing the first metal silicide layer 2081 on the oxide boundary to grow excessively, and the subsequent wet etching cannot remove the first metal silicide layer 2081 on the oxide, resulting in short circuit.

[0080] In this embodiment, the material of the first metal silicide layer 2081 is Pt-containing NiSi.

[0081] Please refer to Figure 13 and Figure 14 , Figure 13 is a top view, Figure 13 only shows the substrate 200, the storage gate 205, and the selection gate 207, Figure 14 is a cross-sectional view along the BB1 direction in Figure 13 The interlayer dielectric layer 2073 and the gate oxide layer 206 are etched in sequence to expose the top of the storage gate 205, forming a second contact hole (not shown in the figure).

[0082] After the step of forming the second contact hole, it further includes depositing a second metal layer on the bottom surface of the second contact hole, and performing an annealing process to make the second metal layer react with the top surface of the storage gate 205 to form a second metal silicide layer 2091.

[0083] After forming the second metal silicide layer 2091, it further includes filling the second contact hole with conductive material to form a second conductive plug 209.

[0084] In the embodiment, the second conductive plug 209 is formed by a chemical vapor deposition process or a physical vapor deposition process.

[0085] In the embodiment, the material of the second conductive plug 209 is copper, aluminum or tungsten.

[0086] In the embodiment, the forming method of the second metal silicide layer 2091 and the second conductive plug 209 is the same as the forming method of the second metal silicide layer 2091 and the second conductive plug 209 described above, which will not be repeated here.

[0087] Please refer to Figure 15 and Figure 16 , Figure 15 is a top view, Figure 15 only shows the substrate 200, the storage gate 205 and the selection gate 207 in the figure, Figure 16 is a cross-sectional view along the CC1 direction in the figure. Figure 15 In the embodiment, the interlayer dielectric layer 2073 is etched in sequence until the top of the selection gate 207 is exposed, and a third contact hole (not shown in the figure) is formed.

[0088] After the step of forming the third contact hole, the method further includes: depositing a third metal layer on the bottom surface of the third contact hole; and performing an annealing process to react the third metal layer with the top surface of the selection gate 207 to form a third metal silicide layer 2101.

[0089] After the third metal silicide layer 2101 is formed, the method further includes: filling the third contact hole with a conductive material to form a third conductive plug 210.

[0090] In the embodiment, the third conductive plug 210 is formed by a chemical vapor deposition process or a physical vapor deposition process.

[0091] In the embodiment, the material of the third conductive plug 210 is copper, aluminum or tungsten.

[0092] In the embodiment, the forming method of the third metal silicide layer 2101 and the third conductive plug 210 is the same as the forming method of the third metal silicide layer 2101 and the third conductive plug 210 described above, which will not be repeated here.

[0093] Correspondingly, please continue to refer to Figure 10The embodiment of the present application also provides a semiconductor structure, a substrate 200; a plurality of openings 203 are separately located in the substrate 200; a storage gate 205 is located in the opening 203, and the top surface of the storage gate 205 is flush with the top surface of the substrate 200; a plurality of selection gates 207 are separately located on the substrate 200, and the selection gate 207 is adjacent to the storage gate 205 in the projection direction perpendicular to the substrate 200.

[0094] In the embodiment, the medium layer is located on the surface of the opening 203, and the medium layer comprises a charge tunneling layer, a charge trapping layer located on the surface of the charge tunneling layer, and a charge blocking layer located on the surface of the charge trapping layer.

[0095] In the embodiment, the gate oxide layer 206 is located on the bottom surface of the selection gate 207, and the sidewall 2072 is located on the sidewall surface of the selection gate 207, and the sidewall 2072 comprises a first silicon oxide layer, a silicon nitride layer located on the surface of the first silicon oxide layer, and a second silicon oxide layer located on the surface of the silicon nitride layer.

[0096] In the embodiment, the source / drain region 2074 is located in the substrate 200 between the selection gate 207 and the storage gate 205.

[0097] In the embodiment, the metal silicide layer is located on the top surface of the source / drain region 2074, the top surface of the storage gate 205 and the top surface of the selection gate 207, the interlayer dielectric layer 2073 is located on the substrate 200, and the contact hole is located in the interlayer dielectric layer 2073.

[0098] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first photoresist layer having a storage gate pattern on the substrate; Using the first photoresist layer as a mask, etching the substrate to form a plurality of discrete openings; forming a memory gate in the opening, wherein a top surface of the memory gate is flush with a top surface of the substrate; forming a select gate layer on the surface of the substrate and the surface of the storage gate; forming a second photoresist layer having a select gate pattern on the select gate layer; The select gate layer is etched using the second photoresist layer as a mask to form a plurality of discrete select gates, wherein the select gates are adjacent to the storage gates in a projection direction perpendicular to the substrate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming several discrete openings is: a dry etching process, the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds; the process parameters for etching the substrate are that the chamber pressure is 5mT to 15mT, the source power is 350W to 1200W, the bias voltage is 150V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

3. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before forming the selection gate layer, forming a storage gate dielectric layer on the opening surface and the substrate surface; After forming the memory gate, the memory gate dielectric layer on the surface of the substrate is removed by etching until the substrate surface is exposed, thereby forming a dielectric layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The steps of forming the storage gate dielectric layer include: forming a charge tunneling layer on the surface of the opening and the surface of the substrate; forming a charge trapping layer on the surface of the charge tunneling layer; A charge blocking layer is formed on the surface of the charge trapping layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before the step of forming the selection gate layer, a gate oxide layer is formed on the substrate and the storage gate; after the step of forming the selection gate, a sidewall spacer is formed on the sidewall of the selection gate.

6. The method for forming a semiconductor structure according to claim 5, wherein: The step of forming a sidewall spacer on the sidewall of the select gate includes: forming a first silicon oxide layer on sidewalls of the select gate; forming a silicon nitride layer on a surface of the first silicon oxide layer; A second silicon oxide layer is formed on the surface of the silicon nitride layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: After the step of forming a plurality of discrete selection gates, the method further includes: performing ion implantation on the substrate between the selection gates and the storage gates to form source / drain regions.

8. The method for forming a semiconductor structure according to claim 7, wherein: After the step of forming the source / drain regions, the method further includes: forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the source / drain regions, the storage gate, and the select gate; The interlayer dielectric layer and the gate oxide layer are sequentially etched until the top of the storage gate, the top of the select gate and the top of the source / drain region are exposed, thereby forming contact holes.

9. The method for forming a semiconductor structure according to claim 8, wherein: After the step of forming the contact hole, the method further comprises: Depositing a metal layer on the bottom surface of the contact hole; An annealing process is performed to react the metal layer with the top surface of the source / drain region, the top surface of the storage gate, and the top surface of the select gate to form a metal silicide layer.

10. A semiconductor structure, characterized in that include: substrate; openings, wherein a plurality of the openings are discretely located in the substrate; a storage gate located in the opening, wherein a top surface of the storage gate is flush with a top surface of the substrate; A plurality of select gates are separately located on the substrate, and the select gates are adjacent to the storage gate in a projection direction perpendicular to the substrate.

11. The semiconductor structure according to claim 10, wherein: Also includes: A dielectric layer is located on the surface of the opening, and the dielectric layer includes a charge tunneling layer, a charge trapping layer located on the surface of the charge tunneling layer, and a charge blocking layer located on the surface of the charge trapping layer.

12. The semiconductor structure according to claim 10, wherein: Also includes: A gate oxide layer located on the bottom surface of the selection gate, and a sidewall located on the sidewall surface of the selection gate, wherein the sidewall includes a first silicon oxide layer, a silicon nitride layer located on the surface of the first silicon oxide layer, and a second silicon oxide layer located on the surface of the silicon nitride layer.

13. The semiconductor structure according to claim 10, wherein: Also includes: A source / drain region is located in the substrate between the select gate and the storage gate.

14. The semiconductor structure according to claim 13, wherein: Also includes: A metal silicide layer located on the top surface of the source / drain region, the top surface of the storage gate, and the top surface of the select gate, an interlayer dielectric layer located on the substrate, and a contact hole located in the interlayer dielectric layer.

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