Semiconductor device and display device

Abstract

The invention relates to a semiconductor device and a display apparatus. The present invention addresses the problem of improving the reliability of a semiconductor device including an oxide semiconductor. The semiconductor device includes: a first insulating layer; the oxide semiconductor layer is arranged on the first insulating layer and is provided with a polycrystalline structure; a gate insulating layer over the oxide semiconductor layer; a gate wiring over the gate insulating layer; and a second insulating layer over the gate wiring, the oxide semiconductor layer having a first region, a second region, and a third region arranged in a first direction, the first region overlapping the gate insulating layer and the gate wiring, the third region being in contact with the second insulating layer, and the third region being in contact with the second insulating layer. The distance from the upper surface of the second region to the upper surface of the second insulating layer is longer than the distance from the upper surface of the third region to the upper surface of the second insulating layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a display device. In particular, one embodiment of the present invention relates to a semiconductor device including an oxide semiconductor and a display device using the semiconductor device including an oxide semiconductor. Background Art

[0002] In recent years, oxide semiconductors have attracted attention as materials for semiconductor devices, replacing amorphous silicon, polycrystalline silicon and single crystal silicon. In particular, as a semiconductor device including an oxide semiconductor, the development of thin film transistors using oxide semiconductors as channels has been continuously advancing (for example, Patent Documents 1 to 6). Thin film transistors using oxide semiconductors as channels can be formed by simple structures and low-temperature processes in the same way as semiconductor devices using amorphous silicon as channels. It is known that thin film transistors using oxide semiconductors as channels have higher field effect mobility than thin film transistors using amorphous silicon as channels.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] However, in the case of existing thin film transistors including oxide semiconductors, if the channel length is reduced, the threshold voltage representing the switching characteristics may shift in the negative direction, or the deviation of the threshold voltage may increase. Therefore, in the case of existing thin film transistors including oxide semiconductors, the degree of freedom in designing the channel length is reduced when the size is miniaturized, and the use is limited.

[0013] One of the objects of the present invention is to improve the reliability of a semiconductor device including an oxide semiconductor.

[0014] Means for solving problems

[0015] A semiconductor device involved in one embodiment of the present invention includes: a first insulating layer; an oxide semiconductor layer having a polycrystalline structure above the first insulating layer; a gate insulating layer above the oxide semiconductor layer; a gate wiring above the gate insulating layer; and a second insulating layer above the gate wiring, wherein the oxide semiconductor layer has a first region, a second region, and a third region arranged in a first direction, the first region overlaps with the gate insulating layer and the gate wiring, the third region is connected to the second insulating layer, and the distance from the upper surface of the second region to the upper surface of the second insulating layer is longer than the distance from the upper surface of the third region to the upper surface of the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic cross-sectional view showing the structure of a semiconductor device in one embodiment of the present invention.

[0017] Figure 2 It is a schematic plan view showing the structure of a semiconductor device in one embodiment of the present invention.

[0018] Figure 3 It is a schematic enlarged cross-sectional view showing the structure of a semiconductor device in one embodiment of the present invention.

[0019] Figure 4A This is a schematic cross-sectional view for explaining the hydrogen barrier effect according to one embodiment of the present invention.

[0020] Figure 4B This is a schematic plan view for explaining the hydrogen barrier effect according to one embodiment of the present invention.

[0021] Figure 5 This is a timing chart showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0022] Figure 6 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0023] Figure 7 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0024] Figure 8 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0025] Fig. 9It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0026] Fig.10 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0027] Fig.11 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0028] Fig.12 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0029] Fig.13 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0030] Fig.14 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0031] Fig.15 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0032] Fig.16 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0033] Fig.17 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0034] Fig.18 It is a schematic cross-sectional view showing the structure of a semiconductor device in one embodiment of the present invention.

[0035] Fig.19 This is a timing chart showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0036] Fig. 20 This is a timing chart showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0037] Fig.21 It is a schematic cross-sectional view showing the structure of a semiconductor device in one embodiment of the present invention.

[0038] Fig. 22 It is a schematic cross-sectional view showing the structure of a semiconductor device in one embodiment of the present invention.

[0039] Fig.23AIt is a schematic plan view showing the structure of a semiconductor device in one embodiment of the present invention.

[0040] Fig. 23B It is a schematic plan view showing the structure of a metal oxide layer in a semiconductor device according to one embodiment of the present invention.

[0041] Fig.24 This is a timing chart showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0042] Fig.25 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0043] Fig.26 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0044] Fig. 27 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0045] Fig.28 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0046] Fig.29 This is a timing chart showing a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0047] Fig.30 It is a schematic plan view showing the overall structure of a display device in one embodiment of the present invention.

[0048] Fig.31 This is a block diagram showing a circuit configuration of a display device in one embodiment of the present invention.

[0049] Fig.32 This is a circuit diagram showing a configuration of a pixel circuit of a display device in one embodiment of the present invention.

[0050] Fig.33 This is a schematic cross-sectional view showing the structure of a pixel of a display device according to one embodiment of the present invention.

[0051] Fig.34 Yes means Fig.32 A schematic top view of the structure of a pixel electrode and a common electrode of a pixel shown.

[0052] Fig.35 This is a circuit diagram showing a configuration of a pixel circuit of a display device in one embodiment of the present invention.

[0053] Fig.36This is a schematic cross-sectional view showing the structure of a pixel of a display device according to one embodiment of the present invention.

[0054] Fig.37 This is a photograph in place of a drawing showing a cross-sectional structure of a semiconductor device in one embodiment of the present invention.

[0055] Fig.38 It is a diagram showing the electrical characteristics of a semiconductor device in one embodiment of the present invention.

[0056] Fig.39 This is a graph showing the relationship between the amount of overetching during etching of the gate insulating layer and the length of the LDD region.

[0057] Fig.40 This is a graph showing the relationship between the overetching amount and the field effect mobility during etching of the gate insulating layer.

[0058] Fig.41 is a graph showing the relationship between the length of the LDD region and the field effect mobility.

[0059] Description of Reference Numerals

[0060] 10, 10a, 10b... semiconductor device, 11... driving transistor, 11... driving transistor, 12... selecting transistor, 20... display device, 21, 21a... pixel, 22... liquid crystal region, 24... sealing region, 26... terminal region, 100... substrate, 105... conductive layer, 110... insulating layer, 120... insulating layer, 121... step difference, 130... metal oxide layer, 130a, 130b... pattern, 1 40 ... oxide semiconductor layer, 140a ... channel region, 140b ... LDD region, 140c ... conductive region, 150 ... gate insulating layer, 150a ... overlapping region, 150b ... non-overlapping region, 160 ... gate wiring, 155 ... metal oxide layer, 160-1 ... metal layer, 162 ... resist layer, 170 ... insulating layer, 171, 173 ... opening, 180 ... insulating layer, 190 ... insulating layer, 200 …source / drain wiring, 201…source wiring, 203…drain wiring, 210…holding capacitor, 211…data signal line, 212…scanning signal line, 213…anode power line, 214…cathode power line, 220…light-emitting element, 300…array substrate, 301, 301a…pixel circuit, 302…source driving circuit, 303…gate driving circuit, 304…data signal line, 305…scanning signal line, 306…terminal portion, 307, 308…connecting wiring, 310…sealing portion, 311…liquid crystal element, 320…counter substrate, 330…flexible printed circuit substrate, 340…IC chip, 350…holding capacitor, 360…insulating layer, 362…insulating layer, 363…opening, 370…common electrode, 380…insulating layer, 381…opening, 390…pixel electrode, 392…light-emitting layer, 394…common electrode DETAILED DESCRIPTION

[0061] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily conceived by a person skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same elements as those described in the accompanying drawings that have appeared, and the detailed description is sometimes appropriately omitted.

[0062] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the above or below phrases are used for explanation, but, for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured in a manner opposite to that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may also be configured between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure having multiple layers stacked. In the case of the expression "the pixel electrode above the transistor", it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of the expression "the pixel electrode vertically above the transistor", it means a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0063] A “display device” refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel that includes an electro-optical layer, or sometimes refers to a structure in which a display unit is equipped with other optical components (such as a polarization component, a backlight source, a touch panel, etc.). As long as no technical contradiction arises, the “electro-optical layer” can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described later, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, and the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0064] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a combination of multiple elements of A to C. In addition, the above expressions do not exclude the case where α includes other elements.

[0065] In this specification, "same" includes not only completely identical but also substantially identical. "Substantially identical" means that although not completely identical, they are within a small difference range that can be regarded as identical, for example, within an error range of ±5% (preferably ±3%).

[0066] <First Embodiment>

[0067] use Figure 1 to Figure 17, a semiconductor device according to an embodiment of the present invention is described by taking a thin film transistor as an example. The semiconductor device according to the embodiment described below may be a thin film transistor used in a display device or may be a thin film transistor used in an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU) or a memory circuit.

[0068] [Semiconductor device structure]

[0069] use Figure 1 to Figure 3 The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described. Figure 1 It is a schematic cross-sectional view showing the structure of a semiconductor device 10 according to one embodiment of the present invention. Figure 2 It is a schematic plan view showing the structure of a semiconductor device 10 according to one embodiment of the present invention. Figure 3 1 is a schematic enlarged cross-sectional view showing the structure of a semiconductor device 10 in one embodiment of the present invention. Specifically, Figure 1 Along with Figure 2 It corresponds to the cross-sectional view taken along the one-dot chain line indicated by AA' shown in FIG. Figure 3 With the general Figure 1 The illustrated embodiment corresponds to an enlarged cross-sectional view of the vicinity of an end portion of the gate insulating layer 150 .

[0070] First, use Figure 1 The cross-sectional structure of the semiconductor device 10 is described. Figure 1 As shown, the semiconductor device 10 is provided on a substrate 100. The semiconductor device 10 includes a conductive layer 105, insulating layers 110 and 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate wiring 160, insulating layers 170 to 190, a source wiring 201, and a drain wiring 203. When the source wiring 201 and the drain wiring 203 are not particularly distinguished, they are sometimes collectively referred to as source / drain wiring 200.

[0071] In this specification, "wiring" refers to a conductive layer that electrically connects between elements, between circuits, or between an element and a circuit. Wiring can also function as an electrode. For example, the portion of the gate wiring 160 that overlaps with the oxide semiconductor layer 140 functions as a gate electrode. In addition, the portions of the source wiring 201 and the drain wiring that are connected to the oxide semiconductor layer 140 function as a source electrode and a drain electrode, respectively.

[0072] The conductive layer 105 is provided on the substrate 100. The conductive layer 105 has a function as a light-shielding film for the oxide semiconductor layer 140.

[0073] The insulating layers 110 and 120 are provided on the substrate 100 and the conductive layer 105. The insulating layer 110 has a function as a barrier film for blocking impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The insulating layer 120 functions as a base for the metal oxide layer 130 disposed thereon.

[0074] exist Figure 1 In the example shown, the upper surface of the insulating layer 120 is in contact with the lower surface of the metal oxide layer 130 below the metal oxide layer 130. However, in the region where the insulating layer 120 and the metal oxide layer 130 do not overlap, the upper surface of the insulating layer 120 is located below the lower surface of the metal oxide layer 130. That is, Figure 1 In the example shown, the insulating layer 120 near the end of the metal oxide layer 130 has a step 121. This is because the upper surface of the insulating layer 120 in the region that does not overlap with the metal oxide layer 130 and the oxide semiconductor layer 140 is etched when the gate insulating layer 150 is etched. However, depending on the etching conditions of the gate insulating layer 150, the step 121 may not be formed. This will be described later.

[0075] The metal oxide layer 130 is provided on the insulating layer 120. The metal oxide layer 130 is in contact with the insulating layer 120. The metal oxide layer 130 is a layer containing a metal oxide having aluminum as a main component, and has a function as a gas barrier film that blocks gases such as oxygen and hydrogen.

[0076] The oxide semiconductor layer 140 is disposed on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. In the present embodiment, the metal oxide layer 130 and the oxide semiconductor layer 140 have the same pattern shape. That is, in cross-sectional observation, the end of the metal oxide layer 130 is substantially aligned with the end of the oxide semiconductor layer 140. In the present embodiment, the configuration in which the metal oxide layer 130 is in contact with the insulating layer 120 and the oxide semiconductor layer 140 is in contact with the metal oxide layer 130 is illustrated, but the present invention is not limited to this configuration. Other layers may also be provided between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0077] In addition, Figure 1 In the embodiment, the side surface of the metal oxide layer 130 and the side surface of the oxide semiconductor layer 140 are arranged substantially in a straight line, but the present invention is not limited to this configuration. The angle of the side surface of the metal oxide layer 130 relative to the main surface of the substrate 100 may be different from the angle of the side surface of the oxide semiconductor layer 140. The cross-sectional shape of the side surface of at least one of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.

[0078] like Figure 1 As shown, the oxide semiconductor layer 140 has a channel region 140a, an LDD region 140b and a conductive region 140c arranged in a first direction. The channel region 140a is a region in the oxide semiconductor layer 140 that overlaps with the gate wiring 160 and functions as a channel of the transistor. The LDD region 140b is a region with a lower resistance than the channel region and functions as a resistance component for carrier movement. The conductive region 140c is a region called a source region or a drain region and functions as a conductive layer connected to the source wiring 201 or the drain wiring 203. The conductive region 140c is a region with a lower resistance than the LDD region 140b.

[0079] It is believed that the LDD region 140b will function in the same manner as the so-called LDD (Light Doped Drain) region with respect to the movement of carriers, and the details will be described later. That is, the LDD region 140b functions as a resistance component with respect to the movement of carriers. Therefore, in this specification, for the sake of convenience, the region between the channel region 140a and the conductive region 140c is referred to as the LDD region.

[0080] The gate insulating layer 150 is provided on the oxide semiconductor layer 140. Specifically, the gate insulating layer 150 has a region ( Figure 3 The overlapping region 150a) and the region not overlapping with the gate wiring 160 ( Figure 3 That is, the width of the gate insulating layer 150 in the first direction (direction D1) is wider than the width of the gate wiring 160. In this regard, Figure 3 The LDD region 140b in the oxide semiconductor layer 140 is located vertically below the non-overlapping region 150b of the gate insulating layer 150 described above. Figure 1 In the illustrated example, the length (width) of the LDD region 140 b in the first direction is set to ΔL.

[0081] The gate insulating layer 150 is removed by etching so that a portion of the periphery of the gate wiring 160 remains, and therefore a portion of the oxide semiconductor layer 140 is not covered by the gate insulating layer 150. In other words, a portion of the oxide semiconductor layer 140 is exposed from the gate insulating layer 150. The gate insulating layer 150 has a function as a gate insulating layer for the top gate (gate wiring 160).

[0082] The gate wiring 160 is opposite to the oxide semiconductor layer 140 via the gate insulating layer 150. That is, the gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate wiring 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. The gate wiring 160 has a function as a top gate of the semiconductor device 10 and a function as a light shielding film for the oxide semiconductor layer 140.

[0083] The insulating layers 170 to 190 are provided on the gate insulating layer 150 and the gate wiring 160. In this embodiment, the stacked structure composed of the insulating layers 170 to 190 is sometimes referred to as a passivation layer. The insulating layers 170 to 190 insulate the gate wiring 160 from the source / drain wiring 200. By providing the insulating layers 170 to 190, the parasitic capacitance between the gate wiring 160 and the source / drain wiring 200 can be reduced.

[0084] In this embodiment, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are used as the insulating layer 170, the insulating layer 180, and the insulating layer 190, respectively. The materials constituting the insulating layers 170 to 190 are not limited to this example, but as described later, it is desirable to have at least one insulating layer containing hydrogen. It should be noted that in this embodiment, by using a silicon oxide layer as the insulating layer 190, it functions as an etching stopper when patterning the source wiring 201 and the drain wiring 203.

[0085] like Figure 1 As shown, the insulating layer 170 constituting a portion of the passivation layer is in contact with the gate wiring 160, the gate insulating layer 150 (specifically, a region of the gate insulating layer 150 that does not overlap with the gate wiring 160), and the oxide semiconductor layer 140. The insulating layers 170 to 190 are provided with openings 171 and 173 that reach the oxide semiconductor layer 140.

[0086] The source wiring 201 is provided inside the opening 171 provided on the insulating layers 170 to 190. The source wiring 201 is in contact with the oxide semiconductor layer 140 (specifically, the conductive region 140c) at the bottom of the opening 171. The drain wiring 203 is provided inside the opening 173 provided on the insulating layers 170 and 180. The drain wiring 203 is in contact with the oxide semiconductor layer 140 (specifically, the conductive region 140c) at the bottom of the opening 173.

[0087] The operation of the semiconductor device 10 is mainly controlled by the gate voltage supplied to the gate wiring 160. An auxiliary voltage may also be supplied to the conductive layer 105. That is, the conductive layer 105 may also function as a gate wiring by being supplied with an auxiliary voltage. However, this example is not limited thereto, and the conductive layer 105 may also be used as a simple light shielding film. In the case where the conductive layer 105 is used simply as a light shielding film, it is also possible to set the conductive layer 105 to a floating state without supplying a specific voltage to the conductive layer 105.

[0088] In this embodiment, as the semiconductor device 10, a top-gate transistor in which the gate wiring 160 is provided above the oxide semiconductor layer 140 is exemplified, but the present invention is not limited to this configuration. For example, as the semiconductor device 10, a dual-gate transistor in which the conductive layer 105 is used as a gate wiring in addition to the gate wiring 160 may be used. When the conductive layer 105 is used as a gate wiring, the insulating layers 110 and 120 function as gate insulating layers. However, the above configuration is only one embodiment, and the present invention is not limited to the above configuration.

[0089] Next, use Figure 2 The planar structure of the semiconductor device 10 is described below. Figure 2 As shown, the first direction (D1 direction) is the direction connecting the source wiring 201 and the drain wiring 203, corresponding to the direction of carrier movement. The length of the channel region 140a in the oxide semiconductor layer 140 in the first direction is the channel length (L), and the length of the channel region 140a in the second direction (D2 direction) is the channel width (W). It should be noted that the second direction is a direction intersecting the first direction. In this embodiment, the second direction is represented as a direction orthogonal to the first direction, but depending on the layout of the oxide semiconductor layer 140, there may be a situation where the first direction and the second direction are not orthogonal.

[0090] As described above, in this embodiment, the metal oxide layer 130 and the oxide semiconductor layer 140 have the same pattern shape. Figure 2 Although not shown in the figure, a metal oxide layer 130 having the same shape is arranged below the oxide semiconductor layer 140. Figure 2In the example shown, a part of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, a structure may be adopted in which the entire lower surface of the channel region 140a is covered by the metal oxide layer 130, and the entire or a part of the lower surface of the LDD region 140b and the conductive region 140c is not covered by the metal oxide layer 130. That is, the entire or a part of the lower surface of the LDD region 140b and the conductive region 140c may not be in contact with the metal oxide layer 130. Conversely, a structure may be adopted in which the entire or a part of the lower surface of the channel region 140a is not covered by the metal oxide layer 130, and the other regions are in contact with the metal oxide layer 130.

[0091] In this embodiment, in the first direction, the width of the conductive layer 105 is wider than the width of the gate wiring 160. The reason for setting such a configuration is to effectively prevent the intrusion of external light into the channel region 140a. However, the present invention is not limited to this example, and the width of the conductive layer 105 may be the same as the width of the gate wiring 160.

[0092] exist Figure 2 , a configuration in which the source / drain wiring 200 does not overlap with the conductive layer 105 and the gate wiring 160 in a plan view is illustrated, but the present invention is not limited to this configuration. For example, the source / drain wiring 200 may overlap with at least one of the conductive layer 105 and the gate wiring 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0093] [Material of each layer of semiconductor device]

[0094] The substrate 100 can support each layer constituting the semiconductor device 10. As the substrate 100, for example, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. In addition, as the substrate, a silicon substrate or other non-light-transmitting rigid substrate can also be used. In addition, as the substrate, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate or a fluororesin substrate or other light-transmitting flexible substrate can be used. In order to improve the heat resistance of the substrate 100, impurities can also be introduced into the above-mentioned resin substrate. It should be noted that a substrate having a silicon oxide film or a silicon nitride film formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0095] The conductive layer 105 can reflect or absorb external light. As described above, the conductive layer 105 has an area larger than the channel region 140a of the oxide semiconductor layer 140, and therefore can block external light incident on the channel region 140a. As the conductive layer 105, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo) or tungsten (W), or alloys or compounds thereof can be used. In addition, when conductivity is not required, a resin layer composed of a black resin or the like can be used instead of the conductive layer 105. The conductive layer 105 can be a single-layer structure or a stacked structure.

[0096] The insulating layers 110, 120, 170 to 190 have a function of preventing impurities from diffusing into the oxide semiconductor layer 140. The insulating layers 110, 120, 170 to 190 may be a single layer structure or a stacked structure. As the insulating layers 110, 120, 170 to 190, for example, silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), aluminum nitride (AlNx), etc. may be used. Here, silicon oxynitride (SiOxNy) and aluminum oxynitride (AlOxNy) are silicon compounds and aluminum compounds respectively containing nitrogen (N) at a ratio (x>y) less than oxygen (O). Silicon nitride oxide (SiNxOy) and aluminum nitride oxide (AlNxOy) are silicon compounds and aluminum compounds containing oxygen at a ratio (x>y) less than nitrogen. In this embodiment, silicon nitride (SiNx) is used as the insulating layers 110 and 180, and silicon oxide (SiOx) is used as the insulating layers 120, 170, and 190.

[0097] As the metal oxide layer 130, a metal oxide containing aluminum as a main component is used. For example, as the metal oxide layer 130, aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), aluminum nitride ... x ) or the like. The expression “a metal oxide layer having aluminum as a main component” means that the ratio of aluminum contained in the metal oxide layer 130 is greater than 1% of the entire metal oxide layer 130. The ratio of aluminum contained in the metal oxide layer 130 may also be greater than 5% and less than 70%, greater than 10% and less than 60%, or greater than 30% and less than 50% of the entire metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.

[0098] In this embodiment, the oxide semiconductor layer 140 has a polycrystalline structure. That is, the oxide semiconductor layer 140 of this embodiment is composed of an oxide semiconductor formed using Poly-OS technology. Poly-OS technology refers to a technology for forming an oxide semiconductor layer having a polycrystalline structure. As the oxide semiconductor layer 140, a metal oxide having semiconductor properties can be used. For example, as the oxide semiconductor layer 140, an oxide semiconductor containing two or more metals including indium (In) is used. The ratio of indium to the overall oxide semiconductor layer 140 is 50% or more. As the oxide semiconductor layer 140, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium dioxide (Zr), and lanthanide elements are used. As the oxide semiconductor layer 140, other elements other than the above may also be used.

[0099] In the oxide semiconductor layer 140 of this embodiment, since the ratio of indium is 50% or more, oxygen deficiency is easily formed. On the other hand, it is difficult for a crystalline oxide semiconductor to form oxygen deficiency compared with an amorphous oxide semiconductor. Therefore, the oxide semiconductor layer 140 has an advantage that it is difficult to form oxygen deficiency even if the ratio of indium is 50% or more.

[0100] The gate insulating layer 150 includes an insulating oxide. Specifically, as the gate insulating layer 150, silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), etc. can be used. The gate insulating layer 150 preferably has a composition close to a stoichiometric ratio. In addition, the gate insulating layer 150 preferably has few defects. For example, as the gate insulating layer 150, an oxide in which no defects are observed when evaluated by electron spin resonance (ESR) can also be used.

[0101] The gate wiring 160, the source wiring 201, and the drain wiring 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys or compounds thereof can be used for each of the gate wiring 160, the source wiring 201, and the drain wiring 203. Each of the gate wiring 160, the source wiring 201, and the drain wiring 203 may have a single-layer structure or a stacked structure.

[0102] (Configuration near the end of the gate wiring)

[0103] use Figure 3 The structure near the end of the gate wiring 160 will be described. Figure 3As shown, the oxide semiconductor layer 140 is divided into a channel region 140a, an LDD region 140b, and a conductive region 140c. The channel region 140a is a region of the oxide semiconductor layer 140 that is located vertically below the gate wiring 160 and is in contact with the gate insulating layer 150. The conductive region 140c is a region of the oxide semiconductor layer 140 that is in contact with the insulating layer 170. The LDD region 140b is a region located between the channel region 140a and the conductive region 140c. Specifically, the LDD region 140b is a region that does not overlap with the gate wiring 160 and is in contact with the gate insulating layer 150.

[0104] Here, the gate insulating layer 150 is divided into an overlapping region 150a overlapping with the gate wiring 160 and a non-overlapping region 150b not overlapping with the gate wiring 160. That is, the channel region 140a can be said to be a region connected to the overlapping region 150a in the gate insulating layer 150. In addition, the LDD region 140b can be said to be a region connected to the non-overlapping region 150b in the gate insulating layer 150.

[0105] In this embodiment, after the gate wiring 160 is patterned, the gate insulating layer 150 is etched using the resist mask used in the etching of the gate wiring 160. The details will be described later. At this time, the end of the gate insulating layer 150 is processed into a tapered shape by using the retreat of the resist mask due to etching (etching in the first direction). That is, Figure 3 As shown, the upper surface of the non-overlapping region 150b is inclined relative to the upper surface of the oxide semiconductor layer 140 (specifically, the LDD region 140b). In this embodiment, the inclination angle (also referred to as the taper angle) of the upper surface of the non-overlapping region 150b relative to the upper surface of the oxide semiconductor layer 140 is set to θ. The inclination angle (θ) is determined by the film thickness of the gate insulating layer 150 and the retreat amount of the resist mask, but it is desirable that the inclination angle (θ) falls within the range of 5° to 20°.

[0106] Thus, in the semiconductor device 10 of the present embodiment, the upper surface of the non-overlapping region 150b becomes an inclined surface. Therefore, the upper surface of the portion of the insulating layer 170 covering the gate wiring 160, the non-overlapping region 150b, and the conductive region 140c, which is located above the non-overlapping region 150b, is inclined along the inclined surface of the non-overlapping region 150b below. That is, the upper surface of the insulating layer 170 located above the non-overlapping region 150b is inclined within a range of 5° to 20° relative to the upper surface of the oxide semiconductor layer 140. Therefore, as Figure 3As shown, the distance H1 from the upper surface of the LDD region 140b to the upper surface of the insulating layer 170 is longer than the distance H2 from the upper surface of the conductive region 140c to the upper surface of the insulating layer 170. Here, “distance H1” and “distance H2” mean distances in the normal direction relative to the upper surface of the oxide semiconductor layer 140.

[0107] As described above, the gate insulating layer 150 (specifically, the non-overlapping region 150b) and the insulating layer 170 are stacked above the LDD region 140b, and the gate insulating layer 150 has a tapered shape. Therefore, in the process of reducing the resistance of the oxide semiconductor layer 140 using hydrogen (the process of forming the conductive region 140c) described later, it is possible to suppress the diffusion of hydrogen into the oxide semiconductor layer 140. By suppressing the diffusion of hydrogen, the LDD region 140b is formed between the channel region 140a and the conductive region 140c.

[0108] In addition, if Figure 3 As shown, the length (width) of the non-overlapping region 150b in the first direction is equivalent to the length (width) of the LDD region 140b in the first direction. Figure 3 , the length of the LDD region 140b in the first direction is represented as ΔL. The length of the non-overlapping region 150b in the first direction is determined by the retreat amount of the resist mask described above. In this embodiment, the etching of the gate insulating layer 150 is continued at least until the conductive region 140c of the oxide semiconductor layer 140 is exposed, so the length of the non-overlapping region 150b is determined according to the time required from the start of etching of the gate insulating layer 150 to the exposure of the conductive region 140c. In addition, the length of the non-overlapping region 150b can be controlled by the time (over-etching time) of continuing the etching process after the conductive region 140c is exposed.

[0109] In this embodiment, the length of the non-overlapping region 150b in the first direction, that is, the length of the LDD region 140b in the first direction is controlled to be 0.3 μm or more (preferably 0.3 μm or more and 1.0 μm or less). As described above, the LDD region 140b functions as a resistance component for the movement of carriers, so if it is too long, it will cause the electrical characteristics of the semiconductor device 10 to be reduced. Therefore, the length of the LDD region 140b is preferably less than 1.0 μm. In the case where the length of the LDD region 140b is too short, the conductive region 140c may not be completely exposed due to insufficient etching of the gate insulating layer 150. In this case, it may cause poor operation of the semiconductor device 10, such as poor connection between the conductive region 140c and the source / drain wiring 200. In addition, if the length of the LDD region 140b is too short, the drain withstand voltage of the semiconductor device 10 is reduced. Therefore, from the perspective of improving reliability, the length of the LDD region 140b is preferably set to 0.3 μm or more.

[0110] It should be noted that, as described later, the inventors of the present application have come to the following conclusion: the result of repeated experiments for the case where the film thickness of the gate insulating layer 150 is 100nm is that the length of the LDD region 140b is preferably set to be greater than 0.3μm. However, the preferred range of the length of the above-mentioned LDD region 140b is not limited to the range of the case where the film thickness of the gate insulating layer 150 is 100nm. For example, when the film thickness of the gate insulating layer 150 is greater than 100nm, the length of the non-overlapping region 150b (i.e., the LDD region 140b) must be greater than 0.3μm. In addition, when the film thickness of the gate insulating layer 150 is less than 100nm, the length of the non-overlapping region 150b is sometimes less than 0.3μm at the time point when the conductive region 140c is completely exposed. However, if the film thickness of the gate insulating layer 150 becomes thinner, the current flowing in the channel region 140a will increase, so it is preferred to increase the drain withstand voltage. Therefore, in order to improve the reliability of the semiconductor device 10 having a gate insulating layer 150 having a thickness less than 100 nm, it is preferred that the etching process of the gate insulating layer 150 be continued until the non-overlapping region 150 b becomes greater than 0.3 μm regardless of whether the conductive region 140 c is exposed.

[0111] As described above, the non-overlapping region 150 b of the gate insulating layer 150 has a function of suppressing the diffusion of hydrogen from above. This point will be described using FIG.

[0112] Figure 4A This is a schematic cross-sectional view for explaining the hydrogen barrier effect according to one embodiment of the present invention. Figure 4B This is a schematic plan view for explaining the hydrogen barrier effect according to one embodiment of the present invention.

[0113] As described later, the semiconductor device 10 of the present embodiment uses hydrogen contained in the insulating layer 180 including silicon nitride to reduce the resistance of the oxide semiconductor layer 140. Specifically, hydrogen is diffused into a portion of the oxide semiconductor layer 140, thereby forming a conductive region 140c. In this process, when the insulating layer 180 including silicon nitride is formed, the hydrogen contained in the insulating layer 180 diffuses downward and supplies hydrogen to a portion of the oxide semiconductor layer 140. In the region supplied with hydrogen, the oxygen contained in the region is reduced to form an oxygen defect. Hydrogen is captured in the formed oxygen defect to form a donor level. As a result, the portion of the oxide semiconductor layer 140 supplied with hydrogen is reduced in resistance to become a conductive region 140c.

[0114] At this time, if Figure 4A As shown, it is believed that there are defects generated during the etching of the gate insulating layer 150 on the upper surface of the non-overlapping region 150b of the gate insulating layer 150 and the upper surface of the insulating layer 120, and hydrogen is trapped by the defects. That is, the upper surface of the non-overlapping region 150b of the gate insulating layer 150 and the upper surface of the insulating layer 120 function as a barrier layer to suppress the diffusion of hydrogen. Therefore, the amount of hydrogen diffusion in the LDD region 140b becomes relatively small relative to the conductive region 140c, and it becomes a region with higher resistance than the conductive region 140c. In addition, since there is almost no hydrogen diffusion in the channel region 140a, the channel region 140a can maintain its function as a semiconductor. In addition, the upper surface and side surfaces ( Figure 1 The defects on the side of the step 121 shown in FIG. 1 play a role in suppressing the diffusion of hydrogen toward the bottom of the oxide semiconductor layer 140. In this way, in the semiconductor device 10 of this embodiment, since a part of the gate insulating layer 150 does not overlap with the gate wiring 160, the channel region 140a, the LDD region 140b, and the conductive region 140c can be formed in the oxide semiconductor layer 140 by a single hydrogen diffusion process.

[0115] In addition, the non-overlapping region 150b of the gate insulating layer 150 is effective in suppressing the diffusion of hydrogen below the gate wiring 160. Figure 4B As shown in FIG. 1 , the gate wiring 160 has a region that does not overlap with the oxide semiconductor layer 140. If the non-overlap region 150b of the gate insulating layer 150 does not exist, the insulating layer 170 and the insulating layer 180 are adjacent to each other at the end of the gate wiring 160. Therefore, hydrogen easily diffuses from the end of the gate wiring 160 toward the bottom of the gate wiring 160, and the diffused hydrogen may diffuse below the gate wiring 160 and reach the channel region 140a.

[0116] In contrast, in this embodiment, if Figure 4B As shown in FIG. 1 , there is a non-overlapping region 150 b around the gate wiring 160. In other words, in a plan view, the gate wiring 160 is surrounded by the non-overlapping region 150 b of the gate insulating layer 150. Therefore, even if hydrogen diffuses in all directions, the hydrogen is captured by the defects formed on the inclined surface of the non-overlapping region 150 b as described above, thereby suppressing the diffusion of hydrogen into the oxide semiconductor layer 140. It should be noted that in FIG. Figure 4B Although not shown in the figure, the upper surface of the insulating layer 120 is in contact with the lower surface of the insulating layer 170 around the oxide semiconductor layer 140 and around the gate insulating layer 150 (specifically, the non-overlapping region 150b). Figure 4B In the illustrated state, defects that trap hydrogen are formed so as to surround the entire oxide semiconductor layer 140 .

[0117] According to the present embodiment, during the process of forming the conductive region 140c in the oxide semiconductor layer 140 (the process of reducing the resistance of the oxide semiconductor layer 140 based on hydrogen diffusion), the diffusion of hydrogen into the channel region 140a can be effectively suppressed. In addition, a low resistance region (LDD region 140b) diffused with hydrogen can be appropriately formed between the channel region 140a and the conductive region 140c (i.e., vertically below the non-overlapping region 150b). Such an LDD region 140b acts as a resistance component for the movement of carriers, and therefore has the function of improving the drain withstand voltage. It should be noted that in the present embodiment, since the non-overlapping region 150b has a conical shape, the concentration of hydrogen in the LDD region 140b increases as it approaches the conductive region 140c from the channel region 140a. That is, it can be said that the resistance value of the LDD region 140b decreases as it approaches the conductive region 140c from the channel region 140a.

[0118] The semiconductor device 10 of the present embodiment having the structure described above can suppress the diffusion of hydrogen to the bottom of the gate wiring 160 in the process of forming the conductive region 140c (the process of reducing the resistance of the oxide semiconductor layer 140), and maintain the semiconductor characteristics of the channel region 140a. Therefore, even if the channel length of the semiconductor device 10 is less than 2μm (preferably less than 1μm), the threshold voltage will not shift in the negative direction, and excellent electrical characteristics are exhibited. In addition, since the semiconductor device 10 has the LDD region 140b between the channel region 140a and the conductive region 140c, it has high reliability due to the improvement of the drain withstand voltage.

[0119] [Method for manufacturing semiconductor device]

[0120] use Figure 5 to Figure 17 A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described. Figure 5 It is a timing chart showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Figure 6 to Figure 17 It is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention.

[0121] like Figure 5 and Figure 6 As shown, a conductive layer 105 is formed on the substrate 100 as a light shielding layer, and insulating layers 110 and 120 are formed on the conductive layer 105 ( Figure 5 As the insulating layer 110, for example, a silicon nitride layer is formed. As the insulating layer 120, for example, a silicon oxide layer is formed. The insulating layers 110 and 120 are formed by a CVD (Chemical Vapor Deposition) method. In this specification, the case of forming a film on a substrate by a sputtering method, a CVD method, etc. is described as "forming a thin film", which is used in the same meaning as the expression "forming a thin film".

[0122] By using a silicon nitride layer as the insulating layer 110, the insulating layer 110 can block, for example, impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The silicon oxide layer used as the insulating layer 120 may include silicon oxide having a property of releasing oxygen under heat treatment.

[0123] In this embodiment, when forming the insulating layers 110 and 120, the film forming temperature is set to 350°C. In particular, for the insulating layer 120 (i.e., the silicon oxide layer), the oxygen content can be increased by setting the film forming temperature relatively low. As described later, by increasing the amount of oxygen contained in the insulating layer 120, the amount of hydrogen diffused into the oxide semiconductor layer 140 can be reduced. It should be noted that the film forming temperature of the insulating layers 110 and 120 can be set to 250°C to 500°C (preferably 300°C to 450°C, more preferably 325°C to 400°C).

[0124] Then, if Figure 5 and Figure 7 As shown, a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on the insulating layer 120 ( Figure 5 In the present embodiment, the metal oxide layer 130 and the oxide semiconductor layer 140 are formed by sputtering. In particular, the oxide semiconductor layer 140 is formed by sputtering using a target material formed of a crystalline oxide semiconductor.

[0125] The thickness of the metal oxide layer 130 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In the present embodiment, the thickness of the metal oxide layer 130 is set to 3 nm. In the present embodiment, an oxide having aluminum as a main component (specifically, aluminum oxide) is used as the metal oxide layer 130. Aluminum oxide has a high barrier property against gases.

[0126] In this embodiment, aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the insulating layer 120 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 140 .

[0127] In the oxide semiconductor layer 140 of this embodiment, the ratio of indium is 50% or more as described above, so a semiconductor device 10 with high mobility can be realized, but on the other hand, oxygen is easily reduced and oxygen defects are easily formed in the layer. Therefore, from the perspective of suppressing the reduction of the oxide semiconductor layer 140, it is preferable to use the metal oxide layer 130 to block hydrogen released from the insulating layer 120.

[0128] In addition, after the oxide semiconductor layer 140 is formed, more oxygen defects are formed on the upper side of the oxide semiconductor layer 140 than on the lower side during various manufacturing processes (patterning process or etching process). That is, the oxygen defects in the oxide semiconductor layer 140 exist in an uneven distribution in the thickness direction. In this case, if a sufficient amount of oxygen is supplied to repair the oxygen defects formed on the upper side of the oxide semiconductor layer 140, oxygen will be excessively supplied to the lower side of the oxide semiconductor layer 140. As a result, defect energy levels different from those of the oxygen defects are formed due to the excessive supply of oxygen, which sometimes leads to characteristics changes in reliability tests or a decrease in field effect mobility. Therefore, it can be said that from the perspective of suppressing the excessive supply of oxygen to the lower side of the oxide semiconductor layer 140, it is also preferable to use the metal oxide layer 130 to block the oxygen released from the insulating layer 120.

[0129] The thickness of the oxide semiconductor layer 140 is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 15 nm to 40 nm. The oxide semiconductor layer 140 is in an amorphous state before heat treatment (OS annealing) described below.

[0130] When the oxide semiconductor layer 140 is to be crystallized by OS annealing described later, it is preferred that the oxide semiconductor layer 140 is in an amorphous state (a state in which the crystal component of the oxide semiconductor is small) from the formation based on the sputtering method to the implementation of the OS annealing. That is, it is preferred that the formation conditions of the oxide semiconductor layer 140 are conditions that do not crystallize the oxide semiconductor layer 140 immediately after formation as much as possible. For example, in the case of forming the oxide semiconductor layer 140 by sputtering, it is desirable to form the oxide semiconductor layer 140 while controlling the temperature of the object to be formed (including the substrate 100 and the structure formed thereon). It should be noted that although the object to be temperature controlled is actually the object to be formed, since the structure formed on the substrate 100 is very thin, it can also be regarded as substantially controlling the temperature of the substrate 100. Therefore, in the following description, the object to be formed is sometimes referred to as a "substrate".

[0131] When a thin film is formed on a substrate by sputtering, ions generated in plasma and atoms recoiled from a sputtering target collide with an object to be formed (specifically, a structure formed on the substrate 100), so the temperature of the substrate rises during the thin film formation process. If the temperature of the substrate rises during the thin film formation process, the oxide semiconductor layer 140 contains microcrystals in a state immediately after formation, which hinders crystallization by OS annealing thereafter.

[0132] In order to control the temperature of the substrate (i.e., the film forming temperature) when the oxide semiconductor layer 140 is formed, for example, the thin film can be formed while the substrate is cooled. For example, the substrate can be cooled from the surface opposite to the formed surface in such a manner that the film forming temperature is below 100°C, below 70°C, below 50°C, or below 30°C. In particular, the film forming temperature of the oxide semiconductor layer 140 of the present embodiment is preferably below 50°C. In the present embodiment, the oxide semiconductor layer 140 is formed at a film forming temperature below 50°C, and the OS annealing described later is performed at a heating temperature above 400°C. Thus, in the present embodiment, the difference between the temperature when the oxide semiconductor layer 140 is formed and the temperature when the oxide semiconductor layer 140 is OS annealed is preferably 350°C or more. By forming the oxide semiconductor layer 140 while cooling the substrate, an oxide semiconductor layer 140 having a small crystal component in the state just after formation can be obtained.

[0133] Then, if Figure 5 and Figure 8 As shown, a pattern (OS pattern) composed of the oxide semiconductor layer 140 is formed ( Figure 5Step S1003). Although not shown in the figure, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask patterned by photolithography. The etching of the oxide semiconductor layer 140 can be wet etching or dry etching. In wet etching, for example, an acidic etchant can be used. Specifically, oxalic acid or hydrofluoric acid can be used as the etchant.

[0134] After the patterning of the oxide semiconductor layer 140, the oxide semiconductor layer 140 is subjected to a heat treatment (OS annealing) ( Figure 5 Step S1004). In the OS annealing, the oxide semiconductor layer 140 is heat-treated in an air atmosphere at a temperature of 250°C to 500°C (preferably 300°C to 500°C, more preferably 350°C to 450°C), thereby crystallizing the amorphous oxide semiconductor layer 140. The heating atmosphere is not limited to the air atmosphere, and is preferably an oxidizing atmosphere (an atmosphere containing oxygen). In addition, the oxidizing atmosphere is more preferably a humid atmosphere (specifically, a humid air atmosphere). In addition, the treatment time of the heat treatment is 15 minutes to 120 minutes, or 30 minutes to 60 minutes after reaching the specified temperature. In this embodiment, the temperature of the OS annealing is set to 350°C.

[0135] In the present embodiment, a substrate having a patterned oxide semiconductor layer 140 is placed in a heating furnace having a heating medium (e.g., a support plate) which is maintained at a set temperature in advance (250° C. to 500° C., 350° C. in the present embodiment). The support plate as a heating medium has the function of supporting the substrate and heating the substrate and the coating (including the oxide semiconductor layer 140) formed on the substrate. When the substrate having the oxide semiconductor layer 140 is placed on the support plate, the oxide semiconductor layer 140 is rapidly heated. When the substrate is placed in the heating furnace, it is desirable to suppress the temperature drop of the support plate to within 15%, within 10%, or within 5% of the set temperature. That is, it is preferred to control the temperature of the support plate in such a way that the oxide semiconductor layer 140 reaches the set temperature in a very short time.

[0136] It should be noted that, in this embodiment, an example of performing OS annealing after forming an OS pattern is illustrated, but the present invention is not limited to this example, and OS annealing may be performed on the oxide semiconductor layer 140 before forming an OS pattern. In this case, since the crystallized oxide semiconductor layer 140 is etched to form the OS pattern, dry etching is preferably used for the etching process.

[0137] Then, if Figure 5 and Fig. 9As shown, a pattern (AlOx pattern) consisting of a metal oxide layer 130 is formed ( Figure 5 Step S1005). The crystallized oxide semiconductor layer 140 has etching resistance to hydrofluoric acid. Therefore, the metal oxide layer 130 of the present embodiment is etched using the oxide semiconductor layer 140 patterned in the above-mentioned process as a mask. The metal oxide layer 130 can be etched using wet etching or dry etching. In wet etching, for example, diluted hydrofluoric acid (DHF) is used. By etching the metal oxide layer 130 using the oxide semiconductor layer 140 as a mask, the photolithography process can be omitted. In addition, since the metal oxide layer 130 is etched using the oxide semiconductor layer 140 as a mask, the metal oxide layer 130 and the oxide semiconductor layer 140 have the same pattern shape.

[0138] It should be noted that, in this embodiment, an example is shown in which an AlOx pattern is formed by using the OS pattern as a mask after forming the OS pattern, but the OS pattern and the AlOx pattern may also be formed together. Figure 5 In step S1003 , the oxide semiconductor layer 140 and the metal oxide layer 130 may be etched together using the same resist mask.

[0139] Then, if Figure 5 and Fig.10 As shown, a gate insulating layer 150 ( Figure 5 Step S1006). As the gate insulating layer 150, for example, a silicon oxide layer is formed. The gate insulating layer 150 is formed by a CVD method. As the gate insulating layer 150, it is desirable to form an insulating layer with as few defects as possible. In the present embodiment, the film forming temperature of the gate insulating layer 150 is set to 350°C. The thickness of the gate insulating layer 150 is, for example, not less than 50nm and not more than 300nm, not less than 60nm and not more than 200nm, or not less than 70nm and not more than 150nm. In the present embodiment, the thickness of the gate insulating layer 150 is set to 100nm.

[0140] Next, in this embodiment, after the gate insulating layer 150 is formed, a metal oxide layer 155 ( Figure 5 The metal oxide layer 155 is formed by sputtering. By using the sputtering method in the film formation of the metal oxide layer 155, oxygen is injected into the gate insulating layer 150 when the metal oxide layer 155 is formed. Therefore, a large amount of oxygen is contained in the gate insulating layer 150 after the metal oxide layer 155 is formed.

[0141] The thickness of the metal oxide layer 155 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 155. As described above, aluminum oxide has a high barrier property against gas, and therefore, during the heat treatment described later, it is possible to suppress the upward diffusion of oxygen injected into the gate insulating layer 150.

[0142] When the metal oxide layer 155 is formed by sputtering, the process gas used for sputtering may remain in the film of the metal oxide layer 155. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer 155. The remaining Ar can be detected by performing SIMS (Secondary Ion Mass Spectrometry) analysis on the metal oxide layer 155, or the like.

[0143] Next, in a state where the metal oxide layer 155 is formed on the gate insulating layer 150, a heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 140 is performed ( Figure 5 Step S1008). In other words, the patterned metal oxide layer 130 and the oxide semiconductor layer 140 are subjected to heat treatment (oxidation annealing). In the process from the formation of the oxide semiconductor layer 140 to the formation of the gate insulating layer 150 on the oxide semiconductor layer 140, oxygen defects may be generated on the upper surface and side surfaces of the oxide semiconductor layer 140. The oxygen released from the insulating layer 120 and the gate insulating layer 150 by the oxidation annealing is supplied to the oxide semiconductor layer 140 to repair the oxygen defects. The oxidation annealing can be performed at a temperature of 250°C to 500°C (preferably 300°C to 500°C, more preferably 350°C to 450°C). In this embodiment, the oxidation annealing is performed at a temperature of 350°C.

[0144] Oxygen released from the insulating layer 120 by the oxidation annealing is blocked by the metal oxide layer 130, so it is difficult to supply oxygen to the lower surface of the oxide semiconductor layer 140. The oxygen released from the insulating layer 120 diffuses from the region where the metal oxide layer 130 is not formed to the gate insulating layer 150, and reaches the oxide semiconductor layer 140 via the gate insulating layer 150. As a result, the oxygen released from the insulating layer 120 is not easily supplied to the lower surface of the oxide semiconductor layer 140, but is mainly supplied to the side and upper surface of the oxide semiconductor layer 140. In addition, by the oxidation annealing, the oxygen released from the gate insulating layer 150 is supplied to the upper surface and side of the oxide semiconductor layer 140. By the above-mentioned oxidation annealing, hydrogen is sometimes released from the insulating layer 110. However, the hydrogen is captured by the oxygen contained in the insulating layer 120 or blocked by the metal oxide layer 130 before reaching the oxide semiconductor layer 140.

[0145] As described above, by oxidation annealing, it is possible to suppress the supply of oxygen to the lower surface of the oxide semiconductor layer 140 having a small amount of oxygen defects, and to supply oxygen to the upper surface and side surfaces of the oxide semiconductor layer 140 having a relatively large amount of oxygen defects. Similarly, during oxidation annealing, the upward diffusion of oxygen injected into the gate insulating layer 150 is blocked by the metal oxide layer 155, thereby suppressing the release of oxygen into the atmosphere. Therefore, during oxidation annealing, oxygen can be efficiently supplied to the oxide semiconductor layer 140.

[0146] Then, if Figure 5 and Fig.11 As shown, after the oxidation annealing, the metal oxide layer 155 is etched to remove ( Figure 5 The etching of the metal oxide layer 155 may be wet etching or dry etching. In wet etching, for example, diluted hydrofluoric acid (DHF) is used. The etching process of step S1009 removes the entire metal oxide layer 155.

[0147] Then, if Figure 5 , Fig.12 , Fig.13 and Fig.14 As shown, a gate wiring 160 is formed on the gate insulating layer 150, and then the gate insulating layer 150 is etched ( Figure 5 Step S1010). First, Fig.12 As shown, a resist layer 162 is formed on a metal layer 160 - 1 formed by sputtering or atomic layer deposition using photolithography.

[0148] Then, if Fig.13 As shown, the metal layer 160 - 1 is dry-etched using the resist layer 162 as a mask, thereby forming the gate wiring 160 .

[0149] Then, if Fig.14 As shown in FIG. 1 , after forming the gate wiring 160, dry etching is further continued to etch the gate insulating layer 150. That is, the gate insulating layer 150 is etched by using the resist layer 162 used in the formation of the gate wiring 160. In this way, in this embodiment, the metal layer and the gate insulating layer 150 are etched together, thereby forming a patterned gate insulating layer 150 and gate wiring 160.

[0150] In this embodiment, the gate insulating layer 150 is etched using the resist layer 162 as a mask, thereby exposing a portion of the oxide semiconductor layer 140 (a region to be the conductive region 140c). At this time, while the gate insulating layer 150 is etched until a portion of the oxide semiconductor layer 140 is exposed, the resist layer 162 gradually retreats inward and becomes narrower (see Fig.14 ). Therefore, the end of the gate insulating layer 150 is processed into a tapered shape. As a result, an overlapping region 150a overlapping with the gate wiring 160 and a non-overlapping region 150b not overlapping with the gate wiring 160 are formed in the gate insulating layer 150. In this embodiment, by controlling the etching time of the gate insulating layer 150, the length of the non-overlapping region 150b in the first direction can be made to fall within the range of 0.3 μm to 1.0 μm, and the inclination angle (θ) of the upper surface of the non-overlapping region 150b can be made to fall within the range of 5° to 20°.

[0151] In addition, if Fig.14 As shown in FIG. 1 , if the gate insulating layer 150 is etched until the oxide semiconductor layer 140 is exposed, the gate insulating layer 150 formed on the insulating layer 120 will also disappear, so that the upper surface of the insulating layer 120 is exposed. Therefore, if the etching process is continued after the oxide semiconductor layer 140 is exposed, the upper surface of the insulating layer 120 is scraped off, and a step 121 is formed near the end of the metal oxide layer 130. Fig.14 In the example shown, the step 121 is formed, but if the etching process is stopped at the time when the oxide semiconductor layer 140 is exposed, the step 121 is not substantially formed. However, if the gate insulating layer 150 remains on the oxide semiconductor layer 140 (specifically, the region used as the conductive region 140c), it may cause poor contact or threshold voltage shift, so it is desirable to continue etching sufficiently until a part of the oxide semiconductor layer 140 is completely exposed. In this embodiment, a slight overetching is performed relative to the etching time required until the upper surface of the oxide semiconductor layer 140 is exposed (for example, the aforementioned etching time is extended by 10%).

[0152] Then, if Figure 5 and Fig.15 As shown, insulating layers 170 to 190 are formed on the gate insulating layer 150 and the gate wiring 160 as passivation layers ( Figure 5 Step S1011). The insulating layers 170 to 190 are formed by a CVD method. In the present embodiment, a silicon oxide layer is formed as the insulating layer 170, and a silicon nitride layer is formed as the insulating layer 180. In addition, a silicon oxide layer is formed as the insulating layer 190. The film forming temperature of the insulating layers 170 to 190 is preferably set to 250°C to 500°C (preferably 300°C to 450°C, more preferably 325°C to 400°C). In the present embodiment, the film forming temperature of the insulating layers 170 to 190 is set to 350°C. In addition, the thickness of the insulating layers 170 to 190 can be set to 30nm to 500nm. In the present embodiment, the thickness of the insulating layer 170 is set to 100nm, and the thickness of the insulating layer 180 is set to 300nm. In addition, the thickness of the insulating layer 190 is set to 30nm.

[0153] The insulating layers 170 to 190 function as a passivation layer (protective layer) for preventing gas and moisture from invading from the outside. In addition, as described above, they also have the function of insulating and separating the gate wiring 160 from the source / drain wiring 200. In addition, in this embodiment, by forming the insulating layers 170 to 190 (especially the insulating layer 180), the conductive region 140c is formed in the oxide semiconductor layer 140.

[0154] The insulating layer 180 of this embodiment is composed of a silicon nitride layer. When the insulating layer 180 is formed by the CVD method, ammonia is used as the raw material gas, so the insulating layer 180 contains a large amount of hydrogen. Therefore, when the insulating layer 180 is formed and after the insulating layer 180 is formed, hydrogen is diffused from the insulating layer 180 by heating the insulating layer 180. The diffused hydrogen reaches the oxide semiconductor layer 140 via the insulating layer 170. At this time, the oxygen contained in the region of the oxide semiconductor layer 140 that is in contact with the insulating layer 170 is reduced to form an oxygen defect. Hydrogen is captured in the formed oxygen defect to form a donor energy level. As a result, a portion of the oxide semiconductor layer 140 supplied with hydrogen is reduced in resistance and becomes a conductive region 140c.

[0155] In contrast, the oxide semiconductor layer 140 located directly below the gate wiring 160 is not reduced in resistance because hydrogen does not reach it, and becomes the channel region 140a. In addition, in the region between the channel region 140a and the conductive region 140c, hydrogen diffuses at a lower concentration than the conductive region 140c, so the region between the channel region 140a and the conductive region 140c becomes the LDD region 140b having a higher resistance than the conductive region 140c.

[0156] As a reason for suppressing the diffusion of hydrogen, a large number of defects can be cited on the upper surface of the insulating layer 120 that functions as a base layer by etching the gate insulating layer 150. In a top view, the insulating layer 120 is directly in contact with the insulating layer 170 around the oxide semiconductor layer 140. Therefore, most of the hydrogen diffused from the insulating layer 180 is captured by the upper surface of the insulating layer 120, and the amount of hydrogen diffused toward the oxide semiconductor layer 140 is suppressed. At this time, the conductive region 140c of the oxide semiconductor layer 140 is directly in contact with the insulating layer 170, so even if the amount of diffused hydrogen is small, the resistance is sufficiently low, but the amount of hydrogen diffused toward the bottom of the gate wiring 160 becomes extremely small. On this basis, in this embodiment, since defects that suppress the diffusion of hydrogen are also formed on the upper surface of the non-overlapping region 150b of the gate insulating layer 150, the diffusion of hydrogen through the gate insulating layer 150 can also be suppressed.

[0157] In addition, as a reason for suppressing the diffusion of hydrogen, the insulating layer 120 that functions as a base layer contains a large amount of oxygen. The oxygen contained in the insulating layer 120 plays a role of capturing hydrogen. In order to increase the oxygen content of the insulating layer 120, it is preferable to set the film forming temperature of the insulating layer 120 to a relatively low temperature. In this embodiment, it is set to 350°C, but it can be within the range of 250°C to 500°C (preferably 300°C to 450°C, more preferably 325°C to 400°C).

[0158] In addition, in this embodiment, a process of forming the metal oxide layer 130 on the insulating layer 120 is included, and this process also helps to increase the oxygen content of the insulating layer 120. Specifically, when aluminum oxide is formed as the metal oxide layer 130 by sputtering, oxygen is injected into the insulating layer 120. Thus, oxygen is further injected into the insulating layer 120 whose oxygen content is increased at the above-mentioned film formation temperature, so that the total amount of oxygen in the insulating layer 120 can be increased.

[0159] As described above, the semiconductor device 10 of the present embodiment has a non-overlapping region 150b that does not overlap with the gate wiring 160 at the end of the gate insulating layer 150. The non-overlapping region 150b of the gate insulating layer 150 suppresses the diffusion of hydrogen through the gate insulating layer 150. Therefore, the region below the non-overlapping region 150b in the oxide semiconductor layer 140 becomes an LDD region having a lower hydrogen concentration (higher resistance) than the conductive region 140c. In this way, according to the present embodiment, by using hydrogen diffused from the insulating layer 180 to reduce the resistance of a portion of the oxide semiconductor layer 140, the LDD region 140b and the conductive region 140c can be formed simultaneously.

[0160] Then, if Figure 5 and Fig.16As shown, openings 171 and 173 are formed in the insulating layers 170 to 190 ( Figure 5 The openings 171 and 173 expose a portion of the conductive region 140c.

[0161] Finally, if Figure 5 and Fig.17 As shown, source / drain wiring 200 ( Figure 5 Step S1013). Through the process described above, the Figure 1 A semiconductor device 10 is shown.

[0162] In the semiconductor device 10 manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region 140a is within a range of 1 μm to 4 μm and the channel width of the channel region 140a is within a range of 2 μm to 25 μm, a field effect mobility of 20 cm 2 / Vs or above, 25cm 2 / Vs or above or 30cm 2 / Vs or above electrical characteristics. The "field effect mobility" in this embodiment refers to the field effect mobility in the saturation region of the semiconductor device 10, which means the maximum value of the field effect mobility in the region where the potential difference (Vd) between the source wiring 201 and the drain wiring 203 is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage (Vg) supplied to the gate wiring 160.

[0163] (Variation Example)

[0164] exist Figure 1 In the figure, an example is shown in which the non-overlapping region 150b of the gate insulating layer 150 is a tapered shape in cross-sectional view, but the present invention is not limited to this example. For example, the non-overlapping region 150b may be a rectangular region in which the film thickness of the gate insulating layer 150 is directly retained. In this case, for example, when etching the gate insulating layer 150, a resist mask for forming the non-overlapping region 150b is separately provided to intentionally retain the gate insulating layer 150 from the end of the gate wiring 160 to a predetermined range.

[0165] <Second Embodiment>

[0166] The semiconductor device 10 of the first embodiment has a structure including the metal oxide layer 130 below the oxide semiconductor layer 140 , but the present invention is not limited to this example, and the metal oxide layer 130 may be omitted.

[0167] Fig.181 is a schematic cross-sectional view showing the structure of a semiconductor device 10a in one embodiment of the present invention. Fig.18 As shown, the oxide semiconductor layer 140 is provided on the insulating layer 120 and is in contact with the insulating layer 120. Even with such a structure, in the formation process of the conductive region 140c described in the first embodiment, the defects provided on the upper surface of the insulating layer 120 and the upper surface of the non-overlapping region 150b of the gate insulating layer 150 are used to suppress the diffusion of hydrogen into the channel region 140a.

[0168] Fig.19 1 is a timing chart showing a method for manufacturing a semiconductor device 10a according to an embodiment of the present invention. The method for manufacturing a semiconductor device 10a according to the present embodiment is as follows: Figure 5 The timing diagram shown in the figure omits the process associated with the metal oxide layer 130. Fig.19 As shown, Figure 5 Step S1002 (OS / AlOx formation) is changed to step S1102 (OS formation), and the step Figure 5 Step S1005. Other processes and Figure 5 The timing diagrams shown are the same.

[0169] In addition, the semiconductor device 10a of this embodiment can also be Fig.19 In the timing chart shown, the process of steps S1007 to S1009 is omitted for manufacturing.

[0170] <Third Embodiment>

[0171] In this embodiment, a semiconductor device manufactured by a method different from that in the first embodiment is described. The semiconductor device of this embodiment has the same structure as the semiconductor device 10 described in the first embodiment. Therefore, in the following description, the semiconductor device of this embodiment is referred to as "semiconductor device 10". In this embodiment, the description is made focusing on the points different from the first embodiment.

[0172] Fig. 20 1 is a timing chart showing a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Fig. 20 As shown, in this embodiment, the Figure 5The two steps of step S1007 (AlOx formation) and step S1009 (AlOx removal) are shown. That is, in this embodiment, after the gate insulating layer 150 is formed, oxidation annealing is directly performed in this state. Through this oxidation annealing, oxygen released from the gate insulating layer 150 is supplied to the oxide semiconductor layer 140, and oxygen defects contained in the oxide semiconductor layer 140 are repaired. The role of the metal oxide layer 130 at this time is the same as that of the first embodiment, so the description here is omitted.

[0173] <Fourth Embodiment>

[0174] In this embodiment, a semiconductor device manufactured by a method different from that in the first embodiment is described. Specifically, in this embodiment, the metal oxide layer 130 is used as an etching stopper when etching the gate insulating layer 150. In this embodiment, the description is made focusing on the points different from the first embodiment.

[0175] Fig.21 and Fig. 22 It is a schematic cross-sectional view showing the structure of a semiconductor device 10 b according to one embodiment of the present invention. Fig.23A It is a schematic plan view showing the structure of a semiconductor device 10 b according to one embodiment of the present invention. Fig. 23B 1 is a schematic top view showing the structure of the metal oxide layer 130 in the semiconductor device 10b according to one embodiment of the present invention. Fig.21 Along with Fig.23A It corresponds to the cross-sectional view taken along the one-dot chain line indicated by AA' shown in FIG. Fig. 22 Along with Fig.23A It corresponds to the cross-sectional view taken along the one-dot chain line indicated by BB' shown in FIG.

[0176] like Fig.21 As shown, in the semiconductor device 10b of this embodiment, the difference from the semiconductor device 10 of the first embodiment is that the insulating layer 120 does not have a step difference 121 (see Figure 1 ) In this embodiment, when the gate insulating layer 150 is etched, the upper surface of the insulating layer 120 is covered by the metal oxide layer 130. Therefore, even if the gate insulating layer 150 above the insulating layer 120 is removed, the upper surface of the insulating layer 120 will not be etched as in the first embodiment. Figure 1 The semiconductor device 10 of the first embodiment shown in the figure is the same as that of the first embodiment, so the detailed description is omitted.

[0177] The cross-sectional view along the first direction is the same as that of the first embodiment, but Fig. 22The cross-sectional view along the second direction shown in FIG. 1 shows a structure different from that of the semiconductor device 10 of the first embodiment. For example, although not shown in the figure, the semiconductor device 10 of the first embodiment is configured such that the ends of the metal oxide layer 130 and the oxide semiconductor layer 140 are aligned in the second direction (direction D2). Fig. 22 As shown, the semiconductor device 10 b of the present embodiment is configured such that the ends of the metal oxide layer 130 and the oxide semiconductor layer 140 do not coincide with each other in the second direction.

[0178] In addition, the metal oxide layer 130 overlaps with the gate insulating layer 150 and the gate wiring 160. Fig. 22 As shown, a non-overlapping region 150b is formed at the end of the gate insulating layer 150 in the second direction. Therefore, although the metal oxide layer 130 overlaps with the gate insulating layer 150 as a whole, a part of the region overlaps with the gate wiring 160. That is, the semiconductor device 10b is configured such that, in the second direction, the end of the metal oxide layer 130 is substantially consistent with the end of the gate insulating layer 150 and is inconsistent with the end of the gate wiring 160.

[0179] As described later, the manufacturing method of the semiconductor device 10b of the present embodiment includes a process of etching the metal oxide layer 130 using the gate wiring 160, the gate insulating layer 150 (specifically, the non-overlapping region 150b of the gate insulating layer 150) and the oxide semiconductor layer 140 as masks. Therefore, the metal oxide layer 130 is patterned in a self-aligned manner using the gate wiring 160, the gate insulating layer 150 and the oxide semiconductor layer 140 as masks. As a result, the metal oxide layer 130 has a pattern shape that is the same as the union of the pattern shape of the gate insulating layer 150 and the pattern shape of the oxide semiconductor layer 140. It should be noted that the union of the pattern shape of the gate insulating layer 150 and the pattern shape of the oxide semiconductor layer 140 is as follows: Fig. 23B The illustrated pattern is a pattern shape obtained by integrating a pattern 130 a derived from the pattern shape of the gate insulating layer 150 and a pattern 130 b derived from the pattern shape of the oxide semiconductor layer 140 .

[0180] according to Fig.21 , Fig. 22 , Fig.23A and Fig. 23B It can be seen that the metal oxide layer 130 has a first region overlapping with the gate wiring 160 and the oxide semiconductor layer 140, a second region overlapping with the oxide semiconductor layer 140 and not overlapping with the gate wiring 160, and a third region overlapping with the gate wiring 160 and the gate insulating layer 150 and not overlapping with the oxide semiconductor layer 140. Fig.21 and Fig.23A In the embodiment, the first region corresponds to the region connected to the channel region 140a. Fig.21 and Fig.23A In FIG. 1 , the second region corresponds to a region in contact with the LDD region 140 b and the conductive region 140 c.

[0181] according to Fig. 22 It can also be seen that the semiconductor device 10b of this embodiment also forms a non-overlapping region 150b at the end of the gate insulating layer 150 in the second direction. Therefore, the semiconductor device 10b can suppress the diffusion of hydrogen along the second direction toward the oxide semiconductor layer 140. The other effects of the semiconductor device 10b are the same as those of the first embodiment.

[0182] Fig.24 It is a timing chart showing a method for manufacturing the semiconductor device 10 b in one embodiment of the present invention. Figure 25 to Figure 28 It is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 10 b according to one embodiment of the present invention.

[0183] First, if Fig.24 As shown, steps S1001 to S1004 are performed by the same process as the first embodiment to complete the heat treatment (OS annealing) of the oxide semiconductor layer 140. After the heat treatment of the oxide semiconductor layer 140 is completed, the metal oxide layer 130 is not etched, but steps S1205 to S1208 are performed to complete the oxidation annealing. Fig.24 Steps S1205 to S1208 are the same as those described in the first embodiment. Figure 5 The process up to steps S1006 to S1009 is the same.

[0184] The cross-sectional view of the state where the process so far has been completed is shown in Fig.25 As shown in Fig.25 As shown, in this embodiment, the metal oxide layer 130 is not etched and remains under the gate insulating layer 150 .

[0185] Then, if Fig.24 , Fig.26 and Fig. 27 As shown, after the gate wiring 160 is formed on the gate insulating layer 150, the gate insulating layer 150 is etched ( Fig.24 Step S1209). First, Fig.26 As shown, a resist layer 162 is formed by photolithography on a metal layer 160 - 1 formed by sputtering or atomic layer deposition.

[0186] Then, if Fig. 27As shown, the metal layer 160-1 is dry-etched using the resist layer 162 as a mask, thereby forming the gate wiring 160. After the gate wiring 160 is formed, dry etching is continued to etch the gate insulating layer 150. The process of etching the metal layer 160-1 and the gate insulating layer 150 is the same as that of the first embodiment.

[0187] At this time, in this embodiment, even if the etching process is continued after a part of the oxide semiconductor layer 140 is exposed, since the upper surface of the insulating layer 120 is covered by the metal oxide layer 130, the etching of the insulating layer 120 can be prevented. That is, the metal oxide layer 130 can function as an etching stopper in the etching process of the gate insulating layer 150. Therefore, it is possible to form the step 121 (see Figure 1 ) is sufficiently increased in etching time of the gate insulating layer 150, thereby ensuring a large process margin for exposing a portion of the oxide semiconductor layer 140 (a region used as the conductive region 140c). In addition, by sufficiently increasing the etching time of the gate insulating layer 150, an LDD region 140b of sufficient length can be formed.

[0188] After the etching process of the gate insulating layer 150 is completed, then, as Fig.24 and Fig.28 As shown, a pattern (AlOx pattern) consisting of a metal oxide layer 130 is formed ( Fig.24 The process of etching the metal oxide layer 130 is the same as that of the first embodiment. It should be noted that when etching the metal oxide layer 130, there is a possibility that the non-overlapping region 150b of the gate insulating layer 150 is also etched. However, in this embodiment, since the film thickness of the gate insulating layer 150 (for example, 100nm) is sufficiently thick relative to the film thickness of the metal oxide layer 130 (3nm in this embodiment), the etching of the non-overlapping region 150b can be substantially ignored.

[0189] The semiconductor device 10b of the present embodiment can obtain a field effect mobility of 20 cm-1 when the channel length L of the channel region 140a is within a range of 1 μm to 4 μm and the channel width of the channel region 140a is within a range of 2 μm to 25 μm. 2 / Vs or above, 25cm 2 / Vs or above or 30cm 2 The definition of field effect mobility in this embodiment is the same as that in the first embodiment.

[0190] <Fifth Embodiment>

[0191] In this embodiment, a semiconductor device manufactured by a method different from that of the fourth embodiment is described. The semiconductor device of this embodiment has the same structure as the semiconductor device 10b described in the fourth embodiment. Therefore, in the following description, the semiconductor device of this embodiment is referred to as "semiconductor device 10b". In this embodiment, the description is made focusing on the points different from the fourth embodiment.

[0192] Fig.29 1 is a timing chart showing a method for manufacturing a semiconductor device 10b in one embodiment of the present invention. Fig.29 As shown, in this embodiment, the Fig.24 The two steps of step S1206 (AlOx formation) and step S1208 (AlOx removal) are shown. That is, in this embodiment, after the gate insulating layer 150 is formed, oxidation annealing is directly performed in this state. Through this oxidation annealing, oxygen released from the gate insulating layer 150 is supplied to the oxide semiconductor layer 140, and oxygen defects contained in the oxide semiconductor layer 140 are repaired. The role of the metal oxide layer 130 at this time is the same as that of the fourth embodiment, so the description here is omitted.

[0193] <Sixth Implementation>

[0194] use Figure 30 to Figure 36 A display device 20 using a semiconductor device in one embodiment of the present invention will be described. In the following embodiment, a configuration in which the semiconductor device 10 described in the first embodiment is applied to a circuit of a liquid crystal display device will be described. However, the present invention is not limited to this example, and any semiconductor device in the second to fourth embodiments may be applied to a circuit of a liquid crystal display device.

[0195] [Overview of Display Device]

[0196] Fig.30 FIG. 2 is a schematic top view showing the overall structure of a display device 20 according to an embodiment of the present invention. Fig.30 As shown, the display device 20 has an array substrate 300, a sealing portion 310, an opposing substrate 320, a flexible printed circuit (FPC) substrate 330 and an IC chip 340. The array substrate 300 and the opposing substrate 320 are bonded together by the sealing portion 310. In the liquid crystal region 22 surrounded by the sealing portion 310, a plurality of pixels 21 are arranged in a matrix. The liquid crystal region 22 is a region that overlaps with the liquid crystal element 311 described later when viewed from above. It should be noted that, with respect to the pixel 21, letters such as "R", "G" and "B" respectively represent pixels corresponding to pixels for red display, pixels for green display and pixels for blue display.

[0197] The sealing region 24 provided with the sealing portion 310 is the region around the liquid crystal region 22. The flexible printed circuit substrate 330 is provided in the terminal region 26. The terminal region 26 is the region exposed from the opposing substrate 320 in the array substrate 300 and is provided outside the sealing region 24. The outside of the sealing region 24 means the outside of the region provided with the sealing portion 310 and the region surrounded by the sealing portion 310. The IC chip 340 is provided on the flexible printed circuit substrate 330. The IC chip 340 is provided for driving each pixel circuit 301 (refer to Fig.31 ) signal.

[0198] [Circuit Configuration of Display Device]

[0199] Fig.31 1 is a block diagram showing a circuit configuration of a display device 20 in one embodiment of the present invention. Fig.31 As shown, a plurality of pixel circuits 301 and Fig.30 The pixels 21 shown are arranged in a matrix shape. A source driving circuit 302 is provided at a position adjacent to the liquid crystal region 22 where the pixel circuit 301 is provided in the Y direction (column direction). In addition, a gate driving circuit 303 is provided at a position adjacent to the liquid crystal region 22 in the X direction (row direction). The source driving circuit 302 and the gate driving circuit 303 are provided in the above-mentioned sealing region 24. However, the region where the source driving circuit 302 and the gate driving circuit 303 are provided is not limited to the sealing region 24, and can be any region as long as it is outside the region where the pixel circuit 301 is provided.

[0200] The data signal line 304 extends from the source driver circuit 302 in the Y direction and is connected to the plurality of pixel circuits 301 arranged in the Y direction. The scanning signal line 305 extends from the gate driver circuit 303 in the X direction and is connected to the plurality of pixel circuits 301 arranged in the X direction.

[0201] The terminal region 26 is provided with a terminal portion 306. The terminal portion 306 and the source driving circuit 302 are connected via a connection wiring 307. Similarly, the terminal portion 306 and the gate driving circuit 303 are connected via a connection wiring 308. By connecting the flexible printed circuit substrate 330 to the terminal portion 306, an external device is connected to the display device 20 via the flexible printed circuit substrate 330. Each pixel circuit 301 provided in the display device 20 is driven by a signal from an external device input via the flexible printed circuit substrate 330.

[0202] The semiconductor device 10 described in the first embodiment is used as a transistor included in the pixel circuit 301 , the source driver circuit 302 , and the gate driver circuit 303 .

[0203] [Pixel circuit of display device]

[0204] Fig.32 2 is a circuit diagram showing the configuration of a pixel circuit 301 of a display device 20 in one embodiment of the present invention. Fig.32 As shown, the pixel circuit 301 includes components such as the semiconductor device 10, a holding capacitor 350 and a liquid crystal element 311.

[0205] The semiconductor device 10 has a gate wiring 160, a source wiring 201, and a drain wiring 203. The gate wiring 160 is connected to a scanning signal line 305. However, the gate wiring 160 and the scanning signal line 305 may also be formed by an integral conductive layer. The source wiring 201 is connected to a data signal line 304. However, the source wiring 201 and the data signal line 304 may also be formed by an integral conductive layer.

[0206] The drain wiring 203 is connected to the storage capacitor 350 and the liquid crystal element 311. It should be noted that the source wiring 201 and the drain wiring 203 may sometimes switch roles depending on the relationship between the voltage supplied to the data signal line 304 and the voltage accumulated in the storage capacitor 350. That is, there is a case where the source wiring 201 functions as a drain wiring and the drain wiring 203 functions as a source wiring.

[0207] [Cross-sectional structure of display device]

[0208] Fig.33 2 is a schematic cross-sectional view showing the structure of a pixel 21 of a display device 20 according to an embodiment of the present invention. Fig.33 As shown in FIG. 1 , the display device 20 is a display device in which a semiconductor device 10 is provided in a pixel 21. In this embodiment, the semiconductor device 10 is used in a pixel circuit 301, but the semiconductor device 10 can also be used in peripheral circuits including a source driver circuit 302 and a gate driver circuit 303. In the following description, the configuration of the semiconductor device 10 is the same as that of the first embodiment. Figure 1 The structures shown are the same, so detailed description is omitted.

[0209] An insulating layer 360 is provided on the source wiring 201 and the drain wiring 203. A common electrode 370 provided in common to a plurality of pixels is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. An opening 381 is provided on the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380 and inside the opening 381. The pixel electrode 390 is connected to the drain wiring 203.

[0210] Fig.34 2 is a schematic top view showing the structure of the pixel electrode 390 and the common electrode 370 of the display device 20 in one embodiment of the present invention. Fig.34 As shown, the common electrode 370 is composed of a flat conductive layer. The pixel electrode 390 is composed of a comb-shaped conductive layer composed of a portion extending along the X direction and a portion extending along the Y direction. The portion extending along the Y direction is composed of a plurality of linear electrodes, which are respectively connected to the portion extending along the X direction.

[0211] The common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a transverse electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. The liquid crystal molecules contained in the liquid crystal element 311 are moved by the transverse electric field, thereby determining the grayscale of the pixel.

[0212] <Seventh Implementation>

[0213] use Fig.35 and Fig.36 A display device 20 using a semiconductor device in one embodiment of the present invention will be described. In the embodiment shown below, the semiconductor device 10 described in the first embodiment above is applied to the circuit structure of an organic EL display device. However, the present invention is not limited to this example, and any semiconductor device in the second to fourth embodiments may be applied to the circuit of an organic EL display device. The overall structure and circuit structure of the display device 20 in this embodiment are different from those in the embodiment shown in FIG. Fig.30 and Fig.31 The situation shown is the same, so the description here is omitted.

[0214] [Pixel circuit of display device]

[0215] Fig.35 2 is a circuit diagram showing the configuration of a pixel circuit 301a of a display device 20 according to an embodiment of the present invention. Fig.35 As shown, the pixel circuit 301 a includes components such as a driving transistor 11 , a selection transistor 12 , a holding capacitor 210 , and a light emitting element 220 .

[0216] The driving transistor 11 and the selecting transistor 12 have the same structure as the semiconductor device 10. The source wiring of the selecting transistor 12 is connected to the data signal line 211, and the gate wiring of the selecting transistor 12 is connected to the scanning signal line 212. The source wiring of the driving transistor 11 is connected to the anode power supply line 213, and the drain wiring of the driving transistor 11 is connected to one end of the light emitting element 220. The other end of the light emitting element 220 is connected to the cathode power supply line 214. The gate wiring of the driving transistor 11 is connected to the drain wiring of the selecting transistor 12. The holding capacitor 210 is connected to the gate wiring and the drain wiring of the driving transistor 11. A grayscale signal that determines the light emission intensity of the light emitting element 220 is supplied to the data signal line 211. A signal for selecting a pixel row to which the grayscale signal is to be written is supplied to the scanning signal line 212.

[0217] [Cross-sectional structure of display device]

[0218] Fig.36 It is a schematic cross-sectional view showing the structure of a pixel 21 a of a display device 20 according to an embodiment of the present invention. Fig.36 The structure of the pixel 21a shown is similar to Fig.33 The pixel 21 shown in FIG. 1 is similar in structure to the pixel 21 in FIG. 21a , but the structure above the insulating layer 360 is different between the pixel 21 and the pixel 21a. Fig.36 The pixel 21a shown in FIG. Fig.33 The same configuration as the pixel 21 shown is not described here, and the differences between the two are described below.

[0219] like Fig.36 As shown, the pixel 21a has a pixel electrode 390, a light-emitting layer 392 and a common electrode 394 above the insulating layer 360. The light-emitting element 220 is composed of the pixel electrode 390, the light-emitting layer 392 and the common electrode 394. The pixel electrode 390 is arranged on the insulating layer 360 and inside the opening 381. Here, the insulating layer 362 is called a bank, a rib, etc., and has the function of defining the light-emitting area. The insulating layer 362 is arranged on the pixel electrode 390. An opening 363 is provided in the insulating layer 362. The opening 363 corresponds to the light-emitting area. The light-emitting layer 392 and the common electrode 394 are arranged on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are respectively arranged for each pixel 21a. On the other hand, the common electrode 394 is commonly arranged with respect to a plurality of pixels 21a. Different materials are used for the light-emitting layer 392 according to the display color of the pixel 21a.

[0220] <Eighth Implementation>

[0221] In the sixth and seventh embodiments, the semiconductor device 10 described in the first embodiment is applied to the configuration of a liquid crystal display device and an organic EL display device, respectively. However, the semiconductor device 10 described in the first embodiment may also be applied to other display devices other than the above-mentioned display device (for example, a self-luminous display device or an electronic paper display device other than the organic EL display device). In addition, the semiconductor device 10 can be applied to display devices ranging from small and medium-sized display devices to large display devices without special limitations. For the above-mentioned display device, it is not limited to the semiconductor device 10 described in the first embodiment, and the various semiconductor devices described in the second to fifth embodiments may also be applied.

[0222] <Example>

[0223] [Structure of semiconductor device]

[0224] Fig.37 1 is a photograph in lieu of a drawing showing a cross-sectional structure of a semiconductor device in one embodiment of the present invention. Specifically, Fig.37 This is a cross-sectional SEM photograph of the semiconductor device 10 of the first embodiment actually manufactured as a prototype. Fig.37 The reference numerals shown are Figure 1 The reference numerals used in the semiconductor device 10 shown in the figure correspond to each other. In addition, the "slope" in the figure refers to the inclined surface formed on the upper surface of the insulating layer 170. Fig.37 In FIG. 1 , since the gate insulating layer 150 and the insulating layer 170 are stacked above the LDD region 140b, the film thickness of the insulating layer 170 is thicker than that of the insulating layer 170 disposed above the conductive region 140c. In addition, it can be seen that since the upper surface of the insulating layer 170 is an inclined surface, the upper surface of the gate insulating layer 150 corresponding to the non-overlapping region 150b is also an inclined surface.

[0225] [Electrical characteristics of semiconductor devices]

[0226] Fig.38 is a diagram showing the electrical characteristics of a semiconductor device 10 in one embodiment of the present invention. Specifically, Fig.38 The ID-VG characteristics of the semiconductor device 10 having a channel length of 2 μm are shown.

[0227] Fig.38 The measurement conditions of the electrical characteristics shown are as follows.

[0228] Channel area size: W / L = 3μm / 2μm

[0229] Source-drain voltage: 0.1V, 10V

[0230] ·Gate voltage: -5V~+20V

[0231] ·Measurement environment: room temperature, dark room

[0232] exist Fig.38 In FIG. 1 , as electrical characteristics of the semiconductor device, the ID-VG characteristics (electrical characteristics indicating the change of drain current with respect to gate voltage) and the field effect mobility (μsat) in the saturation region are shown. Fig.38 In the graph shown, the vertical axis representing the drain current (ID) is shown on the left side of the graph. In addition, the vertical axis representing the field effect mobility in the saturation region calculated based on the drain current is shown on the right side of the graph. The horizontal axis is the gate voltage (VG) supplied to the semiconductor device 10. Fig.38 In FIG. 1 , the ID-VG characteristic represented by the solid line is the characteristic when the source-drain voltage is 10 V, and the ID-VG characteristic represented by the dashed line is the characteristic when the source-drain voltage is 0.1 V. In addition, the field effect mobility in the saturation region is represented by the dotted line.

[0233] like Fig.38 As shown in FIG. 1 , the ID-VG characteristic of the semiconductor device 10 of the first embodiment shows a so-called normally off characteristic in which the drain current ID starts to flow when the gate voltage VG is approximately 0 V. Regardless of whether the source-drain voltage is 0.1 V or 10 V, the drain current can obtain a sufficient value and is very stable. Fig.38 The field effect mobility obtained from the electrical characteristics shown is 36.7 cm 2 / Vs. It should be noted that Fig.38 The ID-VG characteristics shown are examples of the case where the channel length is 2 μm, but even the semiconductor device 10 having a channel length of 1 μm can obtain good electrical characteristics.

[0234] As described above, it can be seen that the semiconductor device 10 of the first embodiment does not shift the threshold voltage even when the channel length is as small as 1 to 2 μm, and has a high field effect mobility. In addition, it can be confirmed that the semiconductor device 10 can output a sufficient on-current despite having the LDD region 140 b, and has both excellent electrical characteristics and high reliability.

[0235] [Explanation of experimental data]

[0236] Fig.39It is a graph showing the relationship between the amount of overetching (represented as "etching depth" in the figure) when etching the gate insulating layer 150 and the length of the LDD region 140b (represented as "LDD length" in the figure). Here, the so-called "overetching amount" refers to the depth of the insulating layer 120 removed by etching after a part of the oxide semiconductor layer 140 (the region used as the conductive region 140c) is exposed during the etching of the gate insulating layer 150. In other words, the "overetching amount" can also be said to be Figure 1 The height of the step 121 is shown.

[0237] exist Fig.39 In FIG. 1 , the horizontal axis represents the depth of the insulating layer 120 etched away due to overetching, and the vertical axis represents the length (ΔL) of the LDD region 140 b. The measured value of the etching depth of 0 nm corresponds to the measured value at the time when a portion of the upper surface of the oxide semiconductor layer 140 is exposed. Fig.39 The graph shown shows the length of the LDD region 140 b when the etching process is performed under the following conditions when the film thickness of the insulating layer 120 and the film thickness of the gate insulating layer 150 are both 100 nm.

[0238] Condition 1: The gate insulating layer 150 is etched to a depth of 50 nm from the upper surface.

[0239] Condition 2: The gate insulating layer 150 is etched to a depth of 100 nm from the upper surface.

[0240] Condition 3: The gate insulating layer 150 is etched to a depth of 100 nm from the upper surface, and the insulating layer 120 is etched to a depth of 50 nm from the upper surface.

[0241] Condition 4: The gate insulating layer 150 is etched to a depth of 100 nm from the upper surface, and the insulating layer 120 is etched to a depth of 100 nm from the upper surface.

[0242] exist Fig.39 In the graph shown, the etching depths of 0 nm, 15 nm, 46 nm, and 91 nm correspond to conditions 1, 2, 3, and 4, respectively. It should be noted that condition 2 corresponds to the timing when the gate insulating layer 150 on the oxide semiconductor layer 140 disappears, but the etching depth of the insulating layer 120 becomes 15 nm. It is believed that this is because the etching process of the gate insulating layer 150 is controlled by time, resulting in a slight error. Regarding conditions 3 and 4, there are also slight errors caused by time control.

[0243] like Fig.39As shown, the following trend can be confirmed: as the etching depth of the insulating layer 120 increases, the length of the LDD region 140b also increases. Specifically, it can be confirmed that there is a roughly linear relationship between the etching depth of the insulating layer 120 and the length of the LDD region 140b. This means that as the etching time in the etching process of the gate insulating layer 150 changes, the length of the non-overlapping region 150b of the gate insulating layer 150 changes linearly. That is, it can be seen that by controlling the etching time of the gate insulating layer 150, the length of the LDD region 140b formed in the oxide semiconductor layer 140 can be controlled with good reproducibility.

[0244] Fig.40 1 is a graph showing the relationship between the overetching amount during etching of the gate insulating layer 150 and the field effect mobility (represented as “Mobility” in the figure). Fig.40 In FIG. 1 , the horizontal axis represents the depth of the insulating layer 120 etched away due to over-etching, and the vertical axis represents the field effect mobility. Fig.40 The “field effect mobility” shown is the field effect mobility in the saturation region of the semiconductor device 10 as described in the first embodiment. Fig.40 In the experiments shown, the field effect mobility was measured for each of the above-mentioned conditions 1 to 4.

[0245] like Fig.40 As shown, the field effect mobility shows an extremely low value under condition 1 (etching depth is 0 nm). Under condition 1, the gate insulating layer 150 remains and the upper surface of the oxide semiconductor layer 140 is not exposed. Therefore, it is predicted that hydrogen is blocked by the remaining gate insulating layer 150 and is not fully supplied to a part of the oxide semiconductor layer 140, and the formation of the conductive region 140c is insufficient. Therefore, it is speculated that under condition 1, sufficient on-current cannot be obtained when driving the semiconductor device 10, resulting in a decrease in field effect mobility.

[0246] In contrast, under condition 2 (etching depth of 15 nm), a depth of more than 30 cm 2 In addition, it can be confirmed that the field effect mobility decreases as the etching depth of the insulating layer 120 increases. Fig.39 As shown in FIG. 1 , the etching depth of the insulating layer 120 is approximately proportional to the length of the LDD region 140 b. Fig.39 The reduction in field effect mobility shown is due to the lengthening of the LDD region 140b. Therefore, the relationship between the LDD region 140b and the field effect mobility in the saturation region of the semiconductor device 10 is Fig.41 Shown.

[0247] Fig.41is a graph showing the relationship between the length of the LDD region 140b and the field effect mobility. Fig.41 In FIG. 1 , the horizontal axis represents the length of the LDD region 140 b , and the vertical axis represents the field effect mobility. Fig.41 The “field effect mobility” shown is also the field effect mobility in the saturation region of the semiconductor device 10. Fig.41 As shown, except for the case of condition 1 (the case where the length of the LDD region 140b is about 217nm), a decrease in field effect mobility is observed as the length of the LDD region 140b becomes longer. That is, Fig.40 and Fig.41 The results shown here mean that the LDD region 140b formed in the semiconductor device 10 effectively functions as a resistance component. Fig.41 As can be seen from the graph, practical electrical characteristics (specifically, field effect mobility) can be obtained when the length of the LDD region 140 b is within a range of 300 nm or more.

[0248] According to the above experimental data, it is confirmed that the non-overlapping region 150b of the gate insulating layer 150 of the semiconductor device of each embodiment can form an LDD region 140b that effectively functions as a resistance component. In addition, it can be seen that the semiconductor device of each embodiment has a high field effect mobility even if it has an LDD region. As described above, the semiconductor device of each embodiment has both excellent electrical characteristics and high reliability.

[0249] The various embodiments described above as embodiments of the present invention can be appropriately combined and implemented as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or designing components appropriately based on the various embodiments, or solutions obtained by adding, omitting or changing conditions of processes, as long as they have the gist of the present invention, are also included in the scope of the present invention.

[0250] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they can of course be understood as the effects brought about by the present invention.

Claims

1. A semiconductor device comprising: a first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the oxide semiconductor layer; a gate wiring on the gate insulating layer; and a second insulating layer on the gate wiring, The oxide semiconductor layer has a first region, a second region, and a third region arranged in a first direction, The first region overlaps with the gate insulating layer and the gate wiring, The third region is in contact with the second insulating layer, A distance from an upper surface of the second region to an upper surface of the second insulating layer is longer than a distance from an upper surface of the third region to an upper surface of the second insulating layer.

2. The semiconductor device according to claim 1, wherein The second region is in contact with the gate insulating layer and does not overlap with the gate wiring.

3. The semiconductor device according to claim 1, wherein An upper surface of the second insulating layer located above the second region is inclined relative to an upper surface of the second region.

4. The semiconductor device according to claim 3, wherein: An inclination angle of an upper surface of the second insulating layer with respect to an upper surface of the second region is not less than 5° and not more than 20°.

5. The semiconductor device according to claim 1, wherein An upper surface of the gate insulating layer located above the second region is inclined relative to an upper surface of the second region.

6. The semiconductor device according to claim 1, wherein The length of the second region in the first direction is not less than 0.3 μm and not more than 1.0 μm.

7. The semiconductor device according to claim 1, wherein An upper surface of the second insulating layer adjacent to an end portion of a portion of the gate wiring that does not overlap with the oxide semiconductor layer within a predetermined distance is inclined relative to an upper surface of the gate wiring.

8. The semiconductor device according to claim 7, wherein: The predetermined distance is not less than 0.3 μm and not more than 1.0 μm.

9. The semiconductor device according to claim 1, wherein: The second insulating layer includes a silicon oxide layer.

10. The semiconductor device according to claim 1, wherein The first region is a channel region, The second region is a region having lower resistance than the channel region.

11. The semiconductor device according to claim 10, wherein: The third region is a region having lower resistance than the second region. 12 . The semiconductor device according to claim 1 , further comprising a metal oxide layer between the first insulating layer and the oxide semiconductor layer.

13. The semiconductor device according to claim 12, wherein: The metal oxide layer has the same pattern shape as the oxide semiconductor layer.

14. The semiconductor device according to claim 1, wherein The oxide semiconductor layer contains two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more.

15. A display device, wherein: The semiconductor device according to any one of claims 1 to 14 is included in each pixel.

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