A back contact cell with specific light-receiving surface passivation and its preparation method and application

Abstract

The present invention belongs to the technical field of back contact batteries, and specifically relates to a back contact battery with a specific light-receiving surface passivation, and its preparation method and application, including a substrate, the substrate having a backlight surface and a light-receiving surface, the light-receiving surface of the substrate is sequentially provided with a first tunneling oxide layer, a doped amorphous silicon layer and a silicon medium anti-reflection layer, the thickness of the first tunneling oxide layer is 0.2-1.5nm, the doped amorphous silicon layer is doped with oxygen elements and hydrogen elements, the first tunneling oxide layer is doped with hydrogen elements, wherein the hydrogen content of the first tunneling oxide layer near the doped amorphous silicon layer side is greater than the hydrogen content near the substrate side. The present invention can take into account both good passivation effect and optical loss, play a role in enhancing passivation, thereby improving the battery passivation effect and current, thereby improving the battery efficiency, and the equipment cost is low.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery with a specific light-receiving surface passivated, and a preparation method and application thereof. Background Art

[0002] The existing back contact cell includes a first semiconductor layer and a second semiconductor layer alternately arranged on the back of a silicon substrate, and a light-receiving surface passivation layer and an anti-reflection layer sequentially arranged on the light-receiving surface of the silicon substrate. The light-receiving surface passivation layer is generally an amorphous silicon passivation layer, a tunneling polycrystalline passivation layer, or a passivation layer of aluminum oxide and silicon nitride. In the preparation, the first semiconductor layer and the second semiconductor layer are sequentially formed on the back, and then the light-receiving surface passivation layer and the anti-reflection layer are formed on the light-receiving surface.

[0003] However, in the above-mentioned back contact cell, the existing composition of the light-receiving surface passivation layer has the following disadvantages:

[0004] ① When the passivation layer on the light-receiving surface is an amorphous silicon passivation layer, intrinsic amorphous silicon is required as the passivation contact layer, and it is combined with N-type amorphous silicon to meet the requirements of passivation performance. In addition, plate-type PECVD is used for formation, and plate-type PECVD equipment is expensive, which greatly increases the equipment cost. At the same time, the intrinsic amorphous silicon and N-type doped amorphous silicon layers have a small bandgap width and high light absorption, which seriously affects the short-circuit current of the battery.

[0005] ② When the light-receiving surface passivation layer is a tunneling polycrystalline passivation layer, the preparation process of the polysilicon layer is relatively complicated. It needs to be deposited and then diffused through high-temperature annealing. In addition, the absorption of polysilicon is large. When used as a light-receiving surface passivation layer, it affects the absorption of sunlight and thus affects the battery current.

[0006] ③ When the passivation layer of the light-receiving surface is a stacked passivation layer of aluminum oxide and silicon nitride, aluminum oxide and silicon nitride need to be coated separately by two devices, which increases the equipment cost.

[0007] In the existing double-sided heterojunction battery, the two semiconductors and their two electrodes are respectively arranged on the light-receiving side and the back side of the battery. There is a technology of using a doped amorphous silicon layer on the light-receiving side. However, in this double-sided structure, the passivation film layer on the light-receiving side needs to consider the conductivity, light transmittance, and carrier extraction performance of the light-receiving side. Double-sided heterojunction batteries and back-contact batteries belong to two different battery systems. The passivation film layer on the light-receiving side of the back-contact battery does not need to consider the conductivity or the carrier extraction performance, but requires higher light transmittance and good passivation performance. That is, different battery systems have different requirements for the passivation film layer on the light-receiving side and face different problems. Moreover, ITO is used as a conductive anti-reflection layer on the light-receiving side of the double-sided heterojunction battery, which only plays a conductive anti-reflection role. However, the use of a simple N-type doped amorphous silicon layer (i.e., only doped with phosphorus) on the light-receiving side of the back-contact battery in the prior art will lead to a significant decrease in passivation, which needs to be further improved.

[0008] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0009] The purpose of the present invention is to overcome the defects of low short-circuit current and high equipment cost of the passivation layer on the light-receiving surface of the back-contact battery in the prior art, and to provide a back-contact battery with a specific light-receiving surface passivation and its preparation method and application, which can take into account good passivation effect and optical loss, play a role in enhancing passivation, thereby improving the battery passivation effect and current, and then improving the battery efficiency, and the equipment cost is low.

[0010] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a back-contact battery with a specific light-receiving surface passivated, comprising a substrate, the substrate having a back-light surface and a light-receiving surface, the light-receiving surface of the substrate being sequentially provided with a first tunneling oxide layer, a doped amorphous silicon layer and a silicon dielectric anti-reflection layer, the thickness of the first tunneling oxide layer is 0.2-1.5nm, the doped amorphous silicon layer is doped with oxygen elements and hydrogen elements, the first tunneling oxide layer is doped with hydrogen elements, wherein the hydrogen content of the first tunneling oxide layer close to the doped amorphous silicon layer side is greater than the hydrogen content close to the substrate side.

[0011] In some preferred embodiments of the present invention, the hydrogen content of the doped amorphous silicon layer is greater than the arithmetic mean of the hydrogen content in the first tunneling oxide layer.

[0012] In some preferred embodiments of the present invention, the doped amorphous silicon layer has an oxygen content of 5-60 at.%, based on the total amount of the doped amorphous silicon layer.

[0013] In some preferred embodiments of the present invention, the doped amorphous silicon layer has a hydrogen content of 1-35 at.%, based on the total amount of the doped amorphous silicon layer.

[0014] In some preferred embodiments of the present invention, the first tunneling oxide layer has a hydrogen content of 1-20 at.%, based on the total amount of elements in the first tunneling oxide layer.

[0015] In some preferred embodiments of the present invention, the oxygen content of the first tunneling oxide layer close to the doped amorphous silicon side is less than the oxygen content of the first tunneling oxide layer close to the substrate side.

[0016] Preferably, the oxygen content in the first tunnel oxide layer is 55-68 at.%.

[0017] In some preferred embodiments of the present invention, the silicon dielectric anti-reflection layer is doped with hydrogen.

[0018] In some preferred embodiments of the present invention, the hydrogen content of the silicon dielectric anti-reflection layer is less than or equal to the hydrogen content of the doped amorphous silicon layer.

[0019] In some preferred embodiments of the present invention, the hydrogen content of the silicon dielectric anti-reflection layer is greater than or equal to the arithmetic mean of the hydrogen content in the first tunneling oxide layer.

[0020] In some preferred embodiments of the present invention, the silicon dielectric anti-reflection layer has a hydrogen content of 1-25 at. %, based on the total amount of elements in the silicon dielectric anti-reflection layer.

[0021] In some preferred embodiments of the present invention, the doped amorphous silicon layer further comprises phosphorus and / or carbon, and based on the total amount of the doped amorphous silicon layer, the carbon content is 0-20 at.%, and the phosphorus content is 0 - 0.5 at.%.

[0022] In some preferred embodiments of the present invention, the phosphorus content in the doped amorphous silicon layer is 0.1-0.3 at.%.

[0023] In some preferred embodiments of the present invention, the bandgap width of the doped amorphous silicon layer is between 1.9 and 6 eV, and the refractive index of the doped amorphous silicon layer at a wavelength of 600 nm is between 2 and 3.7.

[0024] In some preferred embodiments of the present invention, the ratio R of silicon to oxygen in the doped amorphous silicon layer in atomic percentage satisfies: 1<R≤2.2.

[0025] More preferably, 1.5≤R≤2.2.

[0026] In some preferred embodiments of the present invention, the substrate is a single crystal silicon substrate.

[0027] In some preferred embodiments of the present invention, the doped amorphous silicon layer is a single-layer structure.

[0028] In some preferred embodiments of the present invention, the doped amorphous silicon layer is a single-layer or multi-layer structure, and in the case of a multi-layer structure, the corresponding bandgap width gradually increases in a gradient in the thickness direction from the light-receiving surface outward.

[0029] In some preferred embodiments of the present invention, the ratio of the bandgap width of any layer in the multilayer structure to the adjacent layer relatively far away from the light-receiving surface is 1:1.02-5 and the ratio of their thicknesses is 1:0.2-10, preferably the ratio of the bandgap width is 1:1.1-5 and the ratio of their thicknesses is 1:0.5-10.

[0030] In some preferred embodiments of the present invention, the thickness of the doped amorphous silicon layer is 3-40 nm.

[0031] In some preferred embodiments of the present invention, the silicon dielectric anti-reflection layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0032] In some preferred embodiments of the present invention, the thickness of the silicon dielectric anti-reflection layer is 50-120 nm.

[0033] In some preferred embodiments of the present invention, the backlight surface is provided with a film layer including a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is a stack including a second tunneling oxide layer and a first doped polysilicon layer or a stack including a first intrinsic silicon layer and a first doped silicon layer, and the second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer.

[0034] In some preferred embodiments of the present invention, the first semiconductor layer includes a second tunneling oxide layer and a first doped polysilicon layer, the second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer, and the thickness ratio of the doped amorphous silicon layer to the second tunneling oxide layer is 2-30:1.

[0035] In some preferred embodiments of the present invention, the first semiconductor layer comprises a second tunneling oxide layer and a first doped polysilicon layer, and the thickness ratio of the first tunneling oxide layer, the doped amorphous silicon layer and the second tunneling oxide layer is 0.1-1:2-30:1.

[0036] In some preferred embodiments of the present invention, two ends of the second semiconductor layer extend outward to cover the back side of part of the adjacent first semiconductor layer, and a second opening area not covering the second semiconductor layer is opened on the back side of the first semiconductor layer, a first opening area is formed between adjacent first semiconductor layers, the first opening area and the second opening area are arranged at intervals, and the area between them is a spacing area; in the spacing area, a mask layer is arranged between the first semiconductor layer and the second semiconductor layer, or no mask layer is arranged; the back contact battery also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, an isolation groove is opened on the portion of the conductive film layer located in the spacing area; the metal electrode is arranged on the outer surfaces of the conductive film layers corresponding to the first opening area and the second opening area.

[0037] In a second aspect, the present invention provides a method for preparing a back contact cell with a specific light-receiving surface passivation, comprising the following steps:

[0038] Providing a substrate, wherein the substrate has a backlight surface and a light receiving surface;

[0039] A first tunneling oxide layer, a doped amorphous silicon layer and a silicon medium anti-reflection layer are sequentially formed on the light-receiving surface of the substrate, wherein the doped amorphous silicon layer is doped with oxygen elements and hydrogen elements, the first tunneling oxide layer is doped with hydrogen elements, and the hydrogen content of the first tunneling oxide layer close to the doped amorphous silicon layer is greater than the hydrogen content close to the substrate side.

[0040] In some preferred embodiments of the present invention, the first tunneling oxide layer, the doped amorphous silicon layer and the silicon dielectric anti-reflection layer are deposited at one time by tubular PECVD and the deposition temperature is 350-600°C.

[0041] In some preferred embodiments of the present invention, the preparation method further comprises forming a first semiconductor layer and a second semiconductor layer on the backlight surface of the silicon substrate.

[0042] In some preferred embodiments of the present invention, the first semiconductor layer is obtained by annealing after deposition and the annealing temperature is 800-950°C.

[0043] In some preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150-250°C.

[0044] In some preferred embodiments of the present invention, the preparation method specifically comprises the following steps:

[0045] S101, providing a double-sided polished silicon substrate;

[0046] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon substrate;

[0047] S103, performing a first etching opening on the back surface obtained in S102 to form a first opening area;

[0048] S104, then performing texturing and cleaning to form a texturing surface on the light-receiving surface of the silicon substrate and the first opening area, and then selecting whether to perform a step of removing the mask layer outside the first opening area on the back side of the silicon substrate by cleaning according to needs;

[0049] S105, depositing a first tunneling oxide layer, a doped amorphous silicon layer and a silicon dielectric anti-reflection layer on the light-receiving surface of the silicon substrate in sequence, wherein the thickness of the first tunneling oxide layer is 0.2-1.5 nm; the first tunneling oxide layer is doped with hydrogen, and the hydrogen content of the first tunneling oxide layer close to the doped amorphous silicon layer is controlled to be greater than the hydrogen content close to the substrate, and the doped amorphous silicon layer is doped with oxygen and hydrogen;

[0050] S106, depositing a second semiconductor layer on the back surface obtained in S105.

[0051] In some preferred embodiments of the present invention, the formation conditions of the first tunnel oxide layer include: introducing a gas containing an oxygen source at a pressure of 0.5e2 Pa-1e5 Pa, and maintaining the temperature at a set process temperature for 1-30 minutes.

[0052] In some preferred embodiments of the present invention, the deposition conditions of the doped amorphous silicon layer include: a process pressure of 100-500 Pa, a power of 2-15 kW, and a process gas containing silane and a gas source of a desired doping element.

[0053] In some preferred embodiments of the present invention, the deposition conditions of the silicon dielectric anti-reflection layer include: process pressure of 100-500 Pa and power of 5-20 kW.

[0054] In some preferred embodiments of the present invention, controlling the hydrogen content of the first tunnel oxide layer near the doped amorphous silicon layer to be greater than the hydrogen content near the substrate is achieved by at least one of the following methods:

[0055] Method 1: hydrogen is introduced during the deposition of the doped amorphous silicon layer and the hydrogen flow rate is 0.5-30 slm;

[0056] Mode 2: The preparation method further comprises: performing hydrogen treatment after depositing the doped amorphous silicon layer, the conditions of the hydrogen treatment comprising: introducing hydrogen gas, the hydrogen gas flow rate is 0.5-30 slm, the treatment temperature is 350-600° C., and the treatment time is 1-15 min;

[0057] Method 3: hydrogen gas is introduced during the deposition of the silicon dielectric anti-reflection layer, and the hydrogen gas flow rate is 0.5-30 slm.

[0058] In some preferred embodiments of the present invention, the method for preparing the back contact cell with a specific light-receiving surface passivation further comprises:

[0059] S107, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon substrate to form a second opening region spaced apart from the first opening region;

[0060] S108, depositing a conductive film layer on the back surface obtained in S107;

[0061] S109, performing a third etching opening on a portion of the conductive film layer between the second opening region and the first opening region to form an isolation groove;

[0062] S110, forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the second opening area and the first opening area.

[0063] In a third aspect, the present invention provides a back contact cell with a specific light-receiving surface passivated, which is prepared by the preparation method of the back contact cell with a specific light-receiving surface passivated according to the second aspect.

[0064] In a fourth aspect, the present invention provides a photovoltaic module, which includes the back contact cell with a specific light-receiving surface passivated as described in the first aspect, or includes the back contact cell with a specific light-receiving surface passivated as described in the third aspect.

[0065] Beneficial effects:

[0066] The present invention adopts the above technical scheme, especially adopts a first tunneling oxide layer with a suitable doping amount of doped elements, a doped amorphous silicon layer and a silicon dielectric anti-reflection layer on the light-receiving surface. The doped amorphous silicon layer is doped with a suitable amount of oxygen element, which can adjust and control the doped amorphous silicon layer to have a suitable high bandgap width, small light absorption, which is beneficial to improve the short-circuit current, and is combined with doping with a suitable amount of hydrogen element to improve the passivation effect. The simultaneous appropriate doping of oxygen element and hydrogen element can synergistically adjust the refractive index of the doped amorphous silicon layer within a suitable range, and can take into account a good passivation effect and optical loss. The silicon dielectric anti-reflection layer can enhance the passivation effect; and the hydrogen element content close to the doped amorphous silicon layer side in the first tunneling oxide layer is controlled to be greater than the hydrogen element content close to the substrate side, which can better passivate the dangling bonds in the amorphous silicon, which is beneficial to reduce the defects of the amorphous silicon layer, thereby improving the passivation effect and current of the battery, and further improving the battery efficiency.

[0067] Moreover, the doped amorphous silicon layer and the silicon dielectric anti-reflection layer can be formed by one-time high-temperature deposition (deposition temperature is 350-550°C) of tubular PECVD, replacing the plate PECVD low-temperature (about 200°C) deposition of the amorphous silicon layer and the anti-reflection layer, which greatly reduces the equipment cost. In addition, the doped amorphous silicon layer can increase the bandgap width of amorphous silicon by doping oxygen and hydrogen, thereby reducing the absorption of light. The bandgap width of amorphous silicon formed at low temperature by conventional HBC cells is only about 1.7ev, which has a large absorption of light and is not conducive to increasing the short-circuit current.

[0068] In the preferred embodiment of the present invention, a light-receiving surface passivation structure containing a doped amorphous silicon layer is used in the combined passivation structure. Since the back combined passivation structure does not require high-temperature sintering (if it is a conventional HBC battery, the first semiconductor on the back will be seriously ineffective after being deposited at 350-550°C on the front film layer, and if it is a TBC battery, it needs to be sintered at 800°C when forming the metal electrode), the light transmittance of the specific film layer on the light-receiving surface is higher, and the doped amorphous silicon layer does not need to be doped with a high concentration of phosphorus (that is, the phosphorus content in the doped amorphous silicon layer is 0-0.5 at.%), a better passivation effect and a higher short-circuit current can be obtained. Moreover, when used in the combined passivation structure, the formation temperatures corresponding to the first semiconductor layer (maximum annealing temperature 800-950°C), the light-receiving surface film layer (deposition temperature 350-550°C), and the second semiconductor layer (deposition temperature 150-250°C) tend to decrease in a step-wise manner, which is more conducive to passivation retention. The formation temperatures of the second semiconductor layer and the passivation layer in the conventional joint passivation (amorphous silicon layer deposited by plate-type PECVD at low temperature (about 200°C)) are relatively close, while the temperature of the anti-reflection layer in the light-receiving surface film layer is higher than the formation temperature of the second semiconductor layer and the passivation layer in the light-receiving surface film layer (generally 20-50°C higher), and the anti-reflection layer needs to be formed after the passivation layer in the second semiconductor layer and the light-receiving surface film layer. Therefore, the formation of the light-receiving surface passivation layer will destroy the passivation effect of the second semiconductor layer and the light-receiving surface film layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0070] Figure 1 It is a schematic structural diagram of a double-sided polished silicon substrate according to Example 1 of the present invention;

[0071] Figure 2 It is a schematic diagram of the structure of forming a first semiconductor layer and a mask layer on the back side of Embodiment 1 of the present invention;

[0072] Figure 3 It is a schematic diagram of the structure of forming a first opening area on the back side of Embodiment 1 of the present invention;

[0073] Figure 4 This is a schematic diagram of the structure after the back opening area and the light-receiving surface are velvet-finished and the mask layer is removed according to Embodiment 1 of the present invention;

[0074] Figure 5 It is a schematic structural diagram of depositing a first tunneling oxide layer, a doped amorphous silicon layer and an anti-reflection layer on the light-receiving surface of Example 1 of the present invention;

[0075] Figure 6 It is a schematic diagram of the structure of forming a second semiconductor layer on the back side of Embodiment 1 of the present invention;

[0076] Figure 7 It is a schematic diagram of the structure of forming a second opening area on the back side of Embodiment 1 of the present invention;

[0077] Figure 8 This is a schematic diagram of the structure of a transparent conductive film layer deposited on the back side of Example 1 of the present invention;

[0078] Fig. 9 It is a schematic diagram of the structure of forming an isolation groove on the back side of Embodiment 1 of the present invention;

[0079] Fig.10 This is a schematic diagram of the structure of the back-printed metal electrode of Example 1 of the present invention.

[0080] Fig.11 This is a graph showing the progressive changes in the thickness of different film layers obtained by time-of-flight secondary ion mass spectrometry analysis of the film layers on the light-receiving surface of the silicon substrate in the back-contact cell of Example 1 of the present invention, where the horizontal axis is the film thickness (nm) on the light-receiving surface toward the silicon wafer, and the left vertical axis is the absolute doping concentration in cm -3 , the right vertical axis is the relative doping concentration, the unit is c / s, and each vertical axis is the doping concentration in Log10; among them, the film layers corresponding to layer A to layer D are the silicon substrate, the first tunneling oxide layer, the doped amorphous silicon layer and the anti-reflection layer.

[0081] Description of Reference Numerals

[0082] Silicon substrate 1, second tunneling oxide layer 2, first doped polysilicon layer 3, mask layer 4, first opening area W1, second opening area W2, first tunneling oxide layer 5, doped amorphous silicon layer 6, anti-reflection layer 7, intrinsic amorphous silicon layer 8, second doped amorphous silicon layer 9, transparent conductive film layer 10, isolation groove W3, metal electrode 11. DETAILED DESCRIPTION

[0083] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0084] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0085] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0086] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0087] In the present invention, the area close to the silicon substrate is referred to as the inner part, and the area far from the silicon substrate is referred to as the outer part.

[0088] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a back-contact battery with a specific light-receiving surface passivated, comprising a substrate, the substrate having a back-light surface and a light-receiving surface, the light-receiving surface of the substrate being sequentially provided with a first tunneling oxide layer, a doped amorphous silicon layer and a silicon dielectric anti-reflection layer, the thickness of the first tunneling oxide layer is 0.2-1.5nm, the doped amorphous silicon layer is doped with oxygen elements and hydrogen elements, the first tunneling oxide layer is doped with hydrogen elements, wherein the hydrogen content of the first tunneling oxide layer close to the doped amorphous silicon layer side is greater than the hydrogen content close to the substrate side.

[0089] The thickness of the first tunnel oxide layer is 0.2-1.5 nm, for example, it can be 0.2 nm, 0.3 nm, 0.5 nm, 0.8 nm, 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc., and the range between any two point values, for example, it can be preferably 0.3-1.5 nm. Using a thinner first tunnel oxide layer is conducive to increasing the battery current.

[0090] In some preferred embodiments of the present invention, the hydrogen content of the doped amorphous silicon layer is greater than the arithmetic mean of the hydrogen content in the first tunneling oxide layer, which is more conducive to improving the passivation effect of the light-receiving surface of the substrate.

[0091] In the present invention, the arithmetic mean value of the hydrogen content in the first tunneling oxide layer refers to the arithmetic mean value of the maximum and minimum values ​​of the hydrogen content in the first tunneling oxide layer, which is equal to 1 / 2 of the maximum and minimum values ​​of the hydrogen content in the first tunneling oxide layer.

[0092] In some preferred embodiments of the present invention, the doped amorphous silicon layer has an oxygen content of 5-60 at.%, based on the total amount of the doped amorphous silicon layer. Doping the doped amorphous silicon layer with an appropriate amount of oxygen is more conducive to reducing light absorption by the light-receiving surface of the battery, thereby increasing the battery current.

[0093] In some preferred embodiments of the present invention, the doped amorphous silicon layer has a hydrogen content of 1-35 at.%, based on the total amount of the doped amorphous silicon layer. Doping the doped amorphous silicon layer with an appropriate amount of hydrogen is more conducive to improving the passivation effect of the light-receiving surface of the substrate.

[0094] In some preferred embodiments of the present invention, the first tunneling oxide layer has a hydrogen content of 1-20 at.%, more preferably 1-15 at.%, based on the total amount of elements in the first tunneling oxide layer. The first tunneling oxide layer is doped with an appropriate amount of hydrogen, which is more conducive to improving the passivation effect of the substrate light-receiving surface.

[0095] In the present invention, the content of each element in the corresponding film layer in terms of atomic percentage is measured by SIMS (time-of-flight secondary ion mass spectrometry).

[0096] In some preferred embodiments of the present invention, the oxygen content of the first tunneling oxide layer near the doped amorphous silicon side is less than the oxygen content near the substrate side. This preferred solution can reduce defects in the first tunneling oxide layer and amorphous silicon, and is more conducive to improving the passivation effect of the substrate light-receiving surface.

[0097] Further preferably, the oxygen content in the first tunnel oxide layer is 55-68 at.%.

[0098] In some preferred embodiments of the present invention, the silicon dielectric anti-reflection layer is doped with hydrogen elements, which is more conducive to improving the passivation effect of the light-receiving surface of the substrate.

[0099] In some preferred embodiments of the present invention, the hydrogen content of the silicon dielectric anti-reflection layer is less than or equal to the hydrogen content of the doped amorphous silicon layer, which is more conducive to improving the passivation effect of the light-receiving surface of the substrate.

[0100] In some preferred embodiments of the present invention, the hydrogen content of the silicon dielectric anti-reflection layer is greater than or equal to the arithmetic mean of the hydrogen content in the first tunneling oxide layer, which is more conducive to improving the passivation effect of the substrate light-receiving surface.

[0101] In some preferred embodiments of the present invention, the silicon dielectric anti-reflection layer has a hydrogen content of 1-25 at.%, based on the total amount of elements in the silicon dielectric anti-reflection layer, which is more conducive to improving the passivation effect of the substrate light-receiving surface.

[0102] In some preferred embodiments of the present invention, the doped amorphous silicon layer further comprises phosphorus and / or carbon. More preferably, based on the total amount of the doped amorphous silicon layer, the carbon content is 0-20 at.%, and the phosphorus content is 0-0.5 at.%.

[0103] The phosphorus content is 0 - 0.5 at.%, for example, it can be 0, 0.05 at.%, 0.1 at.%, 0.15 at.%, 0.2 at.%, 0.25 at.%, 0.3 at.%, 0.35 at.%, 0.4 at.%, 0.45 at.%, 0.5 at.%, etc., as well as the range between any two point values.

[0104] In some preferred embodiments of the present invention, the phosphorus content in the doped amorphous silicon layer is 0.1-0.5 at.%, more preferably 0.1-0.3 at.%, which is more conducive to improving the front field passivation of the substrate.

[0105] In some more preferred embodiments of the present invention, the doped amorphous silicon layer is not doped with phosphorus, which is beneficial to increasing the band gap width of amorphous silicon and further beneficial to increasing the battery current.

[0106] In some preferred embodiments of the present invention, the bandgap width of the doped amorphous silicon layer is 1.9-6 eV, preferably 3.0-6 eV, and the refractive index of the doped amorphous silicon layer at a wavelength of 600 nm is between 2-3.7. The doped amorphous silicon layer has a suitable bandgap width and refractive index, which is more conducive to reducing the absorption of light and the anti-reflection and anti-transmittance effect, thereby further improving the battery current.

[0107] The bandgap width of the doped amorphous silicon layer is 1.9 - 6 eV, for example, it can be 1.9 eV, 2.0 eV, 2.1 eV, 2.2 eV, 2.3 eV, 2.5 eV, 2.8 eV, 3.0 eV, 3.3 eV, 3.5 eV, 3.7 eV, 4.0 eV, 4.2 eV, 4.5 eV, 4.8 eV, 5.0 eV, 5.2 eV, 5.5 eV, 5.7 eV, 6.0 eV, etc., and the range between any two point values.

[0108] The refractive index of the doped amorphous silicon layer at a wavelength of 600 nm is between 2 and 3.7. For example, the refractive index at a wavelength of 600 nm can be 2.0, 2.2, 2.5, 2.7, 2.9, 3.0, 3.3, 3.5, 3.6, 3.7, etc., and the range between any two point values.

[0109] In some preferred embodiments of the present invention, the ratio R of silicon to oxygen in the doped amorphous silicon layer in atomic percentage satisfies: 1<R≤2.2. With this preferred solution, silicon dioxide can be formed, which is more conducive to increasing the bandgap width of the doped amorphous silicon layer, reducing the absorption of amorphous silicon, and thus increasing the battery current.

[0110] In some preferred embodiments of the present invention, 1.5≤R≤2.2, which is more conducive to increasing the bandgap width of the doped amorphous silicon layer, reducing the absorption of amorphous silicon, and thus increasing the battery current.

[0111] In the present invention, the substrate is a silicon substrate, which may be N-type or P-type.

[0112] In some preferred embodiments of the present invention, the substrate is a single crystal silicon substrate, which is more conducive to improving the battery efficiency than a polycrystalline silicon substrate.

[0113] In some preferred embodiments of the present invention, the doped amorphous silicon layer is a single-layer structure.

[0114] In some preferred embodiments of the present invention, the doped amorphous silicon layer is a multilayer structure of more than two layers, which is more conducive to improving the passivation effect and short-circuit current of the battery.

[0115] Further preferably, the corresponding bandgap width of the multilayer structure gradually increases in a gradient in the thickness direction from the light-receiving surface. Using a multilayer structure with a gradually increasing bandgap width as the doped amorphous silicon layer is more conducive to optical matching and improves battery current.

[0116] In some preferred embodiments of the present invention, the ratio of the bandgap width of any layer in the multilayer structure to the adjacent layer relatively far from the light-receiving surface is 1:1-5, which is more conducive to optical matching and improves the battery current.

[0117] In some preferred embodiments of the present invention, the thickness ratio of any layer in the multilayer structure to the adjacent layer relatively far from the light-receiving surface is 1:0.5-10, preferably 1:1.5-10, and further preferably 1:2.0-10, which is more conducive to optical matching and improves battery current.

[0118] In some preferred embodiments of the present invention, the thickness of the doped amorphous silicon layer is 3-40nm, for example, it can be 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 10nm, 12nm, 15nm, 17nm, 20nm, 23nm, 25nm, 27nm, 30nm, 32nm, 35nm, 38nm, 40nm, etc., and the range between any two point values.

[0119] In some preferred embodiments of the present invention, the backlight surface is provided with a film layer including a first semiconductor layer and a second semiconductor layer.

[0120] In the present invention, preferably, the first semiconductor layer is a stacked layer including a second tunneling oxide layer and a first doped polysilicon layer or a stacked layer including a first intrinsic silicon layer and a first doped silicon layer, and the second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer. The second doped silicon layer may be, for example, a second doped amorphous silicon or a second doped microcrystalline silicon. The second intrinsic silicon layer is preferably intrinsic amorphous silicon.

[0121] In some preferred embodiments of the present invention, the first semiconductor layer includes a second tunneling oxide layer and a first doped polysilicon layer. By adopting a combined passivation structure and cooperating with a light-receiving surface passivation structure, the doped amorphous silicon layer does not need to be doped with a high concentration of phosphorus to obtain a better passivation effect. Moreover, when used in a combined passivation structure, the corresponding formation temperatures of the first semiconductor layer (maximum annealing temperature 800-950°C), the light-receiving surface film layer (deposition temperature 350-550°C), and the second semiconductor layer (deposition temperature 150-250°C) tend to decrease in steps, which is more conducive to passivation maintenance.

[0122] Further preferably, the second semiconductor layer comprises a second intrinsic silicon layer and a second doped silicon layer, and the thickness ratio of the doped amorphous silicon layer to the second tunneling oxide layer is 2-30:1, which is more conducive to improving the passivation effect and short-circuit current of the battery.

[0123] It can be understood in the present invention that one of the first doped polysilicon layer and the second doped silicon layer is of N type, and the other is of P type.

[0124] Further preferably, when the first semiconductor layer includes a second tunneling oxide layer and a first doped polysilicon layer, the thickness ratio of the first tunneling oxide layer, the doped amorphous silicon layer and the second tunneling oxide layer is 0.1-1:2-30:1, further preferably 0.2-0.8:2-20:1, which is more conducive to improving the passivation effect and short-circuit current of the battery.

[0125] Preferably, the thickness of the second tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 50-200 nm, and the corresponding doping element content is 0.1-2 at.%.

[0126] Preferably, in the present invention, the thickness of the second intrinsic silicon layer is 4-12 nm, the thickness of the second doped silicon layer is 7-14 nm, and the corresponding doping element content is 0.05-1 at.%.

[0127] It can be understood that the corresponding doping elements mentioned above are phosphorus or boron.

[0128] In some preferred embodiments of the present invention, the silicon dielectric anti-reflection layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0129] Preferably, the thickness of the silicon dielectric anti-reflection layer is 50-120 nm.

[0130] In some preferred embodiments of the present invention, two ends of the second semiconductor layer extend outward to cover part of the back side of the adjacent first semiconductor layer, and a second opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, and a first opening area is formed between adjacent first semiconductor layers. The first opening area and the second opening area are arranged at intervals, and the area between them is a spacing area.

[0131] Further preferably, in the spacing region, a mask layer is disposed between the first semiconductor layer and the second semiconductor layer, or no mask layer is disposed.

[0132] In some preferred embodiments of the present invention, the back-contact battery also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is opened on the portion of the conductive film layer located in the spacing area; the metal electrode is arranged on the outer surface of the conductive film layer corresponding to each of the first opening area and the second opening area.

[0133] Preferably in the present invention, a portion of the silicon substrate located at the first opening region is a textured surface, and a portion of the silicon substrate at a position corresponding to the first semiconductor layer is a polished surface.

[0134] In a second aspect, the present invention provides a method for preparing a back contact cell with a specific light-receiving surface passivation, comprising the following steps:

[0135] Providing a substrate, wherein the substrate has a backlight surface and a light receiving surface;

[0136] A first tunneling oxide layer, a doped amorphous silicon layer and a silicon medium anti-reflection layer are sequentially formed on the light-receiving surface of the substrate, wherein the doped amorphous silicon layer is doped with oxygen elements and hydrogen elements, the first tunneling oxide layer is doped with hydrogen elements, and the hydrogen content of the first tunneling oxide layer close to the doped amorphous silicon layer is greater than the hydrogen content close to the substrate side.

[0137] In some preferred embodiments of the present invention, the first tunneling oxide layer, the doped amorphous silicon layer and the silicon dielectric anti-reflection layer are deposited at one time by tubular PECVD and the deposition temperature is 350-600°C.

[0138] In some preferred embodiments of the present invention, the preparation method further comprises forming a first semiconductor layer and a second semiconductor layer on the backlight surface of the silicon substrate.

[0139] In some preferred embodiments of the present invention, the first semiconductor layer is obtained by annealing after deposition and the annealing temperature is 800-950°C.

[0140] In some preferred embodiments of the present invention, the deposition temperature of the second semiconductor layer is 150-250°C.

[0141] In some preferred embodiments of the present invention, the preparation method specifically comprises the following steps:

[0142] S101, providing a double-sided polished silicon substrate;

[0143] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon substrate;

[0144] S103, performing a first etching opening on the back surface obtained in S102 to form a first opening area;

[0145] S104, then performing texturing and cleaning to form a texturing surface on the light-receiving surface of the silicon substrate and the first opening area, and then selecting whether to perform a step of removing the mask layer outside the first opening area on the back side of the silicon substrate by cleaning according to needs;

[0146] S105, depositing a first tunneling oxide layer, a doped amorphous silicon layer and a silicon dielectric anti-reflection layer on the light-receiving surface of the silicon substrate in sequence, wherein the thickness of the first tunneling oxide layer is 0.2-1.5 nm; the first tunneling oxide layer is doped with hydrogen, and the hydrogen content of the first tunneling oxide layer close to the doped amorphous silicon layer is controlled to be greater than the hydrogen content close to the substrate, and the doped amorphous silicon layer is doped with oxygen and hydrogen;

[0147] S106, depositing a second semiconductor layer on the back surface obtained in S105.

[0148] In some preferred embodiments of the present invention, the formation conditions of the first tunnel oxide layer include: introducing a gas containing an oxygen source at a pressure of 0.5e2 Pa-1e5 Pa, and maintaining the temperature for 1-30 minutes under a set process temperature condition. The gas containing an oxygen source may include, for example, oxygen, nitrous oxide, and the like.

[0149] In some preferred embodiments of the present invention, the deposition conditions of the doped amorphous silicon layer include: a process pressure of 100-500 Pa, a power of 2-15 kW, and a process gas containing silane and a gas source of a desired doping element. The use of appropriate process pressure and power is more conducive to improving the film quality of the doped amorphous silicon, thereby improving the passivation effect of the battery.

[0150] During the deposition of the doped amorphous silicon layer, a process gas containing silane and a desired doping element source gas is introduced, wherein the desired doping element source gas refers to an oxygen-doped gas source (such as oxygen, nitrous oxide and other gases), an optional carbon-doped gas source (such as methane, carbon dioxide and other gases), an optional phosphorus-doped gas source (such as phosphine and other gases), and an optional hydrogen-doped gas source (such as hydrogen and other gases). The corresponding doping element source gas can be selected according to the desired doping element situation.

[0151] The present invention doped the amorphous silicon layer with hydrogen, and the hydrogen doping methods include: ① silane decomposition; ② hydrogen injection during subsequent film deposition; ③ adding a hydrogen treatment step after depositing the doped amorphous silicon layer; ④ introducing hydrogen while introducing silane. In the present invention, at least one of the above methods can be selected according to the desired concentration of hydrogen doping, as long as the target doping concentration can be obtained.

[0152] In the present invention, the flow rate of the corresponding doping element gas source can be adjusted according to the target doping amount of the doping gas required. Preferably, the silane flow rate is 1-10slm, the nitrous oxide flow rate is 1-10slm, and the methane flow rate is 2-30slm. It is further preferred that phosphine is introduced in the form of a hydrogen-diluted mixed gas, and the flow rate of hydrogen-diluted phosphine (hydrogen flow rate accounts for 90%-99%) is 1-10slm. The deposition time is until the target film layer of the target thickness is reached.

[0153] In some preferred embodiments of the present invention, the deposition conditions of the silicon dielectric anti-reflection layer include: a process pressure of 100-500 Pa and a power of 5-20 kW. During the deposition of the silicon dielectric anti-reflection layer, a desired target gas may be introduced as long as a target film layer can be obtained, for example, a process gas containing silane, ammonia, hydrogen or laughing gas may be introduced.

[0154] In the present invention, preferably, controlling the hydrogen content of the first tunnel oxide layer near the doped amorphous silicon layer to be greater than the hydrogen content near the substrate can be achieved by at least one of the following methods:

[0155] Method 1: During the deposition of the doped amorphous silicon layer, hydrogen is introduced with a hydrogen flow rate of 0.5-30 slm, more preferably 2-30 slm;

[0156] Mode 2: The preparation method further comprises: performing hydrogen treatment after depositing the doped amorphous silicon layer, the conditions of the hydrogen treatment comprising: introducing hydrogen gas, the hydrogen gas flow rate is 0.5-30 slm, the treatment temperature is 350-600° C., and the treatment time is 1-15 min;

[0157] Method 3: hydrogen is introduced during the deposition of the silicon dielectric anti-reflection layer, and the hydrogen flow rate is 0.5-30 slm. Accordingly, controlling the oxygen content of the first tunneling oxide layer close to the doped amorphous silicon side to be less than the oxygen content close to the substrate side can also be achieved by at least one of the above three methods, that is, regulating the oxygen content by controlling the hydrogen content.

[0158] The formation of the first semiconductor layer, the mask layer, and the second semiconductor layer in the present invention can refer to the methods of the prior art, as long as the corresponding film layer with the required thickness and the required doping amount can be obtained. For example, the corresponding doped silicon layer in the first semiconductor layer can be formed by tubular PECVD, LPCVD or PVD in-situ doping deposition annealing, preferably using a tubular polysilicon deposition furnace for sequential deposition and high-temperature annealing; as long as the annealing temperature in these methods meets the scope of the present invention, they can be used in the present invention to achieve the effect of the present invention, and will not be repeated here.

[0159] In the present invention, the first tunnel oxide layer and the second tunnel oxide layer can be formed by any other existing method such as LPCVD, tubular PECVD, wet method, etc. Preferably, the first tunnel oxide layer, the doped amorphous silicon layer and the silicon dielectric anti-reflection layer are all formed at one time by tubular PECVD equipment.

[0160] The thickness of the mask layer may be, for example, 30-90 nm. The type of the mask layer may be, for example, at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0161] In S104 of the present invention, it is selected whether to perform a step of removing the mask layer outside the first opening region on the back side of the silicon substrate by cleaning as required. For example, the mask layer may be completely removed or partially retained.

[0162] In some preferred embodiments of the present invention, the method for preparing the back contact cell with a specific light-receiving surface passivation further comprises:

[0163] S107, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon substrate to form a second opening region spaced apart from the first opening region;

[0164] S108, depositing a conductive film layer on the back surface obtained in S107;

[0165] S109, performing a third etching opening on a portion of the conductive film layer between the second opening region and the first opening region to form an isolation groove;

[0166] S110, forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the second opening area and the first opening area.

[0167] In a third aspect, the present invention provides a back contact cell with a specific light-receiving surface passivated, which is prepared by the preparation method of the back contact cell with a specific light-receiving surface passivated described in the second aspect. The structure and performance of the back contact cell of the third aspect are the same as those of the back contact cell of the first aspect, and will not be repeated here.

[0168] In a fourth aspect, the present invention provides a photovoltaic module, which includes the back contact cell with a specific light-receiving surface passivated as described in the first aspect, or includes the back contact cell with a specific light-receiving surface passivated as described in the third aspect.

[0169] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0170] Example 1

[0171] A back contact cell with a specific light-receiving surface passivated, the preparation method of which is as follows:

[0172] S101, such as Figure 1 As shown, a silicon substrate 1 (single crystal silicon) is provided, and the silicon substrate 1 is polished and cleaned in sequence;

[0173] S102, such as Figure 2 As shown, a first semiconductor layer and a mask layer 4 are sequentially formed on the back side of the silicon substrate 1, and the first semiconductor layer includes a second tunneling oxide layer 2 and an N-type first doped polysilicon layer 3 sequentially formed on the back side; the thickness of the second tunneling oxide layer 2 is 1.5 nm, the thickness of the first doped polysilicon layer 3 is 100 nm, and the phosphorus content is 0.2 at.%, the first semiconductor layer is formed by high-temperature diffusion annealing after LPCVD deposition, and the mask layer 4 is formed by a tubular PECVD deposition furnace, the high-temperature diffusion annealing temperature is in the range of 800-880°C, and the maximum temperature of the high-temperature diffusion annealing is 880°C; the thickness of the mask layer is 70 nm, and the mask layer is silicon nitride;

[0174] S103, such as Figure 3 As shown, the first semiconductor layer and its corresponding mask layer are etched and opened for the first time on the back surface obtained in S102 to form first opening areas W1 distributed at intervals;

[0175] S104, such as Figure 4 As shown, a texture surface is formed in the first opening area W1 on the back and on the light-receiving surface through texture cleaning, and then the mask layer 4 is completely removed;

[0176] S105, such as Figure 5As shown, a first tunneling oxide layer 5, a doped amorphous silicon layer 6 and an anti-reflection layer 7 are sequentially formed on the light-receiving surface, the first tunneling oxide layer 5 has a thickness of 1 nm, and the first tunneling oxide layer 5, the doped amorphous silicon layer 6 and the anti-reflection layer 7 are formed at one time by tubular PECVD and the deposition temperature is 460° C. The anti-reflection layer 7 is a silicon dielectric film silicon nitride with a thickness of 80 nm.

[0177] When the doped amorphous silicon layer 6 is deposited, the process pressure is 200 Pa, the power is 6 kW, the silane flow rate is 5 slm, the silane to nitrous oxide flow rate ratio is 3:2, the hydrogen flow rate is 0.5 slm, and a layer of oxygen-doped amorphous silicon layer with a thickness of 10 nm is deposited, the band gap is 2.50 eV, and the refractive index corresponding to the wavelength of 600 nm is 2.5; and based on the total amount of the oxygen-doped amorphous silicon layer, the total oxygen content is 28 at.%, and the hydrogen content is 22 at.%. The ratio of silicon to oxygen in the oxygen-doped amorphous silicon layer in atomic percentage is R=2.

[0178] The formation conditions of the first tunnel oxide layer 5 are as follows: oxygen is introduced with an oxygen flow rate of 2 slm and a pressure of 0.5e2 Pa, and the temperature is kept constant for 10 minutes under the set process temperature conditions.

[0179] Deposition conditions of the anti-reflection layer 7: 2 slm of silane, 14 slm of ammonia, and 5 slm of hydrogen, the process pressure is 200 Pa, the power is 10 kW, and the hydrogen content in the anti-reflection layer 7 is 15 at.%.

[0180] S106, such as Figure 6 As shown, a second semiconductor layer is formed on the back surface obtained in S105, and the second semiconductor layer includes an intrinsic amorphous silicon layer 8 and a P-type second doped amorphous silicon layer 9 sequentially formed on the back surface; the intrinsic amorphous silicon layer 8 has a thickness of 7 nm, the second doped amorphous silicon layer 9 has a thickness of 10 nm, and a boron content of 0.1 at.%, and the second semiconductor layer is deposited by plate-type PECVD technology at a deposition temperature of 200°C;

[0181] S107, such as Figure 7 As shown, a second etching opening is performed in the polished area of ​​the back surface obtained in S106 (i.e., the interval area where the first semiconductor layer and the second semiconductor layer overlap) to expose the first semiconductor layer, thereby forming a second opening area W2 spaced apart from the first opening area W1;

[0182] S108, such as Figure 8 As shown, a transparent conductive film layer 10 is formed on the back side to fully cover the back side;

[0183] S109, such as Fig. 9 As shown, the transparent conductive film layer 10 located between the second opening area W2 and the first opening area W1 on the back side is etched for the third time to form an isolation groove W3;

[0184] S110, such as Fig.10 As shown, metal electrodes 11 are respectively formed on the outer surfaces of the second opening area W2 and the first opening area W1 corresponding to the back surface.

[0185] The film layers on the light-receiving surface of the silicon substrate in the obtained back contact cell were tested by time-of-flight secondary ion mass spectrometry. The spectrum is shown in Fig.11 As shown, from Fig.11 It can be seen that the hydrogen content of the first tunneling oxide layer 5 near the doped amorphous silicon layer 6 is greater than the hydrogen content near the silicon substrate 1, and the oxygen content of the first tunneling oxide layer 5 near the doped amorphous silicon layer 6 is less than the oxygen content near the silicon substrate 1. The hydrogen content of the first tunneling oxide layer 5 is 5-15at.% (i.e., corresponding to its minimum and maximum values, and the same applies to the others), and the oxygen content is 55-66at.%.

[0186] Example 2

[0187] The method of Example 1 is referred to, except that the doped amorphous silicon layer in S105 is a total of two oxygen-doped amorphous silicon layers with different bandgap widths, the silane flow rate remains unchanged, and the ratio of silane to nitrous oxide is controlled to be 3:1 when the first layer is deposited. The first oxygen-doped amorphous silicon layer has a bandgap of 2.2 eV, a thickness of 3 nm, and a refractive index of 3.7 at a wavelength of 600 nm. When the second layer is deposited, the ratio of silane to nitrous oxide is 1:1, and the second oxygen-doped amorphous silicon layer has a bandgap of 3.5 eV, a thickness of 7 nm, and a refractive index of 2.3 at a wavelength of 600 nm. Based on the total amount of the doped amorphous silicon layer, the total content of oxygen is 31 at.%, and the content of hydrogen is 21 at.%. According to calculation, the ratio of the bandgap widths of the first and second layers of the oxygen-doped amorphous silicon layer is 1:1.59, and the ratio of their thicknesses is 1:2.3. The ratios R of silicon to oxygen in atomic percentage corresponding to the first layer and the second layer of the oxygen-doped amorphous silicon layer are 2.2 and 1.8 respectively.

[0188] Example 3

[0189] The method of Example 2 is followed, except that the thickness of the second layer of the oxygen-doped amorphous silicon layer is adjusted to be the same as the thickness of the first layer, but the respective band gap widths remain unchanged, that is, the thickness ratio of the first layer to the second layer is 1:1. To meet this condition, the deposition time of the second amorphous layer is adjusted accordingly to a thickness of 3 nm.

[0190] Example 4

[0191] The method of Example 2 is referred to, except that the first oxygen-doped amorphous silicon layer is not deposited in S105, that is, the doped amorphous silicon layer in S105 is one layer: the second oxygen-doped amorphous silicon layer of Example 2 has a bandgap of 3.5 eV, a thickness of 10 nm, and a refractive index of 2.3 at a wavelength of 600 nm. The deposition process parameters that need to be adjusted to meet this condition are: adjusting the deposition time of the second amorphous layer to a thickness of 10 nm.

[0192] Example 5

[0193] The method of Example 1 is referred to, except that the doped amorphous silicon layer in S105 is also doped with phosphorus, and accordingly, hydrogen-diluted phosphine (hydrogen flow accounts for 98%) is also introduced during the deposition process, and its flow rate makes the flow ratio of silane: nitrous oxide: hydrogen-diluted phosphine mixed gas be 3:2:1, and the resulting doped amorphous silicon layer has a band gap of 2.45 eV, a thickness of 10 nm, and a refractive index of 2.6 at a wavelength of 600 nm. Based on the total amount of the doped amorphous silicon layer, the total content of oxygen is 24 at.%, the content of hydrogen is 26 at.%, and the content of phosphorus is 0.2 at.%. The ratio of silicon to oxygen in the doped amorphous silicon layer in atomic percentage is R=1.9.

[0194] Example 6

[0195] The method of Example 1 is referred to, except that the doped amorphous silicon layer in S105 is also doped with carbon, and correspondingly methane is also introduced during the deposition process, and the methane flow rate is such that the silane:methane flow rate ratio is 1:3, and the resulting doped amorphous silicon layer has a band gap of 2.3 eV, a thickness of 10 nm, a refractive index of 3.2 at a wavelength of 600 nm, and, based on the total amount of the doped amorphous silicon layer, a total oxygen content of 20 at.%, a hydrogen content of 20 at.%, and a carbon content of 10 at.%.

[0196] Example 7

[0197] The method of Example 6 is referred to, except that the doped amorphous silicon layer in S105 is a total of two carbon-doped amorphous silicon layers with different bandgap widths. Specifically, the second layer of doped amorphous silicon is continuously deposited on the outer surface of the doped amorphous silicon layer of Example 6. When depositing the second layer, the methane flow rate is controlled so that the silane:methane flow rate ratio is 1:6. The second layer of doped amorphous silicon layer has a bandgap width of 2.4 eV, a thickness of 2 nm, and a refractive index of 2.8 at a wavelength of 600 nm. Based on the total amount of the two doped amorphous silicon layers, the hydrogen content is 20 at.%, the carbon content is 11 at.%, and the oxygen content is 19 at.%. According to calculation, the ratio of the bandgap widths of the first layer and the second layer of the doped amorphous silicon layer is 1:1.04, and the ratio of their thicknesses is 1:0.2.

[0198] Example 8

[0199] The method of Example 7 is followed, except that the thickness of the second layer of the doped amorphous silicon layer is adjusted to be the same as the thickness of the first layer, and the bandgap width remains unchanged, that is, the thickness ratio of the first layer to the second layer is 1:1. To meet this condition, the deposition time of the first and second amorphous layers needs to be adjusted until the thickness of each layer is 5 nm.

[0200] Example 9

[0201] The method of Example 1 is referred to, except that in S105, the silicon content is adjusted so that the ratio of silicon to oxygen in the doped amorphous silicon layer in atomic percentage is R=1.2. To meet this condition, corresponding adjustments are made during the deposition process: the silane flow rate is adjusted so that the ratio of silane to nitrous oxide is adjusted to 1:1.

[0202] Example 10

[0203] The method of Example 1 is referred to, except that the thickness of the first tunnel oxide layer is 1.5 nm, and the ratio of the thickness of the first tunnel oxide layer to the second tunnel oxide layer is calculated to be 1:1. The process parameters that need to be adjusted to meet this condition are: oxygen is introduced at a pressure of 5e2 Pa, and correspondingly, the first tunnel oxide layer, based on the total amount of elements in the first tunnel oxide layer, has a hydrogen content of 7-20 at.%, and an oxygen content of 57-68 at.%.

[0204] Embodiment 11

[0205] The method of Example 1 is referred to, except that hydrogen is not introduced during the deposition of the doped amorphous silicon layer, and the bandgap width of the obtained doped amorphous silicon layer is 2.45 eV, and the refractive index corresponding to the wavelength of 600 nm is 2.7. The ratio of silicon to oxygen in the doped amorphous silicon layer in atomic percentage is R=2.1. Accordingly, the hydrogen content of the first tunneling oxide layer close to the doped amorphous silicon layer is greater than the hydrogen content close to the silicon substrate side, and the oxygen content of the first tunneling oxide layer close to the doped amorphous silicon layer is less than the oxygen content close to the silicon substrate side. The hydrogen content in the first tunneling oxide layer is 3-13 at.%, and the oxygen content is 57-67 at.%.

[0206] Example 12

[0207] The method of Example 1 is referred to, except that hydrogen is not introduced during the deposition of the doped amorphous silicon layer, but hydrogen treatment is performed after the deposition of the doped amorphous silicon layer, and the hydrogen treatment process is as follows: the hydrogen flow rate is 10 slm, the treatment temperature is 460°C, and the treatment time is 10 min. The oxygen-doped amorphous silicon layer has a band gap of 2.6 eV, a constant thickness, a refractive index corresponding to a wavelength of 600 nm of 2.45, and based on the total amount of the doped amorphous silicon layer, the total oxygen content is 29 at.%, and the hydrogen content is 21 at.%.

[0208] The same test shows that the hydrogen content in the first tunneling oxide layer close to the doped amorphous silicon layer is greater than that close to the silicon substrate, and the oxygen content in the first tunneling oxide layer close to the doped amorphous silicon layer is less than that close to the silicon substrate.

[0209] Comparative Example 1

[0210] The method of Example 1 is referred to, except that the doped amorphous silicon layer is replaced by a conventional amorphous silicon film layer. Specifically, the conventional amorphous silicon film layer is: intrinsic amorphous silicon, N-type doped amorphous silicon (doped only with phosphorus, not doped with oxygen) are deposited on the light-receiving surface in sequence, and the first tunneling oxide layer is not deposited. The thickness of the intrinsic amorphous silicon is 6 nm, the thickness of the N-type doped amorphous silicon is 10 nm, the phosphorus content is 0.2 at.%, the bandgap width of the conventional amorphous silicon film layer is 1.75 eV, and the refractive index corresponding to the wavelength of 600 nm is 3.9.

[0211] Comparative Example 2

[0212] The method of Example 1 is referred to, except that the doped amorphous silicon layer is replaced by a conventional light-receiving surface passivation film layer. The specific conventional light-receiving surface passivation film layer is: a first tunneling silicon oxide layer (same as Example 1) and N-type doped polysilicon (only phosphorus-doped, not oxygen-doped) are deposited on the light-receiving surface in sequence. The thickness of the N-type doped polysilicon is 5 nm, the phosphorus content is 0.2 at.%, the band gap width of the N-type doped polysilicon is 1.25 eV, and the refractive index corresponding to the wavelength of 600 nm is 4.2.

[0213] Comparative Example 3

[0214] The method of Example 1 is referred to, except that the doped amorphous silicon layer is not doped with oxygen, but only doped with hydrogen (the hydrogen content is the same as that of Example 1), the band gap of the doped amorphous silicon layer is 1.6 eV, and the refractive index corresponding to the wavelength of 600 nm is 4.1. To meet the condition of not doping with oxygen, the deposition process is adjusted accordingly: the laughing gas flow rate is set to 0 when depositing amorphous silicon.

[0215] Comparative Example 4

[0216] The method of Example 1 is referred to, except that the hydrogen content of the first tunnel oxide layer near the doped amorphous silicon layer is equal to the hydrogen content near the substrate, and the oxygen content change trend remains unchanged. To meet this condition, the deposition process is adjusted accordingly: hydrogen is not passed during the deposition of the anti-reflection layer 7.

[0217] Test Case

[0218] The back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0219] Table 1

[0220]

[0221] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can take into account both better passivation effect and optical loss, play a role in enhancing passivation, thereby improving the battery passivation effect and current, and further improving the battery efficiency.

[0222] Furthermore, according to Example 1 and Examples 2-12, it can be seen that the preferred battery structure of the present invention is more conducive to improving the battery passivation effect and current, thereby improving the battery efficiency.

[0223] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A back contact cell with a specific light-receiving surface passivated, comprising a substrate, the substrate having a backlight surface and a light-receiving surface, characterized in that: A first tunneling oxide layer, a doped amorphous silicon layer and a silicon dielectric anti-reflection layer are sequentially arranged on the light-receiving surface of the substrate, the first tunneling oxide layer contacts the light-receiving surface of the substrate, the thickness of the first tunneling oxide layer is 0.2-1.3nm, the doped amorphous silicon layer is doped with oxygen and hydrogen, the first tunneling oxide layer is doped with hydrogen, wherein the hydrogen content of the first tunneling oxide layer close to the doped amorphous silicon layer is greater than the hydrogen content close to the substrate; the doped amorphous silicon layer, based on the total amount of elements in the doped amorphous silicon layer, has an oxygen content of 5-60 at.%, and a hydrogen content of 1-35 at.%; the first tunneling oxide layer, based on the total amount of elements in the first tunneling oxide layer, has a hydrogen content of 1-20 at.%.

2. The back contact cell with specific light-receiving surface passivation according to claim 1, characterized in that: The hydrogen content of the doped amorphous silicon layer is greater than the arithmetic mean of the hydrogen content in the first tunnel oxide layer.

3. The back contact cell with specific light-receiving surface passivation according to claim 1, characterized in that: The oxygen content of the first tunnel oxide layer on the side close to the doped amorphous silicon layer is less than the oxygen content of the first tunnel oxide layer on the side close to the substrate.

4. The back contact cell with specific light-receiving surface passivation according to claim 1, characterized in that: The oxygen content in the first tunnel oxide layer is 55-68at.%.

5. The back contact cell with specific light-receiving surface passivation according to claim 1, characterized in that: The silicon dielectric anti-reflection layer is doped with hydrogen element.

6. The back contact cell with specific light-receiving surface passivation according to claim 5, characterized in that: The hydrogen content of the silicon dielectric anti-reflection layer is less than or equal to the hydrogen content of the doped amorphous silicon layer.

7. The back contact cell with specific light-receiving surface passivation according to claim 5, characterized in that: The hydrogen content of the silicon dielectric anti-reflection layer is greater than or equal to the arithmetic mean value of the hydrogen content in the first tunneling oxide layer.

8. The back contact cell with specific light-receiving surface passivation according to claim 5, characterized in that: The silicon dielectric anti-reflection layer has a hydrogen content of 1-25 at.%, based on the total amount of elements in the silicon dielectric anti-reflection layer.

9. The back contact cell with specific light-receiving surface passivation according to claim 1, characterized in that: The doped amorphous silicon layer further contains phosphorus and / or carbon. Based on the total amount of elements in the doped amorphous silicon layer, the carbon content is 0-20 at.%, and the phosphorus content is 0-0.5 at.%.

10. The back contact cell with specific light-receiving surface passivation according to claim 9, characterized in that: The phosphorus content in the doped amorphous silicon layer is 0.1 - 0.3 at.%.

11. The back contact cell with specific light-receiving surface passivation according to any one of claims 1 to 10, characterized in that: The bandgap width of the doped amorphous silicon layer is between 1.9 and 6 eV, and the refractive index of the doped amorphous silicon layer at a wavelength of 600 nm is between 2 and 3.

7.

12. The back contact cell with specific light-receiving surface passivation according to any one of claims 1 to 10, characterized in that: The ratio R of silicon to oxygen in the doped amorphous silicon layer in terms of atomic percentage satisfies: 1<R≤2.

2.

13. The back contact cell with specific light-receiving surface passivation according to claim 12, characterized in that: 1.5≤R≤2.2。 14. The back contact cell with specific light-receiving surface passivation according to any one of claims 1 to 10, characterized in that: The substrate is a single crystal silicon substrate.

15. The back contact cell with specific light-receiving surface passivation according to any one of claims 1 to 10, characterized in that: The doped amorphous silicon layer is a single-layer structure.

16. The back contact cell with specific light-receiving surface passivation according to any one of claims 1 to 10, characterized in that: The doped amorphous silicon layer is a multi-layer structure, and the bandgap width corresponding to the multi-layer structure gradually increases in a gradient in the thickness direction outward from the light-receiving surface.

17. The back contact cell with specific light-receiving surface passivation according to claim 16, characterized in that: The ratio of the bandgap width of any layer in the multilayer structure to an adjacent layer relatively far from the light-receiving surface is 1:1.1-5, and the ratio of their thicknesses is 1:0.5-10.

18. The back contact cell with specific light-receiving surface passivation according to any one of claims 1 to 10, characterized in that: The thickness of the doped amorphous silicon layer is 3-40 nm.

19. The back contact cell with specific light-receiving surface passivation according to any one of claims 1 to 10, characterized in that: The silicon dielectric anti-reflection layer is at least one of silicon nitride, silicon oxynitride and silicon oxide, and the thickness of the silicon dielectric anti-reflection layer is 50-120 nm.

20. The back contact cell with specific light-receiving surface passivation according to any one of claims 1 to 10, characterized in that: The backlight surface is provided with a film layer including a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is a stack including a second tunneling oxide layer and a first doped polysilicon layer or a stack including a first intrinsic silicon layer and a first doped silicon layer, and the second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer.

21. The back contact cell with specific light-receiving surface passivation according to claim 20, characterized in that: The first semiconductor layer includes a second tunneling oxide layer and a first doped polysilicon layer, the second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer, and the thickness ratio of the doped amorphous silicon layer to the second tunneling oxide layer is 2-30:

1.

22. The back contact cell with specific light-receiving surface passivation according to claim 20, characterized in that: The first semiconductor layer comprises a second tunneling oxide layer and a first doped polysilicon layer, and the thickness ratio of the first tunneling oxide layer, the doped amorphous silicon layer and the second tunneling oxide layer is 0.1-1:2-30:

1.

23. The back contact cell with specific light-receiving surface passivation according to claim 20, characterized in that: The two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a second opening area not covered by the second semiconductor layer is opened on the back side of the first semiconductor layer, and a first opening area is formed between the adjacent first semiconductor layers. The first opening area and the second opening area are arranged at intervals, and the area between them is the interval area; in the interval area, a mask layer is set between the first semiconductor layer and the second semiconductor layer, or no mask layer is set; the back contact battery also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is opened on the part of the conductive film layer located in the interval area; the metal electrode is set on the outer surface of the conductive film layer corresponding to each of the first opening area and the second opening area.

24. A method for preparing a back contact cell with a specific light-receiving surface passivated, characterized in that: The steps include: Providing a substrate, wherein the substrate has a backlight surface and a light receiving surface; A first tunneling oxide layer, a doped amorphous silicon layer and a silicon dielectric anti-reflection layer are sequentially formed on the light-receiving surface of the substrate, wherein the first tunneling oxide layer contacts the light-receiving surface of the substrate, and the thickness of the first tunneling oxide layer is 0.2-1.3 nm. The doped amorphous silicon layer is doped with oxygen and hydrogen, and the first tunneling oxide layer is doped with hydrogen. The content of hydrogen in the first tunneling oxide layer close to the doped amorphous silicon layer is greater than the content of hydrogen close to the substrate. The doped amorphous silicon layer has an oxygen content of 5-60 at.%, and a hydrogen content of 1-35 at.%, based on the total amount of elements in the doped amorphous silicon layer; the first tunneling oxide layer has a hydrogen content of 1-20 at.%, based on the total amount of elements in the first tunneling oxide layer.

25. The method for preparing a back contact cell with a specific light-receiving surface passivation according to claim 24, characterized in that: The first tunneling oxide layer, the doped amorphous silicon layer and the silicon dielectric anti-reflection layer are deposited at one time by tubular PECVD and the deposition temperature is 350-600°C.

26. The method for preparing a back contact cell with a specific light-receiving surface passivation according to claim 24, characterized in that: The preparation method also includes forming a first semiconductor layer and a second semiconductor layer on the backlight surface of the silicon substrate.

27. The method for preparing a back contact cell with a specific light-receiving surface passivation according to claim 26, characterized in that: The first semiconductor layer is obtained by annealing after deposition and the annealing temperature is 800-950°C.

28. The method for preparing a back contact cell with a specific light-receiving surface passivation according to claim 26, characterized in that: The deposition temperature of the second semiconductor layer is 150-250°C.

29. The method for preparing a back contact cell with a specific light-receiving surface passivation according to claim 26, characterized in that: The preparation method specifically comprises the following steps: S101, providing a double-sided polished silicon substrate; S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon substrate; S103, performing a first etching opening on the back surface obtained in S102 to form a first opening area; S104, then performing texturing and cleaning to form a texturing surface on the light-receiving surface of the silicon substrate and the first opening area, and then selecting whether to perform a step of removing the mask layer outside the first opening area on the back side of the silicon substrate by cleaning according to needs; S105, sequentially depositing a first tunneling oxide layer, a doped amorphous silicon layer and a silicon dielectric anti-reflection layer on the light-receiving surface of the silicon substrate; the first tunneling oxide layer is doped with hydrogen, and the hydrogen content of the first tunneling oxide layer close to the doped amorphous silicon layer is controlled to be greater than the hydrogen content close to the substrate, and the doped amorphous silicon layer is doped with oxygen and hydrogen; S106, depositing a second semiconductor layer on the back surface obtained in S105.

30. The method for preparing a back contact cell with a specific light-receiving surface passivation according to claim 24 or 29, characterized in that: The formation conditions of the first tunnel oxide layer include: introducing a gas containing an oxygen source at a pressure of 0.5e2 Pa-1e5 Pa, and maintaining the temperature at a set process temperature for 1-30 minutes; The deposition conditions of the doped amorphous silicon layer include: a process pressure of 100-500 Pa, a power of 2-15 kW, and a process gas containing silane and a gas source of a desired doping element; The deposition conditions of the silicon dielectric anti-reflection layer include: process pressure of 100-500 Pa and power of 5-20 kW.

31. The method for preparing a back contact cell with a specific light-receiving surface passivation according to claim 24, characterized in that: Controlling the hydrogen content of the first tunnel oxide layer near the doped amorphous silicon layer to be greater than the hydrogen content near the substrate is achieved by at least one of the following methods: Method 1: hydrogen is introduced during the deposition of the doped amorphous silicon layer and the hydrogen flow rate is 0.5-30 slm; Mode 2: The preparation method further comprises: performing hydrogen treatment after depositing the doped amorphous silicon layer, the conditions of the hydrogen treatment comprising: introducing hydrogen gas, the hydrogen gas flow rate is 0.5-30slm, the treatment temperature is 350-600°C, and the treatment time is 1-15min; Method 3: hydrogen gas is introduced during the deposition of the silicon dielectric anti-reflection layer, and the hydrogen gas flow rate is 0.5-30 slm.

32. The method for preparing a back contact cell with a specific light-receiving surface passivation according to claim 29, characterized in that: The method for preparing the back contact cell with passivated specific light-receiving surface also includes: S107, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon substrate to form a second opening region spaced apart from the first opening region; S108, depositing a conductive film layer on the back surface obtained in S107; S109, performing a third etching opening on a portion of the conductive film layer between the second opening region and the first opening region to form an isolation groove; S110, forming metal electrodes on the outer surfaces of the conductive film layers corresponding to the second opening area and the first opening area.

33. A back contact cell with a specific light-receiving surface passivated, characterized in that: It is prepared by the method for preparing a back contact cell with a specific light-receiving surface passivated as described in any one of claims 24-32.

34. A photovoltaic module, characterized in that: It comprises a back contact cell with a specific light-receiving surface passivated as claimed in any one of claims 1 to 23, or comprises a back contact cell with a specific light-receiving surface passivated as claimed in claim 33.

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