Semiconductor device and method of manufacturing semiconductor package with graphene for die attachment

Abstract

A semiconductor device has a substrate with a die pad. A conductive material is disposed on the die pad. The conductive material includes a plurality of graphene coated metal balls in a matrix. A semiconductor die is disposed over the conductive material. The conductive material is sintered using an infrared laser. A bond wire is formed between the semiconductor die and the substrate. An encapsulant is deposited over the semiconductor die and the bond wire.

Description

[0001] Domestic priority claim

[0002] This application is a continuation-in-part of U.S. patent application No. 18 / 064,149, filed on December 9, 2022, which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device and method of manufacturing a semiconductor package having graphene for die attach. Background Art

[0004] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide variety of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronics, power conversion, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0005] Semiconductor devices, especially in high-power applications, typically contain one or more semiconductor dies or integrated passive devices (IPDs) to perform the necessary electrical functions. The semiconductor die may contain power devices, such as power transistors, that are capable of conducting large currents at high voltages in high-stress environments. One or more semiconductor dies and / or IPDs may be mounted to a lead frame or other substrate for structural support and electrical interconnection. Encapsulant is deposited on the semiconductor die, IPDs, and lead frame to form a semiconductor package, such as a quad flat no-lead (QFN).

[0006] The semiconductor die and / or IPD must be bonded to the lead frame with sufficient strength to maintain the physical integrity of the package under normal operating conditions, such as high current, high voltage, high frequency and high stress environments found in power applications. Power applications can be robots, solar cells, the Internet of Things (IoT), aerosols and automobiles, including electric vehicles. The semiconductor die can perform voltage conversion and wave number changes. High stress involves high temperature, vibration and physical shock. Given the extreme operating environment, the bonding material (e.g., Ag epoxy) between the semiconductor die and the lead frame must have high reliability for the thermal and physical conditions of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1a-1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0008] Figure 2a-2g A process of forming a semiconductor package is illustrated;

[0009] Figure 3 An adhesive layer comprising a graphene core shell within a matrix is ​​illustrated;

[0010] Figure 4 Another embodiment of an adhesive layer comprising a graphene core shell within a matrix is ​​illustrated;

[0011] Figure 5a-5c The process of forming a graphene core-shell is illustrated;

[0012] Figure 6 Another semiconductor package using an adhesive layer comprising a graphene core shell within a matrix is ​​illustrated;

[0013] Figure 7 A further semiconductor package using an adhesive layer comprising a graphene core shell within a matrix is ​​illustrated;

[0014] Figure 8a -8c illustrates yet another semiconductor package using an adhesive layer comprising a graphene core shell within a matrix;

[0015] Figure 9a-9l illustrates another process of forming a semiconductor package having a graphene-based layer for die attach; and

[0016] Fig.10a and 10b The diagram illustrates the integration of a semiconductor package into an electronic device. DETAILED DESCRIPTION

[0017] The present invention is described in one or more embodiments in the following description with reference to the figures, wherein the same numerals represent the same or similar elements. Although the present invention is described with respect to the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have similar functions to each other. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0018] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between voltage and current necessary to perform the circuit function.

[0019] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scribed and broken along the non-functional areas of the wafer (called saw streets or scribes). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads in the semiconductor package. Electrical connection can be achieved with a conductive layer, a bump, a columnar bump, a conductive paste, or a wire bond. An encapsulant or other molding material is deposited on the semiconductor package to provide physical support and electrical isolation. The completed semiconductor package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0020] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100 separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0021] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, wherein the active surface 110 includes analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers, which are formed on or within the die and are electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as digital signal processors (DSPs), application specific integrated circuits (ASICs), memories, power devices, or other signal processing circuits. The semiconductor die 104 may also include an IPD for RF signal processing, such as an inductor, a capacitor, and a resistor. In some embodiments, the semiconductor die 104 is a photo-reactive device. The active surface 110 may have a light emitting diode (LED) formed thereon to emit light or be photosensitive by including a photodiode or a phototransistor.

[0022] Conductive layer 112 is formed on active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0023] exist Figure 1c , a saw blade or laser cutting tool 118 is used to singulate the semiconductor wafer 100 through the saw streets 106 into individual semiconductor dies 104. The individual semiconductor dies 104 may be inspected and electrically tested for identification of known good dies (KGD) or known good units (KGU) after singulation.

[0024] Figure 2a-2g A process for using a graphene core shell within an adhesive layer for die attach in a semiconductor package is illustrated; Figure 2a A cross-sectional view of a substrate 120 is shown. In one embodiment, the substrate 120 is a lead frame having a flag or die mounting site 122 having a top surface 124 and a bottom surface 126 opposite the top surface. A pad 128 is located around the flag 122. The lead frame embodiment of the substrate 120 is part of a quad flat no-lead (QFN) type semiconductor package useful in power applications such as robotics, solar cells, IoT, aerosols, and automotive, including electric vehicles. Figure 2b 1 is a top view of a substrate 120 showing a flag 122 and pads 128 interconnected by support bars 129 forming a lead frame. Alternatively, the substrate 120 may be a semiconductor wafer or panel substrate having a base substrate material such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, or silicon carbide for structural support.

[0025] exist Figure 2c In the embodiment of the present invention, a graphene filler adhesion layer 130 is deposited on a surface 124 of a logo 122 of a substrate 120. The graphene filler adhesion layer 130 is discussed below.

[0026] exist Figure 2d , use pick and place operations to move objects from Figure 1c The semiconductor die 104 is disposed on the adhesive layer 130. Starting from the back side 108, the semiconductor die 104 is placed in contact with the graphene filler adhesive layer 130. The adhesive layer 130 is cured to fix the semiconductor die 104 to the flag 122, such as Figure 2e As shown in .

[0027] exist Figure 2fIn the embodiment shown in FIG. 1 , a bonding wire 136 is placed between the conductive layer 112 on the semiconductor die 104 and the pad 128 of the lead frame substrate 120. Each end of the bonding wire 136 is reflowed to make a mechanical and electrical connection between the conductive layer 112 and the pad 128.

[0028] exist Figure 2g In the process, an encapsulant or molding compound 138 is deposited on and around semiconductor die 104 and substrate 120 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. Encapsulant 138 can be a liquid or particulate polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with a suitable filler. Encapsulant 138 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0029] Support segments 129 are severed, leaving pads 128 electrically isolated from one another. The combination of substrate 120 , semiconductor die 104 , and encapsulant 138 form a semiconductor package 139 .

[0030] Figure 3 Shown from Figure 2g In one embodiment, the bonding layer 130 includes a plurality of cores 140, wherein the graphene coating 142 is embedded in a matrix 144, such as Figure 3 . The matrix 144 may be a thermosetting material, such as an adhesive or epoxy with a binder and a filler, the filler comprising silicon, alumina, aluminum, aluminum zinc oxide, or other materials with good bonding and thermal properties. The matrix 144 may be a thermal grease, such as silicon or a polymer type, such as polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET). The core 140 may be copper, nickel, a phase change material (PCM), or other suitable metal or similar material. The core 140 is arranged within the matrix 144 so that most (if not all) of the graphene coating 142 covering the core contacts at least one adjacent graphene coating to form a continuous and connected path 146 of the graphene coating between the top surface 124 of the lead frame flag 122 and the surface 108 of the semiconductor die 104. The first graphene coating 142 contacts the second adjacent graphene coating, which in turn contacts the third adjacent graphene coating, and so on, to form a continuous and connected path 146. Core 140 has sufficient density so that most, if not all, of the graphene coating around the core contacts at least one graphene coating around an adjacent core, and typically contacts the graphene coatings of multiple adjacent cores. In one embodiment, continuous and connected path 146 is a thermal path for dissipating heat away from semiconductor package 139.

[0031] In another embodiment, Figure 4 Shown from Figure 2g 144 or 147. In this case, the matrix 147 is a solder containing one or more elements of tin, lead (Pb), or indium (In). Again, the core 140 can be Cu, Ni, PCM, or other suitable metal or similar material. Each core 140 as embedded in the matrix 144 or 147 is surrounded or covered by a graphene coating or shell 142. In one embodiment, a graphene slurry or ink is formed around the Cu core as a graphene core shell 158. An adhesion layer 148 such as Cu / SuS, titanium (Ti), or Ag is formed on the matrix 147 to contact the surface 108 of the semiconductor die 104.

[0032] The cores 140 are arranged within the matrix 147 such that most, if not all, of the graphene coating 142 covering the cores contacts at least one adjacent graphene coating to form a continuous and connected path 149 of the graphene coating between the top surface 124 of the lead frame flag 122 and the adhesive layer 148 at the surface 108 of the semiconductor die 104. The graphene coating 142 of each core 140 contacts the graphene coating of an adjacent core. A first graphene coating 142 contacts a second adjacent graphene coating, which in turn contacts a third adjacent graphene coating, and so on, to form a continuous and connected path 149. The cores 140 have sufficient density such that most, if not all, of the graphene coating around the cores contacts at least one graphene coating around an adjacent core, and typically contacts the graphene coatings of a plurality of adjacent cores.

[0033] Figure 5a-5c Shown are further details of the core 140, graphene coating 142, and graphene core shell 158. In one embodiment, the core 140 is Cu, Ni, PCM, or other suitable metal or similar material. Figure 5b A graphene coating 142 formed on and around a surface 150 of a core 140 is illustrated. Figure 5cMore details of the graphene coating 142 formed as a mesh network around the surface 150 of the core 140 are illustrated, collectively referred to as a graphene core shell 158. Graphene 142 is an allotrope of carbon, having one or more layers of carbon atoms, each arranged in a two-dimensional (2D) honeycomb lattice. The graphene coating 142 can be formed by CVD. The core 140 is placed in a chamber heated to 900-1080°C. A gas mixture of CH4 / H2 / Ar is introduced into the chamber to start the CVD reaction. As the CVD reaction separates carbon atoms from hydrogen atoms, the carbon source decomposes in the high temperature reaction chamber, leaving the graphene coating 142 on the surface 150 of the core 140. The release of carbon atoms on the core 140 forms a continuous sheet of the graphene coating 142. Additional information related to the formation of a graphene coating by CVD is disclosed in U.S. Patent 8535553 and is incorporated herein by reference.

[0034] The core 140 is a PCM capable of phase transition from solid to liquid or from liquid to solid within the operating temperature range of the semiconductor chip (eg, 20-200° C.). A first coating 154 is formed around the PCM core 140. Figure 5b 1465616B1 and discussed in published Korean application KR101465616B1. The first coating 154 may be a polymer intermediate layer. The second coating 142 is formed on the first coating 154. Substrates 144, 147 having a graphene-covered core are further disclosed in U.S. Pat. No. 10421123, and are incorporated herein by reference in their entirety.

[0035] The properties of graphene are summarized in Table 1, as follows:

[0036] parameter

[0037] Electron mobility 2x10 5 cm 2 V -1 s -1

[0038] Current density 10 9 Acm -1

[0039] Fermion (electron) speed 10 6 ms -1

[0040] Thermal conductivity 4000-5000Wm -1 K -1

[0041] Tensile strength: 1.5Tpa

[0042] Destruction strength 42Nm -1

[0043] Transparency 97.7%

[0044] Elasticity limit 20%

[0045] Surface area 2360m 2 g -1

[0046] Table 1 - Properties of graphene

[0047] Graphene 142 has ten times the conductivity of copper. Graphene 142 enables epoxy to exhibit conductivity similar to Ag while reducing or eliminating oxidation. Core shell 158 with Cu and graphene epoxy is low cost compared to sputtering. Graphene 142 has low moisture permeability and 4000-5000W m -1 K -1 The high thermal conductivity of carbon is 10 times that of Cu at room temperature. Since carbon also has good solderability and wettability of solder paste, the bonding layer 130 can be easily formed. The graphene 142 exhibits a high degree of flexibility and remains stable to prevent warping. The bonding layer 130 with the graphene Cu shell 158 improves the die attachment properties and conductivity while reducing manufacturing costs.

[0048] In another embodiment, semiconductor package 160 uses a lead frame substrate 162 having markings 164a and 164b and pads 168a and 168b, similar to lead frame substrate 120, but having multiple markings for mounting multiple semiconductor dies, such as Figure 6 Similar to Figure 2c , an adhesive layer 170 is deposited on the marks 164a and 164b. The adhesive layer 170 is similar to the adhesive layer 130 and includes a matrix and a core shell, such as Figure 3 -5. Similar to Figure 2d-2e , semiconductor die 172 is attached to adhesive layer 170 on flag 164a. Conductive layer 174 connected to the active surface of semiconductor die 170 is coupled to pad 168a using wire bonds 176. Figure 2d-2e , semiconductor die 180 is attached to adhesive layer 178 on the active surface of semiconductor die 172. Adhesion layer 178 can be similar to adhesion layer 130, including a matrix and a core shell, such as Figure 3 -5. Adhesive layer 178 may be other types of adhesive materials, such as epoxy. Each end of bonding wire 176 is reflowed to make mechanical and electrical connections between conductive layer 174 and pad 168a. Although having different forms and functions, semiconductor die 172, 180, and 190 may be similar to those from Figure 1a-1c of chip.

[0049] Similar to Figure 2d-2e, semiconductor die 190 is attached to adhesive layer 170 on flag 164b. Conductive layer 192 connected to the active surface of semiconductor die 190 is coupled to pad 168b with wire bond 194. Conductive layer 184 connected to the active surface of semiconductor die 180 is coupled to conductive layer 192 on semiconductor die 190 with wire bond 188. Each end of bond wires 188 and 194 is reflowed to make mechanical and electrical connections between semiconductor die 180 and 190 and lead frame substrate 162. Adhesive layer 170 with matrix and graphene core shell provides improved die attach properties for semiconductor die 172 and 190, such as for Figure 3 -5 as described with respect to the adhesive layer 130.

[0050] The sealant or molding compound 196 is deposited on and around the semiconductor die 170, 180, and 190 and the lead frame substrate 162 using slurry printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 196 can be a liquid or particulate polymer composite material, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with appropriate fillers. The sealant 196 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0051] In another embodiment, if Figure 7 As shown in FIG. 2 , semiconductor package 200 uses a substrate 204 having a base substrate material, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, for structural support. Figure 2c , an adhesive layer 208 is deposited on the surface 206 of the substrate 204. Figure 3 -5, bonding layer 208 is a die attach feature similar to bonding layer 130, comprising a matrix and a core shell.

[0052] The electrical components 202a-202e are disposed on the surface 206 of the substrate 204. Specifically, similar to Figure 2d-2e , using adhesive layer 208 to place electrical components 202b and 202c on surface 206. Although having different forms and functions, electrical components 202b-202d can be similar to those from Figure 1c The semiconductor die 104 of FIG. 20 is a semiconductor die 104. The electrical components 202a and 202e may be discrete electrical devices or IPDs, such as diodes, transistors, resistors, capacitors, and inductors. Alternatively, the electrical components 202a-202e may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs). Figure 3As described above with the bonding layer 130 in Figure 5, the bonding layer 208 having the matrix and the graphene core shell provides improved die attach properties for the electrical components 202b and 202c.

[0053] Bond wires 210 electrically connect electrical components 202b and 202c to substrate 204. Use paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators to deposit sealant or molding compound 212 on and around electrical components 202a-202e and substrate 204. Sealant 212 can be a liquid or particulate polymer composite material, such as epoxy resin with fillers, epoxy acrylate with fillers, or polymer with appropriate fillers. Sealant 212 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0054] In another embodiment, substrate 222 includes a base substrate material 226 for structural support, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, or silicon carbide, as in Figure 8a 2. In one embodiment, substrate 222 is a PCB. Conductive vias 230 are formed through base substrate material 226. Conductive layer 234 is formed on surface 236 of substrate 222 and is electrically and thermally connected to conductive vias 230. Heat sink 238 is formed on conductive layer 234 to provide heat dissipation from the package. Heat sink 238 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable thermally conductive materials to dissipate heat generated by electrical components 244a-244e. Conductive layer 240 is formed on surface 242 of substrate 222 and is electrically and thermally connected to conductive vias 230.

[0055] exist Figure 8b In the embodiment, a lead frame module 256 is formed using a lead frame substrate 243 including a logo and a pad. Electrical components 244b and 244c are attached to the logo of the lead frame substrate 243 using an adhesive layer 250. Figure 3 -5, so that the bonding layer 250 is similar to the bonding layer 130, including a matrix and a core shell. The bonding wires 252 electrically connect the electrical components 244b and 244c to the pads of the lead frame substrate 243. Similar to Figure 2a-2e , encapsulant 254 is deposited over electrical components 244 b and 244 c , bond wires 252 , and leadframe substrate 243 , providing leadframe module 256 .

[0056] Adhesion layer 246 is deposited on conductive layer 240. Adhesion layer 246 is similar to adhesion layer 130, including a matrix and a core shell, such as Figure 3-5. A pick and place operation is used to position electrical components 244a-244e on the surface 242 of the substrate 222, where electrical components 244b and 244c are part of the lead frame module 256. Electrical components 244a, 244d, and 244e are then reflowed to attach to the conductive layer 240 on the substrate 222. Electrical components 244a, 244d, and 244e are individual semiconductor dies or discrete devices. Electrical components 244b and 244c, which are part of the lead frame module 256, are attached to the conductive layer 240 with an adhesive layer 246. Although having different forms and functions, electrical components 244b, 244c, and 244d can be similar to those from Figure 1c The semiconductor die 104 of FIG. 244 is shown in FIG. 244b and FIG. 244e. The electrical components 244a and 244e may be discrete electrical devices or IPDs, such as diodes, transistors, resistors, capacitors, and inductors. Alternatively, the electrical components 244a-244e may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or IPDs. FIG. 8c shows the electrical components 244a-244e mounted to the substrate 222 as a semiconductor package 220 (wherein the electrical components 244b and 244c are part of the lead frame module 256).

[0057] The bonding layers 246 and 250 having the matrix and graphene core shell provide improved die attach properties for the electrical components 244b and 244c and the substrate 243, such as Figure 3 -5 for the bonding layer 130. In addition, due to the graphene Cu core shell, the bonding layers 246 and 250 have good electrical conductivity and high thermal conductivity. The electrical components 244b and 244c can be electrically connected through the bonding wire 252, the lead frame pad, the bonding layer 246, the conductive layer 240 and the conductive via 230. The heat generated from the lead frame module 256 is conducted through the bonding layers 246 and 250, the conductive layer 234, and is dissipated by the heat sink 238.

[0058] An adhesive layer such as 130 having a graphene core shell such as 158 distributed in a matrix 144 is beneficial for die attachment. The same is true for adhesive layers 170, 208, 246, and 250. The graphene core adhesive layer provides excellent heat dissipation, shock absorption, and vibration damping. The graphene core adhesive layer can be used in power applications such as automotive to support physical stress, vibration, temperature changes, high voltage, high power, and high frequency operation.

[0059] Figure 9a-9l Another process of forming a semiconductor package having a graphene-based layer for die attach is illustrated. Figure 9aA cross-sectional view of a multilayer interconnect substrate 320 including conductive layers 322 and insulating layers 324 is shown. Although only a single substrate 320 suitable for forming three semiconductor packages separated by saw streets 321 is shown, hundreds or thousands of units are typically manufactured and processed as part of a single substrate 320 using the same steps performed as a whole as described herein before being singulated from one another. A separate substrate 320 may also be used for each unit manufactured, with the substrate being Figure 9a The steps shown are previously singulated, and multiple individual substrates are placed on a common carrier for processing.

[0060] Conductive layer 322 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductive layer 322 may be formed using PVD, CVD, electrolytic plating, electroless plating, or another suitable metal deposition process. Conductive layer 322 provides horizontal electrical interconnection across substrate 320 and vertical electrical interconnection between top surface 326 and bottom surface 328 of substrate 320. Portions of conductive layer 322 may be electrically shared or electrically isolated, depending on the design and function of the package being formed.

[0061] The insulating layer 324 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 324 provides physical support for the conductive layer 322 and electrical isolation between the conductive layers 322. Any number of conductive layers 322 and insulating layers 324 can be interlaced on each other to form the substrate 320. In other embodiments, any other suitable type of packaging substrate or lead frame is used for the substrate 320.

[0062] Conductive layer 322 includes a plurality of contact pads formed on bottom surface 328 of substrate 320 for external interconnection of the final package. On top surface 326, conductive layer 322 includes die pad 322a for mounting semiconductor die and a plurality of contact pads 322b for wire bonding semiconductor die to substrate 320. Contact pad 322b may also be present to surface mount additional electrical components to top surface 326, such as discrete active or passive electrical components or additional semiconductor die. Die pad 322a has a footprint size and shape similar to the semiconductor die to be mounted, but may be slightly larger or smaller.

[0063] exist Figure 9b, a conductive material 330 is applied to the die pad 322a. In some embodiments, the conductive material 330 is a paste including graphene-coated silver, graphene-coated copper, or a combination of graphene-coated silver and graphene-coated copper. The conductive material 330 is deposited by aerosol jet printing of a graphene-based conductive ink with a dispenser 332, by electrohydrodynamic (EHD) jet printing, or by another suitable means. The die pad 322a can be completely covered with the conductive material 330 or only partially covered.

[0064] Fig.9c Detail of one of the graphene coated metal balls 358 of the conductive material 330 is shown. The graphene coated metal ball 358 is formed of a core 360 ​​and a graphene shell or coating 362 formed on and around the core. In one embodiment, the core 360 ​​is Cu, Ag, Ni, a phase change material (PCM), or other suitable metal or similar material. In some embodiments, a mixture of some copper cores 360 and some silver cores 360 is used. Fig.9c The details of the graphene shell 362 formed as a mesh network around the core 360 ​​are illustrated. The graphene shell 362 is an allotrope of carbon, having one or more layers of carbon atoms, each arranged in a two-dimensional (2D) honeycomb lattice. The graphene shell 362 can be formed by CVD, wet chemical synthesis or other suitable means. In some embodiments, a plurality of graphene coatings 362 are formed on each core 360.

[0065] For CVD, the core 360 ​​is placed in a chamber heated to 900-1080° C. A gas mixture of CH4 / H2 / Ar is introduced into the chamber to start the CVD reaction. As the CVD reaction separates carbon atoms from hydrogen atoms, the carbon source decomposes in the high temperature reaction chamber, leaving a graphene shell 362 on the core 360. The release of carbon atoms on the core 360 ​​forms a continuous sheet of graphene shell 362. Additional information related to forming the graphene coating 362 is disclosed in U.S. Patent No. 8,535,553, U.S. Patent No. 10,421,123, Korean Patent No. KR101465616, and Korean Patent No. KR101895114, which are all incorporated herein by reference.

[0066] Figure 9dMore details of the conductive material 330 formed by a plurality of graphene-coated metal balls 358 are shown. In one embodiment, the conductive material 330 includes a matrix 364 and a plurality of cores 360, wherein the graphene coating 362 is embedded in the matrix. In one embodiment, the matrix 364 is a thermosetting material, such as an adhesive or epoxy resin with a binder and a filler, and the filler contains aluminum oxide, aluminum, aluminum zinc oxide, or other materials with good conductive properties. The matrix 364 can be a thermal grease, such as silicon or a polymer type, such as polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET). In other embodiments, the matrix 364 can be an epoxy resin, polyester, or propylene. In another embodiment, the matrix 364 is a polymer or composite epoxy resin with dispersed graphene, carbon nanotubes, conductive polymers, etc. The conductive material 330 can be applied as an ink of the graphene-coated metal balls 358 floating in the matrix 364.

[0067] Each core 360 ​​embedded in the matrix 364 is surrounded or covered by a graphene coating or shell 362. In one embodiment, the graphene shell 362 is a graphene paste or ink formed around a Cu or Ag core. In one embodiment, some cores 362 are formed of Cu and other cores are formed of Ag. The graphene coating 362 of each core 360 ​​contacts the graphene coating of one or more adjacent cores. The cores 360 have sufficient density within the matrix 364 so that most, if not all, of the graphene coating around the core contacts at least one graphene coating around an adjacent core, and typically contacts the graphene coating of multiple adjacent cores.

[0068] Each graphene-coated metal sphere 358 is in physical contact with an adjacent graphene-coated metal sphere within matrix 364 to create a conductive path 378 that includes portions of interconnected graphene shells 362 on adjacent spheres 358. Conductive paths 378 are the primary current carriers of conductive material 330. Charge flowing through a number of conductive paths, such as 378 in spheres 358, operates to carry an electrical signal.

[0069] exist Fig.9e 3, semiconductor die 304 is disposed on die pad 322a, wherein conductive material 330 is between die pad and semiconductor die. Semiconductor die 304 is the same or similar to semiconductor die 104. Additional electrical components may also be mounted on substrate 320. For example, the electrical components may be discrete electrical devices, such as diodes, transistors, resistors, capacitors and inductors, other semiconductor die, semiconductor packages, surface mount devices, RF components, and discrete electrical devices. Any number and type of electrical components may be mounted on substrate 320.

[0070] A pick and place machine or operation is used to position the semiconductor die 304 on the substrate 320, oriented with the back side 108 facing the substrate 320, and in contact with the conductive material 330. The conductive material 330 is maintained in a paste or other quasi-solid state so that the shape of the conductive material conforms to the bottom of the semiconductor die 304. The pick and place machine can press the semiconductor die 304 into the conductive material 304 so that the conductive material is displaced outside the semiconductor die footprint and extends upstream to the side surface of the semiconductor die. In other embodiments, the bottom surface 108 of the semiconductor die 304 is only partially covered or completely covered. In embodiments where the conductive material 330 is dispensed to only partially cover the die pad 322a, pressing the semiconductor die 304 can stretch the conductive material so that a greater portion or the entirety of the die pad is covered.

[0071] With semiconductor die 304 in place on conductive material 330, conductive paths 378 established by graphene shell 362 electrically connect semiconductor die 304 to die pad 322a. In some embodiments, semiconductor die 304 is a vertically oriented die, where, for example, surface 110 is a diode cathode and surface 108 is a diode anode. In many other embodiments, back side 108 is a contact or terminal of the die, and one or more contacts are provided as contact pads 312 on surface 110. Surface 108 can be electrically connected to surface 110 by conductive vias formed through semiconductor die 304 or by the semiconductor material itself.

[0072] To ensure the mechanical stability of semiconductor die 304 on substrate 320 and to establish conductive paths 378 between all adjacent balls 358, as shown in FIG. Figure 9f 304. The conductive material 330 is sintered as shown in FIG. 304. In a process commonly referred to as laser assisted bonding (LAB), the sintering is performed using an infrared (IR) laser head 380 that projects a laser emission 382 onto the active surface 110 of the semiconductor die 304. The IR laser emission 382 directly heats the semiconductor die 304, and the thermal energy is transferred through the die to the conductive material 330.

[0073] Laser head 380 is positioned so that infrared laser emission 382 affects the entirety of active surface 110 of one semiconductor die 304. Radiation 382 is emitted by laser head 380 to sinter the conductive material 330 of that semiconductor die before the laser head moves to the next die as indicated by arrow 384. Each semiconductor die 304 has its corresponding conductive material 330 sintered one at a time until all units are completed. In other embodiments, sintering can be done as a group of any number of semiconductor dies 304 at a time, including one embodiment in which laser head 380 is large enough to sinter all units on substrate 320 together.

[0074] Due to the nature of the conductive material 330 formed of graphene coated spheres 358, sintering with an infrared laser 380 takes only about 30 seconds or less, whereas prior art die attach with silver nanoparticles takes 30-90 minutes in an oven at between 150-500° C. Furthermore, the infrared laser 380 is only able to heat the die 304, whereas the oven process heats the entire substrate 320 and a large amount of air surrounding the device.

[0075] In other embodiments, an IPL irradiation process is used for sintering. IPL uses intense pulses of incoherent light emitted over a range of wavelengths. In one embodiment, the IPL wavelength extends from approximately 350 nanometers (nm) to 3200 nm. Xenon flash lamps produce high output bursts of broad spectrum light to perform IPL irradiation.

[0076] Figure 9f The sintering in the molten-carbon film hardens the conductive material 330 so that in addition to the electrical connection, the conductive material also provides a strong mechanical connection of the semiconductor die 304 to the substrate 320 . Figure 9g A substrate 320 is shown having a semiconductor die 304 attached by a conductive material 330 .

[0077] exist Figure 9h In FIG. 3 , a bond wire 390 is formed to electrically couple between the contact pad 312 of the semiconductor die 304 and the contact pad 322 b on the substrate 304. The bond wire 390 may be formed of copper, gold, aluminum, stainless steel, or another suitable conductive material using any suitable bond wire forming method.

[0078] exist Figure 9i In the embodiment of the present invention, a sealant or molding compound 392 is deposited on and around the substrate 320, the semiconductor die 304, and the bonding wire 390 using slurry printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 392 can be a liquid or granular polymer composite material, such as an epoxy resin, epoxy acrylate, or another suitable polymer, with or without a suitable filler. The sealant 392 is non-conductive, provides structural support, and protects the semiconductor device from external elements and contaminants in the environment. In some embodiments in which the active surface 110 of the semiconductor die 304 emits light or reacts to light, the sealant 392 is transparent or translucent to allow light to pass through. In other embodiments, a transparent window or lens is embedded in the opaque sealant 392 to allow light to pass through.

[0079] exist Figure 9jIn the embodiment of the present invention, the device panel is flipped so that the bottom surface 328 of the substrate 320 is oriented upward. The conductive bump material is deposited on the contact pad of the conductive layer 322 on the bottom surface 328 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 322 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 394. In one embodiment, the bump 394 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesion layer. The bump 394 can also be compression bonded or thermocompressed bonded to the conductive layer 322. The bump 394 represents a type of interconnect structure that can be formed on the conductive layer 322. The interconnect structure may also use bonding wires, conductive paste, stud bumps, micro bumps or other electrical interconnects. In other embodiments, the contact pads of the conductive layer 322 remain exposed as a pad grid array.

[0080] exist Figure 9k In the embodiment, a saw blade or laser cutting tool 398 is used to singulate encapsulant 392 and substrate 320 to separate semiconductor dies 304 into semiconductor packages 400 . Figure 9l A completed semiconductor package 400 is shown. The semiconductor die 304 is electrically coupled to the bumps 394 by bonding wires 390, a conductive layer 322, and a conductive material 330. The conductive material 330 is a graphene-based material, such as a graphene-coated silver or copper ball 358. The graphene-coated ball 358 is a lower cost material than the silver nanoparticles used in the prior art. The graphene coating 362 reduces oxidation and ion migration, which improves reliability, especially in a substrate 320 with fine pitch conductive traces in the conductive layer 322. Compared to the typical conductive paste baked in the oven in the prior art, the graphene-based conductive material 330 can be sintered in a faster process using laser assisted bonding using an IR laser 380, which improves the number of units per hour (UPH) that can be manufactured.

[0081] Fig.10a and 10b The integration of the semiconductor package described above (eg, semiconductor package 400 ) into a larger electronic device 500 is illustrated. Fig.10aA partial cross section of a semiconductor package 400 mounted on a printed circuit board (PCB) or other substrate 502 as part of an electronic device 500 is illustrated. Bumps 394 are reflowed onto a conductive layer 504 of the PCB 502 to physically attach and electrically connect the semiconductor package 400 to the PCB. In other embodiments, thermal compression or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package 400 and the PCB 502. The semiconductor die 304 is electrically coupled to the conductive layer 504 via the bumps 394, the substrate 320, the bonding wires 390, and the conductive material 330.

[0082] Fig.10b An electronic device 500 is illustrated having a chip carrier substrate or PCB 502 with a plurality of semiconductor packages disposed on a surface of the PCB 502, including the semiconductor package 400. The electronic device 500 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0083] Electronic device 500 can be an independent system that uses semiconductor package to perform one or more electrical functions. Alternatively, electronic device 500 can be a subcomponent of a larger system. For example, electronic device 500 can be a part of a tablet computer, a cellular phone, a digital camera, a communication system or other electronic device. Alternatively, electronic device 500 can be a graphics card, a network interface card or other signal processing card that can be inserted into a computer. Semiconductor package can include microprocessor, memory, ASICs, logic circuit, analog circuit, RF circuit, discrete device or other semiconductor die or electrical component. Miniaturization and weight reduction are essential for product acceptance by the market. The distance between semiconductor devices can be reduced to achieve higher density. PCB 502 can have a more irregular shape to facilitate installation in a more ergonomic and smaller device shell.

[0084] exist Fig.10b In the embodiment of the present invention, PCB 502 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 504 are formed on the surface or within the layers of PCB 502 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition processes. Signal traces 504 provide electrical communication between each semiconductor package, mounted components and other external system components. Traces 504 also provide power and ground connections to each semiconductor package.

[0085] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only the first level packaging, where the die is mechanically and electrically disposed directly on the PCB.

[0086] For illustrative purposes, several types of first level packages are shown on the PCB 502, including a bond wire package 546 and a flip chip 548. In addition, several types of second level packages, including a ball grid array (BGA) 550, a bump chip carrier (BCC) 552, a land grid array (LGA) 556, a multi-chip module (MCM) or SIP module 558, a quad flat no-lead package (QFN) 560, a quad flat package 562, and an embedded wafer level ball grid array (eWLB) 564, are shown disposed on the PCB 502. In one embodiment, the eWLB 564 is a fan-out wafer level package (Fo-WLP) or a fan-in wafer level package (Fi-WLP).

[0087] Depending on the system requirements, any combination of semiconductor packages configured with any combination of first and second level packaging styles and other electrical components can be connected to PCB 502. In some embodiments, electronic device 500 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in a lower cost to the consumer.

[0088] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate including a die pad; disposing a conductive material on the die pad, wherein the conductive material comprises a plurality of graphene-coated metal balls in a matrix; disposing a semiconductor die on the conductive material; Sintering of conductive materials using infrared lasers; forming a bond wire between the semiconductor die and the substrate; and An encapsulant is deposited over the semiconductor die and the bond wires. 2 . The method of claim 1 , further comprising sintering the conductive material after disposing the semiconductor die on the conductive material. 3 . The method of claim 1 , further comprising sintering the conductive material in 30 seconds or less. The method of claim 1 , wherein the semiconductor die comprises a light emitting diode.

5. The method of claim 1, further comprising forming solder bumps on the substrate opposite the semiconductor die. The method of claim 1 , further comprising depositing the conductive material by jet printing.

7. A method for manufacturing a semiconductor device, comprising: providing a substrate; Disposing a conductive material on a substrate, wherein the conductive material comprises graphene; and A semiconductor die is disposed on the conductive material.

8. The method of claim 7, further comprising sintering the conductive material using an infrared laser.

9. The method of claim 7, further comprising depositing the conductive material by jet printing.

10. A semiconductor device comprising: substrate; a conductive material disposed on a substrate, wherein the conductive material comprises graphene; and A semiconductor die is disposed on the conductive material. The semiconductor device of claim 10 , wherein the semiconductor die comprises a light emitting diode.

12. The semiconductor device of claim 10, wherein the semiconductor die is photosensitive.

13. The semiconductor device of claim 10, further comprising solder bumps formed on the substrate opposite the semiconductor die.

14. The semiconductor device according to claim 10, wherein: Both the die pad and the back side of the semiconductor die are completely covered by the conductive material.

15. The semiconductor device of claim 10, wherein the conductive material comprises a plurality of graphene-coated metal balls.

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