Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a method of manufacturing the same. A method of manufacturing a display device includes: forming a pad portion on an upper surface of a substrate; forming a lower electrode on the lower surface of the substrate; connecting the lower electrode and the flexible circuit board to each other; disposing a conductive material on a side surface of the substrate for electrically connecting the pad portion and the lower electrode to each other; and forming a side surface connection line by irradiating an electromagnetic wave having a wavelength onto the conductive material on the side surface of the substrate by an electromagnetic wave output device. In the display device and the manufacturing method thereof according to the present disclosure, the time required to form the side surface connecting line is shortened.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0090714 filed in the Korean Intellectual Property Office (KIPO) on July 12, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a display device and a method of manufacturing the same. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information increases. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used.

[0005] In order to widen the area of ​​a display region in which an image is displayed in a display device, circuit components required to supply various signals and various voltages may be provided on a rear surface of a substrate in the display device.

[0006] In order to provide signals and voltages to circuit elements located on the front surface of the display device, a conductive material for allowing the circuit elements to conduct electricity may be located at the side surface of the substrate. The side surface connection line may be formed by hardening the conductive material. Summary of the invention

[0007] Embodiments provide a display device and a method of manufacturing the same, which can shorten the time required to form a side surface connection line.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: forming a pad portion on an upper surface of a substrate; forming a lower electrode on a lower surface of the substrate; connecting the lower electrode and a flexible circuit board to each other; providing a conductive material on a side surface of the substrate for electrically connecting the pad portion and the lower electrode to each other; and forming a side surface connecting line by irradiating an electromagnetic wave having a wavelength onto the conductive material on the side surface of the substrate by an electromagnetic wave output device.

[0009] The wavelength of the electromagnetic wave may be in the range of about 1 mm to about 1 m.

[0010] The side surface connection line may include one of silver, molybdenum, aluminum, chromium, gold, titanium, nickel, neodymium, copper, and alloys thereof.

[0011] The upper surface and the lower surface may be arranged parallel to a plane defined by a first direction and a second direction perpendicular to each other. The side surface connection line may extend in a third direction perpendicular to the first direction and the second direction and electrically connect the pad portion and the lower electrode to each other.

[0012] An induced current may be formed in the side surface connection line in the third direction by the electromagnetic wave.

[0013] The electromagnetic wave output device may include at least one electromagnetic wave output unit. The at least one electromagnetic wave output unit may be movable in the first direction or the second direction.

[0014] The at least one electromagnetic wave output unit may irradiate electromagnetic waves with uniform intensity while moving in the first direction or the second direction.

[0015] The at least one electromagnetic wave output unit may move in a first direction along one side of the substrate and move in a second direction along another side of the substrate.

[0016] The speed at which the at least one electromagnetic wave output unit moves in the first direction may be the same as the speed at which the at least one electromagnetic wave output unit moves in the second direction.

[0017] The at least one electromagnetic wave output unit may include: a first electromagnetic wave output unit moving in a first direction along one side of the substrate; and a second electromagnetic wave output unit moving in a second direction along another side of the substrate.

[0018] The moving speed of the first electromagnetic wave output unit may be the same as the moving speed of the second electromagnetic wave output unit.

[0019] The moving speed of the at least one electromagnetic wave output unit may be set according to the thickness of the side surface connection line.

[0020] The moving speed of the at least one electromagnetic wave output unit may be set to be inversely proportional to the thickness of the side surface connection line.

[0021] The side surface connection line may include a planar heating pattern.

[0022] The conductive material can be printed using a stamping method.

[0023] The electromagnetic wave output device may include a magnetron that generates microwaves.

[0024] According to an embodiment of the present disclosure, a display device may include: a pad portion disposed on an upper surface of a substrate; a lower electrode disposed on a lower surface of the substrate, the lower electrode being electrically connected to a flexible film; and a side surface connection line electrically connecting the pad portion and the lower electrode to each other, the side surface connection line comprising a conductive material. The side surface connection line may be formed by heating by an electromagnetic wave having a wavelength.

[0025] The display device may further include: a pixel circuit layer disposed in the display region on the substrate; and a display element layer disposed on the pixel circuit layer. The pad portion may be electrically connected to the pixel circuit layer or the display element layer.

[0026] The display element layer may include micro light emitting diodes.

[0027] The side surface connection line may include a planar heating pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Embodiments will be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0029] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals represent the same elements throughout.

[0030] Figure 1 is a view schematically showing a display device according to an embodiment of the present disclosure.

[0031] Figure 2 It is schematically shown that the Figure 1 A diagram of an embodiment of a pixel in a display device is shown.

[0032] Figure 3 It is schematically shown that the Figure 1 A diagram of another embodiment of a pixel in a display device is shown.

[0033] Figure 4 is a view schematically showing a spliced ​​display device according to an embodiment of the present disclosure.

[0034] Figure 5 is a perspective view schematically showing a display device according to an embodiment of the present disclosure.

[0035] Figure 6 It is schematically shown Figure 5 A view of an embodiment of a portion of the rear surface of a display device is shown.

[0036] Figure 7 It is shown Figure 5 Schematic cross-sectional view of an embodiment of a display device is shown.

[0037] Figure 8 Schematically shows the formation Figure 5 FIG. 1 is a diagram showing an embodiment of a process for connecting lines on the side surfaces of a display device.

[0038] Fig. 9A and Fig. 9B Schematically shows Figure 8 The electromagnetic wave output device shown includes an embodiment of an electromagnetic wave output unit.

[0039] Fig. 10A and Fig. 10B Schematically shows Figure 8 The electromagnetic wave output device shown includes multiple electromagnetic wave output units.

[0040] Fig.11 is schematically shown in Figure 8 The electromagnetic wave output device used in the process shown and Figure 5 A view of the connection lines on the side surface of the display device is shown.

[0041] Fig.12 is schematically shown in Figure 8 The illustrated process is a view of a pattern observed in a side surface connection line formed. DETAILED DESCRIPTION

[0042] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure can be implemented in various forms and is not limited to the embodiments described in the specification.

[0043] Parts not related to the specification will be omitted to clearly describe the present disclosure, and the same or similar constituent elements will be denoted by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used to identify the same or similar elements in different drawings.

[0044] In addition, for better understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. For clear description, the thickness of multiple parts and regions is exaggerated.

[0045] In the description, the expression "equal" may mean "substantially equal." That is, it may mean equivalent to the extent that those skilled in the art can understand equivalent. Other expressions may be expressions in which "substantially" is omitted.

[0046] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or coupled to another element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without the presence of an intervening element. In addition, when an element is referred to as being "in contact with" or "contacting" another element, etc., the element may be "in electrical contact" or "in physical contact" with the other element; or "indirect contact" or "direct contact" with the other element.

[0047] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like may be used herein for descriptive purposes, and thereby to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would then be oriented to be "above" the other elements or features. Thus, the exemplary term "below" may encompass both the above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0048] The terms used herein are for the purpose of describing a particular embodiment, rather than being intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "one", "an" and "the" are intended to also include plural forms. In addition, when used in this specification, the terms "comprise", "comprises", "includes" and / or "includes" represent the existence of stated features, integral bodies, steps, operations, elements, parts and / or its groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or its groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as degree terms, and are therefore used to allow for the inherent deviations in the measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0049] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0050] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 is a view schematically showing a display device 1 according to an embodiment of the present disclosure. Figure 2 It is schematically shown that the Figure 1 A view of an embodiment of a pixel PX in a display device 1 is shown. Figure 3 It is schematically shown that the Figure 1 A view of another embodiment of a pixel PX in a display device 1 is shown.

[0052] refer to Figure 1 , Figure 2 and Figure 3 , the display device 1 may include pixels PX.

[0053] The display device 1 can be a device for displaying moving images or still images, and can be used not only as a display screen for portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs, but also as a display screen for various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT) devices.

[0054] The display device 1 (or display panel) may be formed in a rectangular planar shape having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. The corners where the long side in the first direction DR1 and the short side in the second direction DR2 intersect each other may be formed as a round shape to have a curvature or formed as a right angle. The planar shape of the display device 1 is not limited to a quadrilateral shape, and the display device 1 may be formed in another polygonal shape, a circular shape, or an elliptical shape. The display device 1 may be a flat panel display device, but the present disclosure is not limited thereto. For example, the display device 1 may include a curved portion formed at the left end / right end and having a constant curvature or a varying curvature. The display device 1 may be formed to be sufficiently flexible so as to be rollable, bendable, bendable, foldable, or rollable.

[0055] Each of the pixels PX may be Figure 2 and Figure 3 Each unit pixel UP may include a first pixel SP1, a second pixel SP2, and a third pixel SP3. Figure 2 and Figure 3 , it is shown that the unit pixel UP includes three pixels SP1, SP2, and SP3. However, the embodiments of the present disclosure are not limited thereto.

[0056] The first pixel SP1, the second pixel SP2, and the third pixel SP3 may emit light of different colors. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may have a rectangular, square, or diamond planar shape in a plan view. For example, each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be as shown in FIG. Figure 2 As shown in the plan view, it has a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. In another embodiment, each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be as shown in FIG. Figure 3 The illustrated embodiment has a square or rhombus plan shape in plan view with sides having the same length.

[0057] In an embodiment, if Figure 2 As shown, the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be arranged in the first direction DR1.

[0058] In another embodiment, one of the second pixel SP2 and the third pixel SP3 and the first pixel SP1 may be arranged in the first direction DR1, and the other of the second pixel SP2 and the third pixel SP3 and the first pixel SP1 may be arranged in the second direction DR2. Figure 3 As shown, the second pixels SP2 may be arranged in the first direction DR1 relative to the first pixels SP1, and the third pixels SP3 may be arranged in the second direction DR2 relative to the first pixels SP1.

[0059] The first pixel SP1 may emit a first light, the second pixel SP2 may emit a second light, and the third pixel SP3 may emit a third light. The first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. The red wavelength band may be a wavelength band in the range of about 600 nm (nanometers) to about 750 nm, the green wavelength band may be a wavelength band in the range of about 480 nm to about 560 nm, and the blue wavelength band may be a wavelength band in the range of about 370 nm to about 460 nm. However, embodiments of the present disclosure are not limited thereto.

[0060] The display device 1 may be implemented as, for example, a light receiving and light emitting display device (e.g., a liquid crystal display device) including a light source (e.g., a backlight unit). The display device 1 may be implemented as, for example, a self-luminous display device including a light emitting element. Hereinafter, although an embodiment in which the display device 1 is implemented as a self-luminous display device including a light emitting element is described, the embodiments of the present disclosure are not limited thereto.

[0061] Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may include a light emitting element. The light emitting element may include, for example, an organic light emitting element including an organic light emitting layer. The light emitting element may include, for example, an inorganic light emitting element having an inorganic semiconductor. For example, the inorganic light emitting element may be a flip-chip type micro light emitting diode (LED), but embodiments of the present disclosure are not limited thereto. Hereinafter, an embodiment in which the light emitting element is implemented as an inorganic light emitting element having an inorganic semiconductor is described, but embodiments of the present disclosure are not limited thereto.

[0062] like Figure 2 and Figure 3 As shown, the area of ​​the first pixel SP1, the area of ​​the second pixel SP2, and the area of ​​the third pixel SP3 in the plan view may be substantially the same. However, the embodiments of the present disclosure are not limited thereto. In the plan view, the area of ​​a pixel may be the area of ​​a light emitting element (or light source) included in the corresponding pixel, or the area of ​​an emission region of a light emitting element.

[0063] At least one of the area of ​​the first pixel SP1, the area of ​​the second pixel SP2, and the area of ​​the third pixel SP3 may be different from the other of the area of ​​the first pixel SP1, the area of ​​the second pixel SP2, and the area of ​​the third pixel SP3. In another embodiment, two of the area of ​​the first pixel SP1, the area of ​​the second pixel SP2, and the area of ​​the third pixel SP3 may be substantially the same, and the other of the area of ​​the first pixel SP1, the area of ​​the second pixel SP2, and the area of ​​the third pixel SP3 may be different from the two of the area of ​​the first pixel SP1, the area of ​​the second pixel SP2, and the area of ​​the third pixel SP3. In another embodiment, the area of ​​the first pixel SP1, the area of ​​the second pixel SP2, and the area of ​​the third pixel SP3 may be different from each other.

[0064] Figure 4 2 is a view schematically showing a spliced ​​display device TD according to an embodiment of the present disclosure.

[0065] refer to Figure 4 , the spliced ​​display device TD may include a plurality of display devices 10-1, 10-2, 10-3, and 10-4. For example, the display devices 10-1, 10-2, 10-3, and 10-4 may be arranged in a grid form, but the embodiments of the present disclosure are not limited thereto.

[0066] The shape of the spliced ​​display device TD may vary according to the arrangement of the display devices 10 - 1 , 10 - 2 , 10 - 3 , and 10 - 4 . Figure 4 , the display devices 10 - 1 , 10 - 2 , 10 - 3 , and 10 - 4 are arranged in the first direction DR1 and / or the second direction DR2 to be connected to each other, and thus, the spliced ​​display device TD may have a specific shape.

[0067] The display devices 10-1, 10-2, 10-3, and 10-4 may have the same size, but the embodiments of the present disclosure are not limited thereto. For example, at least some of the display devices 10-1, 10-2, 10-3, and 10-4 may have a size different from that of the other display devices of the display devices 10-1, 10-2, 10-3, and 10-4.

[0068] The spliced ​​display device TD may include a plurality of display devices. Figure 4 The spliced ​​display device TD may include a first display device 10-1, a second display device 10-2, a third display device 10-3, and a fourth display device 10-4. The number of display devices included in the spliced ​​display device TD and the connection relationship between the display devices are not limited to Figure 4 Hereinafter, for the convenience of description, an embodiment in which the spliced ​​display device TD includes four display devices 10 - 1 , 10 - 2 , 10 - 3 , and 10 - 4 is described. However, the embodiments of the present disclosure are not limited thereto.

[0069] The first to fourth display devices 10 - 1 to 10 - 4 may be fixed to the mounting frame to realize a large screen image.

[0070] Each of the first to fourth display devices 10-1 to 10-4 may have a rectangular shape including long sides and short sides in a plan view. The first to fourth display devices 10-1 to 10-4 may be disposed such that long sides or short sides thereof are connected to each other.

[0071] Some of the display devices may be arranged at the edge of the spliced ​​display device TD to form a side of the spliced ​​display device TD. For example, some of the first to fourth display devices 10-1 to 10-4 may be arranged at the edge of the spliced ​​display device TD to form a side of the spliced ​​display device TD.

[0072] Some of the display devices may be disposed at a corner of the spliced ​​display device TD. For example, some of the first to fourth display devices 10-1 to 10-4 may be disposed at a corner of the spliced ​​display device TD and form two adjacent sides of the spliced ​​display device TD.

[0073] Some of the display devices may be disposed inside the tiled display device TD.Although not shown in the drawings, some of the display devices may be disposed inside the tiled display device TD and surrounded by other display devices.

[0074] Each of the display devices may include a display area DA and a non-display area NDA. For example, each of the first display device 10-1, the second display device 10-2, the third display device 10-3, and the fourth display device 10-4 may include a display area DA and a non-display area NDA. The display area DA may include a unit pixel UP and display an image. In some embodiments, the unit pixel UP may include a first pixel SP1, a second pixel SP2, and a third pixel SP3. In some embodiments, each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may include a micro-LED. However, the present disclosure is not limited thereto, and in another embodiment, each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may have an organic light emitting diode including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, or an inorganic LED including an inorganic semiconductor. Hereinafter, an embodiment in which each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 includes a micro-LED is described.

[0075] The non-display area NDA may be disposed at the periphery of the display area DA and surround at least a portion of the display area DA. The non-display area NDA may not display an image.

[0076] refer to Figure 4 , each of the first to fourth display devices 10-1 to 10-4 may include first pixels SP1, second pixels SP2, and third pixels SP3 arranged along multiple rows and columns in the display area DA. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may include an emission area or an opening area defined by a pixel defining layer or a bank, and emits light having a peak wavelength (predetermined or optional peak wavelength) through the emission area or the opening area. The emission area may be an area in which light generated in a light emitting element of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 is emitted to the outside of each of the first to fourth display devices 10-1 to 10-4.

[0077] The first pixel SP1 , the second pixel SP2 , and the third pixel SP3 may be sequentially and repeatedly arranged in the first direction DR1 of the display area DA.

[0078] The spliced ​​display device TD may have a planar shape, but the embodiments of the present disclosure are not limited thereto. The spliced ​​display device TD may have a stereoscopic shape, thereby providing a stereoscopic effect to the user. For example, the spliced ​​display device TD may have a stereoscopic shape, and at least some of the display devices 10-1, 10-2, 10-3, and 10-4 may have a curved shape. In another embodiment, each of the display devices 10-1, 10-2, 10-3, and 10-4 may have a planar shape and be connected to each other at an angle so that the spliced ​​display device TD has a stereoscopic shape.

[0079] The spliced ​​display device TD may include a coupling area SM disposed between the display areas DA. The spliced ​​display device TD may be formed by connecting the non-display areas NDA of the corresponding adjacent display devices. The first to fourth display devices 10-1 to 10-4 may be connected to each other by a coupling member or an adhesive member disposed in the coupling area SM.

[0080] The distance between the display areas DA of the corresponding first display device 10-1 to the fourth display device 10-4 may be close enough so that the connection area SM is not recognized by the user. For example, the first horizontal pixel pitch HPP1 between the pixels of the first display device 10-1 and the pixels of the second display device 10-2 may be substantially equal to the second horizontal pixel pitch HPP2 between the pixels of the second display device 10-2. The first vertical pixel pitch VPP1 between the pixels of the first display device 10-1 and the pixels of the third display device 10-3 may be substantially equal to the second vertical pixel pitch VPP2 between the pixels of the third display device 10-3. The spliced ​​display device TD can prevent the connection area SM between the display devices (e.g., the first display device 10-1 to the fourth display device 10-4) from being recognized by the user, thereby reducing the sense of disconnection between the display devices and improving the concentration of the image.

[0081] Figure 5 is a perspective view schematically showing a display device 10 according to an embodiment of the present disclosure. Figure 6 It is schematically shown Figure 5 A view of an embodiment of a portion of a back surface BS of a display device 10 is shown.

[0082] Figure 5 The configuration based on the pad portion PAD and the side surface connection line SCL is schematically shown, and the configuration of the pad portion PAD and the side surface connection line SCL will be described. Figure 6 An embodiment is shown in which the side surface connection lines SCL are connected to other components on the back surface BS of the substrate SUB. Figure 5 The display device 10 shown can be applied to Figure 1 The display device 1 is shown.

[0083] refer to Figure 5 and Figure 6 The display device 10 may include: a substrate SUB including a display area DA and a non-display area NDA; at least one pad portion PAD disposed on an upper surface US of the substrate SUB; and at least one side surface connection line SCL disposed on an upper surface US, a back surface BS, and a side surface SS between the upper surface US and the back surface BS of the substrate SUB.

[0084] The upper surface US and the back surface BS of the substrate SUB may face each other with respect to the third direction DR3.

[0085] In an embodiment, the substrate SUB may include a chamfered surface CHM formed by chamfering each of an edge between the upper surface US and the side surface SS and an edge between the back surface BS and the side surface SS. The side surface SS of the substrate SUB may have an inclination due to the chamfered surface CHM. Therefore, disconnection of the side surface connection line SCL surrounding the upper surface US, the side surface SS, and the back surface BS of the substrate SUB may be prevented.

[0086] The pad portion PAD may be disposed in the non-display area NDA of the upper surface US of the substrate SUB. Figure 5 , it is shown that the pad portion PAD is disposed at one edge of the upper surface US of the substrate SUB. However, the present disclosure is not limited thereto, and the pad portion PAD may also be disposed at other edges of the upper surface US of the substrate SUB.

[0087] In an embodiment, the pad portion PAD (eg, a pad of the pad portion PAD) may be in contact with the side surface connection line SCL. The side surface connection line SCL may be connected to a circuit for driving the pixel PX (see Figure 1 ) of a data line, a power line, and a clock line. For example, the power line may include a gate driver and / or a pixel PX (see Figure 1 ) provides a power line for various power supplies. A clock signal provided to the gate driver may be provided to a clock line.

[0088] The side surface connection line SCL may be connected to the pad portion PAD (e.g., the pad of the pad portion PAD) one-to-one. The side surface connection line SCL may be physically and electrically connected to the pad portion PAD. In an embodiment, the side surface connection line SCL may completely cover the upper surface of the pad portion PAD. Therefore, the physical and / or electrical connection between the pad portion PAD and the side surface connection line SCL may be enhanced.

[0089] In an embodiment, the width of the side surface connection line SCL may be tens of micrometers (μm). In an embodiment, the distance between adjacent side surface connection lines SCL may be tens of micrometers. In an embodiment, the width of the side surface connection line SCL may be equal to or greater than the distance between adjacent side surface connection lines SCL.

[0090] refer to Figure 6 , at least one lead LDL, at least one back surface electrode (or lower electrode) BTE, a flexible film (or flexible circuit board) FPCB, etc. may be disposed on the back surface BS of the substrate SUB.

[0091] The lead wire LDL may be connected (e.g., physically and / or electrically connected) between the side surface connection wire SCL and the back surface electrode BTE. In an embodiment, one end of the lead wire LDL may be physically connected to the side surface connection wire SCL extending to the back surface BS of the substrate SUB. The other end of the lead wire LDL may be physically connected to the back surface electrode BTE formed on the back surface BS of the substrate SUB.

[0092] The back surface electrode BTE may provide a voltage and / or signal received from the flexible film FPCB to the side surface connection line SCL through the lead line LDL. In an embodiment, the back surface electrode BTE and the flexible film FPCB may be electrically connected to each other through a conductive adhesive member (e.g., an anisotropic conductive film, etc.). For example, at least a portion of the first surface of the flexible film FPCB may be attached to the back surface BS of the substrate SUB through a conductive adhesive member. The second surface of the flexible film FPCB facing the first surface may be connected to a source circuit board, a driver chip, etc.

[0093] Figure 7 It is shown Figure 5 A schematic cross-sectional view of an embodiment of a display device 10 is shown.

[0094] refer to Figure 5 , Figure 6 and Figure 7 The display device 10 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and the like.

[0095] A stack structure may be formed on each of the upper surface US and the back surface BS of the substrate SUB. For example, the pixel circuit layer PCL and the display element layer DPL may be disposed to be stacked on the upper surface US of the substrate SUB.

[0096] refer to Figure 7The pixel circuit layer PCL may include a light blocking layer BML, a buffer layer BF, an active layer ACTL, a first gate insulating layer GI1, a first gate electrode layer GTL1, a second gate insulating layer GI2, a second gate electrode layer GTL2, an interlayer insulating layer ILD, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, a second via layer VIA2, a third source metal layer SDL3, a third via layer VIA3, etc.

[0097] The display element layer DPL may include a fourth source metal layer SDL4 , an anode layer ANDL, a fourth via layer VIA4 , a first protection layer PAS1 , and the like.

[0098] The second protection layer PAS2 , the back surface electrode BTE, the lead LDL, the fifth via layer VIA5 , the third protection layer PAS3 , the flexible film FPCB, etc. may be disposed on the back surface BS of the substrate SUB.

[0099] The side surface connection lines SCL may be disposed on the upper surface US and the back surface BS of the substrate SUB via the side surface SS of the substrate SUB.

[0100] The substrate SUB may fully support the layers stacked on the upper surface US and the back surface BS of the substrate SUB. The substrate SUB may be a base substrate or a base member. The substrate SUB may be a rigid substrate including a glass material. In another embodiment, the substrate SUB may be a flexible substrate that is bendable, foldable, rollable, etc. For example, the substrate SUB may include an insulating material such as a polymer resin including polyimide (PI), but the present disclosure is not limited thereto.

[0101] The light blocking layer BML may be disposed on the substrate SUB. The light blocking layer BML may have a single layer or multiple layers, and is made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0102] In an embodiment, the light blocking layer BML may be connected to an electrode (e.g., a source electrode) of the transistor TFT (e.g., a driving transistor). In an embodiment, the light blocking layer BML may overlap at least a portion of the active layer ACTL of the transistor TFT in a plan view and block light incident on the active layer ACTL, thereby stabilizing the operation of the transistor TFT.

[0103] The buffer layer BF may be disposed on the substrate SUB. The buffer layer BF may include an inorganic material capable of preventing air or moisture from penetrating. The buffer layer BF may include a plurality of inorganic layers alternately stacked with each other. For example, the buffer layer BF may have a multilayer in which one or more inorganic layers among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked with each other.

[0104] The active layer ACTL may be disposed on the buffer layer BF. The active layer ACTL may include a channel CH, a source electrode SE, and a drain electrode DE of a transistor TFT. The transistor TFT may be a transistor constituting a pixel circuit. The source electrode SE and the drain electrode DE may become a conductor by heat treating the active layer ACTL. For example, the active layer ACTL may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. In another embodiment, the active layer ACTL may include a first active layer and a second active layer disposed in different layers. The first active layer may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, or amorphous silicon, and the second active layer may include an oxide semiconductor.

[0105] The first gate insulating layer GI1 may be disposed on the active layer ACTL. The first gate insulating layer GI1 may insulate the gate electrode GE and the channel CH of the transistor TFT from each other. The first gate insulating layer GI1 may include an inorganic layer. For example, the first gate insulating layer GI1 may include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0106] The first gate electrode layer GTL1 may be disposed on the first gate insulating layer GI1. The first gate electrode layer GTL1 may include a fan-out line FOL, a gate electrode GE of the transistor TFT, and a first capacitor electrode CE1 (e.g., a lower electrode) of the first capacitor C1. The first gate electrode layer GTL1 may have a single layer or multiple layers, and is made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0107] The fan-out line FOL may be connected to a pad portion PAD penetrating the interlayer insulating layer ILD and the second gate insulating layer GI2. In an embodiment, the fan-out line FOL may extend from the pad portion PAD to the display area DA to reduce the size of the non-display area NDA.

[0108] The second gate insulating layer GI2 may be disposed on the first gate electrode layer GTL1. The second gate insulating layer GI2 may insulate the first gate electrode layer GTL1 and the second gate electrode layer GTL2 from each other. The second gate insulating layer GI2 may include an inorganic layer. For example, the second gate insulating layer GI2 may include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0109] The second gate electrode layer GTL2 may be disposed on the second gate insulating layer GI2. The second gate electrode layer GTL2 may include a second capacitor electrode CE2 (e.g., an upper electrode) of the first capacitor C1. The second gate electrode layer GTL2 may have a single layer or multiple layers, and may be made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0110] The interlayer insulating layer ILD may be disposed on the second gate electrode layer GTL2. The interlayer insulating layer ILD may insulate the first source metal layer SDL1 and the second gate electrode layer GTL2 from each other. The interlayer insulating layer ILD may include an inorganic layer. For example, the interlayer insulating layer ILD may include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0111] The configuration including the transistor TFT, the buffer layer BF, the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD may constitute the transistor layer TL. For example, the uppermost layer of the transistor layer TL may be the interlayer insulating layer ILD. The transistor layer TL may be part of the pixel circuit layer PCL.

[0112] The first source metal layer SDL1 may be disposed on the interlayer insulating layer ILD of the transistor layer TL. The first source metal layer SDL1 may include a connection electrode CCE.

[0113] The connection electrode CCE may be connected to the anode connection line ACL penetrating the first via layer VIA1. The connection electrode CCE may be connected to the drain electrode DE of the transistor TFT while penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. The connection electrode CCE may electrically connect the anode connection line ACL and the drain electrode DE to each other.

[0114] The first pad electrode PAD1 may be formed together with the first source metal layer SDL1. The first pad electrode PAD1 may be disposed on the interlayer insulating layer ILD in the non-display area NDA.

[0115] The first pad electrode PAD1 may be connected to the fan-out line FOL through a contact hole penetrating the interlayer insulating layer ILD and the second gate insulating layer GI2 .

[0116] Each of the first source metal layer SDL1 and the first pad electrode PAD1 may have a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0117] The first via layer VIA1 may be disposed on the first source metal layer SDL1. The first via layer VIA1 may planarize the upper surface of the first source metal layer SDL1. The first via layer VIA1 may include an organic layer including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and the like.

[0118] In an embodiment, the first via layer VIA1 may be disposed in the display area DA. The first via layer VIA1 may be spaced apart from the first pad electrode PAD1. Therefore, an interlayer insulating layer exposure area IEA may be formed between the first via layer VIA1 and the pad portion PAD (e.g., the first pad electrode PAD1). The interlayer insulating layer exposure area IEA may be a portion between the first via layer VIA1 and the pad portion PAD where the upper surface of the interlayer insulating layer ILD is exposed from the first via layer VIA1.

[0119] The second source metal layer SDL2 may be disposed on the first via layer VIA1. The second source metal layer SDL2 may include an anode connection line ACL. The anode connection line ACL may be connected to an anode connection electrode ACE penetrating the second via layer VIA2.

[0120] The anode connection line ACL may be connected to the connection electrode CCE while penetrating the first via layer VIA1. The anode connection line ACL may electrically connect the anode connection electrode ACE and the connection electrode CCE to each other.

[0121] The second pad electrode PAD2 may be formed together with the second source metal layer SDL2. The second pad electrode PAD2 may be disposed on the first pad electrode PAD1 (eg, directly on the first pad electrode PAD1). The second pad electrode PAD2 may be formed in the non-display area NDA.

[0122] Each of the second source metal layer SDL2 and the second pad electrode PAD2 can have a single layer or a multilayer, which is made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0123] The second via layer VIA2 may be disposed on the first via layer VIA1 and the second source metal layer SDL2. The second via layer VIA2 may planarize the upper surface of the second source metal layer SDL2. The second via layer VIA2 may include an organic layer including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0124] In an embodiment, the second via layer VIA2 may be disposed in the display area DA. The second via layer VIA2 may be spaced apart from the pad portion PAD. In addition, the second via layer VIA2 and the first via layer VIA1 may form a step difference to expose a portion of the upper surface of the first via layer VIA1. The portion of the first via layer VIA1 exposed from the second via layer VIA2 may be a first exposed area EA1. For example, the width of the first exposed area EA1 in the second direction DR2 may be about 10 μm.

[0125] The third source metal layer SDL3 may be disposed on the second via layer VIA2. The third source metal layer SDL3 may include an anode connection electrode ACE. The anode connection electrode ACE may be connected to the first anode electrode AND1 penetrating the third via layer VIA3. The anode connection electrode ACE may be connected to the anode connection line ACL while penetrating the second via layer VIA2. The anode connection electrode ACE may be electrically connected to the anode AND and the anode connection line ACL.

[0126] The third pad electrode PAD3 may be formed together with the third source metal layer SDL3. The third pad electrode PAD3 may be disposed on the second pad electrode PAD2 (eg, directly on the second pad electrode PAD2). The third pad electrode PAD3 may be formed in the non-display area NDA.

[0127] Each of the third source metal layer SDL3 and the third pad electrode PAD3 can have a single layer or a multilayer, which is made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0128] The third via layer VIA3 may be disposed on the second via layer VIA2 and the third source metal layer SDL3. The third via layer VIA3 may planarize the upper surface of the third source metal layer SDL3. The third via layer VIA3 may include an organic layer including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0129] In an embodiment, the third via layer VIA3 may be disposed in the display area DA. The third via layer VIA3 may be spaced apart from the pad portion PAD. In addition, the third via layer VIA3 and the second via layer VIA2 may form a step difference to expose a portion of the upper surface of the second via layer VIA2. The portion of the second via layer VIA2 exposed from the third via layer VIA3 may be the second exposed area EA2. For example, the width of the second exposed area EA2 in the second direction DR2 may be similar to or smaller than the width of the first exposed area EA1 in the second direction DR2.

[0130] Thus, the first via layer VIA1 , the second via layer VIA2 , and the third via layer VIA3 may be stacked while having a stepped shape.

[0131] The fourth source metal layer SDL4 may be disposed on the third via layer VIA3. The fourth source metal layer SDL4 may include a first anode electrode AND1 and a first cathode electrode CTD1. The first anode electrode AND1 may be connected to the anode connection electrode ACE while penetrating the third via layer VIA3. The first cathode electrode CTD1 may be connected to the power line while penetrating the third via layer VIA3. Figure 7 , the anode AND and the cathode CTD are shown to be adjacent to each other in the second direction DR2 to illustrate and describe the shape of the anode AND and the cathode CTD connected to the light emitting element ED and the detailed configuration of the light emitting element ED. However, the arrangement of the anode AND and the cathode CTD is not limited thereto. For example, the anode AND and the cathode CTD may be disposed adjacent to each other in the first direction DR1.

[0132] The fourth pad electrode PAD4 may be formed together with the fourth source metal layer SDL4. The fourth pad electrode PAD4 may be disposed on (eg, directly disposed on) the third pad electrode PAD3. The fourth pad electrode PAD4 may be formed in the non-display area NDA.

[0133] Each of the fourth source metal layer SDL4 and the fourth pad electrode PAD4 can have a single layer or a multilayer, which is made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0134] The anode layer ANDL may be disposed on the fourth source metal layer SDL4. The anode layer ANDL may include a second anode electrode AND2 and a second cathode electrode CTD2. In an embodiment, a thickness of each of the second anode electrode AND2 and the second cathode electrode CTD2 may be smaller than a thickness of each of the first anode electrode AND1 and the first cathode electrode CTD1.

[0135] The fifth pad electrode PAD5 may be formed together with the anode layer ANDL. The fifth pad electrode PAD5 may be disposed on (e.g., directly disposed on) the fourth pad electrode PAD4. For example, the fifth pad electrode PAD5 may contact the upper surface and the side surface of the fourth pad electrode PAD4 to cover the fourth pad electrode PAD4. The thickness of the fifth pad electrode PAD5 may be less than the thickness of the fourth pad electrode PAD4.

[0136] The anode layer ANDL and the fifth pad electrode PAD5 may include a transparent conductive material (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0137] The first and second anode electrodes AND1 and AND2 may form an anode AND (eg, a first pixel electrode), and the first and second cathode electrodes CTD1 and CTD2 may form a cathode CTD (eg, a second pixel electrode). The first to fifth pad electrodes PAD1 to PAD5 may form a pad portion PAD.

[0138] The pad portion PAD may be disposed on the interlayer insulating layer ILD in the non-display area NDA. The pad portion PAD may provide the fan-out line FOL with a voltage and / or signal received from the side surface connection line SCL. The second pad electrode PAD2 may be electrically connected to the lead line LDL through the side surface connection line SCL.

[0139] The fourth via layer VIA4 may be disposed on the third via layer VIA3 on which the anode AND and the cathode CTD are not formed. The fourth via layer VIA4 may planarize the upper surface of the third via layer VIA3. The fourth via layer VIA4 may include an organic layer including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0140] In an embodiment, the fourth via layer VIA4 may be disposed in the display area DA. The fourth via layer VIA4 may be spaced apart from the pad portion PAD. In addition, the fourth via layer VIA4 and the third via layer VIA3 may form a step difference to expose a portion of the upper surface of the third via layer VIA3. The portion of the third via layer VIA3 exposed from the fourth via layer VIA4 may be the third exposed area EA3. For example, the width of the third exposed area EA3 in the second direction DR2 may be similar to or smaller than the width of the second exposed area EA2 in the second direction DR2.

[0141] The first protection layer PAS1 may be disposed on the fourth via layer VIA4 and cover portions of the anode AND, the cathode CTD, and the pad portion PAD. In addition, the first protection layer PAS1 may contact the interlayer insulating layer ILD in the interlayer insulating layer exposure area IEA to cover the portion of the interlayer insulating layer ILD exposed in the interlayer insulating layer exposure area IEA.

[0142] In addition, the first protection layer PAS1 may contact the first via layer VIA1, the second via layer VIA2, and the third via layer VIA3. For example, the first protection layer PAS1 may contact the first via layer VIA1 in the first exposure area EA1, contact the second via layer VIA2 in the second exposure area EA2, and contact the third via layer VIA3 in the third exposure area EA3.

[0143] The first protective layer PAS1 may include an inorganic layer. For example, the first protective layer PAS1 may include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0144] The first protection layer PAS1 may not cover a portion of the upper surface of the anode AND but may expose a portion of the upper surface of the anode AND. The light emitting element ED may contact the anode AND and the cathode CTD not covered by the first protection layer PAS1.

[0145] In an embodiment, the first protection layer PAS1 may cover the exposed portions of the first to third pad electrodes PAD1 to PAD3. For example, the first protection layer PAS1 may contact the exposed portions of the first to third pad electrodes PAD1 to PAD3. As described above, the fourth pad electrode PAD4 may be covered by the fifth pad electrode PAD5 without being exposed to the first protection layer PAS1.

[0146] However, the first protective layer PAS1 may not cover a portion of the upper surface of the fifth pad electrode PAD5 but may expose a portion of the upper surface of the fifth pad electrode PAD5. The side surface connection line SCL may contact (or be connected to) the pad portion PAD not covered by the first protective layer PAS1.

[0147] In an embodiment, a protective layer including an inorganic material may also be disposed in at least one between the first via layer VIA1 and the second via layer VIA2 , between the second via layer VIA2 and the third via layer VIA3 , and between the third via layer VIA3 and the fourth via layer VIA4 .

[0148] The second protective layer PAS2 may be disposed on the back surface BS of the substrate SUB to planarize the back surface BS of the substrate SUB. The second protective layer PAS2 may include an inorganic layer. For example, the second protective layer PAS2 may include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0149] The back surface electrode BTE may be disposed on one surface (e.g., back surface) of the second protection layer PAS2. The back surface electrode BTE may provide a voltage or signal received from the flexible film FPCB to the side surface connection line SCL through the lead line LDL. The back surface electrode BTE may be electrically connected to the flexible film FPCB through the conductive adhesive member ACF.

[0150] The back surface electrode BTE may include a first back surface electrode BTE1 and a second back surface electrode BTE2. The first back surface electrode BTE1 may be disposed on the one surface or the back surface of the second protective layer PAS2. The first back surface electrode BTE1 may have a single layer or multiple layers, and is made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0151] The second back surface electrode BTE2 may be disposed on one surface (eg, back surface) of the first back surface electrode BTE1. The second back surface electrode BTE2 may include a transparent metal material such as ITO or IZO.

[0152] The lead line LDL may be disposed on one surface (eg, the rear surface) of the second protective layer PAS2. The lead line LDL and the first rear surface electrode BTE1 may be formed of the same material in the same layer. The lead line LDL may provide the side surface connection line SCL with a voltage and / or a signal received from the rear surface electrode BTE. For example, Figure 6 As shown, the lead line LDL may be connected (eg, physically connected) to the back surface electrode BTE.

[0153] The side surface connection line SCL may be disposed at edges of the back surface BS, the side surface SS, and the upper surface US of the substrate SUB. One end of the side surface connection line SCL may be connected to the pad portion PAD, and the other end of the side surface connection line SCL may be connected to the lead LDL.

[0154] In an embodiment, on the upper surface US of the substrate SUB, the side surface connection line SCL may overlap with the entire pad portion PAD in a plan view. For example, in a plan view, the side surface connection line SCL may cover the entire pad portion PAD. In an embodiment, the side surface connection line SCL may overlap with the interlayer insulating layer exposed area IEA in a plan view. For example, the side surface connection line SCL may be disposed on the first protection layer PAS1 in the interlayer insulating layer exposed area IEA. On the back surface BS of the substrate SUB, the side surface connection line SCL may cover a portion of the lead LDL. Therefore, the risk of electrical disconnection between the pad portion PAD and the lead LDL can be reduced.

[0155] The side surface connection line SCL may pass through (or cover) side surfaces of the substrate SUB, the buffer layer BF, the first and second gate insulating layers GI1 and GI2 , the interlayer insulating layer ILD, and the first protection layer PAS1 .

[0156] The side surface connection line SCL may have a single layer or multiple layers, and is made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, the side surface connection line SCL may be made of silver (Ag).

[0157] The fifth via layer VIA5 may cover one surface (e.g., the rear surface) of the rear surface electrode BTE and the lead line LDL. In addition, the fifth via layer VIA5 may cover a portion of the side surface connection line SCL. The fifth via layer VIA5 may flatten the lower surface of the substrate SUB. The fifth via layer VIA5 may include an organic layer including acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0158] The third protection layer PAS3 may be disposed on a surface (e.g., rear surface) of the fifth via layer VIA5 to protect the rear surface electrode BTE and the lead line LDL. The third protection layer PAS3 may include an inorganic layer. The third protection layer PAS3 may include one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0159] The flexible film FPCB may be disposed on one surface or the rear surface of the third protective layer PAS3. The flexible film FPCB may be attached to the rear surface of the third protective layer PAS3 using an adhesive member. One side of the flexible film FPCB may provide a voltage and / or a signal to the pad portion PAD through the rear surface electrode BTE, the lead LDL, and the side surface connection line SCL. The other side of the flexible film FPCB may be connected to a source circuit board on the bottom of the substrate SUB, etc. The flexible film FPCB may transmit a signal provided from the source circuit board to the display device 10.

[0160] The conductive adhesive member ACF may attach the flexible film FPCB to the rear surface of the rear surface electrode BTE. For example, the conductive adhesive member ACF may include an anisotropic conductive film. The conductive adhesive member ACF including the anisotropic conductive film may have conductivity in a region where the rear surface electrode BTE and the flexible film FPCB contact each other, and electrically connect the flexible film FPCB to the rear surface electrode BTE.

[0161] The display device 10 may include a flexible film FPCB disposed on a rear surface BS of a substrate SUB, a pad portion PAD disposed on an upper surface US of the substrate SUB, and a rear surface electrode BTE, a lead line LDL, and a side surface connection line SCL electrically connecting the flexible film FPCB and the pad portion PAD to each other, so that the area of ​​the non-display area NDA may be minimized.

[0162] In some embodiments, an outer coating layer (not shown) may be further formed on the side surface connection line SCL. For example, the outer coating layer may be an insulating layer and include an organic insulating material and / or an inorganic insulating material. The outer coating layer may prevent contaminants from penetrating into the side surface SS and edge portion of the display device 10 including the side surface connection line SCL, and protect the side surface connection line SCL.

[0163] The light emitting element ED may be disposed on the anode AND and the cathode CTD. In an implementation, the light emitting element ED may include a flip-chip type micro light emitting diode including first and second contact electrodes CTE1 and CTE2 facing the anode AND and the cathode CTD, respectively.

[0164] The light emitting element ED may include an inorganic material such as GaN. In an embodiment, the width, length, and height of the light emitting element ED may each be tens to hundreds of micrometers. For example, the width, length, and height of the light emitting element ED may each be less than or equal to about 100 μm.

[0165] The light emitting element ED can be formed by growing on a semiconductor substrate such as a silicon wafer. The light emitting element ED can be immediately transferred from the silicon wafer to the anode AND and cathode CTD on the substrate SUB. In another embodiment, the light emitting element ED can be transferred to the anode AND and cathode CTD on the substrate SUB by an electrostatic method using an electrostatic head or a stamp method using a polymer material having elasticity (such as polydimethylsiloxane (PDMS)), silicon, etc. as a transfer substrate.

[0166] The light emitting element ED may include a base substrate SSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1, and a second contact electrode CTE2.

[0167] The base substrate SSUB may be a sapphire substrate, but the present disclosure is not limited thereto.

[0168] The n-type semiconductor NSEM may be disposed on one surface of the base substrate SSUB. For example, the n-type semiconductor NSEM may be disposed on the rear surface of the base substrate SSUB. The n-type semiconductor NSEM may be made of, for example, GaN doped with an n-type conductive dopant such as Si, Ge, Sn, or Se.

[0169] The active layer MQW may be disposed on a portion of a surface of an n-type semiconductor NSEM. The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. The active layer MQW including a material having a multiple quantum well structure may have a structure in which a plurality of well layers and a plurality of barrier layers are alternately stacked with each other. In some embodiments, the well layer may be formed of InGaN, and the barrier layer may be formed of AlGaN. However, the present disclosure is not limited thereto. In some embodiments, the active layer MQW may be in a structure in which a semiconductor material having a high energy band gap and a semiconductor material having a low energy band gap are alternately stacked with each other, and includes Group III to Group V materials according to the wavelength band of the emitted light.

[0170] The p-type semiconductor PSEM may be disposed on one surface (eg, rear surface) of the active layer MQW. The p-type semiconductor PSEM may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, or Be.

[0171] The first contact electrode CTE1 may be disposed on the p-type semiconductor PSEM. The second contact electrode CTE2 may be disposed on another portion of a surface (e.g., a rear surface) of the n-type semiconductor NSEM. Another portion of a surface of the n-type semiconductor NSEM on which the second contact electrode CTE2 is disposed may be disposed to be spaced apart from a portion of a surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

[0172] In an embodiment, the first contact electrode CTE1 and the anode AND may be adhered to each other by a conductive adhesive member. The conductive adhesive member may include, for example, an anisotropic conductive film, an anisotropic conductive paste, etc. In some embodiments, the first contact electrode CTE1 and the anode AND may be adhered to each other by a welding process. When the first contact electrode CTE1 and the anode AND are adhered to each other, resistance may be reduced.

[0173] In an embodiment, the second contact electrode CTE2 and the cathode CTD may be adhered to each other by a conductive adhesive member. The conductive adhesive member may include, for example, an anisotropic conductive film, an anisotropic conductive paste, etc. In some embodiments, the second contact electrode CTE2 and the cathode CTD may be adhered to each other by a welding process. When the second contact electrode CTE2 and the cathode CTD are adhered to each other, the resistance may be reduced.

[0174] The side surface connection lines SCL may be formed by applying a conductive material (e.g., including a metal such as silver (Ag) or copper (Cu)) having viscosity (e.g., predetermined viscosity) to the side surface SS, the upper surface US, and the back surface BS of the substrate SUB and hardening the applied conductive material. In an embodiment, the side surface connection lines SCL may be formed by printing and applying a conductive material to the side surface SS, the upper surface US, and the back surface BS of the substrate SUB using a stamping method and hardening the applied conductive material.

[0175] The side surface connection lines SCL may be completely located on the side surface SS of the substrate SUB, or may be located to be spaced apart from each other in the first direction DR1. A method using a laser may be used as a method for hardening a conductive material to form the side surface connection lines SCL. However, due to the characteristics of the laser, the heating area may be limited to a very narrow range. Therefore, it may take a long time to harden the conductive material using a laser to form the side surface connection lines SCL. Therefore, a method for reducing the time required to form the side surface connection lines SCL is needed.

[0176] Figure 8 Schematically shows the formation Figure 5 FIG. 1 is a diagram showing an embodiment of a process for forming the side surface connection lines SCL of the display device 10 .

[0177] refer to Figure 8 The method of manufacturing the side surface connection line SCL according to the embodiment of the present disclosure may include a step of irradiating electromagnetic waves onto one surface (eg, the side surface) of the substrate SUB using the electromagnetic wave output device 800 . Figure 8 The side surface connection lines SCL shown may be a conductive material for forming the side surface connection lines SCL.

[0178] The electromagnetic wave output device 800 may generate and output electromagnetic waves. The electromagnetic waves may be, for example, microwaves. The electromagnetic wave output device 800 may include a magnetron that generates electromagnetic waves (eg, microwaves). The electromagnetic waves output from the electromagnetic wave output device 800 may have an electric field and a magnetic field. For ease of description, Figure 8 The magnetic field MF of the electromagnetic wave is shown in FIG.

[0179] By the magnetic field MF, an induced current may be formed in the side surface connection line SCL. The direction of the induced current generated in the side surface connection line SCL may be, for example, the third direction DR3.

[0180] By the induction current generated in the side surface connection line SCL, heat may be generated in the side surface connection line SCL. The conductive material may be hardened by the heat generated by the induction current. When the conductive material is hardened, the side surface connection line SCL may be formed.

[0181] The wavelength of the microwave may be in the range of about 1 mm to about 1 m. The electromagnetic wave output device 800 may irradiate electromagnetic waves having a wavelength in the range of about 1 mm to about 1 m (or having a frequency in the range of about 300 MHz (megahertz) to about 30 GHz (gigahertz)) onto the side surface connection lines SCL.

[0182] The wavelength of the electromagnetic wave output from the electromagnetic wave output device 800 may be appropriately selected within the above range according to the kind of conductive material, the thickness of the side surface connection line SCL, etc. For example, a plurality of options for outputting electromagnetic waves with different wavelengths may be provided in the electromagnetic wave output device 800 .

[0183] In an embodiment where the thickness of the side surface connection line SCL is about 2 μm and the conductive material constituting the side surface connection line SCL is silver (Ag), the induced current may flow from the surface of the side surface connection line SCL to a depth of about 2 μm by an electromagnetic wave having a frequency of 2.45 GHz. In an embodiment where the thickness of the side surface connection line SCL is about 2 μm and the conductive material constituting the side surface connection line SCL is copper (Cu), the induced current may flow from the surface of the side surface connection line SCL to a depth of about 1.3 μm by an electromagnetic wave having a frequency of 2.45 GHz. However, the present disclosure is not limited to the above numerical values, and the above embodiments are merely examples for describing the present disclosure.

[0184] The frequency and wavelength of the electromagnetic wave output from the electromagnetic wave output device 800 can be appropriately selected based on the material constituting the side surface connection line SCL, etc. within a range where the frequency and wavelength of the electromagnetic wave are controlled so that the induced current can flow within a range less than or equal to the thickness of the side surface connection line SCL.

[0185] The time when the side surface connection line SCL is heated by the electromagnetic wave output device 800 and the temperature at which the side surface connection line SCL is heated by the electromagnetic wave output device 800 can be variable, as long as the conductive material constituting the side surface connection line SCL can be hardened at the temperature within the time, and the range of the time when the side surface connection line SCL is heated by the electromagnetic wave output device 800 and the temperature at which the side surface connection line SCL is heated by the electromagnetic wave output device 800 is not limited. For example, in an embodiment in which the thickness of the side surface connection line SCL is about 2 μm and the conductive material constituting the side surface connection line SCL is copper (Cu), by irradiating an electromagnetic wave with a frequency of 2.45 GHz for about one second, the temperature of the side surface connection line SCL can be increased to about 500° C. by the induction current. However, the present disclosure is not limited to the above numerical values, and the above embodiments are merely examples for describing the present disclosure.

[0186] The power supplied to the electromagnetic wave output device 800 may be variable as long as electromagnetic waves having a predetermined wavelength and a predetermined frequency can be generated by the power, and the range of the power is not limited.

[0187] Therefore, the conductive material applied in a wide area can be efficiently heated. Therefore, the time required to form the side surface connection line SCL can be shortened.

[0188] Fig. 9A and Fig. 9B Schematically shows Figure 8 The electromagnetic wave output device 800 shown includes an implementation of an electromagnetic wave output unit 910 .

[0189] The electromagnetic wave output unit 910 may irradiate electromagnetic waves onto a side surface of the display device 10 in the first direction DR1 or the second direction DR2 of the display device 10 .

[0190] Although the size of the electromagnetic wave output unit 910 is shown to be smaller than the length of the short side of the display device 10 (e.g., one side in a direction parallel to the first direction DR1), the present disclosure is not limited thereto. For example, the size of the electromagnetic wave output unit 910 may be smaller than the length of the short side of the display device 10, or equal to (or substantially equal to) the length of the short side of the display device 10. In some embodiments, the size of the electromagnetic wave output unit 910 may be smaller than the length of the long side of the display device 10 (e.g., the other side parallel to the second direction DR2), or equal to (or substantially equal to) the length of the long side of the display device 10. In some embodiments, the size of the electromagnetic wave output unit 910 may be greater than the length of the long side of the display device 10.

[0191] The electromagnetic wave output unit 910 may irradiate electromagnetic waves (eg, microwaves) onto the side surface of the display device 10 in a state where the display device 10 is mounted on the stand STG.

[0192] refer to Fig. 9B , the electromagnetic wave output unit 910 may move. The electromagnetic wave output unit 910 may move at a first speed v1 along one side of the display device 10 (e.g., a short side parallel to the first direction DR1 in the display device 10). The electromagnetic wave output unit 910 may move at a second speed v2 along another side of the display device 10 (e.g., a long side parallel to the second direction DR2 in the display device 10). The first speed v1 and the second speed v2 may be equal (or substantially equal), but the present disclosure is not limited thereto. For example, the first speed v1 may be greater than the second speed v2, or the second speed v2 may be greater than the first speed v1. For example, each of the first speed v1 and the second speed v2 may be set to approximately 100 mm / s, but the present disclosure is not limited thereto.

[0193] The depth of the region in which the induced current flows may vary according to the moving speed of the electromagnetic wave output unit 910. For example, in the case where the moving speed of the electromagnetic wave output unit 910 is relatively slow, the side surface connection line SCL (see Figure 8 ) can be relatively large in the depth of the region in which the induced current in the side surface connection line SCL flows. For example, in the case where the moving speed of the electromagnetic wave output unit 910 is relatively fast, the depth of the region in which the induced current in the side surface connection line SCL flows can be relatively small. The moving speed of the electromagnetic wave output unit 910 can be determined within the range in which the side surface connection line SCL can be hardened. For example, in the case where the side surface connection line SCL is formed thin, even if the moving speed of the electromagnetic wave output unit 910 is relatively high, the side surface connection line SCL can be properly hardened. Therefore, the time required to form the side surface connection line SCL can be shortened.

[0194] In some embodiments, the electromagnetic wave output unit 910 may reciprocate along one side and / or another side of the display device 10 .

[0195] The electromagnetic wave output unit 910 may irradiate electromagnetic waves while moving along a side edge of the display device 10 (e.g., a short side edge of the display device 10 parallel to the first direction DR1). For example, the electromagnetic wave output unit 910 may irradiate (e.g., continuously irradiate) electromagnetic waves having uniform intensity while moving along the short side edge of the display device 10. For example, the electromagnetic wave output unit 910 may irradiate (e.g., continuously irradiate) electromagnetic waves having uniform intensity while moving along the long side edge of the display device 10. However, the present disclosure is not limited thereto, and the electromagnetic wave output unit 910 may intermittently irradiate electromagnetic waves while moving along one side edge and / or another side edge of the display device 10.

[0196] Fig. 10A and Fig. 10B Schematically shows Figure 8 The illustrated electromagnetic wave output device 800 includes multiple implementations of electromagnetic wave output units 1010 and 1020 .

[0197] The electromagnetic wave output device 800 (see Figure 8 ) may include a plurality of electromagnetic wave output units 1010 and 1020. Fig. 10A and Fig. 10B The electromagnetic wave output device 800 may include a first electromagnetic wave output unit 1010 and a second electromagnetic wave output unit 1020 .

[0198] refer to Fig. 9A and Fig. 9B The description given of the electromagnetic wave output unit 910 can be equally applied to Fig. 10A and Fig. 10B Each of the electromagnetic wave output units 1010 and 1020 shown.

[0199] The first electromagnetic wave output unit 1010 may irradiate electromagnetic waves onto a side surface of the display device 10 in a second direction DR2 of the display device 10 .

[0200] The second electromagnetic wave output unit 1020 may irradiate electromagnetic waves onto a side surface of the display device 10 in the first direction DR1 of the display device 10 .

[0201] Although the size of the first electromagnetic wave output unit 1010 is shown to be smaller than the length of the short side (e.g., one side in a direction parallel to the first direction DR1) of the display device 10, the present disclosure is not limited thereto. For example, the size of the first electromagnetic wave output unit 1010 may be smaller than the length of the short side of the display device 10, or may be equal to (or substantially equal to) the length of the short side of the display device 10. In some embodiments, the size of the first electromagnetic wave output unit 1010 may be larger than the length of the short side of the display device 10.

[0202] The size of the second electromagnetic wave output unit 1020 may be smaller than the length of the long side (the other side in the direction parallel to the second direction DR2) of the display device 10, or may be equal to (or substantially equal to) the length of the long side of the display device 10. In some embodiments, the size of the second electromagnetic wave output unit 1020 may be larger than the length of the long side of the display device 10.

[0203] Each of the first electromagnetic wave output unit 1010 and the second electromagnetic wave output unit 1020 may irradiate electromagnetic waves (eg, microwaves) onto a side surface of the display device 10 in a state in which the display device 10 is mounted on the stand STG.

[0204] refer to Fig. 10B , the first electromagnetic wave output unit 1010 and the second electromagnetic wave output unit 1020 can move.

[0205] The first electromagnetic wave output unit 1010 may move at a first speed v1 along one side of the display device 10 (e.g., a short side parallel to the first direction DR1 in the display device 10). The second electromagnetic wave output unit 1020 may move at a second speed v2 along another side of the display device 10 (e.g., a long side parallel to the second direction DR2 in the display device 10). The first speed v1 and the second speed v2 may be equal (or substantially equal), but the present disclosure is not limited thereto. For example, the first speed v1 may be greater than the second speed v2, or the second speed v2 may be greater than the first speed v1.

[0206] In some embodiments, the first electromagnetic wave output unit 1010 may reciprocate along one side of the display device 10. In some embodiments, the second electromagnetic wave output unit 1020 may reciprocate along another side of the display device 10.

[0207] The first electromagnetic wave output unit 1010 may irradiate electromagnetic waves while moving along a side of the display device 10 (e.g., a short side parallel to the first direction DR1 in the display device 10). For example, the first electromagnetic wave output unit 1010 may irradiate (e.g., continuously irradiate) electromagnetic waves having uniform intensity while moving along the short side of the display device 10. However, the present disclosure is not limited thereto, and the first electromagnetic wave output unit 1010 may intermittently irradiate electromagnetic waves while moving along a side of the display device 10.

[0208] The second electromagnetic wave output unit 1020 may irradiate electromagnetic waves while moving along another side of the display device 10 (e.g., a long side of the display device 10 parallel to the second direction DR2). For example, the second electromagnetic wave output unit 1020 may irradiate (e.g., continuously irradiate) electromagnetic waves having uniform intensity while moving along the long side of the display device 10. However, the present disclosure is not limited thereto, and the second electromagnetic wave output unit 1020 may intermittently irradiate electromagnetic waves while moving along another side of the display device 10.

[0209] Fig.11 is schematically shown in Figure 8 The electromagnetic wave output device 800 and Figure 5 FIG. 1 is a view of a side surface connection line SCL of a display device shown in FIG.

[0210] refer to Fig.11 , the electromagnetic wave output device 800 may irradiate electromagnetic waves, thereby forming a magnetic field MF, and the magnetic field MF may form an induced current in the side surface connection line SCL.

[0211] The direction of the induced current generated in the side surface connection line SCL may be, for example, a direction parallel to the third direction DR3 .

[0212] The electromagnetic wave output device 800 (for example, the electromagnetic wave output units 910, 1010 and 1020 (see 9A to 10B )) to control the depth D3 of the region in which the induced current in the side surface connection line SCL flows. For example, in the case where the moving speed of the electromagnetic wave output device 800 is relatively low, the depth D3 of the region in which the induced current flows may be relatively large. For example, in the case where the moving speed of the electromagnetic wave output device 800 is relatively high, the depth D3 of the region in which the induced current flows may be relatively small.

[0213] The depth D3 of the region in which the induction current flows may be less than the thickness D1 of the side surface connection line SCL. The thickness D1 of the side surface connection line SCL may correspond to the distance from the upper surface of the side surface connection line SCL to the substrate SUB. In the case where the depth D3 of the region in which the induction current flows is equal to or greater than the thickness D1 of the side surface connection line SCL, the side surface connection line SCL may be hardened in the region in which the side surface connection line SCL and the substrate SUB contact each other. The adhesion between the side surface connection line SCL and the substrate SUB may be weakened. Therefore, the moving speed of the electromagnetic wave output device 800 may be controlled within the range in which the depth D3 of the region in which the induction current flows is less than the thickness D1 of the side surface connection line SCL. For example, the moving speed of the electromagnetic wave output device 800 may be set to be inversely proportional to the thickness D1 of the side surface connection line SCL. For example, the depth D3 of the region in which the induction current flows may be set within the range in which the depth D3 of the region in which the induction current flows is less than the thickness D1 of the side surface connection line SCL and greater than half of the thickness D1 of the side surface connection line SCL. However, the present disclosure is not limited thereto.

[0214] refer to Fig.11 , showing that the range of the magnetic field MF (eg, the magnetic field MF capable of forming an induced current) is greater than the height D2 of the side surface connection line SCL. However, the present disclosure is not limited thereto, and the range of the magnetic field MF may be equal to or less than the height D2 of the side surface connection line SCL.

[0215] Fig.12 is a schematic diagram showing the arrangement in which Figure 8 The illustrated process is a view of a planar heating pattern 1200 in a side surface connection line SCL formed.

[0216] refer to Fig.12 , the side surface connection line SCL according to the embodiment of the present disclosure may include a planar heating pattern 1200. The side surface connection line SCL according to the embodiment of the present disclosure may include a planar heating pattern 1200 through the electromagnetic wave output device 800 (see Figure 8 ) A planar heating pattern 1200 is formed when the side surface connection line SCL is heated in units of a plane.

[0217] The planar heating pattern 1200 can be seen on a plane defined by the first direction DR1 and the third direction DR3 and on a plane defined by the second direction DR2 and the third direction DR3. The planar heating pattern 1200 can be formed by uniformly heating a region having an area and can be distinguished from a line heating pattern presented as a wave pattern. The line heating pattern described above can be formed in a process of heating a narrow region using a laser.

[0218] According to an embodiment of the present disclosure, a wide area of ​​the side surface connection line SCL can be hardened by planar heating. Therefore, the time required to form the side surface connection line SCL can be greatly shortened.

[0219] In the display device and the manufacturing method thereof according to the present disclosure, the time required to form the side surface connection line can be shortened.

[0220] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the above-described disclosed embodiments may be implemented individually or in combination with each other.

[0221] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and it should be interpreted that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A method for manufacturing a display device, the method comprising: forming a pad portion on an upper surface of the substrate; forming a lower electrode on the lower surface of the substrate; connecting the lower electrode and the flexible circuit board to each other; providing a conductive material for electrically connecting the pad portion and the lower electrode to each other on a side surface of the substrate; as well as A side surface connection line is formed by irradiating an electromagnetic wave having a wavelength onto the conductive material on the side surface of the substrate by an electromagnetic wave output device.

2. The method according to claim 1, wherein: The wavelength of the electromagnetic wave is in the range of 1 mm to 1 m.

3. The method according to claim 1, wherein: The upper surface and the lower surface are arranged parallel to a plane defined by a first direction and a second direction perpendicular to each other, and The side surface connection line extends in a third direction perpendicular to the first direction and the second direction, and electrically connects the pad portion and the lower electrode to each other.

4. The method according to claim 3, wherein: The electromagnetic wave output device includes at least one electromagnetic wave output unit, and The at least one electromagnetic wave output unit moves in the first direction or the second direction.

5. The method according to claim 4, wherein: The at least one electromagnetic wave output unit moves in the first direction along one side of the substrate and moves in the second direction along another side of the substrate, and Wherein, a speed at which the at least one electromagnetic wave output unit moves in the first direction is the same as a speed at which the at least one electromagnetic wave output unit moves in the second direction.

6. The method according to claim 4, wherein: The at least one electromagnetic wave output unit comprises: a first electromagnetic wave output unit, moving in the first direction along a side edge of the substrate; and A second electromagnetic wave output unit moves in the second direction along the other side of the substrate, Wherein, the moving speed of the first electromagnetic wave output unit is the same as the moving speed of the second electromagnetic wave output unit.

7. The method according to claim 4, wherein: The moving speed of the at least one electromagnetic wave output unit is set according to the thickness of the side surface connection line, and Wherein, the moving speed of the at least one electromagnetic wave output unit is set to be inversely proportional to the thickness of the side surface connecting line.

8. The method according to claim 1, wherein: The electromagnetic wave output device includes a magnetron that generates microwaves.

9. A display device, comprising: A pad portion is disposed on the upper surface of the substrate; A lower electrode disposed on a lower surface of the substrate, the lower electrode being electrically connected to the flexible film; as well as a side surface connection line electrically connecting the pad portion and the lower electrode to each other, the side surface connection line comprising a conductive material, The side surface connection line is formed by heating with an electromagnetic wave having a wavelength.

10. The display device according to claim 9, further comprising: A pixel circuit layer is arranged on the substrate in the display area; as well as A display element layer is arranged on the pixel circuit layer, wherein the pad portion is electrically connected to the pixel circuit layer or the display element layer, and Wherein, the display element layer includes micro light emitting diodes.

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