Power package with connection components and process for

Abstract

A semiconductor package includes: a metal substrate; at least one transistor die disposed on the metal substrate; and one or more metal contacts configured to be positioned adjacent to the metal substrate through a connection portion. The connection portion is configured as one of a spot welded portion, a laser beam modified portion, a laser beam welded portion, an ultrasonic welded portion, a resistance welded portion, and a fusion welded metal welded portion.

Description

Technical Field

[0001] The present disclosure relates to a power package with a connection component. The present disclosure also relates to a process for realizing a power package with a connection component. Background Art

[0002] A typical power package includes a terminal, an active device, and a heat sink. The terminal is originally part of a lead frame strip. A typical connection method uses a rivet technique to form a connection portion with one or more rivets to combine the heat sink with the lead frame strip. The rivets consume a lot of space on the front side of the heat sink and reduce the amount of available die attachment area of ​​the package. The thicker the heat sink, the more it is necessary to place the rivet inside the package, or towards the middle of the heat sink. This area inside the package cannot be used to place components such as active devices. In addition, the size of the terminal must be designed to avoid the location of the rivet and / or must be sufficiently spaced from the location of the rivet; and the size of the active device must be proportional to the terminal. Therefore, the rivet usually reduces the size of the terminal, reduces the size of the active device, reduces the size of the available die attachment area, and so on. In addition, the rivet manufacturing process is time-consuming and the rivet manufacturing process is costly.

[0003] Therefore, there is a need for a package that implements component connections with more efficient use of space, a package that implements a less expensive manufacturing process, a package that implements a less time-consuming manufacturing process, and the like. Summary of the invention

[0004] One aspect includes a semiconductor package comprising: a metal substrate; at least one transistor die arranged on the metal substrate; and one or more metal contacts configured to be positioned adjacent to the metal substrate through a connection portion, wherein the connection portion is configured as one of the following: a spot welding portion, a laser beam modified portion, a laser beam welding portion, an ultrasonic welding portion, a resistance welding portion, and a fusion metal welding portion.

[0005] One aspect includes a semiconductor package comprising: a metal substrate; at least one transistor die arranged on the metal substrate; and one or more metal contacts configured to be positioned adjacent to the metal substrate via a connection portion, wherein the one or more metal contacts are configured to be positioned adjacent to the metal substrate via a lead frame, and the lead frame is welded to the metal substrate via the connection portion.

[0006] One aspect includes a process for implementing a process for implementing a semiconductor package, comprising: providing a metal substrate; arranging at least one transistor die on the metal substrate; configuring one or more metal contacts to be positioned adjacent to the metal substrate through a connection portion; and forming the connection portion as one of: a spot welding portion, a laser beam modified portion, a laser beam welding portion, an ultrasonic welding portion, a resistance welding portion, and a fusion metal welding portion.

[0007] By considering the following detailed description, drawings and claims, additional features, advantages and aspects of the present disclosure may be illustrated or apparent. In addition, it should be understood that both the foregoing summary of the present disclosure and the following detailed description are exemplary and intended to provide further explanation without limiting the scope of the present disclosure claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification, which illustrate various aspects of the present disclosure and are used to explain the principles of the present disclosure together with the detailed description. It is not intended to show more detailed structural details of the present disclosure than are necessary for a basic understanding and various practical modes of the present disclosure. In the drawings:

[0009] Figure 1 A top view of a package according to the present disclosure is shown.

[0010] Figure 2 Shown according to Figure 1 A cross-sectional side view of the package.

[0011] Figure 3 Shown according to Figure 1 A partial top view of the package.

[0012] Figure 4A , Figure 4B and Figure 4C is a top view of a lead frame strip according to an aspect of the present disclosure.

[0013] Figure 5A and Figure 5B is a top view of a package during an intermediate manufacturing process according to aspects of the present disclosure.

[0014] Fig. 6A is a top view of a package during an intermediate manufacturing process according to aspects of the present disclosure.

[0015] Figure 6B is a top view of a package according to aspects of the present disclosure.

[0016] Figure 7 Shown according to Figure 1A partial top view of the package.

[0017] Figure 8 Shown according to Figure 7 A partial side view of the package.

[0018] Fig. 9 Shown according to Figure 1 Another partial top view of the package.

[0019] Fig.10 An exemplary implementation of a fabrication attachment process according to aspects of the present disclosure is shown.

[0020] Fig.11 An exemplary implementation of a fabrication attachment process according to aspects of the present disclosure is shown.

[0021] Fig.12 Shown according to Figure 1 A cross-sectional side view of the package.

[0022] Fig.13 A process for manufacturing a package according to the present disclosure is shown.

[0023] Fig.14A A current implementation of a lead frame strip is shown.

[0024] Fig. 14B Shows the use of Fig.14A Current implementation of lead frame strip packaging.

[0025] Fig.15A and Fig. 15B Shown is the method for generating Fig.14A The steps of the connection part of the current implementation of the package.

[0026] Fig.16 Another current implementation of encapsulation is shown.

[0027] Fig.17 Another current implementation of encapsulation is shown.

[0028] Fig.18 Implementation problems with current implementations of encapsulation are shown. DETAILED DESCRIPTION

[0029] The various aspects of the present disclosure and its various features and advantageous details are explained more fully with reference to the non-limiting aspects and examples described and / or shown in the accompanying drawings and detailed in the following description. It should be noted that the features shown in the drawings are not necessarily drawn to scale, and as will be appreciated by those skilled in the art, the features of one aspect may be adopted with other aspects even if not explicitly stated herein. The description of well-known components and processing techniques may be omitted so as not to unnecessarily confuse the various aspects of the present disclosure. The examples used herein are intended only to facilitate understanding of the manner in which the present disclosure may be practiced, and further enable those skilled in the art to practice the various aspects of the present disclosure. Therefore, the examples and aspects herein should not be interpreted as limiting the scope of the present disclosure, which is limited only by the appended claims and applicable laws. In addition, it is noted that the same reference numerals represent similar parts throughout the several views of the accompanying drawings and in the different embodiments disclosed.

[0030] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0031] It should be understood that when an element (such as a layer, a region or a substrate) is referred to as being "on" or extending "on" another element, it can be directly on or directly extending to another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on" another element or "directly" extending to "on" another element, there is no intermediate element. Similarly, it should be understood that when an element (such as a layer, a region or a substrate) is referred to as being "on" another element or extending "on" another element, it can be directly on or directly on another element, or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly on" another element or "directly on" another element, there is no intermediate element. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0032] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0033] The terms used herein are only for the purpose of describing specific aspects and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprise", "comprising", "include" and / or "including" when used herein specify the presence of the described features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that the terms used herein should be interpreted as having the same meaning as they have in the context of this specification and in the relevant field, and will not be interpreted as idealized or overly formal meanings unless explicitly defined as such herein.

[0035] Fig.14A A current implementation of a lead frame strip is shown.

[0036] Fig. 14B Shows the use of Fig.14A Current implementation of lead frame strip packaging.

[0037] Fig.15A and Fig. 15B Shown is the method for generating Fig.14A The steps of the connection part of the current implementation of the package.

[0038] Fig.16 Another current implementation of encapsulation is shown.

[0039] like Fig. 14B As shown in , the current implementation of the current package 1 includes terminals 2, active devices 3 and passive devices and a heat sink 4. Fig.14A As shown in FIG, the terminal 2 is originally part of the lead frame strip 9. The current package 1 uses rivet technology to form a connection with the rivet 6 to combine the heat sink 4 (also called flange, heat sink, coin, etc.) with the lead frame strip 9 including the terminal 2. Fig.15A and Fig. 15B The current steps for forming these connections include: Fig.15A As shown in FIG. 5 , a hole 5 is punched on the back side of the heat sink 4 to form a cylindrical protrusion 8 on the front side of the heat sink 4, as shown in FIG. Fig. 15B . The cylindrical protrusion 8 will then provide material for the rivet 6 to rivet the lead frame strip 9 including the terminal 2 to the heat sink 4. The thicker the heat sink 4, the larger the corresponding implementation of the hole and the cylindrical protrusion 8, which requires a more robust tool to create the cylindrical protrusion 8 on the front side of the heat sink 4. Therefore, the thicker implementation of the heat sink 4 requires the resulting configuration of the cylindrical protrusion 8 and the rivet 6 to be larger and moved closer to the center of the heat sink 4, thereby consuming more available space on the heat sink 4. Next, the lead frame strip 9 is positioned on the heat sink 4, which will now be etched or punched into a shape including the eyelet 7. The lead frame strip 9 is then placed on top of the heat sink 4, with the cylindrical protrusion 8 extending through the eyelet 7. The tool is then pressed down on the cylindrical protrusion 8 to deform the cylindrical protrusion 8 and form the rivet 6 to rivet the lead frame strip 9 including the terminal 2 to the heat sink 4, as shown in the right figure of FIG. 15. This procedure of including the rivet 6 consumes a large amount of space on the front side of the heat sink 4 and reduces the amount of available die attach area of ​​the current package 1. The thicker the heat sink 4, the thicker the stamping tool needs to be, and the rivet 6 will have to be placed further inside the current package 1, or towards the middle of the heat sink 4. This area inside the current package 1 cannot be used to place components such as the active device 3. In addition, the size of the terminals 2 must be designed to avoid the location of the rivet 6 to be electrically isolated from each other in the final product. In this regard and with reference to Fig. 14B , the terminal 2 has a terminal width 10 that is smaller than the rivet distance 11, which is the distance between the inner surfaces of adjacent implementations of the rivet 6. In addition, the width of the active device 3, in particular the power device, is generally proportional to the terminal width 10. Therefore, as Fig. 14B As shown in , the current package 1 forms a usable die attach area 14 .

[0040] refer to Fig.16 , the current package 1 is implemented with a thicker implementation of the heat sink 4. As a result, the position of the rivet 6 is moved closer to the center of the heat sink 4, the terminal width 10 of the terminal 2 is reduced, the rivet distance 11 is reduced, and the available die attach area 14 is reduced. Especially for small packages with an implementation of the heat sink 4 of about 1 mm thickness, this "wasted" area outside the available die attach area 14 on the heat sink 4 becomes quite large compared to the available area (effective area - available die attach area 14) available for components on the heat sink 4 of the current package 1.

[0041] Fig.17A location 18 is shown where the pin clamp is located during molding to hold the current package 1 down. Specifically, the pin clamp engages the interior of the package on top of the rivet 6. This need for location 18 further limits the terminal width 10 of the terminal 2.

[0042] Fig.18 FIG. 1 shows a visualization of implementation issues of a current package 1 when implemented as a push-pull package. In this regard, the push-pull package may include two terminals 2 on each side. Fig.18 As shown in , since the position of the rivet 6 coincides with the position of the terminal 2, a push-pull package will not be feasible.

[0043] In this regard, utilizing the rivet technology utilized in current packages 1 reduces the available die attach area 14. Furthermore, the rivet manufacturing process is time consuming and the rivet manufacturing process is costly.

[0044] The present disclosure relates to a device and method, which utilizes a manufacturing attachment process such as spot welding, laser welding, ultrasonic welding, etc. to combine a heat sink to a lead frame. In this regard, a lead frame is a thin metal layer that connects the wires of an electronic terminal on a semiconductor surface to a large-scale circuit system on an electronic device and a circuit board. Almost all semiconductor packages use a lead frame. In various aspects, the heat sink and the lead frame can have the same thickness, or the heat sink and the lead frame have different thicknesses. The heat sink and the lead frame can have the same thickness, or the heat sink and the lead frame have different thicknesses.

[0045] Specifically, the disclosed apparatus and method may combine a lead frame strip with a heat sink, coin, flange, etc. using a fabrication attachment process such as spot welding, laser welding, ultrasonic welding, and the like. The method may not require any preparation on the heat sink side, and thus no cylindrical protrusions are required in preparation for the combination of the two materials.

[0046] In various aspects, a small mark or protrusion of the lead frame may be all that is needed to achieve a fabrication attachment process, such as having a small spot weld connection between the lead frame and the heat sink. The small mark may also be changed for different lead frame configurations without changing the tooling to produce the cylindrical protrusions used in the current process described above. All that may be needed is, for example, changing the pin position on the spot weld tip.

[0047] In addition to spot welding techniques, the disclosed apparatus and methods may use laser spot welding, which uses a laser to create a single point to weld metals together. In this regard, using a manufacturing attachment process such as spot welding, laser spot welding, ultrasonic welding, etc. will be more efficient and create more space in the die tray area of ​​the heat sink compared to current riveted package designs as described above.

[0048] In this regard, the available space for die attachment is proportional to the lead width, and the apparatus and methods of the present disclosure are advantageous in using a fabrication attachment process, such as spot welding techniques, ultrasonic welding techniques, laser welding techniques, etc., to increase the available space for die attachment compared to packages implementing the current riveting methods described above.

[0049] In this case, in some implementations, the disclosed apparatus and methods can achieve approximately 40% more die attach area on the heat sink, which directly translates into how much power the package can achieve. The disclosed apparatus and methods can also improve the efficiency of the package. Specifically, the efficiency of the available die attach area relative to the total package size.

[0050] The spot weld area can then also be used for a mold fixture to hold the package down during subsequent manufacturing, which is located on the outermost side of the package, which is more preferred than a cylindrical pin fixture inside the package on top of the rivet. In addition, the various aspects described herein can be implemented using a package that can also be used to combine lead frame materials to heat sinks for other types of semiconductor devices. In this regard, the disclosed apparatus and method are implemented in response to the difficulty of not having enough available die attach area, as the rivets of current packages can consume almost 50% of the total package size.

[0051] Figure 1 A top view of a package according to the present disclosure is shown.

[0052] Figure 2 Shown according to Figure 1 A cross-sectional side view of the package.

[0053] Figure 3 Shown according to Figure 1 A partial top view of the package.

[0054] Specifically, Figure 1 , Figure 2 and Figure 3 An exemplary implementation of a package 100 is shown, which may be implemented as a power package, a radio frequency (RF) package, an RF transistor package, an RF power amplifier package, an RF power transistor package, an RF power amplifier transistor package, a semiconductor package, etc. as described herein. Figure 1 , the package 100 may include one or more metal contacts 404 and an overmold arrangement 430 .

[0055] refer to Figure 2, the package 100 may include one or more semiconductor devices 400, one or more interconnects 104, and a metal substrate 102. The one or more interconnects 104 may couple the one or more semiconductor devices 400 to a first one of the one or more metal contacts 404, a second one of the one or more metal contacts 404, and so on. In addition, the one or more interconnects 104 may couple multiple implementations of the one or more semiconductor devices 400. In addition, inside the package 100, the one or more semiconductor devices 400 may be arranged on the metal substrate 102 via a die attach material 422.

[0056] For the sake of clarity, Figure 3 The package 100 is shown without the one or more interconnects 104 and the overmold arrangement 430 . Figure 3 It is shown that the package 100 may include a label portion 406 that was originally part of a lead frame 408 as shown in FIG4. In addition, as further described herein, one or more metal contacts 404 are also part of the lead frame 408. The label portion 406 that was originally part of the lead frame 408 has been configured to form a connection 410 to the metal substrate 102. In other words, the connection 410 is formed to attach the lead frame 408, as well as the label portion 406 and the one or more metal contacts 404, to the metal substrate 102 during the manufacture of the package 100, as further described herein.

[0057] Figure 4A , Figure 4B and Figure 4C is a top view of a lead frame strip according to an aspect of the present disclosure.

[0058] Figure 5A and Figure 5B is a top view of a package during an intermediate manufacturing process according to aspects of the present disclosure.

[0059] Fig. 6A is a top view of a package during an intermediate manufacturing process according to aspects of the present disclosure.

[0060] Figure 6B is a top view of a package according to aspects of the present disclosure.

[0061] Specifically, Figure 4A 4 is a top view of the strip of material that will form the lead frame strip 490. In this regard, the Figure 4A The strip of material shown in FIG. 4 is processed to form a lead frame strip 490 having portions of lead frame 408 , as further described herein.

[0062] Figure 4B4 is a top view of lead frame strip 490 after further processing, showing portions of lead frame 408. For ease of illustration, Figure 4C A single portion of the plurality of portions of the lead frame 408 of the lead frame strip 490 is shown. In this regard, Figure 4C The lead frame strip 490 shown in FIG. 4 may include multiple portions of the lead frame 408 , as shown by the dashed lines.

[0063] The lead frame 408 may include one or more metal contacts 404, a marking portion 406, and a lead frame portion 420. The lead frame portion 420 may initially connect the marking portion 406 to the one or more metal contacts 404. Specifically, during manufacture of the package 100, the lead frame 408 may be formed from the one or more metal contacts 404, the marking portion 406, and the lead frame portion 420. In this regard, the lead frame 408 may be formed from a strip of metal material that is processed to form a lead frame strip 490 having the one or more metal contacts 404, the marking portion 406, and the lead frame portion 420. More specifically, the lead frame strip 490 may be stamped, punched, etched (and / or the like) to form the lead frame 408, the one or more metal contacts 404, the marking portion 406, and the lead frame portion 420 from the metal strip. In this regard, as Figure 4B As shown in , a lead frame strip 490, which may have a plurality of lead frames 408, may be formed with open spaces between implementations of one or more metal contacts 404, lead frame portions 420, and / or indicia portions 406. Additionally, indicia portions 406 may be configured as tabs, extensions, portions, and the like.

[0064] also, Figure 4C The lead frame 408 shown in FIG. 4 including the marking portion 406, one or more metal contacts 404, etc. is merely exemplary. In this regard, the lead frame 408 including the marking portion 406, one or more metal contacts 404, etc. can take any desired form depending on the application and / or implementation of the package 100. In addition, the lead frame strip 490 can include multiple lead frames 408 for forming multiple packages 100. In this regard, the lead frame strip 490 can be used in a plurality of packages 100. Figure 4B The x-axis shown in and / or Figure 4B The lead frame 408 may extend in one or both of the Z axes shown in FIG. 4 for use in manufacturing multiple packages 100 .

[0065] like Figure 5A As shown in , thereafter, a lead frame strip 490 that may have multiple portions of a lead frame 408 may be arranged on multiple portions of the metal substrate 102. For ease of illustration, Figure 5BA single portion of the plurality of portions of the lead frame 408 of the lead frame strip 490 and one of the plurality of portions of the metal substrate 102 are shown. In this regard, each connection 410 can be formed to connect one or more metal contacts 404 of the lead frame 408 and the marking portion 406 of the lead frame 408 to the metal substrate 102. Specifically, the connection 410 can be formed to connect one or more metal contacts 404 of the lead frame 408 and the marking portion 406 of the lead frame 408 to the metal substrate 102 using a manufacturing attachment process. The manufacturing attachment process will be further described below. In various aspects, the one or more metal contacts 404 are configured to be positioned within the package 100 by the lead frame 408 of the lead frame strip 490, which is attached to the metal substrate 102 by the connection 410.

[0066] like Fig. 6A As shown in FIG. 1 , one or more semiconductor devices 400 may be arranged on a metal substrate 102, and one or more interconnects 104 may be attached to the one or more semiconductor devices 400 and / or one or more metal contacts 404. Thereafter, as shown in FIG. Figure 6B As shown in , an overmold configuration 430 (shown as transparent with dashed lines for clarity of illustration) may be disposed on one or more of the metal substrate 102, the one or more interconnects 104, the one or more semiconductor devices 400, etc. Thereafter, as Figure 6B As shown in FIG. 4 , portions of lead frame strip 490 and / or lead frame 408 (such as those shown in FIG. 4 ) may be removed from lead frame strip 490 and / or lead frame 408. Fig. 6A ), thereby leaving one or more metal contacts 404 and the marking portion 406 as part of the package 100.

[0067] Implementations of the disclosed package 100 and associated methods may be used to manufacture Figure 4A Thereafter, the lead frame strip 490 may be etched, cut, etc. to form a lead frame strip 490 as shown in FIG. Figure 4B and Figure 4C The lead frame 408 is shown in FIG.

[0068] Afterwards, if Figure 5A and Figure 5B As shown in , implementations of the disclosed package 100 and associated methods may combine a lead frame strip 490 and / or a lead frame 408 with a metal substrate 102 such that the lead frame strip 490 and / or the lead frame 408 may be attached to the metal substrate 102 via a connection 410 .

[0069] Afterwards, if Figure 5A and Figure 5BAs shown in , the disclosed implementation of the package 100 and associated methods may attach one or more semiconductor devices 400 to a metal substrate 102. Figure 5A and Figure 5B As shown in , during attachment of one or more semiconductor devices 400 to the metal substrate 102 , one or more metal contacts 404 and a flag portion 406 may still be attached to a leadframe strip 490 and / or a leadframe 408 having a leadframe portion 420 .

[0070] Afterwards, if Fig. 6A As shown in FIG. 4 , one or more interconnects 104 may be connected between one or more metal contacts 404 and one or more semiconductor devices 400, for example, by wire bonding. Fig. 6A As further shown in , one or more metal contacts 404 and flag portion 406 may still be attached to leadframe strip 490 and / or leadframe 408 having leadframe portion 420 .

[0071] Thereafter, the disclosed implementations of package 100 and associated methods may form overmold configuration 430, and may then trim leadframe strip 490 and / or leadframe 408 so that one or more metal contacts 404 and labeling portion 406 may be separated from leadframe strip 490 and / or leadframe 408 into individual packages or units of package 100. This electrically isolates one or more metal contacts 404 from leadframe strip 490 and / or leadframe 408 and labeling portion 406, as shown in FIG. Figure 6B as shown in .

[0072] Implementations of the disclosed package 100 and associated methods may utilize various techniques to form the connection 410 between the lead frame 408 and the metal substrate 102. Specifically, the lead frame strip 490 and / or the connection 410 between the lead frame 408 and the metal substrate 102 may be formed utilizing a fabrication attachment process, which may include various welding fabrication processes, etc. In various aspects, the connection 410 between the lead frame 408 and the metal substrate 102 may be formed utilizing a fabrication attachment process, which may include spot welding techniques, laser beam welding techniques, ultrasonic welding techniques, resistance welding techniques, fusion welding techniques, etc., to combine the metal substrate 102 to the lead frame 408. In this regard, one or more metal contacts 404, initially as part of the lead frame 408, may be implemented as a thin metal layer that connects wires from electrical terminals on the surface of one or more semiconductor devices 400 to large-scale circuitry on electronic devices and circuit boards. In this regard, the thickness of one or more of the metal contacts 404 , the flag portion 406 , the lead frame strip 490 , and / or the lead frame 408 may be substantially less than the thickness of the metal substrate 102 .

[0073] Specifically, the disclosed apparatus and methods may utilize a fabrication attachment process to combine the lead frame strip 490 and / or the lead frame 408 with the metal substrate 102. In various aspects, utilizing a fabrication attachment process to form the connection 410 may not require any preparation on the metal substrate 102. In this regard, the metal substrate 102 will not require rivets, cylindrical protrusions, and / or the like as described above in connection with the present package in preparation for combining and / or attaching the lead frame strip 490 and / or the lead frame 408 to the metal substrate 102.

[0074] In various aspects, the marking portion 406 or the protruding portion of the lead frame strip 490 and / or the lead frame 408 can be all that is required to implement the manufacturing attachment process, for forming the connection portion 410 as the connection between the lead frame strip 490 and / or the lead frame 408 and the metal substrate 102. The marking portion 406 can also be changed for different configurations of the lead frame strip 490 and / or the lead frame 408, without the need to change the tool to produce the cylindrical protrusion used in the current process described above. All that may be required is to change the process associated with the manufacturing attachment process. For example, a manufacturing attachment process that can be implemented as spot welding may only require changing the pin position on the spot welding tip.

[0075] Compared to current rivet package designs as described above, the disclosed fabrication attachment process may be more efficient in creating more space for one or more semiconductor devices 400 in the die tray area of ​​the metal substrate 102. In this regard and as Figure 3 , the available space for die attach 412 can be proportional to the terminal width 414 of one or more metal contacts 404, and the devices and methods of the present disclosure are advantageous in using a fabrication attachment process that can increase the available space for die attach 412 and / or the available space on the metal substrate 102 for die attach, such as one or more semiconductor devices 400, compared to packages implementing current rivet methods. In this regard, for current packages, the thicker the heat sink, the more space the rivet requires on the heat sink.

[0076] In this case, in some implementations, the disclosed apparatus and methods can obtain approximately 40% more available space for the die attach 412 and / or die attach area on the metal substrate 102, which directly translates into how much power can be utilized by the package 100. The disclosed apparatus and methods can also improve the efficiency of the package 100. Specifically, the efficiency with respect to the available space for the die attach 412 on the metal substrate 102 relative to the overall size of the package 100.

[0077] The area of ​​the manufacturing attachment process (such as spot welding) that forms the connection 410 and / or the marking portion 406 can then also be used for a mold fixture to hold the package 100 down during a subsequent manufacturing process (such as molding). In this regard, the area of ​​the manufacturing attachment process that forms the connection 410 and / or the marking portion 406 can be located on the very outside of the package 100 and / or the metal substrate 102, which is more preferable than the cylindrical pin fixture inside the current package on top of the rivet of the current design. Return to Reference Figure 1 , the package 100 may include a location 492 configured to receive a mold fixture to hold the package 100 down during a subsequent manufacturing process. Additionally, aspects implemented using the package 100 and the fabrication attachment process described herein may also be used to combine lead frame materials to heat sinks for other types of semiconductor devices. In this regard, the disclosed apparatus and method are implemented in response to the difficulty of not having sufficient available die attach area 114 on the metal substrate 102, as the rivets of current packages may consume almost 50% of the total package size.

[0078] Figure 7 Shown according to Figure 1 A partial top view of the package.

[0079] Figure 8 Shown according to Figure 7 A partial side view of the package.

[0080] Specifically, Figure 7 A partial top view of a package 100 is shown, which includes a portion of a metal substrate 102 and a marking portion 406. In this regard, the marking portion 406 as described above can initially be a portion of a lead frame strip 490 and / or a lead frame 408, and the marking portion 406 can have an outer portion 432 disposed outside the metal substrate 102. In addition, the marking portion 406 can have an inner portion 434 disposed on the metal substrate 102. The connection portion 410 can be disposed in the inner portion 434 of the marking portion 406. The marking portion 406 can include any number of the connection portions 410. In various aspects, the marking portion 406 can include 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 implementations of the connection portion 410.

[0081] A fabrication attachment process may be utilized to form the connection 410. In specific aspects, the connection 410 that connects the tag portion 406 to the metal substrate 102 may be achieved without rivets, the metal substrate 102 may be achieved without mechanical fasteners, the metal substrate 102 may be achieved without rivets, the metal substrate 102 may be achieved without mechanical fasteners, etc. In various aspects, utilizing a fabrication attachment process and / or the connection 410 as described herein may allow the upper surface of the metal substrate 102 to be substantially flat, the upper portion of the metal substrate 102 to be flat, the upper portion of the metal substrate 102 to be continuous, and / or adjacent to one or more metal contacts 404, laterally adjacent to one or more metal contacts 404, etc.

[0082] In various aspects, the connection 410 can be produced using a fabrication attachment process to produce a fusion weld of material between the metal substrate 102 and the marked portion 406 of the lead frame 408. In various aspects, the connection 410 can be generated using a fabrication attachment process that utilizes the material of the metal substrate 102 and the marked portion 406 of the lead frame 408. In addition, the fabrication attachment process can utilize various automated manufacturing tools and systems, such as clamps, robotic systems, etc. In various aspects, the connection 410 is configured as a spot weld portion, a laser beam modified portion, a laser beam weld portion, an ultrasonic weld portion, a resistance weld portion, a fusion metal weld portion, etc.

[0083] In various aspects, the fabrication attachment process described herein can be used consistently with any thickness of the metal substrate 102 and any thickness of the tab portion 406 of the lead frame 408. In this regard, current rivet technology requires substantial changes in operation for changes in the thickness of the metal substrate 102 and / or the thickness of the tab portion 406 of the lead frame 408. On the other hand, the fabrication attachment process of the present disclosure operates with any thickness of the metal substrate 102 and any thickness of the tab portion 406 of the lead frame 408. As a result, implementations of the package 100 can utilize thicker implementations of the metal substrate 102 to provide greater thermal conduction from components of the package 100.

[0084] Fig. 9 Shown according to Figure 1 Another partial top view of the package.

[0085] Specifically, Fig. 9 Another implementation of package 100 is shown. Fig. 9 shown in and combined with Fig. 9 The described aspects may be implemented with any other aspect of the present disclosure. In this regard, Fig. 9It is shown that the marking portion 406 and / or the connecting portion 410 can be arranged anywhere on the metal substrate 102 of the package 100 and / or arranged adjacent to the metal substrate. Figure 3 4 shows a centrally located implementation of the connection portion 410 and / or the marking portion 406. Fig. 9 As shown in FIG. 1 , the connection portion 410 and / or the marking portion 406 may be arranged at various locations on the metal substrate 102 of the package 100. In addition, the connection portion 410 and / or the marking portion 406 may be implemented as follows: Figure 3 symmetrically arranged as shown in Fig. 9 In this regard, implementations of the disclosed package 100 may utilize any number or arrangement of marking portions 406 and / or any number or arrangement of connecting portions 410 in the package 100. In addition, Fig. 9 An arrangement of an overmolding arrangement 430 is shown (shown transparently in phantom lines for clarity of illustration).

[0086] In various aspects, the manufacturing attachment process can utilize welding technology. In this regard, the welding technology can be a manufacturing process that joins the material of the metal substrate 102 with the material of the marking portion 406 by using high heat to melt the metal substrate 102 and the parts of the marking portion 406 together to form the connecting portion 410. Therefore, the connecting portion 410 can form a joint between the metal substrate 102 and the marking portion 406. Specifically, the connecting portion 410 can form a joint with the materials of the metal substrate 102 and the marking portion 406. In addition, pressure can be applied to the metal substrate 102 and the marking portion 406 during the manufacturing attachment process. In addition, during the manufacturing attachment process, a shield can be used to protect the metal of the metal substrate 102 and the marking portion 406 from contamination or oxidation. Alternatively, the connecting portion 410 can be formed by brazing and soldering.

[0087] Fig.10 An exemplary implementation of a fabrication attachment process according to aspects of the present disclosure is shown.

[0088] Specifically, Fig.10An exemplary implementation of a fabrication attachment process that can utilize spot welding or resistance spot welding is shown. In this regard, the fabrication attachment process can utilize a type of resistance welding to form a connection 410 by contacting the metal surface points of the metal substrate 102 and the marking portion 406. Specifically, the metal substrate 102 and the marking portion 406 can be joined by heat obtained from the current resistor 436 to form the connection 410. Specifically, the connection 410 can form a joint using the materials of the metal substrate 102 and the marking portion 406. In various aspects, the fabrication attachment process can utilize an electrode 460, and can be a copper alloy electrode of two shapes to concentrate the welding current into a small "spot" to form the connection 410. In various aspects, the fabrication attachment process can simultaneously clamp the metal substrate 102 and the marking portion 406 together under the pressure applied by the electrode 460. In various aspects, the fabrication attachment process can force the current to pass through the point, and can melt the metal and form a weld between the metal substrate 102 and the marking portion 406 to form the connection 410.

[0089] Fig.11 An exemplary implementation of a fabrication attachment process according to aspects of the present disclosure is shown.

[0090] Specifically, Fig.11 An exemplary embodiment of a fabrication attachment process is shown that can utilize laser beam welding (LBW) to form a connection 410 and join the metal substrate 102 with the marking portion 406 by using a laser 440. The beam of the laser 440 can provide a concentrated heat source, thereby allowing narrow and deep welds and high welding rates. Specifically, the connection 410 can form a joint using the materials of the metal substrate 102 and the marking portion 406. In various aspects, the marking portion 406 can be formed with a small hole to assist in the implementation of laser beam welding (LBW) to form the connection 410 and join the metal substrate 102 with the marking portion 406.

[0091] The penetration depth of the laser 440 may be proportional to the amount of power supplied and the location of the focal point. In various aspects, the location of the focal point may be at the lower surface of the marking portion 406 and the upper surface of the metal substrate 102. Depending on the application, the thickness of the metal substrate 102, the thickness of the marking portion 406, etc., the laser 440 may be implemented as a continuous laser beam, a pulsed laser beam, etc.

[0092] In various aspects, the fabrication attachment process may utilize electron beam welding (EBW). In this regard, the fabrication attachment process may be a fusion welding process, in which a high-speed electron beam is applied to the metal substrate 102 and the tag portion 406 to form the connection 410. The metal substrate 102 and the tag portion 406 may melt and flow together because the kinetic energy of the electrons is converted into heat when colliding with the tag portion 406 and the package 100, thereby forming the connection 410. Specifically, the connection 410 may form a joint using the materials of the metal substrate 102 and the tag portion 406. Various aspects of the fabrication attachment process may be performed under vacuum conditions to prevent dissipation of the electron beam.

[0093] In various aspects, the manufacturing attachment process can utilize ultrasonic welding to form the connection 410. Specifically, the manufacturing attachment process can utilize high-frequency ultrasonic vibrations that can be locally applied to the metal substrate 102 and the tag portion 406 held together under pressure to produce a solid-state weld and form the connection 410. Specifically, the connection 410 can form a joint using the materials of the metal substrate 102 and the tag portion 406.

[0094] In various aspects, the fabrication attachment process may utilize eutectic bonding. In this regard, the fabrication attachment process may utilize eutectic bonding between the metal substrate 102 and the tag portion 406 to form the connection 410 as a eutectic system. The eutectic system may be used between the surfaces of the metal substrate 102 and the tag portion 406 connected by the connection 410. The eutectic bonding may utilize metals that may be alloys and / or intermetallic compounds that transition from a solid to a liquid state or from a liquid state to a solid state at a specific composition and temperature. The eutectic alloy may be deposited on the metal substrate 102 and / or the tag portion 406 by sputtering, evaporation, electroplating, etc.

[0095] In various aspects, the connection 410 can be formed by a combination of manufacturing and attaching processes. For example, the connection 410 can be formed in part by welding or using a solder material. The solder material can be a soft solder material, a eutectic material, etc. In addition, the connection 410 can be formed in part by one or more welding processes described herein. For example, the connection 410 can be formed in part by laser beam welding (LBW), spot welding, etc. In this regard, a combination of solder materials (soft or eutectic) and welding (laser and spot welding) can help reduce the temperature requirements, pressure requirements, etc. for forming the connection 410. In various aspects, a spot plating material such as tin (Sn) can be used to produce a low melting point copper-tin (CuSn) alloy, which can be formed using a combination of manufacturing and attaching processes.

[0096] In various aspects, the fabrication attachment process may utilize an adhesive to form the connection 410. Specifically, the fabrication attachment process may utilize an adhesive process that may include applying an intermediate layer to connect the metal substrate 102 to the surface of the marking portion 406, thereby forming the connection 410. The adhesive may be organic or inorganic; and the adhesive may be deposited on one or more surfaces of the metal substrate 102 and the marking portion 406. The adhesive may be used in an adhesive bonding process that may include applying an adhesive material having a specific coating thickness at a specific bonding temperature within a specific processing time while being located in an environment that may include applying a specific tool pressure. In one aspect, the adhesive may be a conductive adhesive, an epoxy-based adhesive, a conductive epoxy-based adhesive, and the like.

[0097] The fabrication attachment process can form the connection 410 faster than the rivets currently utilized by current packages. Additionally, the connection 410 can form a clamping area for subsequent processing of the package 100, including forming an overmold arrangement 430, attaching one or more semiconductor devices 400, arranging one or more interconnects 104, and the like.

[0098] The package 100 using the fabrication attachment process to form the connection 410 can increase the size of the available space for the die attachment 412 and can allow for a larger configuration of one or more semiconductor devices 400. Therefore, the power density of the package 100 is greatly improved compared to current packages. In addition, the power package area of ​​the package 100 is greatly increased compared to current packages. In this regard, the power density of the package 100 implemented using the fabrication attachment process and / or the connection 410 disclosed herein can be increased by 10%, 20%, 30%, 40%, 50%, or 60%.

[0099] In addition, the size of the one or more metal contacts 404 no longer needs to avoid the location of the rivet as required in the current package. Therefore, compared with the terminals of the current package, the one or more metal contacts 404 can have a larger width. In addition, the one or more metal contacts 404 with a larger width can allow a larger implementation of the one or more semiconductor devices 400. In this regard, the width of the one or more metal contacts 404 can determine the implementation size of the one or more semiconductor devices 400, because as shown in Figure 6, it is beneficial for one or more interconnects 104 to extend directly from the one or more metal contacts 404 to the one or more semiconductor devices 400. In this regard, spreading the one or more interconnects 104 from the one or more metal contacts 404 to the one or more semiconductor devices 400 may have an impact on the performance of the package 100.

[0100] The size of the marking portion 406, the location of the marking portion 406, the number of marking portions 406, etc. may be changed for different applications of the package 100, different implementations of the package 100, different configurations of the lead frame 408, different sizes of the lead frame 408, and / or similar situations that are easy to utilize a manufacturing attachment process. In particular, utilizing a manufacturing attachment process as described herein may not require changing the tooling to produce the cylindrical protrusions used in the current process as described above with respect to the current package. For example, various implementations of the marking portion 406 may only require changing Fig.10 The position of electrode 460 is shown in .

[0101] In various aspects, the available space for die attach 412 of package 100 can be increased by 10%, 20%, 30%, 40%, 50%, or 60% compared to the available die attach area 14 of current package 1. In various aspects, the available space for die attach 412 of package 100 can be 70%, 80%, or 90% of the surface area of ​​metal substrate 102.

[0102] In various aspects, such as Figure 3 As shown in , the terminal width 414 can be increased by 10%, 20%, 30%, 40% or 50% compared to the terminal width 10 of the current package 1. In various aspects, the terminal width 414 of the package 100 can be 70%, 80% or 90% of the width of the metal substrate 102.

[0103] Return to reference Figure 1 , Figure 2 and Figure 3 , one or more semiconductor devices 400 can be implemented as one or more of the following: wide bandgap semiconductor devices, ultra-wide band devices, GaN-based devices, metal semiconductor field effect transistors (MESFETs), metal oxide field effect transistors (MOSFETs), junction field effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), wide bandgap (WBG) semiconductors, power modules, gate drivers, components (such as general broadband components, telecommunication components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components), Doherty configurations, etc.

[0104] In this regard, one or more semiconductor devices 400 may be disposed on the metal substrate 102 via a die attach material 422, wherein one or more interconnects 104 are shown in an exemplary configuration, which may connect between the package 100, one or more metal contacts 404, and / or one or more semiconductor devices 400. The metal substrate 102 may dissipate heat generated by the one or more semiconductor devices 400 while isolating and protecting the one or more semiconductor devices 400 from the external environment. In various aspects, the die attach material 422 may utilize adhesives, soldering, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / welding, clip components, and / or the like as described herein.

[0105] The package 100 may include an overmold configuration 430, one or more metal contacts 404 (such as one or more input / output pins), and a metal substrate 102. The overmold configuration 430 may substantially surround one or more semiconductor devices 400 and / or other components mounted on the metal substrate 102 using a die attach material. The overmold configuration 430 may be formed of a plastic or plastic polymer compound that may be injection molded around the metal substrate 102, the one or more semiconductor devices 400, and / or other components, etc., thereby providing protection from the external environment. In addition, before trimming the lead frame strip 490 and / or the lead frame 408, the molding compound of the overmold configuration 430 may hold the lead frame 408 and the one or more metal contacts 404 in a proper position relative to the metal substrate 102. After forming the overmold configuration 430, the lead frame strip 490 and / or the lead frame 408 may be trimmed so that the package 100 includes only the one or more metal contacts 404 and the marking portion 406. In other words, the molding compound of the overmold arrangement 430 keeps the lead frame strip 490 and / or the lead frame 408 connected to the metal substrate 102, so that the trimming operation can disconnect the one or more metal contacts 404 from the lead frame 408, which also isolates the one or more metal contacts 404 from each other. One or more semiconductor devices 400, other components can be coupled to the one or more metal contacts 404 via one or more interconnects 104.

[0106] In one aspect, the overmold configuration can substantially surround one or more semiconductor devices 400, other components, etc. The overmold configuration can be formed of a plastic, a molding compound, a plastic compound, a polymer, a polymer compound, a plastic polymer compound, etc. The overmold configuration can be injection molded, transfer molded, and / or compression molded around one or more semiconductor devices 400, other components, etc., thereby providing protection for the other components, the one or more semiconductor devices 400, and other components of the package 100 from external environmental influences.

[0107] The one or more interconnects 104 may utilize a ball joint, a wedge joint, a compliant joint, a ribbon joint, a metal clip attachment, etc. In one aspect, the one or more interconnects 104 may utilize the same type of connection. In one aspect, the one or more interconnects 104 may utilize different types of connections.

[0108] The one or more interconnects 104 may include various metal materials, including one or more of aluminum, copper, silver, gold, etc. In one aspect, the one or more interconnects 104 may utilize the same type of metal. In one aspect, the one or more interconnects 104 may utilize different types of metals. The one or more interconnects 104 may be connected to multiple interconnect pads of components of the package 100 by adhesives, welding, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / welding, clip components, etc. as described herein.

[0109] The metal substrate 102 may be implemented as a support, a surface, a package support, a package surface, a package support surface, a flange, a metal flange, a heat sink, a common source support, a common source surface, a common source package support, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a lead frame, a metal lead frame, etc. The metal substrate 102 may include an insulating material, a dielectric material, etc. In various aspects, the metal substrate 102 may be silver plated.

[0110] Fig.12 Shown according to Figure 1 A cross-sectional view of the package.

[0111] Specifically, Fig.12 Another implementation of package 100 is shown. Fig.12 shown in and combined with Fig.12 The described aspects may be implemented with any other aspects of the present disclosure. In this regard, the package 100 may further include other components 200 .

[0112] In this regard, the other components 200 may be disposed on the metal substrate 102 via a die attach material 422, wherein one or more interconnects 104 are shown in an exemplary configuration, which may connect between the package 100, the other components 200, and / or the one or more semiconductor devices 400. The metal substrate 102 may dissipate heat generated by the one or more semiconductor devices 400 and other components 200 while isolating and protecting the one or more semiconductor devices 400 and other components 200 from the external environment. In various aspects, the die attach material 422 may utilize adhesives, soldering, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / welding, clip components, and / or the like as described herein.

[0113] The other components 200 may be implemented as at least a portion of an RF circuit. The other components 200 may implement a matching network, a harmonic termination circuit system, an integrated passive device (IPD), a capacitor, a resistor, an inductor, and the like.

[0114] In various aspects, the other components 200 can be used for matching networks, prematching, bias decoupling, thermal grounding, etc. in RF power products, etc. The other components 200 can be attached inside a package (such as an open cavity package or an overmolded package) along with transistor dies (such as gallium nitride (GaN) transistor dies) and other capacitors, IPDs, etc., and connected to each other and to the package leads with bond wires. Metallization on the top and bottom of the substrate together with vias routed through the substrate can enable the creation of bond pads, inductive straps, inductive coils, capacitor stubs, etc.

[0115] Additionally, inside the package 100, other components 200 may be arranged on the metal substrate 102 as described herein and as shown in the exemplary configurations with one or more interconnects 104. Additionally, inside the package 100, other components 200 may be arranged on the metal substrate 102. The package 100 may include an overmold configuration 430, one or more metal contacts 404 (such as one or more input / output pins), and the metal substrate 102. The overmold configuration 430 may substantially surround one or more semiconductor devices 400 and / or other components 200 mounted on the metal substrate 102 using a die attach material. The overmold configuration 430 may be formed of a plastic or plastic polymer compound that may be injection molded around the metal substrate 102, one or more semiconductor devices 400, and / or other components 200, etc., thereby providing protection from the external environment. One or more semiconductor devices 400, other components 200 may be coupled to the one or more metal contacts 404 via one or more interconnects 104.

[0116] In one aspect, the overmold configuration can substantially surround one or more semiconductor devices 400, other components 200, etc. The overmold configuration can be formed of a plastic, a molding compound, a plastic compound, a polymer, a polymer compound, a plastic polymer compound, etc. The overmold configuration can be injection molded, transfer molded, and / or compression molded around one or more semiconductor devices 400, other components 200, etc., thereby providing protection for the other components 200, one or more semiconductor devices 400, and other components of the package 100 from external environmental influences.

[0117] The package 100 may be implemented as an RF package, and the other components 200 may be implemented as a radio frequency device, which may include, connect, support (or similar role) a transmitter, a transmitter function, a receiver, a receiver function, a transceiver, a transceiver function, a matching network function, a harmonic termination circuit system, an integrated passive device (IPD), etc. The other components 200 implemented as a radio frequency device may be configured to support (or similar role) transmitting radio waves and modulating the waves to carry data with allowed transmitter power output, harmonics and / or band edge requirements. The other components 200 implemented as a radio frequency device may be configured to support (or similar role) receiving radio waves and demodulating radio waves. The other components 200 implemented as a radio frequency device may be configured to support (or similar role) transmitting radio waves and modulating the waves to carry data with allowed transmitter power output, harmonics and / or band edge requirements; and may be configured to support (similar role) receiving radio waves and demodulating radio waves.

[0118] In various aspects, package 100 may include any number of one or more semiconductor devices 400 and any number of other components 200. In one aspect, other components 200 may be configured to be attached to metal substrate 102. In one aspect, other components 200 may be configured to be attached directly to metal substrate 102.

[0119] In one aspect, the other components 200 can be configured with an inter-stage matching implementation. In one aspect, the other components 200 can be configured with an output pre-matching implementation. In one aspect, the other components 200 can be configured with an input pre-matching implementation. However, the other components 200 can be implemented for other functions.

[0120] The package 100 may also include one or more feed network components, which may include one or more input split nodes, which may be connected to one or more input bonding pads via one or more transmission lines. The package 100 may also include one or more output IPD components, which may be connected to one or more output bonding pads via one or more transmission lines. In various aspects, the output IPD component may be implemented with a ceramic substrate.

[0121] The other components 200 may be configured as an output pre-matching implementation. In various aspects, the other components 200 are configured as an inter-stage matching implementation and may be placed between a driver implementation of one or more semiconductor devices 400 and a final stage die implementation of one or more semiconductor devices 400. In various aspects, the other components 200 configured as an input pre-matching implementation may transform the input impedance of the final stage die implementation of one or more semiconductor devices 400 into a target impedance of the driver die implementation of one or more semiconductor devices 400.

[0122] In addition, other components 200 may include circuit structures. Specifically, the circuit structures may be arranged and configured to provide inductance, capacitance, resistance, etc. In one aspect, the circuit structures may be metal surfaces arranged on the upper surface, and together with the metallization layer, a capacitor may be formed. In addition, the circuit structures may be configured as inductive strips, inductive coils, capacitor shorts, etc.

[0123] Fig.13 A process for manufacturing a package according to the present disclosure is shown.

[0124] Specifically, Fig.13 A process 700 of forming a package associated with the package 100 described herein is shown. It should be noted that various aspects of the process 700 of forming a package can be performed in a different order consistent with the aspects described herein. In addition, it should be noted that portions of the process 700 of forming a package can be performed in a different order consistent with the aspects described herein. In addition, the process 700 of forming a package can be modified to have more or fewer processes consistent with the various aspects disclosed herein. In addition, the process of forming the package 700 can include any other aspects of the disclosure described herein.

[0125] The process 700 of forming a package may include a process 702 of forming a metal substrate. In various aspects, the process 702 of forming a metal substrate may include a process of forming a metal substrate 102. More specifically, the metal substrate 102 may be constructed, configured, and / or arranged as described herein. In one aspect, the process 702 of forming a metal substrate may include forming the metal substrate 102 into a support, a surface, a package support, a package surface, a package support surface, a flange, a heat sink, a common source heat sink, etc.

[0126] The process 700 of forming a package may include a process 704 of forming one or more metal contacts. In various aspects, the process 704 of forming one or more metal contacts may include a process of forming one or more metal contacts 404. More specifically, the one or more metal contacts 404 may be constructed, configured and / or arranged as described herein. In various aspects, the process 704 of forming one or more metal contacts may include forming a lead frame 408 having one or more metal contacts 404, a tag portion 406, and a lead frame portion 420. The lead frame portion 420 may initially connect the tag portion 406 to the one or more metal contacts 404. Specifically, during the manufacture of the package 100, the lead frame 408 may be composed of the one or more metal contacts 404, the tag portion 406, and the lead frame portion 420. In this regard, the lead frame 408 may be composed of a strip of metal material that is processed to form the one or more metal contacts 404, the tag portion 406, and the lead frame portion 420. More specifically, the lead frame strip 408 may be stamped, punched, etched (and / or the like) to form the one or more metal contacts 404 , the flag portion 406 , and the lead frame portion 420 from the metal strip.

[0127] The process 700 of forming a package may include a process 706 of attaching one or more metal contacts to a metal substrate. In various aspects, the process 706 of attaching one or more metal contacts to a metal substrate may include a process of attaching one or more metal contacts 404 to a metal substrate 102. More specifically, the one or more metal contacts 404 may be attached, configured, and / or arranged as described herein.

[0128] In various aspects, the process 706 of attaching one or more metal contacts to the metal substrate can utilize spot welding or resistance welding. In this regard, the fabrication attachment process can utilize a type of resistance welding to form the connection 410 by contacting the metal surface points of the metal substrate 102 and the tag portion 406. Specifically, the metal substrate 102 and the tag portion 406 can be joined by heat obtained from the current resistor 436 to form the connection 410. Specifically, the connection 410 can form a joint using the materials of the metal substrate 102 and the tag portion 406.

[0129] In various aspects, the process 706 of attaching one or more metal contacts to the metal substrate can utilize laser beam welding (LBW) to form the connection 410 and join the metal substrate 102 with the marking portion 406 by using a laser 440. The beam of the laser 440 can provide a concentrated heat source, thereby allowing narrow and deep welds and high welding rates. Specifically, the connection 410 can form a joint using the materials of the metal substrate 102 and the marking portion 406.

[0130] In various aspects, the process 706 of attaching one or more metal contacts to the metal substrate can utilize electron beam welding (EBW). In this regard, the fabrication attachment process can be a fusion welding process, in which a high-speed electron beam is applied to the metal substrate 102 and the tag portion 406 to form the connection 410. The metal substrate 102 and the tag portion 406 can melt and flow together because the kinetic energy of the electrons is converted into heat when colliding with the tag portion 406 and the package 100, thereby forming the connection 410.

[0131] In various aspects, the process 706 of attaching one or more metal contacts to the metal substrate utilizes ultrasonic welding to form the connection 410. Specifically, the fabrication attachment process can utilize high frequency ultrasonic vibrations that can be locally applied to the metal substrate 102 and the flag portion 406 held together under pressure to create a solid state weld and form the connection 410.

[0132] In various aspects, the process 706 of attaching one or more metal contacts to the metal substrate can utilize eutectic welding. In this regard, the fabrication attachment process can utilize the eutectic bonding between the metal substrate 102 and the flag portion 406 to form the connection 410 as a eutectic system. In various aspects, the process 706 of attaching one or more metal contacts to the metal substrate can utilize an adhesive to form the connection 410.

[0133] The process 700 of forming a package may include a process 708 of attaching one or more semiconductor devices to a metal substrate. In various aspects, the process 708 of attaching one or more semiconductor devices to a metal substrate may include a process of attaching one or more semiconductor devices 400 to a metal substrate 102. More specifically, the one or more semiconductor devices 400 may be attached, configured, and / or arranged as described herein. In various aspects, the process 708 of attaching one or more semiconductor devices to a metal substrate may include a process of attaching one or more semiconductor devices 400 to a metal substrate 102 while a fixture is placed on the marking portion 406 and / or the connection portion 410. In this regard, the fixture may hold the package 100 at least during the manufacturing process.

[0134] The process 700 of forming a package may include a process 710 of forming one or more interconnects. In various aspects, the process 710 of forming one or more interconnects may include a process of forming one or more interconnects 104. More specifically, the one or more interconnects 104 may be attached, configured, and / or arranged as described herein.

[0135] In one aspect, the process 710 of forming one or more interconnects may include forming one or more interconnects 104 by forming one or more wires, leads, vias, edge plating, circuit traces, tracks, etc. In one aspect, the process 710 of forming one or more interconnects may include connecting one or more interconnects 104 by adhesive, welding, sintering, eutectic bonding, ultrasonic welding, clip components, etc. as described herein. In one aspect, the process 710 of forming one or more interconnects may include connecting one or more interconnects 104 by adhesive, welding, sintering, eutectic bonding, ultrasonic welding, clip components, etc. as described herein while a fixture is placed on the flag portion 406 and / or the connection portion 410. In this regard, the fixture may hold the package 100 at least during the manufacturing process.

[0136] Process 700 of forming a package may include process 712 of enclosing the package. In various aspects, process 712 of enclosing the package may include a process of enclosing package 100 with overmold arrangement 430. More specifically, package 100 and overmold arrangement 430 may be configured and / or arranged as described herein.

[0137] In various aspects, the process 712 of enclosing the package can include configuring the overmold configuration 430 to substantially surround the one or more semiconductor devices 400 and / or other components. In various aspects, the process 712 of enclosing the package can include configuring the overmold configuration 430 to substantially surround the one or more semiconductor devices 400 and / or other components while a fixture is placed on the marking portion 406 and / or the connection portion 410. In this regard, the fixture can hold the package 100 at least during the manufacturing process.

[0138] In various aspects, the process 712 of enclosing the package may include forming an overmold configuration 430 of a plastic or plastic polymer compound that may be injection molded around the metal substrate 102, one or more semiconductor devices 400, and / or other components, etc., thereby providing protection from the external environment. In various aspects, the process 712 of enclosing the package may include forming an overmold configuration 430 of a plastic or plastic polymer compound that may be injection molded around the metal substrate 102, one or more semiconductor devices 400, and / or other components, etc., while a fixture is placed on the marking portion 406, the location 492, and / or the connection portion 410. In this regard, the fixture may hold the package 100 at least during the manufacturing process.

[0139] In various aspects, the process 712 of enclosing the package can include trimming the leadframe strip 490 and / or the leadframe 408. Specifically, the leadframe strip 490 and / or the leadframe 408 can be trimmed to remove portions of the leadframe strip 490 and / or the leadframe 408 such that the flag portion 406 and the one or more metal contacts 404 remain. In other words, the leadframe 408 can be trimmed to remove the leadframe portion 420, etc. In various aspects, the trimming electrically isolates the one or more metal contacts 404 from the metal substrate 102, the source of the one or more semiconductor devices 400, etc.

[0140] Package 100 can be implemented in any number of different applications. In this regard, package 100 can be implemented in applications implementing high video bandwidth power amplifier transistors, single path RF power transistors, single stage RF power transistors, multi-path RF power transistors, Doherty configurations, multi-stage RF power transistors, GaN-based RF power amplifier modules, laterally diffused metal oxide semiconductor (LDMOS) devices, LDMOS RF power amplifier modules, RF power devices, ultra-wideband devices, GaN-based devices, metal semiconductor field effect transistors (MESFETs), metal oxide field effect transistors (MOSFETs), junction field effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), wide band gap (WBG) semiconductors, power modules, gate drivers, components (such as general broadband components, telecommunication components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components), etc. Package 100 can be implemented as a power package. Package 100 may be implemented as a power package and may implement applications and components as described herein.

[0141] Package 100 may be implemented as a radio frequency package. Package 100 may be implemented as a radio frequency package and may implement applications and components as described herein. Package 100 implemented as a radio frequency package may include, connect, support (or similar role) a transmitter, a transmitter function, a receiver, a receiver function, a transceiver, a transceiver function, etc. Package 100 implemented as a radio frequency package may be configured to support (or similar role) transmitting radio waves and modulating the waves to carry data with allowed transmitter power output, harmonics and / or band edge requirements. Package 100 implemented as a radio frequency package may be configured to support (or similar role) receiving radio waves and demodulating radio waves. Package 100 implemented as a radio frequency package may be configured to support (or similar role) transmitting radio waves and modulating the waves to carry data with allowed transmitter power output, harmonics and / or band edge requirements; and may be configured to support (or similar role) receiving radio waves and demodulating radio waves.

[0142] The other components 200 may be active devices, passive devices, IPDs, transistor devices, etc. The other components 200 may include any electronic components for any application. In this regard, the other components 200 may be high video bandwidth power amplifier transistors, single-path RF power transistors, single-stage RF power transistors, multi-path RF power transistors, multi-stage RF power transistors, GaN-based RF power amplifier modules, lateral diffused metal oxide semiconductor (LDMOS) devices, LDMOS RF power amplifier modules, RF power devices, ultra-wideband devices, GaN-based devices, metal semiconductor field effect transistors (MESFETs), metal oxide field effect transistors (MOSFETs), junction field effect transistors (JFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), wide band gap (WBG) semiconductors, power modules, gate drivers, components (such as general broadband components, telecommunication components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components), etc. Other components 200 implemented as radio frequency devices may be configured to support (or act similarly) transmitting radio waves and modulating the waves to carry data with allowed transmitter power output, harmonics, and / or band edge requirements. Other components 200 implemented as radio frequency devices may be configured to support (or act similarly) receiving radio waves and demodulating radio waves. Other components 200 implemented as radio frequency devices may be configured to support (or act similarly) transmitting radio waves and modulating the waves to carry data with allowed transmitter power output, harmonics, and / or band edge requirements; and may be configured to support (or act similarly) receiving radio waves and demodulating radio waves.

[0143] In various aspects, the connection portion 410 is configured as one of the following: a spot welding portion, a laser beam modification portion, a laser beam welding portion, an ultrasonic welding portion, a resistance welding portion, and a molten metal welding portion. In various aspects, the connection portion 410 is arranged on the surface of the metal substrate 102. In various aspects, the connection portion 410 includes the material of the metal substrate 102 and the material of the marking portion 406. In various aspects, the connection portion 410 includes the material of the metal substrate 102 and the material of a portion of the lead frame 408. In various aspects, one or more metal contacts 404 are configured to be positioned adjacent to the metal substrate 102 through the lead frame 408, and the lead frame is attached to the metal substrate 102 through the connection portion 410. In various aspects, the marking portion 406 and the connection portion 410 connect the marking portion 406 to the surface of the metal substrate 102. In various aspects, the flag portion 406 is configured to position one or more metal contacts 404 adjacent to the metal substrate 102 through the lead frame 408, and the flag portion 406 is configured to be subsequently released from the lead frame 408. In various aspects, the metal substrate 102 is free of rivets.

[0144] Thus, the present disclosure has provided a package that enables component connections with more efficient use of space, a package that enables a less costly manufacturing process, a package that enables a less time-consuming manufacturing process, and the like.

[0145] The following are a number of non-limiting examples of various aspects of the present disclosure. One example includes: Example 1: A semiconductor package includes: a metal substrate; at least one transistor die arranged on the metal substrate; and one or more metal contacts configured to be positioned adjacent to the metal substrate through a connection portion, wherein the connection portion is configured as one of the following: a spot welding portion, a laser beam modified portion, a laser beam welding portion, an ultrasonic welding portion, a resistance welding portion, and a fusion metal welding portion.

[0146] The examples mentioned above may also include any one of the following examples or a combination of more than one examples: 2. A semiconductor package according to any example herein, wherein the connection portion is arranged on the surface of the metal substrate. 3. A semiconductor package according to any example herein, wherein the connection portion includes a material of the metal substrate and a material of the marking portion. 4. A semiconductor package according to any example herein, wherein the connection portion includes a material of the metal substrate and a material of a portion of a lead frame. 5. A semiconductor package according to any example herein, wherein one or more metal contacts are configured to be positioned adjacent to the metal substrate through a lead frame, and the lead frame is attached to the metal substrate through the connection portion. 6. A semiconductor package according to any example herein, comprising a marking portion, and the connection portion connects the marking portion to the surface of the metal substrate. 7. A semiconductor package according to any example herein, wherein the marking portion is configured to position one or more metal contacts adjacent to the metal substrate through the lead frame; and wherein the marking portion is configured to be subsequently detached from the lead frame. 8. A semiconductor package according to any example herein, wherein the metal substrate does not have a rivet. 9. A semiconductor package according to any of the examples herein, comprising a cover molding member arranged on a metal substrate, wherein one or more metal contacts extend within and outside the cover molding member. 10. A semiconductor package according to any of the examples herein, wherein the at least one transistor die comprises one or more LDMOS transistor dies. 11. A semiconductor package according to any of the examples herein, wherein the at least one transistor die comprises one or more GaN-based HEMTs. 12. A semiconductor package according to any of the examples herein, wherein at least one of the one or more GaN-based HEMTs comprises a silicon carbide substrate. 13. A semiconductor package according to any of the examples herein, wherein the semiconductor package comprises a plurality of the at least one transistor die. 14. A semiconductor package according to any of the examples herein, wherein the plurality of the at least one transistor die is configured in a Doherty configuration.

[0147] An example includes: Example 15: A semiconductor package includes: a metal substrate; at least one transistor die arranged on the metal substrate; and one or more metal contacts configured to be positioned adjacent to the metal substrate through a connecting portion, wherein the one or more metal contacts are configured to be positioned adjacent to the metal substrate through a lead frame, and the lead frame is welded to the metal substrate through the connecting portion.

[0148] The examples mentioned above may also include any one of the following examples or a combination of more than one examples: 16. A semiconductor package according to any example herein, wherein the connection portion is arranged on the surface of the metal substrate. 17. A semiconductor package according to any example herein, wherein the connection portion includes a material of the metal substrate and a material of the marking portion. 18. A semiconductor package according to any example herein, wherein the connection portion includes a material of the metal substrate and a material of a portion of the lead frame. 19. A semiconductor package according to any example herein, wherein the connection portion is configured as one of: a spot welding portion, a laser beam modified portion, a laser beam welding portion, an ultrasonic welding portion, a resistance welding portion, and a molten metal welding portion. 20. A semiconductor package according to any example herein, comprising a marking portion, and the connection portion connects the marking portion to the surface of the metal substrate. 21. The semiconductor package according to claim 20, wherein the marking portion is configured to position one or more metal contacts adjacent to the metal substrate through the lead frame; and wherein the marking portion is configured to be subsequently detached from the lead frame. 22. A semiconductor package according to any of the examples herein, wherein the metal substrate does not have rivets. 23. A semiconductor package according to any of the examples herein, comprising a cover molding member arranged on the metal substrate, wherein one or more metal contacts extend within and outside the cover molding member. 24. A semiconductor package according to any of the examples herein, wherein the at least one transistor die comprises one or more LDMOS transistor dies. 25. A semiconductor package according to any of the examples herein, wherein the at least one transistor die comprises one or more GaN-based HEMTs. 26. A semiconductor package according to any of the examples herein, wherein at least one of the one or more GaN-based HEMTs comprises a silicon carbide substrate. 27. A semiconductor package according to any of the examples herein, wherein the semiconductor package comprises a plurality of the at least one transistor die. 28. A semiconductor package according to any of the examples herein, wherein the plurality of the at least one transistor die is configured in a Doherty configuration.

[0149] An example includes: Example 29: A process for implementing a process for implementing a semiconductor package, comprising: providing a metal substrate; arranging at least one transistor die on the metal substrate; configuring one or more metal contacts to be positioned adjacent to the metal substrate through a connecting portion; and forming the connecting portion as one of: a spot welding portion, a laser beam modified portion, a laser beam welding portion, an ultrasonic welding portion, a resistance welding portion, and a fusion metal welding portion.

[0150] The above-mentioned examples may also include any one of the following examples or a combination of more than one examples: 30. A process for implementing a semiconductor package according to any example herein, wherein the connection portion is arranged on the surface of the metal substrate. 31. A process for implementing a semiconductor package according to any example herein, wherein the connection portion includes a material of the metal substrate and a material of the marking portion. 32. A process for implementing a semiconductor package according to any example herein, wherein the connection portion includes a material of the metal substrate and a material of a portion of a lead frame. 33. A process for implementing a semiconductor package according to any example herein, wherein one or more metal contacts are configured to be positioned adjacent to the metal substrate through a lead frame, and the lead frame is attached to the metal substrate through the connection portion. 34. A process for implementing a semiconductor package according to any example herein, further comprising providing a marking portion, and configuring the connection portion to connect the marking portion to the surface of the metal substrate. 35. A process for implementing a semiconductor package according to any example herein, wherein the marking portion is configured to position one or more metal contacts adjacent to the metal substrate through the lead frame; and wherein the marking portion is configured to be subsequently detached from the lead frame. 36. A process for implementing a semiconductor package according to any example herein, wherein the metal substrate does not have rivets. 37. A process for implementing a semiconductor package according to any example herein, comprising arranging a cover molding member on the metal substrate, wherein one or more metal contacts extend within and outside the cover molding member. 38. A process for implementing a semiconductor package according to any example herein, wherein the at least one transistor die comprises one or more LDMOS transistor dies. 39. A process for implementing a semiconductor package according to any example herein, wherein the at least one transistor die comprises one or more GaN-based HEMTs. 40. A process for implementing a semiconductor package according to any example herein, wherein at least one of the one or more GaN-based HEMTs comprises a silicon carbide substrate. 41. A process for implementing a semiconductor package according to any example herein, wherein the process for implementing a semiconductor package comprises a plurality of the at least one transistor die. 42. A process for implementing a semiconductor package according to any example herein, wherein the plurality of the at least one transistor die is configured in a Doherty configuration.

[0151] The adhesive of the present disclosure can be used in an adhesive bonding process that can include applying an intermediate layer to connect the surfaces to be connected. The adhesive can be organic or inorganic; and the adhesive can be deposited on one or both surfaces to be connected. The adhesive can be used in an adhesive bonding process that can include applying an adhesive material with a specific coating thickness at a specific bonding temperature for a specific processing time while being located in an environment that can include applying a specific tool pressure. In one aspect, the adhesive can be a conductive adhesive, an epoxy-based adhesive, a conductive epoxy-based adhesive, etc.

[0152] The solder of the present disclosure can be used to form a solder interface, which can include solder and / or be formed by solder. The solder can be any fusible metal alloy that can be used to form a joint between surfaces to be connected. The solder can be lead-free solder, lead solder, eutectic solder, etc. Lead-free solder can contain tin, copper, silver, bismuth, indium, zinc, antimony, a small amount of other metals, etc. Lead solder can contain lead, other metals (such as tin, silver), etc. As needed, the solder can also include flux.

[0153] The sintering of the present disclosure can utilize a process of compacting and forming a conductive material block by heat and / or pressure. The sintering process can be operated without melting the material to the liquefaction point. The sintering process can include sintering metal nano or mixed powders in a paste or epoxy resin. The sintering process can include sintering in a vacuum. The sintering process can include sintering using a protective gas.

[0154] Eutectic bonding of the present disclosure may utilize a eutectic welding process that may form a eutectic system. A eutectic system may be used between surfaces to be joined. Eutectic bonding may utilize metals that may be alloys and / or intermetallic compounds that transition from a solid to a liquid state or from a liquid state to a solid state at a specific composition and temperature. Eutectic alloys may be deposited by sputtering, evaporation, electroplating, and the like.

[0155] Ultrasonic welding of the present disclosure may utilize a process of locally applying high frequency ultrasonic vibrations to parts held together under pressure. Ultrasonic welding may produce a solid state weld between surfaces to be joined. In one aspect, ultrasonic welding may include applying sonic force.

[0156] Although the present disclosure has been described in exemplary aspects, those skilled in the art will recognize that modifications can be made to practice the present disclosure within the spirit and scope of the appended claims. The examples given above are merely illustrative and are not intended to be an exhaustive list of all possible designs, aspects, applications or modifications of the present disclosure.

Claims

1. A semiconductor package, comprising: metal substrate; at least one transistor die disposed on the metal substrate; as well as one or more metal contacts configured to be positioned adjacent to the metal substrate via a connecting portion, The connection portion is configured as one of a spot welding portion, a laser beam modified portion, a laser beam welding portion, an ultrasonic welding portion, a resistance welding portion, and a molten metal welding portion.

2. The semiconductor package according to claim 1, wherein The connection portion is arranged on a surface of the metal substrate.

3. The semiconductor package according to claim 1, wherein: The connection portion includes a material of the metal substrate and a material of a marking portion.

4. The semiconductor package according to claim 1, wherein: The connection portion includes a material of the metal substrate and a material of a portion of a lead frame.

5. The semiconductor package according to claim 1, wherein The one or more metal contacts are configured to be positioned adjacent to the metal substrate by a lead frame attached to the metal substrate by the connection portion. 6 . The semiconductor package according to claim 1 , further comprising a marking portion, and the connecting part connects the marking portion to a surface of the metal substrate.

7. The semiconductor package according to claim 6, in, The marking portion is configured to position the one or more metal contacts adjacent to the metal substrate through the lead frame; and Wherein the marking portion is configured to be subsequently detached from the lead frame.

8. The semiconductor package according to claim 1, wherein The metal substrate has no rivets.

9. The semiconductor package according to claim 1 , further comprising a cover molding member disposed on the metal substrate, in, The one or more metal contacts extend within the overmold and outside the overmold.

10. The semiconductor package according to claim 1, wherein The at least one transistor die includes one or more LDMOS transistor dies.

11. The semiconductor package according to claim 1, wherein The at least one transistor die includes one or more GaN-based HEMTs.

12. The semiconductor package according to claim 11, wherein At least one of the one or more GaN-based HEMTs includes a silicon carbide substrate.

13. The semiconductor package according to claim 1, wherein The semiconductor package includes a plurality of the at least one transistor die.

14. The semiconductor package according to claim 13, wherein: The plurality of the at least one transistor dies are arranged in a Doherty configuration.

15. A semiconductor package, comprising: metal substrate; at least one transistor die disposed on the metal substrate; as well as one or more metal contacts configured to be positioned adjacent to the metal substrate via a connecting portion, The one or more metal contacts are configured to be positioned adjacent to the metal substrate via a lead frame, and the lead frame is welded to the metal substrate via the connection portion.

16. The semiconductor package according to claim 15, wherein: The connection portion is arranged on a surface of the metal substrate.

17. The semiconductor package according to claim 15, wherein: The connection portion includes a material of the metal substrate and a material of a marking portion.

18. The semiconductor package according to claim 15, wherein: The connection portion includes a material of the metal substrate and a material of a portion of a lead frame.

19. The semiconductor package according to claim 15, wherein: The connection portion is configured as one of a spot welding portion, a laser beam modified portion, a laser beam welding portion, an ultrasonic welding portion, a resistance welding portion, and a molten metal welding portion. 20 . The semiconductor package according to claim 15 , further comprising a marking portion, and the connection part connects the marking portion to a surface of the metal substrate.

21. The semiconductor package according to claim 20, in, The marking portion is configured to position the one or more metal contacts adjacent to the metal substrate through the lead frame; and Wherein the marking portion is configured to be subsequently detached from the lead frame.

22. The semiconductor package according to claim 15, wherein The metal substrate has no rivets.

23. The semiconductor package according to claim 15, further comprising a cover molding member disposed on the metal substrate, in, The one or more metal contacts extend within the overmold and outside the overmold.

24. The semiconductor package according to claim 15, wherein The at least one transistor die includes one or more LDMOS transistor dies.

25. The semiconductor package according to claim 15, wherein The at least one transistor die includes one or more GaN-based HEMTs.

26. The semiconductor package according to claim 25, wherein At least one of the one or more GaN-based HEMTs includes a silicon carbide substrate.

27. The semiconductor package according to claim 15, wherein: The semiconductor package includes a plurality of the at least one transistor die.

28. The semiconductor package according to claim 27, wherein The plurality of the at least one transistor dies are arranged in a Doherty configuration.

29. A process for implementing a semiconductor packaging process, comprising: Provide a metal substrate; disposing at least one transistor die on the metal substrate; configuring one or more metal contacts to be positioned adjacent to the metal substrate via a connection portion; as well as The connection portion is formed as one of a spot welding portion, a laser beam modified portion, a laser beam welding portion, an ultrasonic welding portion, a resistance welding portion, and a molten metal welding portion.

30. The process for realizing semiconductor packaging according to claim 29, wherein: The connection portion is arranged on a surface of the metal substrate.

31. The process for realizing semiconductor packaging according to claim 29, wherein: The connection portion includes a material of the metal substrate and a material of a marking portion.

32. The process for realizing semiconductor packaging according to claim 29, wherein: The connection portion includes a material of the metal substrate and a material of a portion of a lead frame.

33. The process for realizing semiconductor packaging according to claim 29, wherein: The one or more metal contacts are configured to be positioned adjacent to the metal substrate by a lead frame attached to the metal substrate by the connection portion.

34. The process for realizing a semiconductor package according to claim 29, further comprising providing a marking portion, and configuring the connecting portion to connect the marking portion to a surface of the metal substrate.

35. The process for realizing semiconductor packaging according to claim 34, in, The marking portion is configured to position the one or more metal contacts adjacent to the metal substrate through the lead frame; and Wherein the marking portion is configured to be subsequently detached from the lead frame.

36. The process for realizing semiconductor packaging according to claim 29, wherein: The metal substrate has no rivets.

37. The process for realizing semiconductor packaging according to claim 29, further comprising disposing a cover molding member on the metal substrate, in, The one or more metal contacts extend within the overmold and outside the overmold.

38. The process for realizing semiconductor packaging according to claim 29, wherein: The at least one transistor die includes one or more LDMOS transistor dies.

39. The process for realizing semiconductor packaging according to claim 29, wherein: The at least one transistor die includes one or more GaN-based HEMTs.

40. The process for realizing semiconductor packaging according to claim 39, wherein: At least one of the one or more GaN-based HEMTs includes a silicon carbide substrate.

41. The process for realizing semiconductor packaging according to claim 29, wherein: The process of implementing a semiconductor package includes a plurality of the at least one transistor die.

42. The process for realizing semiconductor packaging according to claim 41, wherein: The plurality of the at least one transistor dies are arranged in a Doherty configuration.

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