Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The method comprises the following steps: forming a plurality of capacitor holes penetrating through stacked layers in a first region and a second region; forming a first electrode layer on the inner wall of the capacitor hole; forming a dielectric layer on one side of the stack layer; removing at least part of the dielectric layer in the second region; second electrode layers are formed, the second electrode layers in the first area and the second area are arranged at intervals, and the first electrode layer and the second electrode layer in the second area are connected.

Description

Semiconductor structure and manufacturing method thereof, memory and memory system

Technical field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, a memory, and a memory system. [Background Technology]

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device. DRAM consists of a number of repeated memory cells. Each memory cell includes a capacitor structure configured to store charge. The capacitor structure affects the storage capacity of the DRAM.

[0003] The capacitor structure in existing DRAM is usually located in the core area. However, when forming the capacitor holes in the core area, a serious etching loading effect is easily caused, thereby affecting the reliability of the final capacitor structure.

[0004] [Summary of the invention]

[0005] The present application aims to provide a semiconductor structure and a manufacturing method thereof, a memory and a memory system, which can effectively improve the etching load effect of the core area when manufacturing capacitor holes and improve the reliability of the capacitor structure.

[0006] In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0007] forming a plurality of capacitor holes penetrating the stacked layer along a stacking direction, the stacked layer including a first region and a second region, the capacitor holes being located in the first region and the second region;

[0008] forming a first electrode layer on the inner wall of the capacitor hole;

[0009] forming a dielectric layer on one side of the stacked layer in the first region and the second region;

[0010] removing at least a portion of the dielectric layer in the second region;

[0011] A second electrode layer is formed in the first region and the second region. The second electrode layer in the first region and the second electrode layer in the second region are spaced apart from each other, and the first electrode layer and the second electrode layer in the second region are connected.

[0012] On the other hand, an embodiment of the present application further provides a semiconductor structure, including:

[0013] A stacked structure comprising a first region and a second region;

[0014] First electrode layers located in the first region and the second region, the first electrode layers penetrating the stack structure along a stacking direction and being arranged at intervals;

[0015] a dielectric layer located at least in the first region;

[0016] The second electrode layer is located in the first region and the second region, the second electrode layer in the first region and the second electrode layer in the second region are spaced apart, and the first electrode layer and the second electrode layer in the second region are connected, and the dielectric layer is provided between the first electrode layer and the second electrode layer in the first region.

[0017] On the other hand, an embodiment of the present application further provides a memory, comprising the semiconductor structure described in any one of the above items and a peripheral circuit structure, wherein the peripheral circuit structure and the semiconductor structure are electrically connected.

[0018] On the other hand, an embodiment of the present application further provides a memory system, comprising at least one of the above-mentioned memories, and a controller coupled to the memory, wherein the controller is used to control the memory to store data.

[0019] The semiconductor structure and its manufacturing method, memory and memory system provided by the embodiments of the present application form multiple capacitor holes that penetrate the stacked layer along the stacking direction. The stacked layer includes a first area and a second area. The capacitor holes are located in the first area and the second area, thereby greatly avoiding a serious etching load effect in the first area when forming the capacitor holes, and ensuring the size consistency of the capacitor holes in the first area as much as possible, and preventing insufficient etching. Subsequently, a first electrode layer is formed on the inner wall of the capacitor hole; a dielectric layer is formed on one side of the stacked layer in the first area and the second area; at least part of the dielectric layer in the second area is removed; a second electrode layer is formed in the first area and the second area, the second electrode layer in the first area and the second electrode layer in the second area are spaced apart, and the first electrode layer and the second electrode layer in the second area are connected, thereby forming a capacitor structure with uniform size in the first area, thereby improving the reliability of the capacitor structure.

Brief Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0021] FIG1 is a schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0022] 2A to 2J are schematic cross-sectional views of a semiconductor structure according to an embodiment of the present application at different process steps;

[0023] FIG3A is a schematic cross-sectional view of the structure along line C1-C1 in FIG2D ;

[0024] FIG3B is a schematic cross-sectional view of the structure along line C2-C2 in FIG2E;

[0025] FIG3C is a schematic cross-sectional view of the structure along line C3-C3 in FIG2F ;

[0026] FIG3D is a schematic cross-sectional view of the structure along line C4-C4 in FIG2G ;

[0027] FIG3E is a schematic cross-sectional view of the structure along line C5-C5 in FIG2H;

[0028] FIG3F is a schematic cross-sectional view of the structure along line C6-C6 in FIG2I ;

[0029] FIG3G is a schematic cross-sectional view of the structure along line C7-C7 in FIG2J ;

[0030] 4A to 4H are schematic cross-sectional views of another embodiment of the semiconductor structure according to different process steps;

[0031] FIG5A is a schematic cross-sectional view of the structure along line D1-D1 in FIG4A;

[0032] FIG5B is a schematic cross-sectional view of the structure along line D2-D2 in FIG4B;

[0033] FIG5C is a schematic cross-sectional view of the structure along line D3-D3 in FIG4C;

[0034] FIG5D is a schematic cross-sectional view of the structure along line D4-D4 in FIG4D;

[0035] FIG5E is a schematic cross-sectional view of the structure along line D5-D5 in FIG4E;

[0036] FIG5F is a schematic cross-sectional view of the structure along line D6-D6 in FIG4F;

[0037] FIG5G is a schematic cross-sectional view of the structure along line D7-D7 in FIG4G ;

[0038] FIG5H is a schematic cross-sectional view of the structure along line D8-D8 in FIG4H;

[0039] FIG6A is a schematic cross-sectional view of another semiconductor structure provided in an embodiment of the present application;

[0040] FIG6B is a schematic cross-sectional view of the structure along line dd in FIG6A ;

[0041] FIG7 is a schematic diagram of the structure of a system provided in an embodiment of the present application;

[0042] FIG8 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0043] FIG9 is a schematic cross-sectional structural diagram of a memory provided in an embodiment of the present application. [Specific implementation method]

[0044] The present application will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only intended to illustrate the present application and are not intended to limit the scope of the present application. Similarly, the following examples are only some examples of the present application and are not intended to be exhaustive. All other examples obtained by persons of ordinary skill in the art without creative effort are intended to fall within the scope of protection of the present application.

[0045] In the description herein, it should be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting this application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0046] In this description, it should be noted that, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0047] It will be understood that the meanings of “on,” “over,” and “over” in the description herein should be interpreted in the broadest manner, such that “on” not only means “on” something with no intervening features or layers (i.e., directly on something), but also includes “on” something with intervening features or layers.

[0048] The terms used herein are intended only to describe specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a", "an", "an item" used herein are also intended to include the plural form. The meaning of "plurality" is two or more. It should also be understood that the terms "include" and / or "comprising" used herein specify the presence of stated features, integers, steps, operations, units and / or components, and do not exclude the presence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0049] Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, a memory, and a memory system.

[0050] Please refer to FIG1 , which is a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present application. The method for manufacturing a semiconductor structure may include the following steps S101-S105, wherein:

[0051] Step S101. Forming a plurality of capacitor holes penetrating a stacked layer along a stacking direction, wherein the stacked layer includes a first region and a second region, and the capacitor holes are located in the first region and the second region;

[0052] Step S102. forming a first electrode layer on the inner wall of the capacitor hole;

[0053] Step S103. forming a dielectric layer on one side of the stacked layer in the first region and the second region;

[0054] Step S104: removing at least a portion of the dielectric layer in the second region;

[0055] Step S105 . Form a second electrode layer in the first region and the second region, wherein the second electrode layer in the first region and the second electrode layer in the second region are spaced apart, and the first electrode layer and the second electrode layer in the second region are connected.

[0056] It should be understood that the steps shown in the above production method are not exclusive, and other steps may be performed before, after or between any of the steps shown.

[0057] Please refer to Figures 2A to 2J and Figures 4A to 4H. Figures 2A to 2J are schematic cross-sectional views of the semiconductor structure 10 at different process steps according to an embodiment of the present application. Figures 4A to 4H are another schematic cross-sectional view of the semiconductor structure 10 at different process steps according to an embodiment of the present application. The semiconductor structure 10 may include a cup-type capacitor structure or a pillar-type capacitor structure. The above steps S101-S105 will be further described below in conjunction with Figures 2A to 2J and Figures 4A to 4H, wherein:

[0058] Step S101 . Form a plurality of capacitor holes Q1 penetrating the stacked layer 11 along a stacking direction z. The stacked layer 11 includes a first area AA and a second area BB. The capacitor holes Q1 are located in the first area AA and the second area BB.

[0059] Among them, if the semiconductor structure 10 is a cup-type capacitor structure or a pillar-type capacitor structure, please refer to Figures 2A to 2D and Figure 3A above. Figure 3A is a schematic diagram of the cross-sectional structure along the C1-C1 line in Figure 2D. The first area AA is the area corresponding to the storage array, and the second area BB is other areas. The first area AA and the second area BB can be adjacent to each other, for example, the second area BB is arranged around the first area AA. The capacitor holes Q1 can be distributed in the entire area of ​​the stacked layer 11 and are arranged at intervals inside. Preferably, these capacitor holes Q1 can be set to the same size and the same spacing.

[0060] Specifically, the stacked layer 11 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The stacked layer 11 can be formed by alternating layers of different insulating materials, such as alternating layers of silicon dioxide and silicon nitride.

[0061] Capacitor holes Q1 can be formed in both the first area AA and the second area BB of the stacked layer 11 through two orthogonal or angled patterning processes. In this case, since the pattern of the capacitor holes Q1 is relatively uniformly distributed across the entire surface of the stacked layer 11, that is, the density difference between the etching patterns corresponding to the first area AA and the second area BB is relatively small, the difference in etching depth and size of the capacitor holes Q1 formed in the first area AA and the second area BB is relatively small, thereby minimizing the occurrence of a severe etching loading effect. Furthermore, even if a certain etching loading effect exists, affecting the etching depth and hole size of the capacitor holes Q1 at the edge, since the second area BB is generally disposed around the first area AA, the etching loading effect generally only affects the outermost capacitor holes Q1 in the second area BB and is unlikely to affect the capacitor holes Q1 in the first area AA. Therefore, by forming the capacitor holes Q1 in both the first area AA and the second area BB, the serious etching load effect in the first area AA can be greatly avoided, and the etching depth and size of the capacitor holes Q1 in the first area AA can be kept consistent as much as possible, avoiding the phenomenon that some capacitor holes Q1 have insufficient etching depth or are too small in size.

[0062] In other embodiments, please refer to Figures 6A and 6B. Figure 6A shows a schematic cross-sectional structure diagram of another semiconductor structure 20 provided in an embodiment of the present application, and Figure 6B is a schematic cross-sectional structure diagram along line dd in Figure 6A. Among them, the semiconductor structure 20 includes a first stacked structure 21, and a second stacked layer 22 located on the first stacked structure 21. The first stacked structure 21 includes a channel structure 211. The second stacked layer 22 includes a core area aa and a non-core area bb. A capacitor hole q is formed in the core area aa. Specifically, the capacitor hole q can be directly formed in the core area aa, and then the first electrode layer, the dielectric layer and the second electrode layer are made to obtain a capacitor structure located in the core area aa.

[0063] However, since capacitor hole q does not need to be made in non-core area bb when making capacitor hole q, that is, the density difference of the etching patterns of core area aa and non-core area bb is large, the capacitor hole q at the junction of core area aa and non-core area bb will have a serious etching load effect, so that the capacitor hole q at the edge of core area aa and the capacitor hole q in the middle of core area aa have obvious differences in etching depth 2 and hole size. For example, the etching depth of capacitor hole q at the edge of core area aa is shallow and cannot penetrate the stacking layer 22 along the stacking direction z, thereby causing the capacitor structure finally formed at the edge of core area aa to be unable to be electrically connected to the channel structure 211, or the size of capacitor hole q is too small, which affects the formation of subsequent capacitor structure and affects the reliability of the capacitor structure. The semiconductor structure 10 provided in the embodiment of the present application at least partially solves the above technical problems.

[0064] It should be noted that, in the semiconductor structure 10 provided in the embodiment of the present application, the capacitor structure may be formed after the channel structure is formed. That is, referring to FIG. 2A to FIG. 2D , before the above step S101 , the manufacturing method may further include:

[0065] A plurality of active portions 122 extending along a first direction x and spaced apart along a second direction y are formed on a substrate 121 ;

[0066] performing a doping process of a first concentration on the active portion 122 corresponding to the second region BB;

[0067] forming a gate structure 123 extending along the second direction y and connecting at least the active portion 122 in the first area AA, wherein the gate structure 123 penetrates the active portion along the stacking direction z to obtain a plurality of channel structures 122 a, wherein the first direction x, the second direction y, and the stacking direction z are perpendicular to each other;

[0068] The stacked layer 11 is formed on a side of the substrate 121 close to the channel structure 122 a .

[0069] Wherein, if the semiconductor structure 10 is a cup-type capacitor structure or a pillar-type capacitor structure, please continue to refer to Figures 2A to 2C, the substrate 121 may include single crystal silicon (Si), single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials or at least one of other semiconductor materials known in the art. The first direction x and the second direction y may be the extension direction of the stacked layer 11, which is perpendicular to the stacking direction z of the stacked layer 11. The gate structure 123 may include a gate spacer 1231 and a gate layer 1232. The material of the gate spacer 1231 may include an insulating material such as oxide, and the material of the gate layer 1232 may be any one or combination of tungsten, cobalt, copper, aluminum or polysilicon, doped crystalline silicon.

[0070] Specifically, the active portion 122 can be formed by etching the substrate 121, and insulating material can be further filled between adjacent gate structures 123 along the first direction x to isolate and electrically insulate adjacent gate structures 123. After filling with the insulating material, the substrate 121 outside the active portion 122 (i.e., the bottom substrate 121) can be removed, and bit lines 124 can be formed, which are connected to the channel structure 122a.

[0071] It should be noted that the gate structure 123 may be formed at positions corresponding to both the first area AA and the second area BB (see, for example, Figures 2C and 2D above), or may be formed only at positions corresponding to the first area AA, without limitation. The active portion 122 corresponding to the second area BB is doped primarily to improve the conductivity of the active portion 122 corresponding to the second area BB.

[0072] In some embodiments, before forming the gate structure 123, the fabrication method may further include: performing a doping treatment on the active portion 122 of the first region AA at a second concentration, wherein the first concentration is greater than the second concentration. In other embodiments, doping may be performed after forming the gate structure 123, that is, doping the channel structure 122a at the second concentration.

[0073] Among them, the active portion 122 (or channel structure 122a) of the first area AA is doped mainly to improve the conductivity of the active portion 122 (or channel structure 122a) of the first area AA, thereby forming a corresponding source region, which is electrically connected to the subsequently manufactured capacitor structure.

[0074] Step S102 : Forming a first electrode layer 13 on the inner wall of the capacitor hole Q1 .

[0075] Among them, if the semiconductor structure 10 is a cup-type capacitor structure or a pillar-type capacitor structure, please continue to refer to Figures 2D, 2E and 3B. Figure 3B is a schematic cross-sectional structure diagram along line C2-C2 in Figure 2E. The material of the first electrode layer 13 includes a conductive material such as metal, such as tungsten, copper, etc. A layer of conductive material can be first formed on one side of the stacked layer 11, and then the conductive material outside the capacitor hole Q1 is removed to obtain the first electrode layer 13 located in the capacitor hole Q1.

[0076] It should be pointed out that since the capacitor hole Q1 is arranged at intervals in the first area AA and the second area BB, the first electrode layer 13 in the first area AA and the first electrode layer 13 in the second area BB are also arranged at intervals, that is, the first electrode layer 13 in the first area AA and the first electrode layer 13 in the second area BB both include multiple isolated parts, and these parts are not connected to each other.

[0077] Step S103 . Form a dielectric layer 14 on one side of the stacked layer 11 in the first area AA and the second area BB.

[0078] The dielectric layer 14 is made of a material with a high dielectric constant. Different types of capacitor structures have different steps for forming the dielectric layer 14, which is mainly reflected in the different specific positions of the dielectric layer 14 in the first area AA and the second area BB.

[0079] In some embodiments, for example, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2E, 2F, and 3C. Figure 3C is a schematic cross-sectional structural diagram along line C3-C3 in Figure 2F. Specifically, after forming the first electrode layer 13, a dielectric layer 14 can be formed. The dielectric layer 14 not only covers the side of the first electrode layer 13 facing away from the stacked layer 11, but also covers the top of the stacked layer 11.

[0080] In some embodiments, for example, if the semiconductor structure 10 is a pillar-type capacitor structure, please refer to Figures 4A to 4H, which are another cross-sectional structural schematic diagram of the semiconductor structure 10 provided in the embodiment of the present application under different process steps. Among them, please continue to refer to Figure 2E, Figures 4A to 4C and Figures 5A to 5C, Figure 5A is a cross-sectional structural schematic diagram along the D1-D1 line in Figure 4A, Figure 5B is a cross-sectional structural schematic diagram along the D2-D2 line in Figure 4B, and Figure 5C is a cross-sectional structural schematic diagram along the D3-D3 line in Figure 4C. Specifically, for the pillar-type capacitor structure, after forming the first electrode layer 13, it is necessary to first remove a portion of the stacked layer 11 and then form the dielectric layer 14. That is, the stacked layer 11 may include a sacrificial layer 112. Before the above-mentioned step S103, the manufacturing method further includes:

[0081] A support layer 15 is formed on one side of the stacked layer 11 in the first area AA and the second area BB, and the support layer 15 fills the capacitor hole Q1;

[0082] A plurality of spacing holes Q2 are formed along the stacking direction z through the support layer 15 and extending into the stacking layer 11, and the sacrificial layer 112 is removed to form a hollow groove Q3, wherein the spacing holes Q2 are located in the first area AA and the second area BB;

[0083] The support layer 15 outside the capacitor hole Q1 is removed.

[0084] The stacked layer 11 may include alternating spacer layers 111 and sacrificial layers 112. The sacrificial layers 112 may be made of silicon dioxide, and the spacer layers 111 may be made of silicon nitride. The material of the support layer 15 is generally different from that of the stacked layer 11, such as carbon. In addition to filling the capacitor hole Q1, the support layer 15 may further cover the top of the stacked layer 11.

[0085] Specifically, the spacing hole Q2 can be formed by multiple etchings. For example, a hole pattern corresponding to the spacing hole Q2 is first formed on the support layer 15 and the adjacent spacer layer 111 through a mask. Then, the sacrificial layer 112 is removed by wet etching or dry etching through the hole pattern, exposing a portion of the adjacent spacer layer 111 below. Then, the exposed spacer layer 111 is further etched downward to further expose the adjacent sacrificial layer 112 below. Then, the sacrificial layer 112 is removed through the exposed position of the sacrificial layer 112. Through this multiple etching method, all sacrificial layers 112 in the stacked layer 11 are removed, leaving only the spacer layer 111 at the bottom, thereby obtaining a spacing hole Q2 that penetrates the support layer 15 along the stacking direction z and extends into the stacked layer 11.

[0086] At the same time, during the formation of the spacing hole Q2, the sacrificial layer 112 is also removed to form the empty groove Q3. After the spacing hole Q2 and the empty groove Q3 are formed, the dielectric layer 14 is formed. At this time, the dielectric layer 14 is not only located on the stacked layer 11 in the first area AA and the second area BB (that is, covering the top of the stacked layer 11), but also covers the inner wall of the empty groove Q3 and the inner wall of the spacing hole Q2. During the removal of the sacrificial layer 112 in the stacked layer 11, since the capacitor hole Q1 is filled with the support layer 15, the stacked layer 11 will not collapse under the support of the support layer 15.

[0087] It should be noted that the figure only illustrates one cross-sectional shape (circular in the figure) and arrangement of the spacing holes Q2. In other embodiments, the spacing holes Q2 may have other cross-sectional shapes (e.g., trapezoidal) and arrangements, without limitation. Furthermore, in addition to the aforementioned multiple etching method, the spacing holes Q2 may also be formed using other methods, such as a single etching method, without limitation.

[0088] Step S104 : removing at least a portion of the dielectric layer 14 in the second region BB.

[0089] Among them, for different capacitor structures, the removal steps of the dielectric layer 14 are different. For example, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2F, 2G and 3D. Figure 3D is a schematic diagram of the cross-sectional structure of the C4-C4 line in Figure 2G. The above-mentioned step S104 can specifically include: removing the dielectric layer 14 in the second area BB and exposing the first electrode layer 13 in the second area BB.

[0090] Specifically, for the cup-type capacitor structure, all the dielectric layers 14 in the second area BB can be removed by etching, that is, the dielectric layer 14 on the top of the stacked layer 11 in the second area BB and the dielectric layer 14 in the capacitor hole Q1 in the second area BB are removed, and at the same time, the first electrode layer 13 in the capacitor hole Q1 in the second area BB is exposed.

[0091] In other embodiments, for example, if the semiconductor structure 10 is a pillar-type capacitor structure, please continue to refer to Figures 4C, 4D and 5D, Figure 5D is a schematic diagram of the cross-sectional structure along the D4-D4 line in Figure 4D, wherein the above-mentioned step S104 may specifically include: removing the dielectric layer 14 on the stacked layer 11 in the second area BB, and exposing part of the first electrode layer 13 in the second area BB.

[0092] Specifically, for the pillar-type capacitor structure, part of the dielectric layer 14 in the second area BB can be removed by etching, that is, the dielectric layer 14 on the top of the stacked layer 11 in the second area BB is removed, and at the same time, the first electrode layer at the corresponding position (top) in the capacitor hole Q1 is exposed, while the dielectric layer 14 on the inner wall of the empty groove Q3 and the dielectric layer 14 on the inner wall of the spacing hole Q2 are retained.

[0093] Step S105. Form a second electrode layer 16 in the first area AA and the second area BB, wherein the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are spaced apart, and the first electrode layer 13 and the second electrode layer 16 in the second area BB are connected.

[0094] Among them, the first electrode layer 13, the dielectric layer 14 and the second electrode layer 16 together serve as a capacitor structure, which can store charge. The material of the second electrode layer 16 is mainly a conductive material, and any one or combination of tungsten, cobalt, copper, aluminum or polysilicon, doped crystalline silicon can be selected. The second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are arranged at intervals, which mainly means that the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are separated from each other, and there is no direct contact area between the two. Subsequent power-on realizes electrical insulation between the two. The first electrode layer 13 and the second electrode layer 16 in the second area BB are connected, which mainly means that there is at least a partial area of ​​direct contact between the first electrode layer 13 in the second area BB and the second electrode layer 16 in the second area BB, and subsequent power-on realizes electrical connection between the two.

[0095] Specifically, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2G to 2I, as well as Figures 3E and 3F, wherein Figure 3E is a schematic cross-sectional structural diagram along line C5-C5 in Figure 2H, and Figure 3F is a schematic cross-sectional structural diagram along line C6-C6 in Figure 2I. The above step S105 may include:

[0096] forming a second electrode layer 16 on one side of the stacked layer 11, the second electrode layer 16 being located in the first area AA and the second area BB, and covering the side of the dielectric layer 14 facing away from the stacked layer 11 and the exposed first electrode layer 13, and filling the capacitor hole Q1;

[0097] A first groove 171 is formed along the stacking direction z and passes through the second electrode layer 16 on the stacking layer 11. The first groove 171 extends along the first direction x and separates the second electrode layer 16 in the first area AA and the second area BB along the second direction y. The first direction x, the second direction y and the stacking direction z are perpendicular to each other.

[0098] In the cup-type capacitor structure, since the dielectric layer 14 in the second region BB is completely removed, the first electrode layer 13 in the second region BB is completely exposed. As a result, the second electrode layer 16 formed in the second region BB can directly contact the entire first electrode layer 13 in the second region BB, achieving a connection between the two. After subsequent power is applied, the connected first electrode layer 13 and the second electrode layer 16 are short-circuited to achieve electrical connection. At the same time, since the dielectric layer 14 in the first region AA is not removed, the first electrode layer 13 and the second electrode layer 16 in the first region AA can be separated by the dielectric layer 14.

[0099] The function of the first groove 171 is to cut the entire second electrode layer 16 into two parts, namely, the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB, so as to separate the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB, thereby achieving electrical insulation between the two. The first groove 171 can be located at a corresponding position at the boundary edge between the second area BB and the first area AA.

[0100] In some embodiments, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to FIG. 2H , FIG. 2I , and FIG. 3F , the manufacturing method may further include:

[0101] At least one second groove 172 is formed along the stacking direction z and penetrates the second electrode layer 16 on the stacked layer 11 in the second region BB. The second groove 172 divides the second electrode layer 16 in the second region BB into multiple parts.

[0102] The second groove 172 can be formed by etching. The second groove 172 is used to separate the second electrode layer 16 in the second region BB into multiple portions, that is, to separate the second electrode layer 16 into multiple, independently controllable local portions. The first groove 171 and the second groove 172 can be formed in the same etching process or in different etching processes, and the order of formation is not limited.

[0103] Any localized second electrode layer 16 formed by cutting in the second region BB is typically connected to the correspondingly cut first electrode layer 13. The connected first and second electrode layers 13 and 16 can serve as a contact structure M, thereby obtaining multiple contact structures M that extend through the stacked layer 11 along the stacking direction z. The specific number and location of the second grooves 172 can be determined based on the number and location of the contact structures M to be fabricated, and are not limited here.

[0104] In some embodiments, if the semiconductor structure 10 is a pillar-type capacitor structure, please continue to refer to Figures 4D to 4G, and Figures 5F to 5G, wherein Figure 5E is a schematic cross-sectional structural diagram along line D5-D5 in Figure 4E, Figure 5F is a schematic cross-sectional structural diagram along line D6-D6 in Figure 4F, and Figure 5G is a schematic cross-sectional structural diagram along line D7-D7 in Figure 4G. The above-mentioned step S105 may include:

[0105] A second electrode layer 16 is formed on one side of the stacked layer 11, and the second electrode layer 16 covers the side of the dielectric layer 14 in the empty groove Q3 and the spacing hole Q2 facing away from the stacked layer 11, and the exposed first electrode layer 13;

[0106] A third groove 173 is formed along the stacking direction z, penetrating the second electrode layer 16 on the stacking layer 11. The third groove 173 extends along the first direction x and separates the second electrode layer 16 in the first area AA and the second area BB along the second direction y. The first direction x, the second direction y and the stacking direction z are perpendicular to each other.

[0107] Among them, for the pillar-type capacitor structure, since only a portion of the dielectric layer 14 in the second area BB is removed, only a portion of the first electrode layer 13 in the second area BB is exposed (the first electrode layer 13 at the top of the capacitor hole Q1 is exposed), so that the second electrode layer 16 formed in the second area BB is only in direct contact with the portion of the first electrode layer 13 exposed in the second area BB, thereby achieving connection between the two. After subsequent power-on, the connected first electrode layer 13 and the second electrode layer 16 are short-circuited to achieve electrical connection.

[0108] At the same time, the second electrode layer 16 will also be filled in the empty groove Q3 and the spacing hole Q2, that is, the second electrode layer 16 will exist at the top of the stacked layer 11, in the empty groove Q3 and in the spacing hole Q2 at the same time. Compared with the cup-type capacitor structure in which the empty groove Q3 is not formed, the pillar-type capacitor structure greatly increases the effective area of ​​the second electrode layer 16, thereby improving the charge storage capacity of the capacitor structure.

[0109] Similar to the function of the first groove 171 in the above-mentioned cup-type capacitor structure, the function of the third groove 173 is to cut the entire second electrode layer 16 into two parts, so that the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are separated from each other to achieve electrical insulation between the two.

[0110] In some embodiments, for a pillar-type capacitor structure, please continue to refer to FIG. 4E and FIG. 4F , and FIG. 5E and FIG. 5F , the manufacturing method may further include:

[0111] A semiconductor layer 18 is formed on a side of the second electrode layer 16 facing away from the stacked layer 11 , and the semiconductor layer 18 fills the empty groove Q3 and the isolation hole Q2 .

[0112] The semiconductor layer 18 covers the second electrode layer 16 on top of the stacked layer 11 in the first region AA and the second region BB, and fills the empty trench Q3 and the spacing hole Q2. The material of the semiconductor layer 18 may include polysilicon and / or silicide, such as silicon germanium (SiGe). The aforementioned third trench can be formed after the semiconductor layer 18 is formed. Since the semiconductor layer 18 and the second electrode layer 16 are in direct contact (i.e., connected), in order to separate the second electrode layer 16 in the second region BB from the second electrode layer 16 in the first region AA, the third trench must at least penetrate the semiconductor layer 18 and the second electrode layer 16 along the stacking direction z. Furthermore, if the first electrode layer 13 is also located at the corresponding position of the third trench, the third trench must also continue to penetrate the first electrode layer 13.

[0113] In some embodiments, for a pillar-type capacitor structure, please continue to refer to FIG. 4F , FIG. 4G , and FIG. 5G , the manufacturing method may further include:

[0114] A fourth groove 174 is formed along the stacking direction z through the semiconductor layer 18 and the second electrode layer 16 . The fourth groove 174 divides the second electrode layer 16 in the second region BB into multiple parts.

[0115] Similar to the function of the second groove 172 in the aforementioned cup-type capacitor structure, the fourth groove 174 serves to divide the second electrode layer 16 in the second region BB into multiple portions. Furthermore, if the first electrode layer 13 is located at the corresponding position of the fourth groove 174, the fourth groove 174 must continue to penetrate the first electrode layer 13.

[0116] For any local second electrode layer 16 formed by cutting in the second area BB, it is connected to the corresponding isolated first electrode layer 13 and semiconductor layer 18. The connected first electrode layer 13, second electrode layer 16 and semiconductor layer 18 can be used as a contact structure N as a whole, thereby obtaining multiple contact structures N, which penetrate the stacking layer 11 along the stacking direction z.

[0117] In some embodiments, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2I and 2J, and Figure 3G, which is a schematic cross-sectional structural diagram along the C7-C7 line in Figure 2J. After forming the first groove 171 and the second groove 172, a first insulating layer 191 can be formed on the side of the second electrode layer 16 away from the stacked layer 11, and the first insulating layer 191 fills the first groove 171 and the second groove 172. Thereafter, a lead 192 is formed on the side of the first insulating layer 191 away from the second electrode layer 16, and the lead 192 passes through the first insulating layer 191 along the stacking direction z and extends to the second electrode layer 16, thereby electrically connecting the lead 192 and the second electrode layer 16.

[0118] If the semiconductor structure 10 is a pillar-type capacitor structure, please continue to refer to Figures 4G, 4H and 5H. Figure 5H is a schematic cross-sectional structural diagram along the D8-D8 line in Figure 4H. After forming the third groove 173 and the fourth groove 174, a first insulating layer 191 can be formed on the side of the semiconductor layer 18 away from the stacked layer 11, and the first insulating layer 191 fills the third groove 173 and the fourth groove 174. Thereafter, a lead 192 is formed on the side of the first insulating layer 191 away from the semiconductor layer 18, and the lead 192 passes through the first insulating layer 191 along the stacking direction z and extends to the semiconductor layer 18, thereby electrically connecting the lead 192 and the semiconductor layer 18.

[0119] The material of the first insulating layer 191 may include an oxide, such as silicon dioxide. The material of the lead wire 192 may include a conductive material, such as metallic copper. The lead wire 192 is used to electrically connect to an external host and to receive signals from the external host. Similar to the second electrode layer 16, the lead wire 192 also includes a plurality of partitioned portions (which can be considered to be spaced apart within the lead wire 192), and the partitioned second electrode layer 16 (or the partitioned semiconductor layer 18) is electrically connected to the corresponding partitioned lead wire 192.

[0120] In some embodiments, if the semiconductor structure 10 includes a cup-type capacitor structure or a pillar-type capacitor structure, please continue to refer to Figures 2J and 4H. After forming the lead line 192, multiple grooves can be formed along the stacking direction z that penetrate the bit line 124 to separate the inside of the bit line 124 into multiple unconnected parts, that is, the inside of the bit line 124 is spaced apart, and the separation position of the bit line 124 should correspond to the separation position of the second electrode layer 16 or the semiconductor layer 18, thereby achieving independent control of a single contact structure M or N. Subsequently, a second insulating layer 125 is formed on the side of the bit line 124 away from the channel structure 122a, and the second insulating layer 125 fills the groove in the bit line 124. The material of the second insulating layer 125 may include an oxide, such as silicon dioxide.

[0121] For example, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to FIG2J . The position and number of the grooves formed in the bit line 124 should correspond to the position and total number of the first groove 171 and the second groove 172 in FIG2I . If the semiconductor structure 10 is a pillar-type capacitor structure, please continue to refer to FIG4H . The position and number of the grooves formed in the bit line 124 should correspond to the position and total number of the third groove 173 and the fourth groove 174 in FIG3G .

[0122] In other embodiments, in addition to forming multiple grooves penetrating the bit lines 124 along the stacking direction z after forming the lead lines 192, multiple grooves penetrating the bit lines 124 along the stacking direction z may also be formed after forming the bit lines 124. This is not a limitation herein. The present application also provides a semiconductor structure 10 including a cup-type capacitor structure or a pillar-type capacitor structure. Please continue to refer to the above-mentioned Figures 2J and 3G, as well as Figures 4H and 5H, wherein the semiconductor structure 10 includes: a stacking structure 11a, the stacking structure 11a includes a first area AA and a second area BB; a first electrode layer 13 located in the first area AA and the second area BB, the first electrode layer 13 passes through the stacking structure 11a along the stacking direction z and is arranged at intervals; a dielectric layer 14 located at least in the first area AA; a second electrode layer 16 located in the first area AA and the second area BB, the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are arranged at intervals, and the first electrode layer 13 and the second electrode layer 16 in the second area BB are connected, and the dielectric layer 14 is provided between the first electrode layer 13 and the second electrode layer 16 in the first area AA.

[0123] Among them, the first direction x and the second direction y can be the extension direction of the stacked layer 11, which are perpendicular to the stacking direction z of the stacked layer 11. The first area AA is the area corresponding to the memory array, and the second area BB is other areas. The first area AA and the second area BB can be adjacent to each other, for example, the second area BB is arranged around the first area AA. The material of the first electrode layer 13 includes conductive materials such as metals, such as tungsten, copper, etc. The material of the dielectric layer 14 is a material with a high dielectric constant. The material of the second electrode layer 16 is mainly a conductive material, and any one or combination of tungsten, cobalt, copper, aluminum, polysilicon, and doped crystalline silicon can be selected.

[0124] The second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are spaced apart from each other, primarily meaning that the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are isolated from each other and do not have any direct contact area therebetween. The first electrode layer 13 and the second electrode layer 16 in the second area BB are connected, primarily meaning that at least a portion of the first electrode layer 13 in the second area BB and the second electrode layer 16 in the second area BB are in direct contact with each other.

[0125] The first electrode layer 13 in the first area AA and the first electrode layer 13 in the second area BB are both spaced apart, that is, the first electrode layer 13 in the first area AA and the first electrode layer 13 in the second area BB each include a plurality of separated parts that are not connected to each other.

[0126] In some embodiments, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2J and 3G. The stacked layer 11 may include alternating spacer layers 111 and sacrificial layers 112. The material of the sacrificial layer 112 may include silicon dioxide, and the material of the spacer layer 111 may include silicon nitride.

[0127] In some embodiments, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2J and 3G, the dielectric layer is located on the stacked structure in the first region, and covers the side of the first electrode layer in the first region facing away from the stacked structure; the second electrode layer is located on the stacked structure in the first region and the second region, and covers the side of the dielectric layer in the first region facing away from the first electrode layer, and the side of the first electrode layer in the second region facing away from the stacked structure.

[0128] In some embodiments, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2J and 3G. The semiconductor structure 10 may also include a support layer 15 located in the first area AA and the second area BB and spaced apart, and the first electrode layer 13 surrounds the support layer 15.

[0129] The material of the support layer 15 is generally different from the material of the stacked structure 11 a , and may be carbon, for example.

[0130] In some embodiments, if the semiconductor structure 10 is a pillar-type capacitor structure, please continue to refer to Figures 4G and 5G, the dielectric layer 14 is located on the stacked structure 11a in the first area AA, and penetrates part of the stacked structure 11a in the first area AA and the second area BB along the stacking direction z; the second electrode layer 16 is located on the stacked structure 11a in the first area AA and the second area BB, and covers the side of the dielectric layer 14 away from the first electrode layer 13.

[0131] In some embodiments, if the semiconductor structure 10 is a pillar capacitor structure, referring to Figures 4G and 5G , the stacked structure 11a includes a plurality of stacked spacer layers 111, which are spaced apart along the stacking direction z. Furthermore, the dielectric layer 14 and the second electrode layer 16 are located between two adjacent spacer layers 111 in the second region BB and the first region AA along the stacking direction z.

[0132] In some embodiments, if the semiconductor structure 10 is a pillar capacitor structure, please continue to refer to Figures 4G and 5G. The semiconductor structure 10 may further include a semiconductor layer 18. The semiconductor layer 18 is located on the side of the second electrode layer 16 in the first area AA and the second area BB facing away from the dielectric layer 14. The second electrode layer 16 between the two adjacent spacer layers 111 surrounds the semiconductor layer 18. The semiconductor layer 18 in the first area AA and the semiconductor layer 18 in the second area BB are spaced apart. The semiconductor layer 18 in the second area BB is spaced apart.

[0133] The material of the semiconductor layer 18 may include polysilicon and / or silicide, such as silicon germanium (SiGe). The semiconductor layers 18 in the first region AA and the second region BB are spaced apart, meaning that they are separated and not connected (directly in contact). The semiconductor layer 18 in the second region BB is spaced apart internally, meaning that the semiconductor layer 18 in the second region BB is separated into multiple portions, and these portions are not connected (in contact) with each other.

[0134] In some embodiments, if the semiconductor structure 10 includes a cup-type capacitor structure or a pillar-type capacitor structure, please continue to refer to Figures 2J and 3G, as well as Figures 4G and 5G. The semiconductor structure 10 may further include a channel structure 122a and a gate structure 123. The channel structure 122a is arranged at intervals along the first direction x and the second direction y, and is located on a side of the stacked structure 11a away from the second electrode layer 16. The gate structure 123 extends along the second direction y and is connected to at least the channel structure 122a corresponding to the first area AA.

[0135] The position of the channel structure 122a corresponds to the position of the first electrode layer 13, and the first direction x, the second direction y, and the stacking direction z are mutually perpendicular. The gate structure 123 may include a gate spacer layer 1231 and a gate layer 1232. The material of the gate spacer layer 1231 may include an insulating material such as an oxide, and the material of the gate layer 1232 may be any one or a combination of tungsten, cobalt, copper, aluminum, polysilicon, and doped crystalline silicon. Adjacent gate structures 123 along the first direction x may be further separated by insulating material to achieve electrical isolation between adjacent gate structures 123.

[0136] It should be noted that the gate structure 123 may be formed at positions corresponding to both the first area AA and the second area BB, or may be formed only at positions corresponding to the first area AA, which is not limited here.

[0137] In some embodiments, if the semiconductor structure 10 includes a cup-type capacitor structure or a pillar-type capacitor structure, please continue to refer to Figures 2J and 3G, as well as Figures 4G and 5G. The semiconductor structure 10 may further include a bit line 124, which may be located on a side of the channel structure 122a away from the stack structure 11a and connected to the channel structure 122a.

[0138] In some embodiments, if the semiconductor structure 10 includes a cup-type capacitor structure or a pillar-type capacitor structure, please continue to refer to Figures 2J and 3G, as well as Figures 4G and 5G, the channel structure 122a corresponding to the first area AA and the second area BB have different doping concentrations, and the doping concentration of the channel structure 122a in the second area BB is greater than the doping concentration of the channel structure 122a in the first area AA.

[0139] The greater the doping concentration, the stronger the conductivity, so the conductivity of the channel structure 122 a in the second area BB is greater than the conductivity of the channel structure 122 a in the first area AA.

[0140] It should be pointed out that if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2J and 3G. For any local second electrode layer 16 of the internal partition in the second area BB, it is usually connected to the first electrode layer 13 of the corresponding partition. The connected first electrode layer 13 and second electrode layer 16 can be used as a contact structure M as a whole, thereby obtaining multiple contact structures M, which penetrate the stacking structure 11a along the stacking direction z and extend to the channel structure 122a.

[0141] In some embodiments, if the semiconductor structure 10 is a pillar-type capacitor structure, please continue to refer to Figures 4G and 5G. For any local second electrode layer 16 of the internal partition in the second region BB, it is connected to the first electrode layer 13 and the semiconductor layer 18 of the corresponding partition. The connected first electrode layer 13, the second electrode layer 16 and the semiconductor layer 18 can be used as a contact structure N as a whole, thereby obtaining multiple contact structures N, which penetrate the stacking layer 11a along the stacking direction z and extend to the channel structure 122a.

[0142] In some embodiments, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2J and 3G. The semiconductor structure 10 further includes a first insulating layer 191 and a lead 192, wherein the first insulating layer 191 is located on the side of the second electrode layer 16 facing away from the stacked structure 11a, and also fills between two adjacent internally partitioned second electrode layers 16. The lead 192 is located on the side of the first insulating layer 191 facing away from the second electrode layer 16, and also penetrates the first insulating layer 191 along the stacking direction z and extends to the second electrode layer 16, thereby electrically connecting the lead 192 to the second electrode layer 16.

[0143] In some embodiments, if the semiconductor structure 10 is a pillar capacitor structure, please continue to refer to Figures 4G and 5G. The semiconductor structure 10 further includes a first insulating layer 191 and a lead 192, wherein the first insulating layer 191 is located on the side of the second electrode layer 16 facing away from the stacked structure 11a, and also fills between two adjacent internally partitioned second electrode layers 16. The lead 192 is located on the side of the first insulating layer 191 facing away from the second electrode layer 16, and also penetrates the first insulating layer 191 along the stacking direction z and extends to the second electrode layer 16, thereby electrically connecting the lead 192 and the semiconductor layer 18.

[0144] The material of the first insulating layer 191 may include an oxide, such as silicon dioxide. The material of the lead wire 192 may include a conductive material, such as metallic copper. The lead wire 192 is used to electrically connect to an external host and to receive signals from the external host. Similar to the second electrode layer 16, the lead wire 192 also includes a plurality of partitioned portions (which can be considered to be spaced apart within the lead wire 192), and the partitioned second electrode layer 16 (or the partitioned semiconductor layer 18) is electrically connected to the corresponding partitioned lead wire 192.

[0145] It should be understood that the structures and manufacturing processes of the various components of the semiconductor structure 10 in the embodiment of the present application can refer to the above-mentioned embodiment of the manufacturing method of the semiconductor structure 10, and will not be repeated here.

[0146] In summary, the manufacturing method of the semiconductor structure 10 and the semiconductor structure 10 provided in the embodiment of the present application form a plurality of capacitor holes Q1 penetrating the stacking layer 11 along the stacking direction z, and the stacking layer 11 includes a first area AA and a second area BB. The capacitor holes Q1 are located in the first area AA and the second area BB, thereby greatly avoiding a serious etching load effect in the first area AA when forming the capacitor holes Q1, and ensuring the size consistency of the capacitor holes Q1 in the first area AA as much as possible, and preventing insufficient etching. Subsequently, a first electrode layer 13 is formed on the inner wall of the capacitor hole Q1; the stacking layer 11 in the first area AA and the second area BB A dielectric layer 14 is formed on one side; at least a portion of the dielectric layer 14 in the second area BB is removed; a second electrode layer 16 is formed in the first area AA and the second area BB, the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are spaced apart, and the first electrode layer 14 and the second electrode layer 16 in the second area BB are connected. Therefore, on the one hand, a capacitor structure with uniform size can be formed in the first area AA, thereby improving the reliability of the capacitor structure. On the other hand, the first electrode layer 14 and the second electrode layer 16 connected in the second area BB can serve as a contact structure, without the need for additional contact structure, thereby simplifying the production process and increasing flexibility.

[0147] In addition, see Figure 7, Figure 7 is a structural diagram of an exemplary system 100 provided in an embodiment of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage therein. As shown in Figure 7, system 100 may include a host 101 and a memory system 102, and memory system 102 includes one or more memories 1021 and a controller 1022. Host 101 can be a processor (e.g., a central processing unit (CPU)) or an on-chip memory system (System on Chip, SOC) (e.g., an application processor (AP)) of an electronic device. Host 101 can be configured to send data to memory 1021 or receive data from memory 1021.

[0148] In the examples of the present application, the memory 1021 is not limited to a three-dimensional DRAM memory. Without violating the disclosure or teachings of the present application, the memory 1021 can be implemented as various other types of volatile memories that lose stored data when the power is disconnected.

[0149] In some embodiments, the controller 1022 is coupled to the memory 1021 and the host 101 and is configured to control the memory 1021, such as controlling the memory 1021 to perform data write and read operations. The controller 1022 can manage data stored in the memory 1021 and communicate with the host 101.

[0150] The controller 1022 may be configured to control operations of the memory 1021, such as read, erase, and program operations. The controller 1022 may also be configured to manage various functions regarding data stored or to be stored in the memory 1021, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.

[0151] The controller 1022 and one or more memories 1021 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of electronic products.

[0152] 8 is a schematic diagram of the structure of a memory 200 provided in an embodiment of the present application. The memory 200 includes any of the aforementioned semiconductor structures 201 and a peripheral circuit structure 202 coupled to the semiconductor structure 201. The peripheral circuit structure 202 can be configured to perform operations such as read, write, erase, and verify on the semiconductor structure 201.

[0153] In some embodiments, the peripheral circuit structure 202 may further include word line drivers, bit line drivers, column decoders, sensing circuits, data buffers, program verification logic, and erase verification circuits, etc., which may perform the above operations according to the acquired computer program instructions.

[0154] It should be noted that the peripheral circuit structure 202 and the semiconductor structure 201 can be stacked or tiled, which is not limited here.

[0155] For example, see Figure 9, which is a schematic cross-sectional view of a memory device 300, wherein the memory device 300 includes a semiconductor structure 10 having any of the aforementioned cup-type capacitor structures, and a peripheral circuit structure 301 coupled to the semiconductor structure 10. The peripheral circuit structure 301 and the semiconductor structure 10 are stacked and located on a side of the second insulating layer 125 facing away from the bit line 124, and are electrically connected to the bit line 124 via a contact.

[0156] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor structure, wherein: include: forming a plurality of capacitor holes penetrating through the stacked layer along a stacking direction, the stacked layer comprising a first region and a second region, the capacitor holes being located in the first region and the second region; forming a first electrode layer on the inner wall of the capacitor hole; forming a dielectric layer on one side of the stacked layer in the first region and the second region; removing at least a portion of the dielectric layer in the second region; A second electrode layer is formed in the first region and the second region. The second electrode layer in the first region and the second electrode layer in the second region are spaced apart from each other, and the first electrode layer and the second electrode layer in the second region are connected.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first electrode layers in the first region and the second region are arranged at intervals.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The removing at least a portion of the dielectric layer in the second region comprises: The dielectric layer in the second region is removed, and the first electrode layer in the second region is exposed.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The forming of a second electrode layer in the first region and the second region comprises: forming a second electrode layer on one side of the stacked layer, wherein the second electrode layer is located in the first region and the second region, covers the side of the dielectric layer away from the stacked layer and the exposed first electrode layer, and fills the capacitor hole; A first groove is formed along the stacking direction through the second electrode layer on the stacking layer, wherein the first groove extends along the first direction and separates the second electrode layer from the stacking layer along the second direction. In the first region and the second electrode layer in the second region, the first direction, the second direction and the stacking direction are perpendicular to each other.

5. The method for manufacturing a semiconductor structure according to claim 4, further comprising: At least one second groove is formed along the stacking direction and penetrates the second electrode layer on the stacking layer in the second region, wherein the second groove divides the second electrode layer in the second region into a plurality of parts.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The stacked layer includes a sacrificial layer, and before forming the dielectric layer, further includes: forming a supporting layer on one side of the stacked layer in the first region and the second region, and the supporting layer fills the capacitor hole; Forming a plurality of spacing holes penetrating the support layer along the stacking direction and extending into the stacking layer, and removing the sacrificial layer to form empty grooves, wherein the spacing holes are located in the first region and the second region; Removing the support layer outside the capacitor hole; The dielectric layer is located on the stacked layers in the first region and the second region, and covers the inner wall of the empty groove and the inner wall of the spacing hole.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The removing at least a portion of the dielectric layer in the second region comprises: The dielectric layer on the stacked layer in the second region is removed, and a portion of the first electrode layer in the second region is exposed.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: The forming of a second electrode layer in the first region and the second region comprises: Forming a second electrode layer on one side of the stacked layer, wherein the second electrode layer covers the side of the dielectric layer in the empty groove and the spacing hole away from the stacked layer, and the exposed first electrode layer; A third groove is formed along the stacking direction through the second electrode layer on the stacking layer, wherein the third groove extends along the first direction and separates the second electrode layer from the stacking layer along the second direction. In the first region and the second electrode layer in the second region, the first direction, the second direction and the stacking direction are perpendicular to each other.

9. The method for manufacturing a semiconductor structure according to claim 8, further comprising: forming a semiconductor layer on a side of the second electrode layer away from the stacked layer, wherein the semiconductor layer fills the empty groove and the spacing hole; The third groove at least penetrates the semiconductor layer and the second electrode layer along the stacking direction.

10. The method for manufacturing a semiconductor structure according to claim 9, further comprising: A fourth groove is formed to penetrate the semiconductor layer and the second electrode layer along the stacking direction, and the fourth groove divides the second electrode layer in the second region into a plurality of parts.

11. The method for manufacturing a semiconductor structure according to any one of claims 1 to 10, further comprising: forming a plurality of active portions extending along a first direction and spaced apart along a second direction on a substrate; performing a doping process of a first concentration on the active portion corresponding to the second region; forming a gate structure extending along the second direction and at least connecting the active portion in the first region, wherein the gate structure penetrates the active portion along the stacking direction to obtain a plurality of channel structures, and the first direction, the second direction and the stacking direction are perpendicular to each other; The stacked layer is formed on a side of the substrate close to the channel structure.

12. The method for manufacturing a semiconductor structure according to claim 11, further comprising: The active portion of the first region is doped with a second concentration, wherein the first concentration is greater than the second concentration.

13. A semiconductor structure comprising: A stacked structure, the stacked structure comprising a first region and a second region; First electrode layers located in the first region and the second region, the first electrode layers penetrating the stacking structure along a stacking direction and being arranged at intervals; a dielectric layer located at least in the first region; The second electrode layer is located in the first region and the second region, the second electrode layer in the first region and the second electrode layer in the second region are arranged at intervals, and the first electrode layer and the second electrode layer in the second region are connected, and the dielectric layer is arranged between the first electrode layer and the second electrode layer in the first region.

14. The semiconductor structure according to claim 13, wherein: The first electrode layers in the first region and the second region are arranged at intervals.

15. The semiconductor structure according to claim 13, wherein: The second electrode layers in the second region are arranged at intervals.

16. The semiconductor structure according to claim 13, wherein: The dielectric layer is located on the stacked structure in the first region and covers a side of the first electrode layer in the first region that is away from the stacked structure; the second electrode layer is located on the stacked structure in the first region and the second region and covers a side of the dielectric layer in the first region that is away from the first electrode layer and a side of the first electrode layer in the second region that is away from the stacked structure.

17. The semiconductor structure according to claim 13, wherein: The dielectric layer is located on the stacked structure in the first region and penetrates part of the stacked structure in the first region and the second region along the stacking direction; the second electrode layer is located on the stacked structure in the first region and the second region and covers a side of the dielectric layer away from the first electrode layer.

18. The semiconductor structure according to claim 17, wherein: The stacking structure includes a plurality of spacer layers stacked together, and the dielectric layer and the second electrode layer are also located between two adjacent spacer layers in the second region and the first region along the stacking direction.

19. The semiconductor structure according to claim 18 further includes a semiconductor layer, wherein the semiconductor layer is located on the side of the second electrode layer in the first region and the second region facing away from the dielectric layer, and the second electrode layer between two adjacent spacing layers along the stacking direction surrounds the semiconductor layer, and the semiconductor layer in the first region and the semiconductor layer in the second region are spaced apart.

20. The semiconductor structure of claim 19, wherein: The semiconductor layers in the second region are arranged at intervals. 21 . The semiconductor structure according to claim 13 , further comprising a support layer located in the first region and the second region and spaced apart from each other, wherein the first electrode layer surrounds the support layer.

22. The semiconductor structure according to any one of claims 13 to 21, wherein: The semiconductor structure further includes a channel structure and a gate structure, wherein the channel structure is arranged at intervals along a first direction and a second direction and is located on a side of the stacked structure away from the second electrode layer, and the gate structure extends along the second direction and is at least connected to the channel structure corresponding to the first region; The position of the channel structure corresponds to the position of the first electrode layer, and the first direction, the second direction and the stacking direction are perpendicular to each other.

23. The semiconductor structure of claim 22, wherein: The channel structures corresponding to the first region and the second region have different doping concentrations, and the doping concentration of the channel structure in the second region is greater than the doping concentration of the channel structure in the first region.

24. A memory, wherein: It comprises a semiconductor structure and a peripheral circuit structure as described in any one of claims 13 to 23, wherein the peripheral circuit structure and the semiconductor structure are electrically connected.

25. A memory system, wherein: The device comprises at least one memory as claimed in claim 24, and a controller coupled to the memory, wherein the controller is used to control the memory to store data.

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