Random clock generating device and clock signal output method

Abstract

An embodiment of the present application provides a random clock generating device and a clock signal output method. The random clock generating device includes: a random sequence generator, a selection and switching unit, and a clock pool, where the clock pool and the random sequence generator are respectively connected to the selection and switching unit; wherein, the random sequence generator is used to generate a random sequence; the selection and switching unit is used to select and switch the master clock of the random clock generating device, and detect whether a set low-frequency sequence appears in the random sequence; when the low-frequency sequence is detected, identify the clock number from the random sequence and select the corresponding clock to replace the current clock to become the master clock of the random clock generating device; the master clock is used to output a clock signal controlled by the random sequence. The method of the present application improves the usage effect of the random clock generating device when defending against side-channel attack clock switching.

Description

Technical Field

[0001] This application relates to the technical field of clock signal processing for cryptographic security, and particularly to a random clock generation device and a clock signal output method. Background Art

[0002] In the field of information security, side-channel attacks analyze information such as leaked energy and radiation during cryptographic operations, and use statistical analysis methods to obtain keys, becoming an important factor threatening the security of cryptographic chips and applications. Therefore, enhancing the defense against side-channel attacks, especially by improving the difficulty of external statistical analysis through techniques such as clock randomization to ensure the inconsistency of key data and external information in space and time, has become a key measure to ensure the cryptographic security of chips. Clock randomization effectively disrupts the analysis path of attackers based on clock-related side-channel information by introducing unpredictability, and is one of the effective means to resist such attacks.

[0003] Currently, random clock generation devices use clock randomization technology to defend against side-channel attacks, that is, during cryptographic operations, different clock sources are switched by setting a time period. The regularity of this switching leads to a significant reduction in randomness, making the system more vulnerable to analysis and prediction by potential attackers. Summary of the Invention

[0004] This application provides a random clock generation device and a clock signal output method to solve the problem that the existing random clock generation device has a poor usage effect due to the poor randomness of clock switching when defending against side-channel attacks.

[0005] On the one hand, this application provides a random clock generation device, which includes a random sequence generator, a selection and switching unit, and a clock pool. The clock pool and the random sequence generator are respectively connected to the selection and switching unit; wherein,

[0006] The random sequence generator is used to generate a random sequence;

[0007] The selection and switching unit is used to select and switch the main clock of the random clock generation device, and detect whether a set low-frequency sequence appears in the random sequence;

[0008] When a low-frequency sequence is detected, the clock number is identified from the random sequence and the corresponding clock is selected to replace the current clock to become the main clock of the random clock generation device;

[0009] The main clock is used to output a clock signal controlled by the random sequence.

[0010] In a possible implementation manner, the clock number is determined according to a target bit, and the target bit is determined according to the position of the low-frequency sequence in the random sequence.

[0011] In a possible implementation, the random clock generating device includes a reference clock and a frequency division circuit. The frequency division circuit is connected between the reference clock and the clock pool, and the clocks in the clock pool are obtained by the frequency division circuit dividing the reference clock.

[0012] In a possible implementation, the selection and switching unit includes a first configurator and a selection and switching circuit;

[0013] The first configurator is configured to, in response to a configuration operation, configure and detect a low-frequency sequence in the random sequence, and when the low-frequency sequence is detected, identify a clock number from the random sequence according to the low-frequency sequence;

[0014] The selection and switching circuit is configured to select a corresponding clock according to the clock number identified from the random sequence to replace the current clock and become the master clock of the random clock generating device.

[0015] In a possible implementation, the occurrence frequency of the low-frequency sequence in the random sequence is determined according to the run length of the low-frequency sequence.

[0016] In a possible implementation, the random clock generating device further includes a gating unit, and the gating unit is respectively connected to the random sequence generator and the selection and switching unit;

[0017] The gating unit is configured to, when a high-frequency sequence in the random sequence is detected, perform a gating operation on the master clock connected to the selection and switching unit, and the gating operation is used to prevent the random clock signal output by the master clock from performing a clock flip.

[0018] In a possible implementation, the gating unit includes an efficiency regulation circuit, a clock gating subunit, and a second configurator. The random sequence generator is connected to the efficiency regulation circuit and the clock gating subunit. The clock gating subunit is further connected to the selection and switching unit, and the second configurator is connected to the efficiency regulation circuit;

[0019] The second configurator is configured to configure the high-frequency sequence;

[0020] The efficiency regulation circuit is configured to detect the high-frequency sequence set by the second configurator in the random sequence, and output a gating signal when the high-frequency sequence in the random sequence is detected;

[0021] The clock gating subunit is configured to perform a gating operation on the master clock connected to the selection and switching unit according to the gating signal.

[0022] In a possible implementation, the occurrence frequency of the high-frequency sequence in the random sequence is determined according to the run length of the high-frequency sequence.

[0023] On the other hand, the present application provides a cryptographic chip, including a random clock generating device.

[0024] On the other hand, the present application provides a clock signal output method, which is applied to a random clock generating device. The random clock generating device includes a selection and switching unit. The method includes:

[0025] Detecting whether a set low-frequency sequence appears in the random sequence, where the random sequence is generated by a random sequence generator in the random clock generating device;

[0026] When the low-frequency sequence is detected, identifying the clock number from the random sequence and selecting the corresponding clock to replace the current clock to become the main clock of the random clock generating device. The main clock is used to output a clock signal controlled by the random sequence.

[0027] In a possible implementation manner, the random clock generating device further includes a gating unit, and the method further includes:

[0028] When a set high-frequency sequence in the random sequence is detected, performing a gating operation on the main clock connected to the selection and switching unit. The gating operation is used to prevent the random clock signal output by the main clock from performing clock inversion.

[0029] On the other hand, the present application provides a control device for a random clock generating device, which is applied to the random clock generating device. The random clock generating device includes a selection and switching unit, and includes:

[0030] An identification module, configured to detect whether a set low-frequency sequence appears in the random sequence, where the random sequence is generated by a random sequence generator in the random clock generating device;

[0031] A replacement module, configured to, when the low-frequency sequence is detected, identify the clock number from the random sequence and select the corresponding clock to replace the current clock to become the main clock of the random clock generating device. The main clock is used to output a clock signal controlled by the random sequence.

[0032] On the other hand, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0033] The memory stores computer execution instructions;

[0034] The processor executes the computer execution instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementation manners of the first aspect.

[0035] On the other hand, an embodiment of the present application provides a computer-readable storage medium. Computer execution instructions are stored in the computer-readable storage medium. When the computer execution instructions are executed by a processor, they are used to implement the above first aspect and / or various possible implementation manners of the first aspect.

[0036] On the other hand, an embodiment of the present application provides a computer program product, including a computer program, which when executed by a processor implements the above first aspect and / or various possible implementation manners of the first aspect.

[0037] The random clock generating device and the clock signal output method provided by the present application include a random sequence generator, a selection and switching unit, and a clock pool through the random clock generating device. The clock pool and the random sequence generator are respectively connected to the selection and switching unit; the random sequence generator is used to generate a random sequence; the selection and switching unit is used to select and switch the master clock of the random clock generating device, and detect whether a set low-frequency sequence appears in the random sequence; when the low-frequency sequence is detected, identify the clock number from the random sequence and select the corresponding clock to replace the current clock to become the master clock of the random clock generating device; the master clock is used to output a clock signal controlled by the random sequence. Using a random source or a pseudo-random source as an input and the run length of random numbers as a regulation factor, the random sequence is mapped to the random clock output in real time, so that when the random clock generating device is used, compared with the method of preventing side-channel attacks by switching the clock through a fixed time period, the randomness of clock switching can be improved by the non-fixed frequency of the low-frequency sequence appearing in the random sequence. Thus, the use effect of the random clock generating device is better, and it can effectively resist the attack means based on time side-channel analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0039] Figure 1 Structural schematic of a random clock generating device provided by an embodiment of the present application Figure 1 ;

[0040] Figure 2 Structural schematic of a random clock generating device provided by an embodiment of the present application Figure 2 ;

[0041] Figure 3 Structural schematic of a random clock generating device provided by an embodiment of the present application Figure 3 ;

[0042] Figure 4 Structural schematic of a random clock generating device provided by an embodiment of the present application Figure 4 ;

[0043] Figure 5 Structural schematic of another random clock generating device provided by an embodiment of the present application;

[0044] Figure 6 Schematic flowchart of a clock signal output method provided by an embodiment of the present application;

[0045] Figure 7 Schematic flowchart of another clock signal output method provided by an embodiment of the present application;

[0046] Figure 8 Schematic structural diagram of a clock signal output device provided by an embodiment of the present application;

[0047] Figure 9 Schematic structural diagram of an electronic device provided by an embodiment of the present application.

[0048] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0049] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] First, the terms involved in the present application are explained:

[0051] The clock signal may refer to the timing signal that controls the cryptographic operation process. The operations inside the cryptographic chip are driven by a fixed clock signal, which can determine the start and end times of each operation.

[0052] The random sequence (Random Walk Sequence) may refer to a mathematical model that describes a random process, where the direction and / or distance of each step are randomly determined. In information security and cryptography, the random sequence can be used to generate unpredictable signals to increase the security of the system. For example, it can be used to generate random clock signals, making it difficult for attackers to analyze and infer the internal state of the system through side-channel attacks.

[0053] A Random Sequence Generator (RSG) can be a circuit or algorithm used to generate random bit sequences. Common implementation methods include Linear Feedback Shift Registers (LFSRs) and True Random Number Generators (TRNGs). LFSRs generate pseudo-random sequences through feedback polynomials and are suitable for applications that require long periods and predictability; while TRNGs utilize physical noise or other unpredictable natural phenomena to generate truly random sequences and are suitable for scenarios with extremely high requirements for randomness, such as encryption and security applications.

[0054] A low-frequency sequence refers to a relatively long sequence composed of "0" or "1" in a random sequence. Since its length is long, in terms of probability, the probability of its occurrence in the random sequence is relatively low.

[0055] A high-frequency sequence refers to a relatively short sequence composed of "0" or "1" in a random sequence. Since its length is short, in terms of probability, the probability of its occurrence in the random sequence is relatively high.

[0056] A bit is the smallest unit in the binary number system, representing one of two possible states, usually denoted by 0 and 1. In clock randomization techniques, bits can be used to represent different states of a clock signal. For example, 0 can represent one phase of the clock and 1 can represent another phase. By randomizing these bits, a more complex and unpredictable clock signal can be generated.

[0057] In related technologies, although the multi-clock switching technology provides a certain degree of flexibility in clock management to some extent, its inherent mechanism inevitably weakens the randomness of the system. That is, when the system switches between different clock sources, this switching is only selected from the clock pool at a certain time, and the selection is also limited, resulting in low randomness.

[0058] The random clock generating device and clock signal output method provided by this application, through the random clock generating device, includes a random sequence generator, a selection and switching unit, and a clock pool. Among them, the random sequence generator and the selection and switching unit are respectively connected to the clock pool; when the device works, the random sequence generator is used to generate a random sequence, and the selection and switching unit detects whether a set low-frequency sequence appears in the random sequence. When it detects that the low-frequency sequence appears in the random sequence, it identifies the clock number from the random sequence and selects the corresponding clock to replace the current clock, becoming the master clock of the random clock generating device, and outputs a clock signal. In this process, since the appearance of the set low-frequency sequence in the random sequence is random, compared with the technical means of preventing side-channel attacks by switching clocks at fixed time intervals, the switching of the master clock has randomness. When preventing side-channel attacks, the switching period of the clock switching becomes more unpredictable. Therefore, the use effect of the random clock generating device is better, and it can effectively resist the attack means based on time side-channel analysis.

[0059] The following uses specific embodiments to detail the technical solution of this application and how the technical solution of this application solves the above technical problems. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The following will describe the embodiments of this application in conjunction with the drawings.

[0060] Figure 1 Structural schematic of a random clock generating device provided by an embodiment of this application Figure 1 , as Figure 1 shown, the random clock generating device includes a random sequence generator, a selection and switching unit, and a clock pool. The clock pool and the random sequence generator are respectively connected to the selection and switching unit, where:

[0061] The random sequence generator is used to generate a random sequence;

[0062] The selection and switching unit is used to select and switch the master clock of the random clock generating device, and detect whether a set low-frequency sequence appears in the random sequence;

[0063] When the low-frequency sequence is detected, the clock number is identified from the random sequence and the corresponding clock is selected to replace the current clock, becoming the master clock of the random clock generating device;

[0064] The master clock is used to output a clock signal controlled by the random sequence.

[0065] Among them, the random sequence can be used as a random input. The run of the random sequence is a subsequence composed of consecutive '0's or '1's in the sequence, and the leading and trailing elements of this subsequence are different from its own elements. The randomness test of the random sequence requires that its runs conform to a specific distribution. This stable probability distribution in randomness can provide a stable component in randomness. Through specific runs, while maintaining a high degree of randomness of the clock output, a selection with a specific efficiency can be achieved. As a result, the generated clock signal is not only difficult to predict but also has excellent anti-analysis performance. At the same time, its working efficiency is effectively guaranteed, avoiding possible fluctuations in system performance caused by randomness.

[0066] In some embodiments, within a segment of the random sequence, the number of runs of '0's and the number of runs of '1's with the same length are basically equal, and for each 1-bit increase in the run length, the number of runs should be close to being halved. Thus, it can be approximated to a continuous '1' sequence with a run length of 1, that is, the sequence '010' appears in the random number, and the number is close to 1 / 4; a continuous '1' sequence with a run length of 2, that is, the sequence '0110' appears in the random number, and the number is close to 1 / 8, and so on. By controlling the selection of runs, it can be ensured that within a long period, a specific number of data appears randomly. Corresponding random clock changes are generated according to this random point.

[0067] The low-frequency sequence can be a sequence that appears in the random sequence. In the embodiments of the present application, the low-frequency sequence can be set arbitrarily according to needs. For example, the low-frequency sequence can be a '0' sequence such as the sequence '1{10 zeros}1' with a run length of 10, or it can also be a '1' sequence such as the sequence '0{11 ones}0' with a run length of 10. The run length of the low frequency is not limited here because low frequency and high frequency are relative.

[0068] Detecting the low-frequency sequence in the random sequence can refer to the situation when the low-frequency sequence appears in the random sequence. When the low-frequency sequence appears, the clock number to be pre-switched can be identified from the random sequence. In the embodiments of the present application, the clock number can be determined according to the target bit.

[0069] Among them, the target bit can refer to the bit selected from the random sequence. According to the target bit, the corresponding clock number can be determined. Thus, according to the pre-set mapping relationship, the corresponding clock can be determined from the clock pool.

[0070] In the embodiments of the present application, the target bit is determined according to the position of the low-frequency sequence in the random sequence. For example, after detecting the low-frequency sequence in the random sequence, the subsequent or previous N bits can be used as the target bit, or according to the preset rule as needed, the subsequent or previous N bits can be selected, where N is a positive integer.

[0071] In some embodiments, the position of the target bit in the random sequence can be determined according to the number of clocks in the clock pool. For example, when the number of clocks in the clock pool is 16, the target bit can include four bits, that is, when the random sequence generator generates this low-frequency sequence, the subsequent 4 bits in the random sequence are used as the ID representing the clock identifier.

[0072] The mapping relationship can refer to the corresponding relationship between the pre-set clock identifiers and different clocks in the clock pool. Among them, different target bits correspond to different clock identifiers, and different clock identifiers correspond to different clocks.

[0073] For example, in the embodiments of the present application, when the low-frequency sequence is "1{10 zeros}1" and the random sequence generator generates this random sequence, the subsequent 4 bits are used as the ID, and one of the 16 alternative clocks is selected as the master clock (for example, if the ID is 8, then according to the mapping relationship, clock 8 is selected as the master clock. If the sequence output by clock 8 detects "1{10 zeros}1" again, then the clock switching is triggered again) and the switching of the master clock is completed through the clock switching circuit.

[0074] In the embodiments of the present application, the clocks in the clock pool are obtained by frequency-dividing a reference clock.

[0075] Among them, the frequency division process can refer to reducing the frequency of the reference clock signal through a frequency division circuit to generate a series of lower-frequency clock signals. For example, after the reference clock signal passes through the frequency division circuit, its 2-frequency division, 4-frequency division, and 8-frequency division clock signals will be generated. Among them, when the reference clock signal includes clk0, clk1, clk2, clk3, each reference clock signal will generate 4 different-frequency clock signals (the original reference clock, 2-frequency division, 4-frequency division, 8-frequency division), and a total of 16 alternative clocks are formed in the clock pool. These frequency-divided clock signals provide the system with a variety of frequency options to meet different clock requirements.

[0076] Therefore, the random clock generation device provided by the embodiments of the present application ensures that the entire process becomes more unpredictable when the clock is switched through the randomness of the low-frequency sequence appearing in the random sequence, making the clock signal exhibit a high degree of unpredictability and randomness. Therefore, compared with the method of switching the clock through a fixed time period, due to its better randomness and being less likely to be predicted, it can effectively resist the attack means based on time side-channel analysis, ensure the security of the random clock generation device, and make the use effect of the random clock generation device better.

[0077] Meanwhile, the random clock generation device provided by the embodiment of the present application can adjust the random clock signal output by the random clock generation device through clock switching. Among them, clock switching refers to switching between clock signals with different frequencies or sources. Since this kind of switching usually involves a relatively long time period, frequent switching will increase the circuit complexity and power consumption. Therefore, using a low-frequency run (that is, not switching the clock for a long time) can ensure the stability of clock switching.

[0078] In addition, in the embodiment of the present application, the random numbers in the random sequence itself have the statistical characteristics of the run distribution. Therefore, when using the run length of the random numbers as a regulation factor, by adjusting the run length of the random numbers, when the random clock generation device is used, it can control the switching frequency of the random clock according to needs (for example, if the security requirement is high, the length of the run can be adjusted to make the clock switching more random and frequent; if the device performance is poor, the length of the run can also be adjusted to reduce the switching frequency of the clock), and thus control the frequency distribution of the random clock, improving the uncontrollability of the random clock generation device during use caused by the too strong randomness of the random sequence. Thereby, the control effect on the random clock generation device is improved, enabling the performance of the random clock to be prospectively predicted and flexibly regulated, so as to minimize the potential impact of randomness on the system stability and reliability while ensuring randomness. And avoid the negative impact on the random clock generation device when using random numbers.

[0079] In addition, the present application can also be designed to be simple and efficient in design. It abandons complex hardware architectures and cumbersome software algorithms, and instead relies on a simple and effective principle: as long as the effectiveness of the random source is ensured (that is, it can continuously and stably generate high-quality random numbers or pseudo-random numbers), it can directly drive the system to generate the required random clock output. This design not only reduces the implementation cost, but also greatly simplifies the maintenance and upgrade processes, making the present application have extremely high practical value and promotion potential in various application scenarios that require random clock support. Figure 2 The structural schematic of a random clock generation device provided by an embodiment of the present application Figure 2 , as Figure 2 shown, in the embodiment of the present application, the selection and switching unit in the random clock generation device includes a first configurator and a selection and switching circuit; among them,

[0080] The first configurator is used to respond to a configuration operation, configure and detect the low-frequency sequence in the random sequence, and when detecting the low-frequency sequence, identify the clock number from the random sequence according to the low-frequency sequence;

[0081] A selection and switching circuit is used to select a corresponding clock according to the clock number identified from the random sequence to replace the current clock and become the master clock of the random clock generating device.

[0082] Among them, the first configurator may refer to a low-frequency run selection configuration unit, that is, a unit that can be used for users to configure low-frequency sequences. In the embodiments of the present application, the first configurator can configure low-frequency sequences in a software or hardware manner. For example, a pattern matcher can be preset through hardware logic (such as using an FPGA), and this matcher can be used to detect whether the input random sequence conforms to the pattern of "1{10 zeros}1". When the sequence of "1{10 zeros}1" is detected, the hardware logic will automatically trigger subsequent steps. For example, read the 4 bits immediately following as the clock number, and accordingly, the selection and switching circuit selects one of the 16 alternative clocks as the new master clock for switching. For example, it can also be implemented by writing program code. The software can continuously monitor the data stream from the random sequence generator and apply algorithms to find the pattern of "1{10 zeros}1". When this sequence is detected, the software can execute corresponding instructions, such as parsing the subsequent 4 bits and sending commands to the selection and switching circuit to select a new master clock.

[0083] The selection and switching circuit can be a master clock selection and switching circuit, and this circuit can include circuits such as a multiplexer (MUX), a combination of a register and a decoder, a state machine-controlled multiplexer, and a programmable logic device (PLD / FPGA).

[0084] In the random clock generating device provided by the embodiments of the present application, in view of the run distribution statistical characteristics inherent in the low-frequency sequence as a random number, by configuring low-frequency sequences with different run lengths through the first configurator, the frequency of the low-frequency sequence appearing in the random sequence can be adjusted. For example, when the run length of the low-frequency sequence is longer, the frequency of the low-frequency sequence appearing in the random sequence is lower; conversely, when the run length of the low-frequency sequence is shorter, the frequency of the low-frequency sequence appearing in the random sequence is higher. Thus, by adjusting the frequency of clock switching, clock switching under different factors such as different processing speeds, power consumption management, real-time requirements, and security considerations can be achieved.

[0085] In the related art, when a random clock generation device is in use, the clock signal output by its master clock itself is transmitted by flipping according to a fixed period. In this way, when facing a side-channel attack, since the clock signal transmitted by flipping according to a fixed period has strong regularity, therefore, the predictability of the power consumption characteristics and electromagnetic radiation pattern of its signal is relatively strong, resulting in an attacker being able to infer the internal operation state or sensitive information of the random clock generation device by analyzing these characteristics, reducing the defense effect when facing a side-channel attack and increasing the risk of the random clock generation device. Therefore, in the embodiments of the present application, in order to make the clock signal transmitted by the random clock generation device more difficult to predict, thereby further improving the defense effect of the random clock generation device against side-channel attacks, the random clock generation device in the embodiments of the present application can perform a gating operation on the clock signal, so that the output clock signal becomes difficult to be used for attack due to lack of regularity. That is:

[0086] Figure 3 is a schematic structural diagram of a random clock generation device provided by an embodiment of the present application Figure 3 , such as Figure 3 shown, the random clock generation device may further include a gating unit, and the gating unit is respectively connected to the random sequence generator and the selection and switching unit;

[0087] The gating unit is configured to perform a gating operation on the master clock connected to the selection and switching unit when detecting a set high-frequency sequence in the random sequence, and the gating operation is used to prevent the random clock signal output by the master clock from performing a clock transition.

[0088] Among them, a clock transition may refer to the process in which a clock signal changes from a low level to a high level (rising edge) or from a high level to a low level (falling edge) within one period. Among them, when the clock is in use, it usually flips along a fixed period, so the output signal is usually vulnerable to side-channel attacks, thus affecting the use of the random clock generation device. By performing a gating operation on the master clock in the embodiments of the present application, the clock can be effectively controlled to be turned on or off. Thereby, the predictability of the power consumption characteristics and electromagnetic radiation pattern of the random clock generation device during the encryption operation can be effectively reduced.

[0089] The random clock generating device provided by the embodiment of the present application adjusts the gating period through gating operation, and further adjusts the random clock signal output by the random clock generating device. Among them, the gating period refers to the period during which the clock signal is turned off within a specific time period, that is, no clock flip occurs within this period, while clock flip can occur during the non-gating period. The gating period can be determined according to the gating operation. Gating can frequently control the clock behavior of a single period to improve the randomness and flexibility of the system. In order to further effectively reduce the power consumption characteristics and the predictability of the electromagnetic radiation pattern of the random clock generating device during the encryption operation, a high-frequency sequence is adopted in the embodiment of the present application for gating operation. So that when the clock signal is output, the gating period can be adjusted according to the high-frequency sequence appearing in the random sequence. For example, when the run length of the high-frequency sequence is less, the gating operation can be more frequent.

[0090] Figure 4 The structural schematic diagram of a random clock generating device provided by the embodiment of the present application Figure 4 , as Figure 4 shown, the gating unit in the random clock generating device includes an efficiency regulation circuit and a clock gating subunit. The random sequence generator is connected to the efficiency regulation circuit and the clock gating subunit, and the clock gating subunit is also connected to the selection and switching unit;

[0091] The efficiency regulation circuit is used to detect the high-frequency sequence in the random sequence and output a gating signal when detecting the high-frequency sequence in the random sequence;

[0092] The clock gating subunit is used to perform gating operation on the main clock connected to the selection and switching unit according to the gating signal.

[0093] Among them, the efficiency regulation circuit can refer to a unit that checks the high-frequency run length and outputs gating signals for different schemes of the main clock to achieve different clock efficiencies. The efficiency regulation circuit can be changed by hardware or software methods to generate a random clock suitable for the product performance. It can regulate and select sequences such as "101" or "010" with a length of 1, "1001" or "0110" with a length of 2,..., "1{N zeros}1" or "0{N ones}0" with a length of N, or select both "0" and "1" series at the same time.

[0094] The gating signal can refer to a signal used to turn on or off the gating operation of the main clock. The gating operation can temporarily turn on or off the transmission of the main clock signal through the gating signal, so as to achieve the purpose of adjusting the output clock frequency. For example, when a specific high-frequency sequence "10001" is detected, the gating unit will perform a gating operation on the main clock, that is, block the transmission of the main clock signal for a certain period of time, so that the output random clock signal has intermittent pauses. Thus, by controlling the length and frequency of gating, fine adjustment of the output clock signal frequency can be achieved.

[0095] The clock gating sub-unit can refer to a unit used to receive the gating signal and perform the gating operation. In the embodiment of the present application, the clock gating sub-unit can be a clock gating circuit, and the clock gating circuit can include an AND gate circuit, a D-type flip-flop (DFF), a transmission gate, a tristate buffer, a multiplexer (MUX), etc. Among them, when the clock gating circuit is a tristate buffer, the working process of the clock gating circuit can be: when the gating signal is a high-level signal, the tristate buffer outputs the main clock signal; when the gating signal is a low-level signal, the tristate buffer enters a high-impedance state, and the output is in a high-impedance state, thereby blocking the main clock signal.

[0096] Among them, in the embodiment of the present application, the gating unit further includes a second configurator, and the second configurator is connected to the efficiency regulation circuit;

[0097] The second configurator is used to configure the high-frequency sequence so that the efficiency regulation circuit can detect the high-frequency sequence in the random sequence.

[0098] Among them, the second configurator can refer to a unit used to configure the high-frequency sequence to detect the random sequence. For example, the high-frequency sequence configured by the second configurator can be the "10001" sequence. In the embodiment of the present application, the second configurator and the first configurator can be configuration units with the same structure and function but different usage purposes. Thus, when the efficiency regulation circuit detects the "10001" sequence, it can output a gating signal to the gating unit, where the efficiency regulation circuit can be a sequence detector to detect the high-frequency sequence.

[0099] In summary, through the combination of clock switching and gating period, the use effect of the random clock generating device in defending side-channel attacks is significantly improved.

[0100] Figure 5 For another structural schematic diagram of the random clock generating device provided by the embodiment of the present application, as Figure 5As shown in the figure, the random clock generation device includes: a frequency division circuit, a clock pool, a master clock selection and switching circuit, a random sequence generator, an efficiency regulation circuit, and a clock gating circuit. Among them, the usage process of the random clock generation device may include:

[0101] Using four clock sources, namely reference clock clk0, reference clock clk1, reference clock clk2, and reference clock clk3, the original reference clock and its 2-divided clock, 4-divided clock, and 8-divided clock of the four clocks are generated through the frequency division circuit, so as to form a clock pool of 16 alternative clocks.

[0102] The software or hardware configures the low-frequency run selection sequence "1{10 zeros}1". When the random sequence generator generates this random sequence, the subsequent 4 bits in the random sequence are used as the ID, and one of the 16 alternative clocks is selected as the master clock and the switching of the master clock is completed through the clock switching circuit.

[0103] The software or hardware configures the high-frequency run as the input for efficiency regulation. For example, the 0-run sequence "10001" with a length of 3 is selected as the regulation point. Each time the sequence "10001" is detected, a gating operation is performed on the master clock, and finally an adjustable random clock is output; alternatively, the 0-run sequence "100001" with a length of 4 can be selected as the regulation point. Each time the sequence "100001" is detected, a gating operation is performed on the master clock, and finally an adjustable random clock is output; the length of the low-frequency run is not limited here because low frequency and high frequency are relative. At the same time, the efficiency regulation circuit also retains the full-efficiency state without gating, and at this time the random clock is exactly the same as the master clock. The master clock selection and switching circuit also supports the direct selection of specific clocks. These functions can all support the output of stable alternative clocks and provide multiple clock scheme selections.

[0104] This random clock can combine low-frequency runs and high-frequency runs to achieve various predictable random clock outputs. When both the low-frequency run and the high-frequency run are adjusted to the highest frequency level, the randomness of the random clock is the highest at this time, but its efficiency will be halved. The influencing factors of the random clock efficiency can be clearly calculated. Among them:

[0105] 1. In the long run, the selection of the master clock for the low-frequency run will not affect the efficiency of the random clock because it only performs switching, the random expectation of the master clock remains unchanged, and the clock frequency is (clk0 + clk1 + clk2 + clk3) * (1 + 1 / 2 + 1 / 4 + 1 / 16) * (1 / 4) = (clk0 + clk1 + clk2 + clk3) * (29 / 64). After clarifying clk0 / 1 / 2 / 3, the current master clock status can be understood.

[0106] 2. Adjusting the efficiency of high-frequency runs for gating will affect the efficiency of the random clock. When selecting the "010" sequence with a number close to 1 / 4 as the gating point, the overall random clock efficiency will decrease by 1 / 4. Selecting other sequences can also obtain corresponding efficiency degradation evaluations.

[0107] Therefore, by determining the efficiency of the current random clock operation, that is, the main clock expectation * gating efficiency, and accelerating or decelerating through the efficiency adjustment of high-frequency runs, while maintaining randomness.

[0108] The embodiment of the present application also provides a cryptographic chip, which may include the random clock generating device in the embodiment of the present application.

[0109] The random clock generating device provided by the embodiment of the present application can generate a clock signal that is highly random at the microscopic level and exhibits statistical regularity characteristics macroscopically. Using this clock as the core working clock of the cryptographic chip can effectively disrupt the distribution patterns of sensitive information such as power consumption and radiation in the time domain, significantly enhance the defense ability against potential attackers, increase the cracking difficulty, and at the same time have an evaluation and optimization function, which can accurately measure the specific impact of the random clock on the system operation performance. While ensuring the stable operation of the system, it optimizes the working performance through intelligent regulation, achieving a dual guarantee of security and efficiency. Compared with the traditional random scheme, the random clock generating device provided by the embodiment of the present application shows significant advantages in the control of random output, can effectively avoid system instability problems caused by out-of-control randomness, and provides a more reliable and efficient solution for cryptographic chips and other application scenarios that require high-precision random clocks.

[0110] Figure 6 It is a flowchart of a clock signal output method provided by the embodiment of the present application. As Figure 6 shown, this method is applied to a random clock generating device, and the random clock generating device includes a selection and switching unit. This method includes:

[0111] S601. Detect whether a set low-frequency sequence appears in the random sequence, where the random sequence is generated by a random sequence generator in the random clock generating device;

[0112] S602. When the low-frequency sequence is detected, identify the clock number from the random sequence and select the corresponding clock to replace the current clock as the main clock of the random clock generating device. The main clock is used to output a clock signal controlled by the random sequence. Among them, when the low-frequency sequence in the random sequence is detected, the selection and switching unit determines the clock corresponding to the clock number from the clock pool, and switches the clock corresponding to the bit as the main clock of the random clock generating device, and outputting the corresponding random clock signal may further include:

[0113] The first configurator in the selection switching unit configures the low-frequency sequence, and determines the target bit when detecting the low-frequency sequence in the random sequence;

[0114] The selection switching circuit in the selection switching unit determines the clock corresponding to the target bit from the clock pool, and switches the clock corresponding to the bit as the main clock of the random clock generating device to output the corresponding random clock signal.

[0115] Figure 7 It is a schematic flowchart of another clock signal output method provided by an embodiment of the present application. As Figure 7 shown, this method is applied to a random clock generating device, and the random clock generating device includes a gating unit. This method includes:

[0116] S701. When detecting the set high-frequency sequence in the random sequence, perform a gating operation on the main clock connected to the selection switching unit. The gating operation is used to prevent the random clock signal output by the main clock from performing clock flipping.

[0117] Among them, the random clock generating device includes a gating unit, and the gating unit includes a clock gating subunit, a second configurator, and an efficiency regulation circuit. In the embodiment of the present application, when the gating unit detects the high-frequency sequence in the random sequence, performing a gating operation on the main clock so that the main clock outputs the corresponding random clock signal may include:

[0118] The second configurator configures the high-frequency sequence and detects the high-frequency sequence in the random sequence;

[0119] When the efficiency regulation circuit detects the high-frequency sequence in the random sequence, it sends a gating signal to the clock gating subunit;

[0120] When the clock gating subunit receives the gating signal, it performs a gating operation on the main clock to prevent the random clock signal output by the main clock from performing clock flipping.

[0121] One clock signal output method and another clock signal output method provided by this embodiment can be used in the above-mentioned random clock generating device. Their implementation principles and technical effects are similar, and will not be elaborated here in this embodiment.

[0122] Figure 8 It is a schematic structural diagram of a clock signal output device provided by an embodiment of the present application. As Figure 8 shown, the clock signal output device 80 provided in this embodiment includes:

[0123] An identification module 801, configured to detect the low-frequency sequence in the random sequence and identify the clock number to be pre-switched from the random sequence. The random sequence is generated by a random sequence generator in the random clock generating device;

[0124] A replacement module 802, configured to identify a clock number from a random sequence when a low-frequency sequence is detected, and select a corresponding clock to replace the current clock to become the master clock of the random clock generating device, where the master clock is used to output a clock signal controlled by the random sequence.

[0125] In a possible implementation manner, the replacement module 802 may further be specifically configured to:

[0126] In response to a configuration operation, configure and detect a low-frequency sequence in the random sequence, and when the low-frequency sequence is detected, determine a target bit from the random sequence according to the low-frequency sequence;

[0127] According to the target bit, select a clock from the clock pool that has a mapping relationship with the target bit, and switch the clock that has a mapping relationship with the target bit to be the master clock of the random clock generating device.

[0128] In a possible implementation manner, the replacement module 802 may further be specifically configured to:

[0129] When a high-frequency sequence in the random sequence is detected, perform a gating operation on the master clock connected to the selection switching unit, where the gating operation is used to prevent the random clock signal output by the master clock from performing a clock flip.

[0130] In a possible implementation manner, the replacement module 802 may further be specifically configured to:

[0131] Detect a high-frequency sequence in the random sequence, and when the high-frequency sequence in the random sequence is detected, output a gating signal;

[0132] According to the gating signal, perform a gating operation on the master clock connected to the selection switching unit.

[0133] In a possible implementation manner, the replacement module 802 may further be specifically configured to:

[0134] Configure a high-frequency sequence so that the efficiency regulation circuit detects a high-frequency sequence in the random sequence.

[0135] The clock signal output device provided in this embodiment may execute the method provided in the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here in this embodiment.

[0136] Figure 9 It is a schematic structural diagram of an electronic device provided in an embodiment of the present application. As Figure 9 shown, the electronic device 90 provided in this embodiment includes: at least one processor 901 and a memory 902. Optionally, the electronic device 90 further includes a communication component 903. Among them, the processor 901, the memory 902, and the communication component 903 are connected through a bus.

[0137] In a specific implementation process, at least one processor 901 executes computer-executable instructions stored in a memory 902, so that at least one processor 901 executes the above-mentioned method.

[0138] For the specific implementation process of the processor 901, reference may be made to the above method embodiments. Their implementation principles and technical effects are similar, and will not be elaborated here in this embodiment.

[0139] In the above embodiments, it should be understood that the processor may be a central processing unit (Central Processing Unit, CPU for short), or other general-purpose processors, digital signal processors (Digital Signal Processor, DSP for short), application-specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in combination with the invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

[0140] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0141] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0142] This application also provides a computer program product, including a computer program, which when executed by a processor implements the above-mentioned method.

[0143] This application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When the processor executes the computer-executable instructions, the above-mentioned method is implemented.

[0144] The above-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible by a general-purpose or special-purpose computer.

[0145] An exemplary readable storage medium is coupled to the processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in a device.

[0146] The division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices, or units, and can be in electrical, mechanical, or other forms.

[0147] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, the functional units in various embodiments of the present invention can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0149] If a function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present invention. The foregoing storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs and other various media that can store program codes.

[0150] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When this program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium includes: ROMs, RAMs, magnetic disks, or optical discs and other various media that can store program codes.

[0151] Finally, it should be noted that: After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily think of other implementation manners of the present invention. The present invention is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include common general knowledge or conventional technical means in the technical field not disclosed in the present invention. It is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A random clock generating device, characterized in that The random clock generating device includes a random sequence generator, a selection and switching unit, and a clock pool. The clock pool and the random sequence generator are respectively connected to the selection and switching unit. Among them, the random sequence generator is used to generate a random sequence. The random sequence includes a low-frequency sequence and a high-frequency sequence. the selection and switching unit is used to select and switch the master clock of the random clock generating device, and to detect whether a set low-frequency sequence appears in the random sequence. When the low-frequency sequence is detected, according to the low-frequency sequence, a clock number is identified from the random sequence and the corresponding clock is selected to replace the current clock to become the master clock of the random clock generating device. Among them, the low-frequency sequence is a sequence whose run length is greater than the run length of the high-frequency sequence. The master clock is used to output a clock signal controlled by the random sequence.

2. The random clock generation device according to claim 1, wherein The clock number is determined according to a target bit, and the target bit is determined according to the position of the low-frequency sequence in the random sequence.

3. The random clock generating device according to claim 1, wherein The random clock generating device includes a reference clock and a frequency division circuit. The frequency division circuit is connected between the reference clock and the clock pool, and the clocks in the clock pool are obtained by the frequency division circuit dividing the reference clock.

4. The random clock generating device according to claim 1, wherein The selection and switching unit includes a first configurator and a selection and switching circuit. The first configurator is used to, in response to a configuration operation, configure and detect the low-frequency sequence in the random sequence, and when the low-frequency sequence is detected, identify the clock number from the random sequence according to the low-frequency sequence. The selection and switching circuit is used to select the corresponding clock to replace the current clock according to the clock number identified from the random sequence to become the master clock of the random clock generating device.

5. The random clock generating device according to any one of claims 1-4, characterized in that The appearance frequency of the low-frequency sequence in the random sequence is determined according to the run length of the low-frequency sequence.

6. The random clock generation device according to claim 1, wherein The random clock generating device further includes a gating unit. The gating unit is respectively connected to the random sequence generator and the selection and switching unit. The gating unit is used to, when a high-frequency sequence in the random sequence is detected, perform a gating operation on the master clock connected to the selection and switching unit. The gating operation is used to prevent the random clock signal output by the master clock from flipping.

7. The random clock generating device according to claim 6, wherein The gating unit includes an efficiency regulation circuit, a clock gating subunit, and a second configurator. The efficiency regulation circuit is respectively connected to the random sequence generator and the clock gating subunit. The clock gating subunit is connected to the selection and switching unit. The second configurator is connected to the efficiency regulation circuit. The second configurator is used to configure the high-frequency sequence. The efficiency regulation circuit is used to detect the high-frequency sequence set by the second configurator in the random sequence, and output a gating signal when the high-frequency sequence in the random sequence is detected. The clock gating subunit is used to perform a gating operation on the master clock connected to the selection and switching unit according to the gating signal.

8. The random clock generating device according to any one of claims 6-7, characterized in that, The appearance frequency of the high-frequency sequence in the random sequence is determined according to the run length of the high-frequency sequence.

9. A clock signal output method, characterized in that Applied to a random clock generating device, the random clock generating device includes a selection and switching unit, and the method includes: Detecting whether a set low-frequency sequence appears in the random sequence, wherein the random sequence is generated by a random sequence generator in the random clock generating device; the random sequence includes a low-frequency sequence and a high-frequency sequence; When the low-frequency sequence is detected, according to the low-frequency sequence, identifying a clock number from the random sequence and selecting a corresponding clock to replace the current clock to become the master clock of the random clock generating device, and the master clock is used to output a clock signal controlled by the random sequence; wherein, the low-frequency sequence is a sequence in the random sequence whose run length is greater than that of the high-frequency sequence.

10. The method according to claim 9, wherein The random clock generating device further includes a gating unit, and the method further includes: When a set high-frequency sequence in the random sequence is detected, performing a gating operation on the master clock connected to the selection and switching unit, and the gating operation is used to prevent the random clock signal output by the master clock from flipping the clock.

Images