Method for constructing hybrid mapping structure and related device

Abstract

The application relates to the technical field of data storage, and discloses a construction method of a hybrid mapping structure and related devices. The construction method of the hybrid mapping structure comprises the following steps: acquiring a mapping pair; judging whether a logical address is a continuous non-large-page alignment address according to a global bitmap table; if the logical address is not the continuous non-large-page alignment address, judging whether the continuity of a logical address segment corresponding to the logical address is greater than a continuity threshold; if the continuity of the logical address segment is greater than the continuity threshold, inserting the mapping pair into a compact array; and if the continuity of the logical address segment is less than or equal to the continuity threshold, inserting the mapping pair into a range bucket hash structure. The mapping pair is stored by using the hybrid mapping structure combining the global bitmap table, the compact array and the range hash bucket structure, so that the memory overhead of a flash memory device can be optimized, the memory can be saved in a pure sequential read-write scene, and the performance of the array can be maintained in a pure random read-write scene.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to the technical field of data storage, in particular to a construction method of a hybrid mapping structure and a related device. BACKGROUND

[0002] In a modern solid state disk (SSD), a logical address to physical address mapping table (L2P table) is an important component of a flash translation layer (FTL), which directly affects the read-write performance and occupies most of the memory resources of the SSD. In addition, the size of the mapping table increases with the increase of the flash capacity, but the physical space available for memory particles in the SSD is close to the limit. With the exponential increase of global data volume, the emergence of large-capacity QLC SSD, the contradiction of internal memory shortage of the SSD is increasingly prominent.

[0003] At present, in order to solve the problem of SSD memory shortage, there are two types of existing technical solutions: the first type is the most widely used array-based mapping table, the subscript of the array represents the logical address (LPA) of the page, and the corresponding element value represents the physical address (PPA) of the page. This type of structure can save memory by adjusting the page size. If the array with 4K as a page is the traditional scheme, the performance is high, but the memory consumption is large; if the array with 16K as a page is called a large page scheme, the performance is low, and 75% of the memory can be saved. The second type is a structure that uses external storage to save the mapping table, including a selective index cache (DFTL) scheme that uses flash memory to store the mapping table, which stores part of the table in the memory of the SSD and the remaining mapping table in the flash memory or the host memory. Although this scheme can save memory, it has poor performance due to the involvement of flash page swapping. In summary, both of these two existing technical solutions cannot balance performance and memory overhead. SUMMARY

[0004] The embodiment of the present application provides a construction method of a hybrid mapping structure and a related device, which stores mapping pairs by using a hybrid mapping structure combining a global bitmap table, a compact array and a range hash bucket structure, can optimize the memory overhead of the flash device, and can save memory in a pure sequential read-write scenario and maintain the performance of the array in a pure random read-write scenario.

[0005] The embodiment of the present application provides the following technical solutions:

[0006] In a first aspect, the embodiment of the present application provides a construction method of a hybrid mapping structure, the hybrid mapping structure including a global bitmap table, a compact array and a range bucket hash structure, and the method includes:

[0007] Obtaining a mapping pair, wherein the mapping pair includes a logical address and a physical address corresponding to the logical address;

[0008] determining, according to the global bitmap table, whether the logical address is a continuous non-large page alignment address;

[0009] if the logical address is not the continuous non-large page alignment address, determining whether a continuity degree of a logical address segment corresponding to the logical address is greater than a continuity degree threshold;

[0010] if the continuity degree of the logical address segment is greater than the continuity degree threshold, inserting the mapping pair into the compact array;

[0011] if the continuity degree of the logical address segment is less than or equal to the continuity degree threshold, inserting the mapping pair into the range bucket hash structure.

[0012] In some embodiments, the global bitmap table is used to store metadata information corresponding to each logical address segment, the metadata information including the continuity degree, and the metadata information further including an allocation bitmap, the allocation bitmap being used to store a first state of the logical address, the first state including a mapping state and a non-mapping state, and the method further comprising:

[0013] determining, according to the allocation bitmap, whether the first state corresponding to the logical address is the mapping state;

[0014] if the first state corresponding to the logical address is the non-mapping state, modifying the first state corresponding to the logical address to the mapping state.

[0015] In some embodiments, the metadata information further includes a continuity bitmap, the continuity bitmap being used to store a second state of the logical address, the second state including a continuous state and a non-continuous state, and determining, according to the global bitmap table, whether the logical address is a continuous non-large page alignment address, comprising:

[0016] determining whether the logical address is a non-large page alignment address;

[0017] if the logical address is the non-large page alignment address, determining, according to the global bitmap table, whether the logical address is continuous with a logical address in the global bitmap table;

[0018] if the logical address is continuous with the logical address in the global bitmap table, determining the continuity bitmap corresponding to the logical address as the continuous state.

[0019] In some embodiments, the range bucket hash structure includes a global range table, a range bucket, and a range array, wherein the global range table is used to store a mapping pointer corresponding to a logical address segment, and inserting the mapping pair into the range bucket hash structure, comprising:

[0020] determining, according to the global range table, whether the mapping pointer corresponding to the logical address segment points to the range bucket;

[0021] if the mapping pointer corresponding to the logical address segment points to the range bucket, inserting the mapping pair into the range bucket;

[0022] If the mapping pointer corresponding to the logical address segment does not point to a range bucket, the mapping pair is inserted into the range array.

[0023] In some embodiments, after inserting the mapping pair into the range bucket, the method further comprises:

[0024] determining whether the capacity of the range bucket reaches a capacity threshold;

[0025] If the capacity of the range bucket reaches the capacity threshold, determining whether the contiguity of the range bucket is greater than a contiguity threshold;

[0026] If the contiguity of the range bucket is less than or equal to the contiguity threshold, determining whether the density of the range bucket is greater than a density threshold;

[0027] If the density of the range bucket is less than or equal to the density threshold, splitting the range bucket into at least two range buckets;

[0028] If the density of the range bucket is greater than the density threshold, splitting the range bucket into at least two range arrays.

[0029] In some embodiments, the method further comprises:

[0030] determining whether the contiguity of the compact array is less than or equal to a contiguity threshold;

[0031] If the contiguity of the compact array is less than the contiguity threshold, obtaining all mapping pairs in the compact array that have established mapping relationship;

[0032] inserting all mapping pairs that have established mapping relationship into the range bucket, and releasing the memory of the compact array to restore the compact array to the range bucket.

[0033] In some embodiments, after inserting the mapping pair into the range array, the method further comprises:

[0034] determining whether the density of the range array is less than a density threshold;

[0035] If the density of the range array is less than the density threshold, obtaining all mapping pairs in the range array;

[0036] inserting all mapping pairs in the range array into the range bucket, and releasing the memory of the range array to restore the range array to the range bucket.

[0037] In some embodiments, after inserting the mapping pair into the range bucket, the method further comprises:

[0038] determining whether there is a logical address segment in the range bucket whose contiguity is greater than a contiguity threshold;

[0039] If there is a logical address segment in the range bucket whose contiguity is greater than the contiguity threshold, obtaining the logical address segment and the mapping pair corresponding to the logical address segment;

[0040] Create a compact array for the logical address segments, and move the mapping pairs corresponding to the logical address segments from the range bucket to the compact array;

[0041] After moving the mapping pairs corresponding to the logical address segments from the range bucket to the compact array, if the density of the range bucket is less than the density threshold, the range bucket is merged with the surrounding range buckets to form a new range bucket.

[0042] Secondly, embodiments of this application provide a physical address query method based on a hybrid mapping structure, wherein the hybrid mapping structure includes a global bitmap, a compact array, and a range bucket hash structure, and the method includes:

[0043] Get the logical address;

[0044] Based on the global bitmap, check whether a mapping relationship has been established for logical addresses;

[0045] If a mapping relationship has been established for logical addresses, then determine whether the logical addresses are consecutive;

[0046] If the logical addresses are consecutive, then traverse the global bitmap to obtain the starting logical address of the address segment corresponding to the logical address;

[0047] If the starting logical address is a big page aligned address, then the physical address corresponding to the logical address is obtained through a compact array;

[0048] If the logical addresses are not contiguous, the physical address corresponding to the logical address is obtained through the range bucket hash structure.

[0049] In some embodiments, the range bucket hash structure includes a global range table, range buckets, and a range array. The global range table stores mapping pointers corresponding to logical address segments. Obtaining the physical address corresponding to the logical address through the range bucket hash structure includes:

[0050] Based on the global range table, determine whether the mapping pointer corresponding to the logical address segment points to the range bucket;

[0051] If the mapping pointer corresponding to the logical address segment points to the range bucket, then the physical address corresponding to the logical address is obtained from the range bucket;

[0052] If the mapping pointer corresponding to the logical address segment does not point to the range bucket, then the physical address corresponding to the logical address is obtained from the range array.

[0053] In some embodiments, the metadata information includes an allocation bitmap, which stores a first state of a logical address. The first state includes a mapped state and a non-mapped state. Determining whether a mapping relationship has been established for the logical address includes:

[0054] According to the allocation bitmap, it is judged whether the first state corresponding to the logical address is a mapping state;

[0055] If the first state corresponding to the logical address is the mapping state, it is determined that the logical address has established a mapping relationship.

[0056] If the first state corresponding to the logical address is the non-mapping state, it is determined that the logical address has not established a mapping relationship, and a result of query failure is output.

[0057] In some embodiments, the metadata information further includes a continuous bitmap, the continuous bitmap is used to store a second state of the logical address, the second state includes a continuous state and a non-continuous state, and it is judged whether the logical address is continuous, including:

[0058] According to the continuous bitmap, it is judged whether the second state corresponding to the logical address is the continuous state.

[0059] If the second state corresponding to the logical address is the continuous state, the logical address is determined as a continuous logical address.

[0060] If the second state corresponding to the logical address is the non-continuous state, the logical address is determined as a non-continuous logical address.

[0061] In some embodiments, before the physical address corresponding to the logical address is obtained through the compact array, the method further includes:

[0062] It is judged whether the address segment has established the compact array.

[0063] If the address segment has established the compact array, the physical address corresponding to the logical address is obtained through the compact array.

[0064] If the address segment has not established the compact array, the physical address corresponding to the logical address is obtained through the range bucket hash structure.

[0065] In a third aspect, an embodiment of the present application provides a flash memory device controller, including:

[0066] at least one processor; and

[0067] a memory connected in communication with the at least one processor; wherein

[0068] the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the construction method of the hybrid mapping structure as in the first aspect, or the physical address query method based on the hybrid mapping structure as in the second aspect.

[0069] In a fourth aspect, an embodiment of the present application provides a flash memory device, including:

[0070] A flash memory device controller as claimed in the third aspect;

[0071] At least one flash memory medium in communication connection with the flash memory device controller.

[0072] The application embodiment has the beneficial effect that: different from the prior art, the application embodiment provides a construction method of a hybrid mapping structure, the hybrid mapping structure includes a global bitmap table, a compact array, and a range bucket hash structure, and the method includes: obtaining a mapping pair, wherein the mapping pair includes a logical address and a physical address corresponding to the logical address; determining whether the logical address is a continuous non-large page alignment address according to the global bitmap table; if the logical address is not a continuous non-large page alignment address, determining whether a continuity degree of a logical address segment corresponding to the logical address is greater than a continuity degree threshold; if the continuity degree of the logical address segment is greater than the continuity degree threshold, inserting the mapping pair into the compact array; and if the continuity degree of the logical address segment is less than or equal to the continuity degree threshold, inserting the mapping pair into the range bucket hash structure. The application can store the mapping pair by using the hybrid mapping structure combined with the global bitmap table, the compact array, and the range hash bucket structure, can optimize the memory overhead of the flash memory device, and can save memory in a pure sequential read-write scenario and maintain the performance of the array in a pure random read-write scenario. BRIEF DESCRIPTION OF DRAWINGS

[0073] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are schematic and not intended to be limiting of the embodiments, and in which like reference numerals designate similar items in the figures, in which: the drawings do not limit the proportion.

[0074] Figure 1 is a structure schematic diagram of a hybrid mapping structure provided by the application embodiment;

[0075] Figure 2 is a relationship schematic diagram of a range hash bucket structure provided by the application embodiment;

[0076] Figure 3 is a flow schematic diagram of a construction method of a hybrid mapping structure provided by the application embodiment;

[0077] Figure 4 is a flow schematic diagram of a method for determining whether a first state corresponding to a logical address is a mapping state provided by the application embodiment;

[0078] Figure 5 is a flow schematic diagram of a method for determining whether a logical address is a continuous non-large page alignment address provided by the application embodiment;

[0079] Figure 6 is Figure 3 is a refinement flow schematic diagram of step S305 in

[0080] Figure 7 This is a flowchart illustrating a process for determining whether the capacity of a range bucket has reached a capacity threshold, provided in an embodiment of this application.

[0081] Figure 8 This is a flowchart illustrating a method for determining whether the continuity of a compact array is less than or equal to a continuity threshold, provided in an embodiment of this application.

[0082] Figure 9 This is a flowchart illustrating a method for determining whether the density of a range array is less than a density threshold, provided in an embodiment of this application.

[0083] Figure 10 This is a flowchart illustrating a process for determining whether a logical address segment in a range bucket has a continuity greater than a continuity threshold, as provided in an embodiment of this application.

[0084] Figure 11 This is a schematic diagram of the overall process of constructing a hybrid mapping structure according to an embodiment of this application;

[0085] Figure 12 This is a flowchart illustrating a physical address query method based on a hybrid mapping structure provided in an embodiment of this application;

[0086] Figure 13 yes Figure 12 A detailed flowchart of step S1202 in the process;

[0087] Figure 14 yes Figure 12 A detailed flowchart of step S1204 in the process;

[0088] Figure 15 yes Figure 12 A detailed flowchart of step S1205 in the process;

[0089] Figure 16 This is a flowchart illustrating a method for determining whether a compact array has been established for an address segment, as provided in an embodiment of this application.

[0090] Figure 17 This is a schematic diagram of the overall process of a physical address query method based on a hybrid mapping structure provided in an embodiment of this application;

[0091] Figure 18 This is a schematic diagram of the structure of a flash memory controller provided in an embodiment of this application;

[0092] Figure 19 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application.

[0093] Explanation of icon numbers:

[0094] Reference Name Reference Name 100 Flash memory device 200 Host 110 Flash memory media 180 Flash memory device controller 181 Processor 182 Memory DETAILED DESCRIPTION

[0095] The technical solutions of the present application are specifically described below in combination with the accompanying drawings of the specification:

[0096] Referring to Figure 1 , Figure 1 is a structure diagram of a hybrid mapping structure provided by an embodiment of the present application;

[0097] As Figure 1 shown, the hybrid mapping structure is stored in the memory space of the flash device, and the hybrid mapping structure includes a global bitmap table, a compact array, and a range bucket hash table (RBHT, Range Bucket Hash Table), wherein the range hash bucket structure includes a global range table (GRT, Global Range Table), a range bucket (RB, Range Bucket), and a range array (RA, Range Array). In some embodiments, the range array structure in the range hash bucket structure is exchanged to the host memory when the SSD memory is short, and the remaining array storage structures are located inside the SSD. It can be understood that the global bitmap table, the compact array, and the range bucket hash table three structures can exist at the same time and can be converted to each other according to the load condition, thereby dynamically adjusting the proportion of each data storage structure. By using the hybrid mapping structure combined with the global bitmap table, the compact array, and the range hash bucket structure three data structures to store the mapping pair, the present application can optimize the memory overhead of the flash device, save memory in the pure sequential read-write scenario, and maintain the performance of the array in the pure random read-write scenario.

[0098] Referring to Figure 2 , Figure 2 is a relationship diagram of a range hash bucket structure provided by an embodiment of the present application;

[0099] As Figure 2As shown, the global bitmap table includes metadata information, and is composed of a plurality of address segments, each corresponding to a continuity degree, each address segment including a plurality of logical addresses. The application will dynamically convert the mapping table according to the continuity degree, and each mapping table structure dynamically occupies memory. Each address segment stores its mapping table address through a pointer. Each logical address corresponds to a continuous bitmap and an allocation bitmap. The allocation bitmap represents whether each logical address has established a mapping relationship with a physical address. Querying the allocation bitmap in advance can avoid the time delay caused by mapping table query failure. The continuity degree refers to the total number of continuous bitmaps in each address segment. If the continuity degree is greater than a continuity degree threshold, it means that the address segment has good continuity, and a compact array should be selected for mapping. If the continuity degree is less than or equal to the continuity degree threshold, it means that the address segment has poor continuity, and a range bucket hash bucket structure should be selected for mapping. In the embodiment of the application, in order to facilitate the management of logical addresses, logical addresses with a fixed address length are set as address segments. The fixed address length can be set according to actual needs, for example, the address length is set to 4096. In some embodiments, in order to avoid too long forward lookup, the application will combine every 8 logical addresses LPA into a group, and the bits of the 8-byte aligned address are fixedly set to 0. The physical address PPA of the 8-byte aligned address is recorded by the compact array, and only 1 / 8 of the mapping table entries need to be recorded, saving memory space.

[0100] The compact array is divided into a plurality of arrays according to the size of the address segment. When the address segment length is 4096, the compact array table entry has 512, each table entry occupies 4 bytes, and a total of 2048 bytes. When building the compact array table, the FTL will apply for memory with a size of 2KB per block. When the continuity degree of the address segment drops below the threshold, the FTL will convert the compact array into a range bucket, and release the original memory.

[0101] The range bucket hash table is composed of a global range table, a range bucket and a range array. The global range table is used to record the mapping table address corresponding to each logical address range (logical address segment), and store the mapping pointer corresponding to the logical address segment. It should be noted that the range in the global range table is indefinite length, which dynamically changes according to the splitting and merging of the range bucket and the range array. The starting address of each range is stored in the global range table, and the starting address of the next range is also the termination address of the previous range. The range bucket is a hash table structure, and the range bucket has a fixed size and is used to store the mapping pair of the logical address LPA and the physical address PPA in the range, wherein the mapping pair is composed of two fields of LPA and PPA. Compared with the array structure, the range bucket is more suitable for storing sparse mapping pairs. When the density of the range bucket reaches the upper limit of the range bucket for storing mapping pairs, that is, the capacity of the range bucket reaches the capacity threshold, the range bucket will be split, and according to the actual situation, the range bucket can be split into two range buckets, or multiple range arrays, or a combination of range arrays and range buckets. The range array is a fixed-length array, which is organized according to the structure of the traditional array scheme and stores the PPA of a range. The base address of each range array is recorded in the global range table, and when the number of valid mappings in the range array decreases, it will be converted into a range bucket. Compared with the range bucket, the insertion and query performance of the range array is higher, and it is more suitable to be placed in the host memory. In some embodiments, due to the possibility of hash collision in range bucket query, linear probing may cause multiple memory accesses. The range array only needs one memory access to obtain the PPA, and placing it in the host memory can reduce the number of PCIe requests, so in some embodiments, when a large number of range arrays are generated in a random scenario, the application reduces the memory pressure of the SSD by placing the range arrays in the host memory.

[0102] Please refer to Figure 3 , Figure 3 is a flowchart of a construction method of a hybrid mapping structure provided in an embodiment of the present application;

[0103] In an embodiment of the present application, the hybrid mapping structure includes a global bitmap table, a compact array and a range bucket hash structure, wherein the global bitmap table is used to store the metadata information corresponding to each logical address segment, the metadata information includes continuity, the compact array is used to store the logical address and the physical address corresponding to the logical address which have a continuity greater than a continuity threshold and are large page aligned, and the range bucket hash structure is used to store the logical address and the physical address corresponding to the logical address which are not stored in the compact array.

[0104] As shown in Figure 3 , the flow of the construction method of the hybrid mapping structure includes:

[0105] Step S301: obtaining a mapping pair, wherein the mapping pair includes a logical address and a physical address corresponding to the logical address;

[0106] Specifically, a mapping pair needs to be inserted into the hybrid mapping structure, wherein the mapping pair includes a logical address and a physical address corresponding to the logical address, and it should be noted that a mapping relationship exists between the logical address and the physical address corresponding to the logical address.

[0107] In the embodiment of the present application, after the mapping pair is obtained, the mapping relationship between the logical address and the physical address in the mapping pair needs to be recorded in the allocation bitmap of the global bitmap table, so as to facilitate subsequent query of whether a mapping relationship exists between the logical address and the physical address through the global bitmap table, and improve the query efficiency of the physical address.

[0108] Please refer to Figure 4 , Figure 4 is a flowchart for judging whether the first state of the logical address corresponds to a mapping state provided by the embodiment of the present application;

[0109] Step S401: obtaining a global bitmap table;

[0110] Specifically, the global bitmap table is obtained, and the global bitmap table is used to store metadata information corresponding to each logical address segment, and the metadata information includes continuity, an allocation bitmap, and a continuity bitmap. In the embodiment of the present application, the allocation bitmap is used to store the first state of the logical address, wherein the first state includes a mapping state and a non-mapping state, the mapping state means that a mapping relationship has been established between the logical address and the physical address, and the non-mapping state means that no mapping relationship has been established between the logical address and the physical address. The continuity bitmap is used to store the second state of the logical address, wherein the second state includes a continuous state and a non-continuous state, the continuous state means that the current logical address is continuous with a certain logical address recorded in the global bitmap table, and the non-continuous state means that there is no certain logical address in the global bitmap table that is continuous with the current logical address. The continuity is the total sum of the number of the continuous state corresponding to the logical address of a certain address segment. For example, a certain address segment includes 10 logical addresses, wherein the continuity bitmap of 6 logical addresses is in the continuous state, and the continuity bitmap of 4 logical addresses is in the non-continuous state, and then the continuity of the address segment is 6.

[0111] Step S402: judging whether the first state of the logical address corresponds to a mapping state according to the allocation bitmap;

[0112] Specifically, the allocation bitmap corresponding to the logical address is queried through the global bitmap table, and the first state corresponding to the logical address is obtained, and then it is judged whether the first state of the logical address corresponds to a mapping state. If the first state of the logical address is a non-mapping state, step S403 is entered. If the first state of the logical address is a mapping state, step S404 is entered.

[0113] Step S403: modifying the first state corresponding to the logical address to a mapping state;

[0114] Specifically, if the first state corresponding to the logical address is the non-mapping state, it indicates that the mapping relationship between the logical address and the physical address has not been recorded in the global bitmap table, that is, the first state of the logical address is the non-mapping state, the allocation bitmap in the global bitmap table is modified, the first state corresponding to the logical address is modified to the mapping state, for example, assuming that the mapping state is 1 and the non-mapping state is 0, the first state is modified from 0 to 1, so as to record the mapping relationship between the logical address and the physical address in the global bitmap table. After the first state corresponding to the logical address is modified to the mapping state, step S404 is entered.

[0115] Step S404: inserting the mapping pair into the hybrid mapping structure;

[0116] Specifically, if the first state corresponding to the logical address is the mapping state, it indicates that the mapping relationship between the logical address and the physical address has been recorded in the global bitmap table, the mapping pair is inserted into the hybrid mapping structure according to steps S302 to S306.

[0117] Please refer to Figure 5 , Figure 5 is a flowchart of judging whether a logical address is a continuous non-large page alignment address provided by an embodiment of the present application;

[0118] As shown in Figure 5 , the flow of judging whether a logical address is a continuous non-large page alignment address includes:

[0119] Step S501: obtaining a logical address;

[0120] Specifically, according to the mapping pair, the logical address in the mapping pair is obtained.

[0121] Step S502: judging whether the logical address is a non-large page alignment address;

[0122] Specifically, it is judged whether the logical address is a non-large page alignment address. If the logical address is a non-large page alignment address, step S503 is entered. If the logical address is not a non-large page alignment address, step S504 is entered. In the embodiments of the present application, large page alignment (Large Page Al ignment) refers to allocating or mapping memory to a larger memory block than a standard page size (such as 4 KB). These larger memory blocks are usually referred to as large pages. A large page alignment address refers to a coarse-grained page, that is, a large page includes multiple 4 KB pages. Large page alignment can ensure that data can be continuously and efficiently read or written. For example, large page alignment can reduce the number of page table entries, thereby reducing memory occupancy and improving memory access speed, and reducing memory fragmentation, so that memory management is more efficient. A non-large page alignment address refers to a starting address of data that is not an integer multiple of the number of bytes of a data unit. A large page alignment address includes but is not limited to an 8-byte alignment address. A non-large page alignment address includes but is not limited to a non-8-byte alignment address. For example, if it is necessary to judge whether the logical address is an 8-byte alignment address, the logical address is divided by 8, and a remainder is obtained. If the remainder is not equal to 0, it indicates that the logical address is a non-8-byte alignment address. If the remainder is equal to 0, it indicates that the logical address is an 8-byte alignment address.

[0123] Step S503: According to the global bitmap table, it is judged whether the logical address is continuous with the logical address in the global bitmap table.

[0124] Specifically, if the logical address is a non-large page alignment address, it is judged according to the global bitmap table whether the logical address is continuous with the logical address in the global bitmap table. The global bitmap table includes a continuous bitmap. The continuous bitmap includes a second state. The second state includes a continuous state and a non-continuous state. If the logical address is continuous with the logical address in the global bitmap table, the continuous bitmap corresponding to the logical address is determined as the continuous state, and step S505 is entered. If the logical address is not continuous with the logical address in the global bitmap table, the continuous bitmap corresponding to the logical address is determined as the non-continuous state, and step S504 is entered.

[0125] Step S504: It is judged whether the continuity degree of the logical address segment corresponding to the logical address is greater than a continuity degree threshold.

[0126] Specifically, when the logical address is a large page alignment address, or the logical address is not continuous with the logical address in the global bitmap table, it is determined whether the continuity of the logical address segment corresponding to the logical address is greater than a continuity threshold, where the continuity refers to the total number of continuous states in the address segment corresponding to the logical address, if the continuity of the logical address segment corresponding to the logical address is greater than the continuity threshold, step S506 is entered; if the continuity of the logical address segment corresponding to the logical address is less than or equal to the continuity threshold, step S507 is entered; in the embodiment of the present application, the continuity threshold can be set according to actual needs, for example, the continuity threshold is set to 7, assuming that the address segment corresponding to the logical address contains 10 logical addresses, of which 8 logical addresses have continuous bitmaps in the continuous state, and 2 logical addresses have non-continuous bitmaps, the continuity of the address segment is 8, that is, it is determined that the continuity of the address segment is greater than the continuity threshold.

[0127] Step S505: determining the continuous bitmap corresponding to the logical address as a continuous state;

[0128] Specifically, if the logical address is a non-large page alignment address, and the logical address is continuous with the logical address in the global bitmap table, that is, the logical address is a continuous non-large page alignment address, the continuous bitmap corresponding to the logical address is determined as a continuous state, which represents that the logical address is continuous with the previous logical address. In the embodiment of the present application, the logical address does not need to be stored in the memory space, but the continuous bitmap in the global bitmap table can be used to determine whether the current logical address is continuous with the previous logical address. It can be understood that for continuous addresses, the present application only needs to record the starting address of each address segment in the global bitmap table, and record the second state of other addresses to the continuous bitmap. Based on the continuity of the address, when the logical address is continuous, only the physical address of the previous address needs to be known in the process of querying the physical address, and the physical address corresponding to the current logical address can be obtained by adding 1, that is, the compression of the memory can be realized. Compared with storing all logical addresses in the memory space, this method can save the memory space of the flash device, and can improve the query efficiency of the physical address.

[0129] Step S506: inserting the mapping pair into the compact array;

[0130] Specifically, if the continuity of the logical address segment corresponding to the logical address is greater than the continuity threshold, the mapping pair corresponding to the logical address is inserted into the compact array to construct the compact array.

[0131] Step S507: inserting the mapping pair into the range hash bucket structure;

[0132] Specifically, if the continuity of the logical address segment corresponding to the logical address is less than or equal to the continuity threshold, the mapping pair corresponding to the logical address is inserted into the range hash bucket structure to construct the range hash bucket structure.

[0133] Step S302: According to the global bitmap table, it is judged whether the logical address is a continuous non-large page alignment address.

[0134] Specifically, the non-large page alignment address includes a non-8-byte alignment address. According to the global bitmap table, the first state corresponding to the logical address is obtained, and the logical address is divided by 8 and the remainder is taken. If the first state corresponding to the logical address is the continuous state, and the remainder corresponding to the logical address is not equal to 0, it is determined that the logical address is a continuous non-large page alignment address, and then step S303 is entered. Otherwise, it is determined that the logical address is not a continuous non-large page alignment address, and then step S304 is entered.

[0135] Step S303: Modify the global bitmap table to record the logical address in the global bitmap table.

[0136] Specifically, if the logical address is a continuous non-large page alignment address, the global bitmap table is modified, and the second state corresponding to the logical address is modified to the continuous state to record the logical address in the global bitmap table.

[0137] Step S304: It is judged whether the continuity of the logical address segment corresponding to the logical address is greater than a preset threshold.

[0138] Specifically, it is judged whether the continuity of the logical address segment corresponding to the logical address is greater than the continuity threshold, wherein the continuity refers to the total number of continuous states in the address segment corresponding to the logical address. If the continuity of the logical address segment corresponding to the logical address is greater than the continuity threshold, step S306 is entered. If the continuity of the logical address segment corresponding to the logical address is less than or equal to the continuity threshold, step S305 is entered.

[0139] Step S305: Insert the mapping pair into the range bucket hash structure.

[0140] Specifically, please refer to Figure 6 , Figure 6 is Figure 3 the detailed flowchart of step S305 in

[0141] As shown in Figure 6 , step S305: Insert the mapping pair into the range bucket hash structure, which includes:

[0142] Step S351: Obtain the global range table.

[0143] Specifically, the range hash bucket structure includes a global range table, a range array and a range bucket, and the global range table is acquired, wherein the global range table is used to store a mapping pointer corresponding to a logical address segment, and the mapping pointer points to the range bucket or the range array.

[0144] Step S352: According to the global range table, it is judged whether the mapping pointer corresponding to the logical address segment points to the range bucket.

[0145] Specifically, according to the global range table, it is judged whether the mapping pointer corresponding to the logical address segment points to the range bucket, if the mapping pointer corresponding to the logical address segment points to the range bucket, step S354 is entered, and if the mapping pointer corresponding to the logical address segment points to the range array, step S353 is entered.

[0146] Step S353: Insert the mapping pair into the range array.

[0147] Specifically, if the mapping pointer corresponding to the logical address segment points to the range array, the mapping pair is inserted into the range array.

[0148] Step S354: Insert the mapping pair into the range bucket.

[0149] Specifically, if the mapping pointer corresponding to the logical address segment points to the range bucket, the mapping pair is inserted into the range bucket.

[0150] Step S306: Insert the mapping pair into the compact array.

[0151] Specifically, if the continuity of the logical address segment corresponding to the logical address is greater than the continuity threshold, the mapping pair is inserted into the compact array.

[0152] Please refer to Figure 7 , Figure 7 is a flowchart provided by the embodiment of the application for judging whether the capacity of the range bucket reaches the capacity threshold;

[0153] As shown in Figure 7 , the flow of judging whether the capacity of the range bucket reaches the capacity threshold includes:

[0154] Step S701: After the mapping pair is inserted into the range bucket, the capacity of the range bucket is acquired.

[0155] Specifically, after the mapping pair is inserted into the range bucket, the capacity of the range bucket is acquired, wherein the capacity of the range bucket refers to the number of mapping pairs stored in the range bucket at present / the total number of mapping pairs that the range bucket can store at most.

[0156] Step S702: Judge whether the capacity of the range bucket reaches the capacity threshold.

[0157] Specifically, it is judged whether the capacity of the range bucket reaches a capacity threshold value. If the capacity of the range bucket reaches the capacity threshold value, step S704 is entered. If the capacity of the range bucket does not reach the capacity threshold value, step S703 is entered. In the embodiment of the present application, the capacity threshold value can be set according to actual needs. For example, the capacity threshold value is set to 95%.

[0158] Step S703: the range bucket is not split;

[0159] Specifically, if the capacity of the range bucket does not reach the capacity threshold value, it indicates that the current range bucket does not need to be split into other data storage structures in the present application. Therefore, the range bucket is not split.

[0160] Step S704: it is judged whether the continuity of the range bucket is greater than a continuity threshold value;

[0161] Specifically, if the capacity of the range bucket reaches the capacity threshold value, it is further judged whether the continuity of the range bucket is greater than the continuity threshold value. If the continuity of the range bucket is greater than the continuity threshold value, step S705 is entered. If the continuity of the range bucket is less than or equal to the continuity threshold value, step S706 is entered.

[0162] Step S705: the mapping pairs in the range bucket are moved to a compact array;

[0163] Specifically, if the continuity of the range bucket is greater than the continuity threshold value, the condition for constructing a compact array is met. All mapping pairs in the range bucket are obtained, the mapping pairs are moved to a compact array, and the memory space of the range bucket is released.

[0164] Step S706: it is judged whether the density of the range bucket is greater than a density threshold value;

[0165] Specifically, the density of the range bucket is obtained, where the density of the range bucket = the number of valid mapping pairs in the range bucket / the address range of the range bucket. It is judged whether the density of the range bucket is greater than the density threshold value. If the density of the range bucket is greater than the density threshold value, step S707 is entered. If the density of the range bucket is less than or equal to the density threshold value, step S708 is entered. In the embodiment of the present application, the density threshold value can be set according to actual needs. For example, the density threshold value is set to 50%.

[0166] Step S707: the range bucket is split into at least two compact arrays;

[0167] Specifically, if the density of the range bucket is greater than the density threshold value, the range bucket is split into at least two compact arrays.

[0168] Step S708: the range bucket is split into at least two range buckets;

[0169] Specifically, if the density of the range bucket is less than or equal to the density threshold, the range bucket is split into at least two range buckets.

[0170] In the embodiment of the present application, when the continuity of the address segment in the range bucket is lower than the continuity threshold, if the density of the range bucket is greater than the density threshold, it can be considered that the current mapping is under random write load. The present application adopts the range bucket to store the mapping pairs corresponding to the sparsely allocated address segment, and the range array to store the mapping under the random write load of dense allocation, wherein the sparsely allocated refers to the mapping pair with the density less than or equal to the density threshold, and the dense allocation refers to the mapping pair with the density greater than the density threshold. In the steps S701 to S708, the present application can adaptively change the storage structure of the data according to the capacity of the data structure or the density of the mapping pair, and realize the conversion among the range bucket, the range array and the compact array, thereby saving the memory space of the flash device and improving the memory utilization.

[0171] Please refer to Figure 8 , Figure 8 is a flowchart of judging whether the continuity of the compact array is less than or equal to the continuity threshold provided by the embodiment of the present application;

[0172] As shown in Figure 8 , the flow of judging whether the continuity of the compact array is less than or equal to the continuity threshold comprises:

[0173] Step S801: After inserting the mapping pair into the compact array, the continuity of the compact array is obtained;

[0174] Specifically, after inserting the mapping pair into the compact array, the continuity of the current compact array is obtained, wherein the continuity refers to the total number of the continuous states in the address segment corresponding to the compact array.

[0175] Step S802: Judge whether the continuity of the compact array is less than or equal to the continuity threshold;

[0176] Specifically, judge whether the continuity of the compact array is less than or equal to the continuity threshold. If the continuity of the compact array is less than or equal to the continuity threshold, go to step S804; if the continuity of the compact array is greater than the continuity threshold, go to step S803.

[0177] Step S803: Do not process the compact array;

[0178] Specifically, if the continuity of the compact array is greater than the continuity threshold, it indicates that the continuity of the compact array meets the condition of constructing the compact array, and the compact array does not need to be converted into other data storage structure, and the compact array is not processed.

[0179] Step S804: obtaining all mapping pairs with established mapping relationship in the compact array;

[0180] Specifically, if the continuity degree of the compact array is less than or equal to the continuity degree threshold, it indicates that the current continuity degree of the compact array does not satisfy the condition for constructing the compact array, and all mapping pairs with established mapping relationship in the compact array are obtained so as to move the mapping pairs subsequently.

[0181] Step S805: inserting all mapping pairs with established mapping relationship into the range bucket, and releasing the memory of the compact array so as to restore the compact array to the range bucket;

[0182] Specifically, since the address segment of the compact array is considered to be converted from the sequential write load to the random write load when the continuity degree of the address segment is reduced due to the insertion of new mapping pairs, it is necessary to store the mapping pairs into the range bucket for storing the mapping of the random write load, that is, all mapping pairs with established mapping relationship are inserted into the range bucket, and the memory of the compact array is released so as to restore the compact array to the range bucket.

[0183] Please refer to Figure 9 , Figure 9 is a flowchart provided by an embodiment of the present application for judging whether the density of the range array is less than the density threshold;

[0184] As shown in Figure 9 , the flow of judging whether the density of the range array is less than the density threshold comprises:

[0185] Step S901: obtaining the density of the range array after inserting the mapping pair into the range array;

[0186] Specifically, the density of the range array is obtained after inserting the mapping pair into the range array, wherein the density of the range array = the number of valid mapping pairs / the range of the range array, and the valid mapping pair refers to the mapping pair with the first state being the mapping state.

[0187] Step S902: judging whether the density of the range array is less than the density threshold;

[0188] Specifically, whether the density of the range array is less than the density threshold is judged, if the density of the range array is less than the density threshold, step S904 is entered, and if the density of the range array is greater than or equal to the density threshold, step S903 is entered, wherein the density threshold can be set according to actual needs, for example, the density threshold is set to 50%.

[0189] Step S903: not processing the range array;

[0190] Specifically, if the density of the range array is greater than or equal to the density threshold, it indicates that the range array does not need to be converted into other data storage structures, and the range array is not processed.

[0191] Step S904: obtaining all mapping pairs in the range array;

[0192] Specifically, if the density of the range array is less than the density threshold, it indicates that the range array meets the condition of being converted into the range bucket, and all mapping pairs in the range array are obtained so as to subsequently move the mapping pairs in the range array to the range bucket.

[0193] Step S905: inserting all mapping pairs in the range array into the range bucket, and releasing the memory of the range array so as to restore the range array to the range bucket;

[0194] Specifically, since the range bucket is used to store the mapping pairs corresponding to the sparsely allocated address segment, and the range array is used to store the mappings of the densely allocated random write load, when the density of the range array is reduced to be lower than the density threshold, all mapping pairs in the range array need to be inserted into the range bucket, and the memory of the range array is released so as to restore the range array to the range bucket.

[0195] Please refer to Figure 10 , Figure 10 is a flowchart provided by an embodiment of the present application for judging whether there is a logical address segment in the range bucket whose continuity is greater than a continuity threshold;

[0196] As shown in Figure 10 , the flow of judging whether there is a logical address segment in the range bucket whose continuity is greater than a continuity threshold includes:

[0197] Step S1001: obtaining the continuity of the logical address segment in the range bucket after inserting the mapping pair into the range bucket;

[0198] Specifically, after inserting the mapping pair into the range bucket, the continuity of each logical address segment in the range bucket is obtained, wherein the continuity is the total sum of the number of continuous states corresponding to the logical addresses of the logical address segment.

[0199] Step S1002: judging whether there is a logical address segment in the range bucket whose continuity is greater than a continuity threshold;

[0200] Specifically, according to the continuity of each logical address segment in the range bucket, it is judged whether there is a logical address segment in the range bucket whose continuity is greater than a continuity threshold, if there is a logical address segment in the range bucket whose continuity is greater than a continuity threshold, step S1004 is entered; if there is no logical address segment in the range bucket whose continuity is greater than a continuity threshold, step S1003 is entered.

[0201] Step S1003: no processing is performed on the range bucket;

[0202] Specifically, if the continuity of a certain logical address segment in the range bucket is greater than the continuity threshold, it indicates that the range bucket does not need to be converted into other data storage structures, and no processing is performed on the range bucket.

[0203] Step S1004: obtaining a logical address segment and a mapping pair corresponding to the logical address segment;

[0204] Specifically, if the continuity of a certain logical address segment in the range bucket is greater than the continuity threshold, the logical address segment and a mapping pair corresponding to the logical address segment are obtained.

[0205] Step S1005: establishing a compact array for the logical address segment, and moving the mapping pair corresponding to the logical address segment from the range bucket to the compact array;

[0206] Specifically, since the continuity of the logical address segment in the current range bucket meets the condition for constructing a compact array, a compact array is established for the logical address segment, and the mapping pair corresponding to the logical address segment is moved from the range bucket to the compact array. After the moving is completed, the memory space occupied by the range bucket is released.

[0207] Step S1006: after the mapping pair corresponding to the logical address segment is moved from the range bucket to the compact array, it is determined whether the density of the range bucket is less than a density threshold;

[0208] Specifically, after the mapping pair corresponding to the logical address segment is moved from the range bucket to the compact array, the density of the range bucket needs to be further obtained to determine whether the density of the range bucket is less than a density threshold. If the density of the range bucket is less than the density threshold, step S1008 is entered. If the density of the range bucket is greater than or equal to the density threshold, step S1007 is entered. The density of the range bucket is equal to the total number of valid mapping pairs / the maximum capacity of the range bucket.

[0209] Step S1007: no processing is performed on the range bucket;

[0210] Specifically, if the density of the range bucket is greater than or equal to the density threshold, no processing is performed on the range bucket.

[0211] Step S1008: merging the range bucket and surrounding range buckets into a new range bucket;

[0212] Specifically, if the density of the range bucket is less than the density threshold, it indicates that the density of the current range bucket is too low, and the range bucket needs to be merged, i.e., the range bucket and surrounding range buckets are merged into a new range bucket.

[0213] Please refer to Figure 11 , Figure 11is a whole flow schematic diagram of a mixed mapping structure construction method provided by an embodiment of the present application;

[0214] As shown in the whole flow of the mixed mapping structure construction method, Figure 11

[0215] Step S1101: Obtain a mapping pair;

[0216] Specifically, a mapping pair that needs to be inserted into the mixed mapping structure is obtained, wherein the mapping pair includes a logical address and a physical address corresponding to the logical address. It should be noted that a mapping relationship exists between the logical address and the physical address corresponding to the logical address.

[0217] Step S1101: Determine whether the first state corresponding to the logical address is a mapping state according to the allocation bitmap;

[0218] Specifically, the allocation bitmap corresponding to the logical address is queried through the global bitmap table, and the first state corresponding to the logical address is obtained, and then it is determined whether the first state corresponding to the logical address is a mapping state. If the first state corresponding to the logical address is a non-mapping state, step S1103 is entered. If the first state corresponding to the logical address is a mapping state, step S1104 is entered.

[0219] Step S1103: Modify the first state corresponding to the logical address to a mapping state;

[0220] Specifically, if the first state corresponding to the logical address is a non-mapping state, it indicates that the mapping relationship between the logical address and the physical address has not been recorded in the global bitmap table, that is, the current first state of the logical address is a non-mapping state. Therefore, the allocation bitmap in the global bitmap table is modified, the first state corresponding to the logical address is modified to a mapping state, for example, assuming that the mapping state is 1 and the non-mapping state is 0, the first state is modified from 0 to 1, so as to record the mapping relationship between the logical address and the physical address in the global bitmap table. After the first state corresponding to the logical address is modified to a mapping state, step S1104 is entered.

[0221] Step S1104: Determine whether the logical address is a continuous non-large page alignment address;

[0222] Specifically, it is determined whether the logical address is a continuous non-large page alignment address. If the logical address is a continuous non-large page alignment address, step S1105 is entered. If the logical address is not a continuous non-large page alignment address, step S1106 is entered.

[0223] Step S1105: Modify the continuous bitmap corresponding to the logical address to a continuous state;

[0224] ​Specifically, if the logical address is a continuous non-large page alignment address, the continuous bitmap corresponding to the logical address is determined as a continuous state, representing that the logical address is continuous with the previous logical address.

[0225] Step S1106: judging whether the address segment corresponding to the logical address has established a compact array;

[0226] Specifically, if the logical address is not a continuous non-large page alignment address, it is judged whether the address segment corresponding to the logical address has established a compact array. If the address segment corresponding to the logical address has established a compact array, step S1107 is entered. If the address segment corresponding to the logical address has not established a compact array, step S1108 is entered.

[0227] Step S1107: inserting the mapping pair into the compact array;

[0228] Specifically, if the address segment corresponding to the logical address has established a compact array, the mapping pair is directly inserted into the compact array corresponding to the logical address.

[0229] Step S1108: judging whether the continuity of the address segment corresponding to the logical address is greater than a continuity threshold;

[0230] Specifically, if the address segment corresponding to the logical address has not established a compact array, it is judged whether the continuity of the address segment corresponding to the logical address is greater than a continuity threshold. If the continuity of the address segment corresponding to the logical address is greater than the continuity threshold, step S1109 is entered. If the continuity of the address segment corresponding to the logical address is less than or equal to the continuity threshold, step S1110 is entered.

[0231] Step S1109: establishing a compact array for the address segment corresponding to the logical address, and inserting the mapping pair into the compact array;

[0232] Specifically, if the continuity of the address segment corresponding to the logical address is greater than the continuity threshold, a compact array is established for the address segment corresponding to the logical address, and the mapping pair is inserted into the compact array.

[0233] Step S1110: judging whether the mapping pointer corresponding to the logical address segment points to a range bucket according to the global range table;

[0234] Specifically, if the continuity of the address segment corresponding to the logical address is less than or equal to the continuity threshold, it is judged whether the mapping pointer corresponding to the logical address segment points to a range bucket according to the global range table. If the mapping pointer corresponding to the logical address segment points to a range bucket, step S1112 is entered. If the mapping pointer corresponding to the logical address segment does not point to a range bucket, step S1111 is entered.

[0235] Step S1111: inserting the mapping pair into the range array;

[0236] Specifically, if the mapping pointer corresponding to the logical address segment does not point to the range bucket, the mapping pair is inserted into the range array.

[0237] Step S1112: Insert the mapping pair into the range bucket.

[0238] Specifically, if the mapping pointer corresponding to the logical address segment points to the range bucket, the mapping pair is inserted into the range bucket.

[0239] Step S1113: Determine whether the capacity of the range bucket is greater than the capacity threshold.

[0240] Specifically, after the mapping pair is inserted into the range bucket, it is determined whether the capacity of the range bucket is greater than the capacity threshold. If the capacity of the range bucket is greater than the capacity threshold, step S1114 is entered. If the capacity of the range bucket is less than or equal to the capacity threshold, it indicates that the insertion of the mapping pair is completed.

[0241] Step S1114: Determine whether the continuity of the range bucket is greater than the continuity threshold.

[0242] Specifically, if the capacity of the range bucket is greater than the capacity threshold, it is further determined whether the continuity of the range bucket is greater than the continuity threshold. If the continuity of the range bucket is greater than the continuity threshold, step S1115 is entered. If the continuity of the range bucket is less than or equal to the continuity threshold, step S1116 is entered.

[0243] Step S1115: Establish a compact array for the logical address segment, and move the mapping pair corresponding to the logical address segment from the range bucket to the compact array.

[0244] Specifically, if the continuity of the range bucket is greater than the continuity threshold, a compact array is established for the logical address segment, and the mapping pair corresponding to the logical address segment is moved from the range bucket to the compact array corresponding to the logical address segment.

[0245] Step S1116: Determine whether the density of the range bucket is greater than the density threshold.

[0246] Specifically, if the continuity of the range bucket is less than or equal to the continuity threshold, it is further determined whether the density of the range bucket is greater than the density threshold. If the density of the range bucket is greater than the density threshold, step S1117 is entered. If the density of the range bucket is less than or equal to the density threshold, step S1118 is entered.

[0247] Step S1117: Split the range bucket into a range array.

[0248] Specifically, if the density of the range bucket is greater than the density threshold, the range bucket is split into a range array.

[0249] Step S1118: Split the range bucket into two range buckets.

[0250] Specifically, if the density of the range bucket is less than or equal to the density threshold, the range bucket is split into two range buckets.

[0251] In the embodiment of the present application, a construction method of a hybrid mapping structure is provided, the hybrid mapping structure comprising a global bitmap table, a compact array and a range bucket hash structure, and the method comprises: obtaining a mapping pair, wherein the mapping pair comprises a logical address and a physical address corresponding to the logical address; judging whether the logical address is a continuous non-large page alignment address according to the global bitmap table; if the logical address is not a continuous non-large page alignment address, judging whether the continuity degree of a logical address segment corresponding to the logical address is greater than a continuity degree threshold; if the continuity degree of the logical address segment is greater than the continuity degree threshold, inserting the mapping pair into the compact array; and if the continuity degree of the logical address segment is less than or equal to the continuity degree threshold, inserting the mapping pair into the range bucket hash structure. The present application can store the mapping pair by using the hybrid mapping structure combining the global bitmap table, the compact array and the range hash bucket structure, can optimize the memory overhead of the flash device, and can save the memory in the pure sequential read-write scenario and maintain the performance of the array in the pure random read-write scenario.

[0252] Please refer to Figure 12 , Figure 12 is a flowchart of a physical address query method based on a hybrid mapping structure provided by the embodiment of the present application;

[0253] As Figure 12 shown, the flow of the physical address query method based on the hybrid mapping structure comprises:

[0254] Step S1201: obtaining a logical address;

[0255] Specifically, the logical address is obtained, and the logical address is used to query the corresponding physical address in the hybrid mapping structure.

[0256] Step S1202: querying whether a mapping relationship of the logical address has been established according to a global bitmap table;

[0257] Specifically, please refer to Figure 13 , Figure 13 is a detailed flowchart of step S1202 in Figure 12 ;

[0258] As Figure 13 shown, step S1202: querying whether a mapping relationship of the logical address has been established according to a global bitmap table, comprises:

[0259] Step S1221: querying an allocation bitmap in the global bitmap table to obtain a first state corresponding to the logical address;

[0260] Specifically, the hybrid mapping structure includes a global bitmap table, wherein the global bitmap table is configured to store metadata information corresponding to each logical address segment, and the metadata information includes an allocation bitmap; the allocation bitmap in the global bitmap table is queried to obtain a first state corresponding to the logical address, wherein the first state includes a mapping state and a non-mapping state.

[0261] Step S1222: determining, according to the allocation bitmap, whether the first state corresponding to the logical address is the mapping state.

[0262] Specifically, according to the allocation bitmap, it is determined whether the first state corresponding to the logical address is the mapping state, wherein the mapping state indicates that there is a mapping relationship between the logical address and the physical address corresponding to the logical address, and the non-mapping state indicates that there is no mapping relationship between the logical address and the physical address corresponding to the logical address. If the first state corresponding to the logical address is the mapping state, the step S1214 is entered; if the first state corresponding to the logical address is the non-mapping state, the step S1223 is entered.

[0263] Step S1223: determining that the logical address has not established a mapping relationship, and outputting a query failure result.

[0264] Specifically, if the first state corresponding to the logical address is the non-mapping state, it is determined that the logical address and the physical address have not established a mapping relationship, and a query failure result is outputted.

[0265] In the embodiment of the present application, the global bitmap table is used to query whether the logical address and the physical address have established a mapping relationship, when the logical address and the physical address have not established a mapping relationship, a query failure result is directly outputted, which can improve the query efficiency of the physical address, so as to avoid wasting a lot of time for querying when the logical address and the physical address have not established a mapping relationship.

[0266] Step S1214: determining that the logical address has established a mapping relationship.

[0267] Specifically, if the first state corresponding to the logical address is the mapping state, it is determined that the logical address and the physical address have established a mapping relationship, and the query steps S1204 to S1208 are continued to be executed.

[0268] Step S1203: determining that the logical address has not established a mapping relationship, and outputting a query failure result.

[0269] Specifically, if the first state corresponding to the logical address is the non-mapping state, it is determined that the logical address and the physical address have not established a mapping relationship, and a query failure result is outputted.

[0270] Step S1204: determining whether the logical address is continuous.

[0271] Specifically, please refer to Figure 14 , Figure 14 is Figure 12 the detailed flowchart of step S1204 in

[0272] As shown in Figure 14 , step S1204: judging whether the logical address is continuous, comprises:

[0273] Step S1241: querying the continuous bitmap in the global bitmap table to obtain the second state corresponding to the logical address;

[0274] Specifically, after determining that there is a mapping relationship between the logical address and the physical address through the allocation bitmap in the global bitmap table, the continuous bitmap in the global bitmap table is queried according to the global bitmap table to obtain the second state corresponding to the logical address, wherein the second state comprises a continuous state or a non-continuous state.

[0275] Step S1242: judging whether the second state corresponding to the logical address is the continuous state according to the continuous bitmap;

[0276] Specifically, whether the second state corresponding to the logical address is the continuous state is judged according to the continuous bitmap, if the second state corresponding to the logical address is the continuous state, step S1244 is entered; if the second state corresponding to the logical address is the non-continuous state, step S1243 is entered.

[0277] Step S1243: determining the logical address as the non-continuous logical address;

[0278] Specifically, if the second state corresponding to the logical address is the non-continuous state, it indicates that the logical address is not continuous with the previous logical address, and the logical address is determined as the non-continuous logical address.

[0279] Step S1244: determining the logical address as the continuous logical address;

[0280] Specifically, if the second state corresponding to the logical address is the continuous state, it indicates that the logical address is continuous with the previous logical address, and the logical address is determined as the continuous logical address.

[0281] Step S1205: obtaining the physical address corresponding to the logical address through the range bucket hash structure;

[0282] Specifically, please refer to Figure 15 , Figure 15 is Figure 12 the detailed flowchart of step S1205 in

[0283] As shown in Figure 15 , step S1205: obtaining the physical address corresponding to the logical address through the range bucket hash structure, comprises:

[0284] Step S1251: obtaining a global range table;

[0285] Specifically, the range hash bucket structure includes a global range table, a range array and a range bucket, and the global range table is obtained, wherein the global range table is used to store a mapping pointer corresponding to a logical address segment, and the mapping pointer points to the range bucket or the range array.

[0286] Step S1252: judging whether the mapping pointer corresponding to the logical address segment points to the range bucket according to the global range table;

[0287] Specifically, whether the mapping pointer corresponding to the logical address segment points to the range bucket is judged according to the global range table, if the mapping pointer corresponding to the logical address segment points to the range bucket, step S1254 is entered; if the mapping pointer corresponding to the logical address segment points to the range array, step S1253 is entered.

[0288] Step S1253: obtaining the physical address corresponding to the logical address in the range array;

[0289] Specifically, if the mapping pointer corresponding to the logical address segment points to the range array, it indicates that the physical address corresponding to the logical address is stored in the range array, and the physical address corresponding to the logical address is obtained in the range array.

[0290] Step S1254: obtaining the physical address corresponding to the logical address in the range bucket;

[0291] Specifically, if the mapping pointer corresponding to the logical address segment points to the range bucket, it indicates that the physical address corresponding to the logical address is stored in the range bucket, and the physical address corresponding to the logical address is obtained in the range bucket.

[0292] Step S1206: traversing the global bitmap table to obtain the starting logical address of the address segment corresponding to the logical address;

[0293] Specifically, if the logical address is continuous, the starting logical address of the address segment corresponding to the logical address is obtained by traversing the global bitmap table forward according to the logical address.

[0294] Step S1207: judging whether the starting logical address is a large page alignment address;

[0295] Specifically, it is judged whether the starting logical address is a large page alignment address. If the starting logical address is a large page alignment address, step S1208 is entered. If the starting logical address is not a large page alignment address, step S1205 is entered. In the embodiment of the present application, the large page alignment address refers to the starting address of data being an integer multiple of the data unit byte number. The large page alignment can ensure that the data can be continuously and efficiently read or written. The non-large page alignment address refers to the starting address of data not being an integer multiple of the data unit byte number. The large page alignment address includes but is not limited to an 8-byte alignment address. For example, if it is needed to judge whether the logical address is an 8-byte alignment address, the logical address is divided by 8, and a remainder is obtained. If the remainder is not equal to 0, it indicates that the logical address is a non-8-byte alignment address. If the remainder is equal to 0, it indicates that the logical address is an 8-byte alignment address.

[0296] Step S1208: obtaining the physical address corresponding to the logical address through the compact array.

[0297] Specifically, if the starting logical address is a large page alignment address, the physical address corresponding to the logical address is obtained through the compact array.

[0298] Please refer to Figure 16 , Figure 16 is a flowchart provided by the embodiment of the present application for judging whether the address segment has established a compact array.

[0299] As shown in Figure 16 , the flow of judging whether the address segment has established a compact array includes:

[0300] Step S1601: obtaining the address segment corresponding to the logical address.

[0301] Specifically, before the physical address is queried through the compact array, the address segment corresponding to the logical address is obtained according to the logical address.

[0302] Step S1602: judging whether the address segment has established a compact array.

[0303] Specifically, it is judged whether the logical address segment corresponding to the logical address has established a compact array. If the logical address segment corresponding to the logical address has established a compact array, step S1604 is entered. If the logical address segment corresponding to the logical address has not established a compact array, step S1603 is entered.

[0304] Step S1603: obtaining the physical address corresponding to the logical address through the range bucket hash structure.

[0305] Specifically, the range hash bucket structure includes a global range table, a range array and a range bucket, the global range table is acquired, wherein the global range table is used to store a mapping pointer corresponding to a logical address segment, the mapping pointer points to the range bucket or the range array. According to the global range table, it is judged whether the mapping pointer corresponding to the logical address segment points to the range bucket; if the mapping pointer corresponding to the logical address segment points to the range bucket, the physical address corresponding to the logical address is queried through the range bucket; if the mapping pointer corresponding to the logical address segment points to the range array, the physical address corresponding to the logical address is queried through the range array.

[0306] Step S1604: acquiring the physical address corresponding to the logical address through the compact array;

[0307] Specifically, if the compact array of the logical address segment corresponding to the logical address has been established, the physical address corresponding to the logical address is acquired through the compact array.

[0308] Please refer to Figure 17 , Figure 17 is a whole flowchart of a physical address query method based on a hybrid mapping structure provided by the embodiment of the application;

[0309] As Figure 17 shown, the whole flowchart of the physical address query method based on the hybrid mapping structure includes:

[0310] Step S1701: acquiring a logical address;

[0311] Specifically, the logical address is acquired, and the logical address is used to query the physical address corresponding thereto in the hybrid mapping structure.

[0312] Step S1702: querying whether the logical address has established a mapping relationship according to a global bitmap table;

[0313] Specifically, whether the logical address has established a mapping relationship is queried according to the allocation bitmap in the global bitmap table, if the logical address has established a mapping relationship, step S1704 is entered; if the logical address has not established a mapping relationship, step S1703 is entered.

[0314] Step S1703: determining that the logical address has not established a mapping relationship, and outputting a query failure result;

[0315] Specifically, if the logical address has not established a mapping relationship, it is determined that the logical address has not established a mapping relationship, and a query failure result is outputted.

[0316] Step S1704: judging whether the logical address is continuous;

[0317] Specifically, if the logical address has established a mapping relationship, it is further judged whether the logical address is continuous with the previous logical address, if the logical address is continuous with the previous logical address, step S1705 is entered; if the logical address is not continuous with the previous logical address, step S1708 is entered.

[0318] Step S1705: traversing the global bitmap table to obtain the starting logical address of the address segment corresponding to the logical address;

[0319] Specifically, if the logical address is continuous with the previous logical address, the global bitmap table is traversed to obtain the starting logical address of the address segment corresponding to the logical address.

[0320] Step S1706: judging whether the starting logical address is a large page alignment address;

[0321] Specifically, it is judged whether the starting logical address is a large page alignment address, wherein the large page alignment address includes an 8-byte alignment address, if the starting logical address is a large page alignment address, step S1707 is entered; if the starting logical address is not a large page alignment address, step S1708 is entered.

[0322] Step S1707: obtaining the physical address corresponding to the logical address through the compact array;

[0323] Specifically, if the starting logical address is a large page alignment address, the physical address corresponding to the logical address is obtained through the compact array.

[0324] Step S1708: obtaining the global range table;

[0325] Specifically, when the logical address is not continuous with the previous logical address, or the starting logical address is not a large page alignment address, the global range table is obtained to query the physical address corresponding to the logical address through the range hash bucket structure.

[0326] Step S1709: judging whether the mapping pointer corresponding to the logical address segment points to the range bucket according to the global range table;

[0327] Specifically, it is judged whether the mapping pointer corresponding to the logical address segment points to the range bucket according to the global range table, if the mapping pointer corresponding to the logical address segment points to the range bucket, step S1710 is entered; if the mapping pointer corresponding to the logical address segment does not point to the range bucket, step S1711 is entered.

[0328] Step S1710: obtaining the physical address corresponding to the logical address in the range bucket;

[0329] Specifically, if the mapping pointer corresponding to the logical address segment points to the range bucket, the physical address corresponding to the logical address is obtained in the range bucket.

[0330] Step S1711: obtaining the physical address corresponding to the logical address in the range array;

[0331] Specifically, if the mapping pointer corresponding to the logical address segment does not point to the range bucket, the physical address corresponding to the logical address is obtained in the range array.

[0332] In the embodiment of the present application, by providing a physical address query method based on a hybrid mapping structure, the hybrid mapping structure includes a global bitmap table, a compact array and a range bucket hash structure, the method includes: obtaining a logical address; querying whether the logical address has established a mapping relationship according to the global bitmap table; if the logical address has established a mapping relationship, judging whether the logical address is continuous; if the logical address is continuous, traversing the global bitmap table to obtain the starting logical address of the address segment corresponding to the logical address; if the starting logical address is a large page alignment address, obtaining the physical address corresponding to the logical address through the compact array; if the logical address is not continuous, obtaining the physical address corresponding to the logical address through the range bucket hash structure, the present application can query the physical address corresponding to the logical address through the hybrid mapping structure, and improve the query efficiency of the physical address.

[0333] In the embodiment of the present application, the execution subject of the construction method of the hybrid mapping structure and the physical address query method based on the hybrid mapping structure is a flash memory device, specifically, the flash memory device is controlled by a flash memory device controller to execute each method step in the construction method of the hybrid mapping structure or the physical address query method based on the hybrid mapping structure, the flash memory device includes a solid state disk or other storage device with flash memory medium as storage medium, and the flash memory device controller includes a controller of the solid state disk or other storage device with flash memory medium as storage medium.

[0334] Please refer to Figure 18 , Figure 18 is a structure schematic diagram of a flash memory controller provided in the embodiment of the present application;

[0335] As shown in Figure 18 , the flash memory controller 180 includes one or more processors 181 and a memory 182. Among them, Figure 18 take one processor 181 as an example.

[0336] The processor 181 and the memory 182 can be connected through a bus or other means, Figure 18 take the connection through the bus as an example.

[0337] The processor 181 is configured to provide computing and control capabilities to control the flash controller 180 to perform corresponding tasks, for example, to control the flash controller 180 to perform the construction method of the hybrid mapping structure in any of the above method embodiments, the hybrid mapping structure including a global bitmap table, a compact array, and a range bucket hash structure, and the method including: obtaining a mapping pair, wherein the mapping pair includes a logical address and a physical address corresponding to the logical address; determining, according to the global bitmap table, whether the logical address is a continuous non-large page alignment address; if the logical address is not a continuous non-large page alignment address, determining whether the continuity of a logical address segment corresponding to the logical address is greater than a continuity threshold; if the continuity of the logical address segment is greater than the continuity threshold, inserting the mapping pair into the compact array; if the continuity of the logical address segment is less than or equal to the continuity threshold, inserting the mapping pair into the range bucket hash structure, and the physical address query method based on the hybrid mapping structure, the hybrid mapping structure including a global bitmap table, a compact array, and a range bucket hash structure, and the method including: obtaining a logical address; determining, according to the global bitmap table, whether the logical address has established a mapping relationship; if the logical address has established a mapping relationship, determining whether the logical address is continuous; if the logical address is continuous, traversing the global bitmap table to obtain a starting logical address of an address segment corresponding to the logical address; if the starting logical address is a large page alignment address, obtaining the physical address corresponding to the logical address through the compact array; and if the logical address is not continuous, obtaining the physical address corresponding to the logical address through the range bucket hash structure.

[0338] The present application can store mapping pairs by using a hybrid mapping structure combining a global bitmap table, a compact array, and a range hash bucket structure, can optimize the memory overhead of a flash device, can save memory in a pure sequential read-write scenario, can maintain the performance of an array in a pure random read-write scenario, and can query the physical address corresponding to a logical address through the hybrid mapping structure to improve the query efficiency of the physical address.

[0339] The processor 181 can be a general processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; and can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0340] The memory 182, as a non-transitory computer readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as the construction method of the hybrid mapping structure in the embodiments of the present application, or the program instructions / modules corresponding to the physical address query method based on the hybrid mapping structure. The processor 181 can implement the construction method of the hybrid mapping structure or the physical address query method based on the hybrid mapping structure in any of the method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 182. Specifically, the memory 182 can include a volatile memory (VM), such as a random access memory (RAM); the memory 182 can also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), or other non-transitory solid-state storage devices; and the memory 182 can also include a combination of the above types of memories.

[0341] The memory 182 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state memory device. In some embodiments, the memory 182 can optionally include a memory disposed remotely relative to the processor 181, which can be connected to the processor 181 through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0342] One or more modules are stored in the memory 182, which, when executed by the one or more processors 111, perform the construction method of the hybrid mapping structure in any of the above method embodiments, or the physical address query method based on the hybrid mapping structure.

[0343] In the embodiments of the present application, the flash memory controller 180 can also have components such as a wired or wireless network interface, a keyboard, and an input and output interface, so as to perform input and output. The flash memory controller 180 can also include other components for realizing the functions of the device, which are not described herein.

[0344] The embodiments of the present application also provide a computer readable storage medium, such as a memory including program codes, which can be executed by a processor to complete the construction method of the hybrid mapping structure in the above embodiments, or the physical address query method based on the hybrid mapping structure. For example, the computer readable storage medium can be a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a compact disc read-only memory (Compact Disc Read-Only Memory, CDROM), a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0345] Please refer to Figure 19 , Figure 19 is a structural schematic diagram of a flash memory device provided by the embodiments of the present application.

[0346] As Figure 19 shown, the flash memory device 100 includes a flash memory medium 110 and a flash memory device controller 110 connected with the flash memory medium 110. Wherein, the flash memory device 100 is connected with a host 200 in a wired or wireless manner, so as to realize data interaction.

[0347] Wherein, the flash memory device controller 180 includes:

[0348] at least one processor 181; and,

[0349] a memory 182 connected in communication with the at least one processor 181; wherein,

[0350] The memory 182 is configured to store instructions executable by the at least one processor 181, and the instructions are executed by the at least one processor to enable the at least one processor to perform the construction method of the hybrid mapping structure or the physical address query method based on the hybrid mapping structure.

[0351] The flash medium 110, as the storage medium of the flash device 100, is also referred to as a flash, a Flash, a Flash memory or a Flash grain, belongs to a memory device, is a nonvolatile memory that can store data for a long time without power supply, and has a storage characteristic equivalent to a hard disk, so that the flash medium 110 can become the basis of the storage medium of various portable digital devices.

[0352] The flash medium 110 can be a Nand FLASH. The Nand FLASH uses a single transistor as a binary signal storage unit, and its structure is very similar to that of a common semiconductor transistor, except that the single transistor of the Nand FLASH has a floating gate and a control gate. The floating gate is used to store electrons, and the surface is covered by a layer of silicon oxide insulator and is coupled to the control gate through a capacitor. When negative electrons are injected into the floating gate under the action of the control gate, the storage state of the single transistor of the Nand FLASH changes from “1” to “0”, and when the negative electrons are removed from the floating gate, the storage state changes from “0” to “1”. The insulator covering the surface of the floating gate is used to trap the negative electrons in the floating gate to achieve data storage. That is, the storage unit of the Nand FLASH is a floating gate transistor, and the floating gate transistor is used to store data in the form of electric charge. The amount of stored electric charge is related to the size of the voltage applied to the floating gate transistor.

[0353] A Nand FLASH includes at least one Chip chip, each Chip chip is composed of a plurality of Block physical blocks, and each Block physical block includes a plurality of Page pages. The Block physical block is the smallest unit of the Nand FLASH for performing an erase operation, and the Page page is the smallest unit of the Nand FLASH for performing a read / write operation. The capacity of a Nand FLASH is equal to the number of Block physical blocks * the number of Page pages contained in one Block physical block * the capacity of one Page page. Specifically, the flash medium 110 can be divided into SLC, MLC, TLC and QLC according to different levels of voltage of the storage unit.

[0354] The embodiments of the present application further provide a non-volatile computer readable storage medium, for example, a memory including program codes, which can be executed by a processor to complete the construction method of the hybrid mapping structure or the physical address query method based on the hybrid mapping structure in the above embodiments. For example, the non-volatile computer readable storage medium can be a Read-Only Memory (ROM), a Random Access Memory (RAM), a Compact Disc Read-Only Memory (CDROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0355] The embodiments of the present application further provide a computer program product including one or more program codes stored in a non-volatile computer readable storage medium. The processor of the flash memory device reads the program codes from the non-volatile computer readable storage medium, and the processor executes the program codes to complete the construction method of the hybrid mapping structure or the method steps of the physical address query method based on the hybrid mapping structure provided in the above embodiments. It can be understood by those skilled in the art that all or part of the steps of the above embodiments can be completed by hardware, or by program codes related to hardware, and the program can be stored in a non-volatile computer readable storage medium. The storage medium mentioned above can be a Read-Only Memory, a magnetic disk or an optical disk, etc.

Claims

1. A method for constructing a hybrid mapping structure, characterized in that, The hybrid mapping structure includes a global bitmap, a compact array, and a range bucket hash structure. The range bucket hash structure includes a global range table, range buckets, and a range array. The global range table stores mapping pointers corresponding to logical address segments. The method includes: Obtain a mapping pair, wherein the mapping pair includes a logical address and the physical address corresponding to the logical address; Based on the global bitmap, determine whether the logical address is a contiguous non-big-page aligned address; If the logical address is not a contiguous non-big-page aligned address, then determine whether the continuity of the logical address segment corresponding to the logical address is greater than the continuity threshold. If the continuity of the logical address segment is greater than the continuity threshold, then the mapping pair is inserted into the compact array; If the continuity of the logical address segment is less than or equal to the continuity threshold, then the mapping pair is inserted into the range bucket hash structure; The step of inserting the mapping pair into the range bucket hash structure includes: Based on the global range table, determine whether the mapping pointer corresponding to the logical address segment points to the range bucket; If the mapping pointer corresponding to the logical address segment points to the range bucket, then the mapping pair is inserted into the range bucket; If the mapping pointer corresponding to the logical address segment does not point to the range bucket, then the mapping pair is inserted into the range array.

2. The method according to claim 1, characterized in that, The global bitmap is used to store metadata information corresponding to each logical address segment. The metadata information includes continuity. The metadata information also includes an allocation bitmap, which is used to store a first state of the logical address. The first state includes a mapped state and a non-mapped state. The method further includes: Based on the allocation bitmap, determine whether the first state corresponding to the logical address is a mapping state; If the first state corresponding to the logical address is a non-mapped state, then the first state corresponding to the logical address is modified to a mapped state.

3. The method according to claim 2, characterized in that, The metadata information also includes a continuous bitmap, which stores a second state of the logical address. This second state includes a continuous state and a non-contiguous state. The step of determining whether the logical address is a continuous, non-big-page aligned address based on the global bitmap includes: Determine whether the logical address is a non-bigpage aligned address; If the logical address is a non-big page aligned address, then according to the global bitmap, it is determined whether the logical address is continuous with the logical address in the global bitmap; If the logical address is continuous with the logical address in the global bitmap, then the continuous bitmap corresponding to the logical address is determined to be in a continuous state.

4. The method according to claim 1, characterized in that, After inserting the mapping pair into the range bucket, the method further includes: Determine whether the capacity of the range bucket has reached the capacity threshold; If the capacity of the range bucket has reached the capacity threshold, then determine whether the continuity of the range bucket is greater than the continuity threshold. If the continuity of the range bucket is less than or equal to the continuity threshold, then determine whether the density of the range bucket is greater than the density threshold. If the density of the range bucket is less than or equal to the density threshold, then the range bucket is split into at least two range buckets; If the density of the range bucket is greater than the density threshold, then the range bucket is split into at least two range arrays.

5. The method according to claim 1, characterized in that, The method further includes: Determine whether the continuity of the compact array is less than or equal to a continuity threshold; If the continuity of the compact array is less than the continuity threshold, then all mapping pairs with established mapping relationships in the compact array are obtained; Insert all the established mapping pairs into the range bucket and release the memory of the compact array to restore the compact array to the range bucket.

6. The method according to claim 1, characterized in that, After inserting the mapping pair into the range array, the method further includes: Determine whether the density of the range array is less than a density threshold; If the density of the range array is less than the density threshold, then all mapping pairs in the range array are obtained; Insert all mapping pairs in the range array into the range bucket and release the memory of the range array to restore the range array to the range bucket.

7. The method according to claim 1, characterized in that, After inserting the mapping pair into the range bucket, the method further includes: Determine whether there exists a logical address segment in the range bucket whose continuity is greater than a continuity threshold; If the continuity of a logical address segment in the range bucket is greater than the continuity threshold, then the logical address segment and the mapping pair corresponding to the logical address segment are obtained. A compact array is created for the logical address segment, and the mapping pairs corresponding to the logical address segment are moved from the range bucket to the compact array; After moving the mapping pair corresponding to the logical address segment from the range bucket to the compact array, if the density of the range bucket is less than the density threshold, the range bucket is merged with the surrounding range buckets into a new range bucket.

8. A physical address lookup method based on a hybrid mapping structure, characterized in that, The hybrid mapping structure includes a global bitmap, a compact array, and a range bucket hash structure. The range bucket hash structure includes a global range table, range buckets, and a range array. The global range table stores mapping pointers corresponding to logical address segments. The method includes: Get the logical address; Based on the global bitmap, query whether a mapping relationship has been established for the logical address; If a mapping relationship has been established for the logical addresses, then determine whether the logical addresses are consecutive; If the logical addresses are consecutive, then traverse the global bitmap to obtain the starting logical address of the address segment corresponding to the logical address; If the starting logical address is a big page aligned address, then the physical address corresponding to the logical address is obtained through the compact array; If the logical addresses are not contiguous, the physical address corresponding to the logical address is obtained through the range bucket hash structure. The step of obtaining the physical address corresponding to the logical address through the range bucket hash structure includes: Based on the global range table, determine whether the mapping pointer corresponding to the logical address segment points to the range bucket; If the mapping pointer corresponding to the logical address segment points to the range bucket, then the physical address corresponding to the logical address is obtained from the range bucket; If the mapping pointer corresponding to the logical address segment does not point to the range bucket, then the physical address corresponding to the logical address is obtained from the range array.

9. The method according to claim 8, characterized in that, The global bitmap is used to store metadata information corresponding to each logical address segment. The metadata information includes an allocation bitmap, which stores a first state of the logical address. The first state includes a mapped state and a non-mapped state. Determining whether a mapping relationship has been established for the logical address includes: Based on the allocation bitmap, determine whether the first state corresponding to the logical address is a mapping state; If the first state corresponding to the logical address is a mapping state, then it is determined that a mapping relationship has been established for the logical address; If the first state corresponding to the logical address is a non-mapping state, it is determined that no mapping relationship has been established for the logical address, and the query failure result is output.

10. The method according to claim 9, characterized in that, The metadata information also includes a continuous bitmap, which stores a second state of the logical address. This second state includes a continuous state and a non-contiguous state. Determining whether the logical address is continuous includes: Based on the continuous bitmap, determine whether the second state corresponding to the logical address is a continuous state; If the second state corresponding to the logical address is a continuous state, then the logical address is determined to be a continuous logical address; If the second state corresponding to the logical address is a non-contiguous state, then the logical address is determined to be a non-contiguous logical address.

11. The method according to claim 8, characterized in that, Before obtaining the physical address corresponding to the logical address through the compact array, the method further includes: Determine whether a compact array has been created for the address segment; If a compact array has been established for the address segment, the physical address corresponding to the logical address can be obtained through the compact array. If the address segment does not have a compact array, the physical address corresponding to the logical address is obtained through the range bucket hash structure.

12. A flash memory device controller, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method for constructing a hybrid mapping structure as described in any one of claims 1-7, or the physical address lookup method based on a hybrid mapping structure as described in any one of claims 8-11.

13. A flash memory device, characterized in that, include: The flash memory device controller as described in claim 12; At least one flash memory medium that is communicatively connected to the flash memory device controller.

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