Bit stream file management method for refreshing and reconstructing multiple satellite-borne FPGAs (Field Programmable Gate Array)

Abstract

The invention discloses a bit stream file management method for satellite-borne multi-FPGA (Field Programmable Gate Array) refreshing and reconstruction, and relates to the technical field of satellite-borne equipment management. According to the bit stream file management method oriented to spaceborne multi-FPGA refreshing and reconstruction, a BIT file is adopted for uploading, automatic paraphrasing and marking of the uploading file are achieved through a control management FPGA, storage of the bit stream file configured by the multi-target FPGA in a single large-capacity NOR FLASH is achieved, the utilization rate of a FLASH chip is increased, the cost is saved, the load-bearing power consumption of spaceborne equipment is reduced, and the space-borne multi-FPGA refreshing and reconstruction efficiency is improved. The method also has the advantage of quick positioning and extraction of bit stream information, and provides convenient and reliable guarantee for refreshing and reconstruction of the target FPGA while the management and maintenance complexity is low.

Description

Technical Field

[0001] The present invention relates to the technical field of satellite-borne equipment management, and in particular to a bit stream file management method for satellite-borne multi-FPGA refresh and reconstruction. Background Art

[0002] FPGA, or Field Programmable Gate Array, is a programmable logic device that is highly favored in all walks of life for its powerful reconfiguration capabilities and strong real-time performance. SRAM-type FPGAs have the highest usage rate due to their higher integration, lower dynamic power consumption, higher speed, and lower price. However, this type of FPGA may change the configuration data of the configurable SRAM units inside the device when hit by high-energy particles, thereby causing logical errors that affect device functions. This phenomenon is usually called the single particle upset effect.

[0003] Due to the particularity of the environment in which the onboard equipment is located, the FPGA carried by it will be continuously exposed to high-energy particle irradiation for a long time, so it is more likely to have configuration data errors flipped. In order to improve the operating reliability of this type of SRAM-type FPGA device, it is necessary to continuously update the configuration file in the SRAM-type FPGA. At present, dynamic refresh is usually used in combination with online reload to ensure the reliable operation of the configuration file. Among them, dynamic refresh refers to pulling part of the content in the original FPGA configuration file from the storage area at regular intervals to replace the static configuration area of ​​the FPGA, thereby ensuring that the current function of the FPGA is not interrupted and effectively avoiding functional errors caused by data flipping in the static configuration area; online reload refers to pulling the complete configuration bit stream from the storage area to update the entire FPGA functional circuit. Therefore, whether it is refreshed or reloaded, the FPGA configuration bit stream must always be stored in the onboard equipment. In order to increase the reliability of the onboard FPGA function, a single FPGA usually needs to store two main and backup bit stream files.

[0004] The current management method for refresh and reload bitstreams is usually based on a single FLASH chip, that is, according to the chip type of the target FPGA to be refreshed and reloaded, a NOR FLASH of a suitable size is selected to store a bitstream file. Although this method simplifies the access method of the bitstream, the utilization rate of the FLASH storage space is greatly reduced, especially for compressed bitstreams.

[0005] Based on the search of the above data, it can be seen that the existing refresh and reconstruction scheme usually requires at least one dedicated control FPGA plus two FLASH to maintain one functional FPGA. In view of the particularity of the onboard environment, it is often necessary to select NOR FLASH with higher stability to achieve this. However, the chip structure of NOR FLASH is often larger and more expensive. Therefore, this scheme design will inevitably bring disadvantages such as increased cost, increased equipment volume and power consumption. In addition, a single onboard device often has many functional FPGAs that need to be reconstructed and maintained online, and the configuration files that need to be updated for each FPGA are different. The current method of storing one bit stream in one FLASH cannot accurately know the actual meaning and position of each bit stream in the subsequent use of the bit stream, and can only be distinguished based on the FLASH bit number. This requires manual indexing in advance, and the newly added bit stream files also need to be manually re-maintained. The use is extremely inflexible. Therefore, a bit stream file management method for onboard multi-FPGA refresh and reconstruction is proposed. Multiple bit stream files are stored in large-capacity NOR FLASH, and the bit stream information is automatically interpreted and marked to achieve the purpose of rapid positioning and extraction of bit stream information. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention provides a bitstream file management method for onboard multi-FPGA refresh and reconstruction, which solves the problems raised in the above-mentioned background technology.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions: a bitstream file management method for onboard multi-FPGA refresh and reconstruction, including: an external controller, a control management FPGA, several target FPGAs and a large-capacity NORFLASH;

[0008] The external controller is used to inject the configuration bit stream file data frame into the control management FPGA through the serial port;

[0009] The control management FPGA is used to import the configuration bit stream file data frame into the large-capacity NOR FLASH according to the preset bit stream file names corresponding to the target FPGA device numbers;

[0010] It is also used to read the configuration bit stream file of the corresponding target FPGA from the large-capacity NOR FLASH according to several target FPGA device numbers, and load it to the target FPGA through the SelectMAP interface to refresh and reconstruct the target FPGA;

[0011] The large-capacity NOR FLASH includes a main partition and a backup partition, wherein the main partition is used to separately store the configuration bit stream file according to the bit stream file name, wherein the backup partition is a mirror image of the main partition.

[0012] The present invention is further configured as follows: the configuration bitstream file data frame sent by the external controller to the control management FPGA through the serial port is a BIT file, wherein the BIT file not only has complete FPGA configuration information, but also has a file frame header that describes the bitstream file's own information, and the frame header contains the file name, compression information, user ID, Vivado software version number, target device type and file generation time information.

[0013] The present invention is further configured as follows: the control management FPGA includes a file transmission module, a loading control module, a file management system and a FLASH controller;

[0014] The file transmission module is used to receive the configuration bit stream file data frame and verify it. When an error occurs, the external controller is required to retransmit the configuration bit stream file data frame that generates the error.

[0015] The loading control module is used to preset the corresponding bitstream file name according to several target FPGA device numbers, and to select and load the target FPGA;

[0016] The file management system is used to manage repeated coverage, independent storage and index extraction of a plurality of configuration bit stream files;

[0017] The FLASH controller is used to manage the read, write and erase operations of the large-capacity NOR FLASH.

[0018] The present invention is further configured as follows: the file management system comprises:

[0019] Bitstream data frame receiving, the bitstream data frame receiving is used to receive a configuration bitstream file data frame;

[0020] Storage area selection, the storage area selection is used to control the storage area flow;

[0021] File list update, the file list update is used to generate updated file list information, the file list information includes but is not limited to configuration file name, version and burning time information;

[0022] File read and write control, which is used to drive the FLASH controller to read and write large-capacity NOR FLASH;

[0023] The response processing return is used to complete the storage of the bit stream file configuration in each frame and return the frame processing result.

[0024] The present invention is further configured as follows: the primary partition includes an existing file list area, a free area list area and a bit stream file storage area;

[0025] The existing file list area is used to record detailed information of the stored bitstream file, and the detailed information includes the configuration bitstream file name, FPGA device model, storage time, start address and file size information;

[0026] The free area list area is used to record the list information of unused free blocks in FLASH, and the list information includes the starting address and block size information;

[0027] The bitstream file storage area is used to record the content of the bitstream file noted above.

[0028] The present invention is further configured as follows: the method of configuring the bit stream file data frame to be injected into the large-capacity NOR FLASH includes:

[0029] A1. The user selects a configuration bit stream file X.bit that needs to be uploaded through an external controller and starts uploading;

[0030] A2. The external controller sends the start injection command to the control management FPGA;

[0031] A3. After the control management FPGA confirms that the large-capacity NOR FLASH is normal, it opens the file upload channel;

[0032] A4, the external controller sends the first frame configuration bit stream file according to the 1024-byte payload;

[0033] A5. The control management FPGA intercepts the frame header data in the first frame configuration bit stream file, and parses the configuration bit stream file name for this injection, which is recorded as X.bit.

[0034] A6, control management FPGA compares the information in the current file list area one by one according to the file name X.bit to confirm whether the configuration bit stream file noted above exists. If yes, go to A7; otherwise, go to A8;

[0035] A7, the control management FPGA first erases the original file data, and marks the block corresponding to the erased original file data as unused, and records it in the free area list area;

[0036] A8, the control management FPGA determines the minimum storage space required according to the size of the configuration bit stream file;

[0037] A9, the control management FPGA starts to search the free area list area information in the large-capacity NOR FLASH in turn, and after finding the smallest free block larger than the minimum storage space, it goes to A10; otherwise, it goes to A12;

[0038] A10, write the configuration bitstream file noted above into the smallest free block found, and when there is excess space in the smallest free block, return the excess space to the free area list area and update the free area list area; otherwise, when there is no excess space, delete the smallest free block record from the free area list area;

[0039] A11, after all configuration bitstream files are written, update the record information in the existing file list area;

[0040] A12. Configuration of the bitstream file is completed.

[0041] The present invention is further configured as follows: the method for controlling and managing FPGA to read the configuration bit stream file from the large-capacity NOR FLASH includes:

[0042] B1, the loading control module determines the configuration bit stream file name X.bit required by the target FPGA;

[0043] B2. The file management system compares the information in the current file list area one by one according to the configuration bit stream file name X.bit to confirm whether the configuration bit stream file to be extracted exists. If yes, go to B3; otherwise, go to B6;

[0044] B3, determining the location where the configuration bitstream file is stored according to the starting address information of the configuration bitstream file stored in the existing file list area;

[0045] B4, the file management system drives the FLASH controller to read the configuration bit stream file from the starting address of the configuration bit stream file in the large-capacity NOR FLASH;

[0046] B5, stop when the amount of data read by the FLASH controller from the large-capacity NOR FLASH is equal to the file size of the configuration bit stream file recorded in the existing file list area;

[0047] B6. Bitstream file extraction is completed.

[0048] The present invention provides a bitstream file management method for onboard multi-FPGA refresh and reconstruction. It has the following beneficial effects:

[0049] The present invention adopts BIT files for annotation and uses control management FPGA to realize automatic interpretation and marking of the annotation files, so as to realize the storage of configuration bitstream files required by multi-target FPGAs in a single large-capacity NOR FLASH, improve the utilization rate of FLASH chips, save costs, and reduce the load power consumption of satellite-borne equipment. It also has the advantages of fast positioning and extraction of bitstream information, low management and maintenance complexity, and provides convenient and reliable guarantee for the refresh and reconstruction of the target FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a functional architecture schematic diagram of the present invention;

[0051] Figure 2 It is a schematic diagram of the architecture of the file management system of the present invention;

[0052] Figure 3 A schematic diagram of the process of configuring the bitstream file of the present invention;

[0053] Figure 4 It is a schematic diagram of the partition of the large-capacity NOR FLASH of the present invention;

[0054] Figure 5 A schematic diagram of the reading process of the bit stream file configured for the present invention;

[0055] Figure 6 It is a schematic diagram of the architecture when a 2Gb NOR FLASH is used to perform refresh and reload management on at least 8 target FPGAs in an embodiment of the present invention;

[0056] Figure 7 It is a schematic diagram of the architecture of using n 2Gb NOR FLASH to manage the refresh and reload of at least 8n target FPGAs in an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0058] See also Figure 1-7The embodiment of the present invention provides the following technical solutions: a bitstream file management method for onboard multi-FPGA refresh and reconstruction, including: an external controller, a control management FPGA, several target FPGAs and a large-capacity NORFLASH, wherein the control management FPGA includes a file transfer module, a loading control module, a file management system and a FLASH controller, and the external controller has a built-in FPGA software development tool Vivado generated FPGA-specific configuration file. According to the Xilinx official U470 manual, Vivado can generate FPGA configuration files of BIT, RBT, BIN, MCS and HEX5 types. In the present invention, the annotation file abandons the traditional BIN file annotation method and adopts BIT file annotation. Compared with BIN file, BIT file not only has complete FPGA configuration information, but also has a file frame header that describes the information of the bitstream file itself. The frame header contains valid information such as file name, compression information, user ID, Vivado software version number, target device type and file generation time. Therefore, using BIT file as the annotation file is more conducive to the classification management of multiple bitstream files. This information is not only conducive to FPGA identification of bitstream files, but can also be used in file management system to provide convenient conditions for indexing, storing and reading configuration bitstream files.

[0059] In order to achieve the management of repeated overwriting, independent storage and index extraction of several configuration bitstream files, as shown in the attached Figure 2 As shown, the file management system includes:

[0060] Bit stream data frame receiving, the bit stream data frame receiving is used to receive a configuration bit stream file data frame;

[0061] Storage area selection, which is used to control the storage area transfer, specifically including the transfer of blocks between the following existing file list area and space area list area;

[0062] File list update, file list update is used to generate updated file list information;

[0063] File read and write control: File read and write control is used to drive the FLASH controller to read and write large-capacity NOR FLASH;

[0064] Response processing return: Response processing return is used to complete the bit stream file storage configuration of each frame and return the frame processing result.

[0065] As a preferred solution, in order to achieve effective storage of configuration bitstream data, the large capacity NOR FLASH is divided into a primary partition and a backup partition, wherein the backup partition is a mirror of the primary partition, and the primary partition is used to store the configuration bitstream file separately according to the bitstream file name, as shown in the attached Figure 4As shown, both the primary partition and the backup partition include an existing file list area, a free area list area, and a bitstream file storage area;

[0066] The existing file list area is used to record the detailed information of the stored bitstream files, including the configuration bitstream file name, FPGA device model, storage time, start address and file size information;

[0067] The free area list area is used to record the list information of unused free blocks in FLASH, and the list information includes the starting address and block size information;

[0068] The bitstream file storage area is used to record the content of the bitstream file noted above.

[0069] As a detailed explanation, the large-capacity NOR FLASH not only realizes the dual storage of the configuration bit stream information, but also provides reliable reference data for the minimum capacity storage and quick indexing of the configuration bit stream information with the cooperation of the configuration bit stream file name, FPGA device model, starting address and file size information.

[0070] As a detailed explanation, the management of refresh and reconstruction of multiple FPGA devices mainly includes two parts: bitstream file annotation and bitstream file extraction.

[0071] The bitstream file annotation process is as follows Figure 3 As shown, specifically including:

[0072] A1. The user selects a configuration bit stream file X.bit that needs to be uploaded through the human-computer interaction interface of the external controller and starts uploading;

[0073] A2. The external controller sends the start injection command to the control management FPGA;

[0074] A3. After the control management FPGA confirms that the large-capacity NOR FLASH is normal, it opens the file upload channel;

[0075] A4, the external controller sends the first frame configuration bit stream file according to the 1024-byte payload;

[0076] A5. The file transmission module intercepts the frame header data in the first frame configuration bit stream file, and parses out the configuration bit stream file name noted this time, which is recorded as X.bit. Specifically, the file transmission module receives the configuration bit stream file data frame and verifies it. When an error occurs, the external controller is required to retransmit the configuration bit stream file data frame that generates the error.

[0077] A6, the file management system compares the information in the current file list area one by one according to the file name X.bit to confirm whether the configuration bit stream file noted above exists. If it exists, go to A7; otherwise, go to A8;

[0078] A7. The file management system first erases the original file data, and marks the block corresponding to the erased original file data as unused, and records it in the free area list area. This process realizes the management of repeated overwriting;

[0079] A8. The file management system determines the minimum storage space required based on the size of the bitstream file configured above;

[0080] A9, the file management system starts to search the free area list area information in the large-capacity NOR FLASH in turn, and after finding the smallest free block larger than the minimum storage space, it goes to A10; otherwise, it goes to A12;

[0081] A10, the file management system writes the configuration bit stream file noted above to the smallest free block found through the FLASH controller. When there is extra space in the smallest free block, the extra space is returned to the free area list area and the free area list area is updated; otherwise, when there is no extra space, the smallest free block record is deleted from the free area list area. This process realizes the management of independent storage;

[0082] A11, after all configuration bitstream files are written, update the record information in the existing file list area;

[0083] A12. Configuration of the bitstream file is completed.

[0084] As a preferred solution, in order to achieve the refresh reconstruction of the target RPGA device, the bitstream file is extracted, which specifically includes:

[0085] B1, the loading control module determines the configuration bit stream file name X.bit required by the target FPGA;

[0086] B2. The file management system compares the information in the current file list area one by one according to the configuration bit stream file name X.bit to confirm whether the configuration bit stream file to be extracted exists. If yes, go to B3; otherwise, go to B6;

[0087] B3, determining the location where the configuration bitstream file is stored according to the starting address information of the configuration bitstream file stored in the existing file list area;

[0088] B4, the file management system drives the FLASH controller to read the configuration bit stream file from the starting address of the configuration bit stream file in the large-capacity NOR FLASH. This process realizes the configuration bit stream file index extraction;

[0089] B5, stop when the amount of data read by the FLASH controller from the large-capacity NOR FLASH is equal to the file size of the configuration bit stream file recorded in the existing file list area;

[0090] B6. Bitstream file extraction is completed.

[0091] For the extracted configuration bitstream file, the loading control module loads the configuration bitstream file into the target FPGA through the SelectMAP interface to achieve refresh and reconstruction of the target FPGA.

[0092] As an optional embodiment, as shown in the attached Figure 6 As shown, the target FPGA takes Xilinx XC7K325T as an example, and the NOR FLASH takes 2Gb capacity as an example. A 2Gb NOR FLASH is mounted under a control management FPGA to realize the refresh and reload management of at least 8 target FPGAs. At this time, a single NOR FLASH is evenly divided into two partitions, the main and the backup. All the uploaded bitstream files will be automatically stored in the two partitions. Under this solution, if the uncompressed original bitstream is stored, at least 8 completely different configuration bitstream files can be stored, which is enough to realize the refresh and reload of 8 target FPGAs; if the compressed bitstream is stored, more files can be stored.

[0093] As an optional embodiment, as shown in the attached Figure 7 As shown, the target FPGA takes Xilinx XC7K325T as an example, and the NOR FLASH takes 2Gb capacity as an example. n 2Gb NOR FLASH are mounted under a control management FPGA to realize the refresh and reload management of at least 8n target FPGAs. At this time, every two NOR FLASHes are grouped as the main and backup areas for storing bit streams respectively. All uploaded bit stream files will be automatically stored in two different NOR FALSHs. The actual number of NOR FLASHes and target FPGAs that can be mounted under this solution needs to be combined with the actual resource amount of the control management FPGA.

[0094] In summary, the hardware design architecture of the present invention realizes the refresh and reload of multiple FPGAs based on a single-chip large-capacity NOR FLASH, which provides an effective reference for reducing the load-bearing energy consumption of satellite-borne equipment. In addition, the design idea of ​​partitioning the bitstream files and realizing automatic identification and management of the bitstream files by annotating the BIT files has the advantage of rapid positioning and extraction of bitstream information.

[0095] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0096] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A bitstream file management method for onboard multi-FPGA refresh and reconstruction, characterized by: include: External controller, control management FPGA, several target FPGAs and large-capacity NOR FLASH; The external controller is used to inject the configuration bit stream file data frame into the control management FPGA through the serial port; The control management FPGA is used to import the configuration bit stream file data frame into the large-capacity NOR FLASH according to the preset bit stream file names corresponding to the target FPGA device numbers; It is also used to read the configuration bit stream file of the corresponding target FPGA from the large-capacity NOR FLASH according to several target FPGA device numbers, and load it to the target FPGA through the SelectMAP interface to refresh and reconstruct the target FPGA; The large-capacity NOR FLASH includes a main partition and a backup partition, wherein the main partition is used to separately store the configuration bit stream file according to the bit stream file name, wherein the backup partition is a mirror image of the main partition.

2. The method for managing bitstream files for onboard multi-FPGA refresh and reconstruction according to claim 1, characterized in that: The configuration bit stream file data frame sent by the external controller to the control management FPGA through the serial port is a BIT file.

3. The method for managing bitstream files for onboard multi-FPGA refresh and reconstruction according to claim 1, characterized in that: The control management FPGA includes a file transfer module, a loading control module, a file management system and a FLASH controller; The file transmission module is used to receive the configuration bit stream file data frame and verify it. When an error occurs, the external controller is required to retransmit the configuration bit stream file data frame that generates the error. The loading control module is used to preset the corresponding bitstream file name according to several target FPGA device numbers, and to select and load the target FPGA; The file management system is used to manage repeated coverage, independent storage and index extraction of a plurality of configuration bit stream files; The FLASH controller is used to manage the read, write and erase operations of the large-capacity NOR FLASH.

4. The method for managing bitstream files for onboard multi-FPGA refresh and reconstruction according to claim 3, characterized in that: The document management system comprises: Bitstream data frame receiving, the bitstream data frame receiving is used to receive a configuration bitstream file data frame; Storage area selection, the storage area selection is used to control the storage area flow; File list update, wherein the file list update is used to generate updated file list information; File read and write control, which is used to drive the FLASH controller to read and write large-capacity NOR FLASH; The response processing is returned, and the response processing is returned to complete the storage of the bit stream file configuration in each frame and to return the frame processing result.

5. The method for managing bitstream files for onboard multi-FPGA refresh and reconstruction according to claim 4, characterized in that: The main partition includes an existing file list area, a free area list area and a bit stream file storage area; The existing file list area is used to record detailed information of the stored bitstream file, and the detailed information includes the configuration bitstream file name, FPGA device model, storage time, start address and file size information; The free area list area is used to record the list information of unused free blocks in FLASH, and the list information includes the starting address and block size information; The bitstream file storage area is used to record the content of the bitstream file noted above.

6. The method for managing bitstream files for onboard multi-FPGA refresh and reconstruction according to claim 5, characterized in that: The configuration bit stream file data frame is injected into the large capacity NOR FLASH in the following manner: A1. The user selects a configuration bit stream file X.bit that needs to be uploaded through an external controller and starts uploading; A2. The external controller sends the start injection command to the control management FPGA; A3. After the control management FPGA confirms that the large-capacity NOR FLASH is normal, it opens the file upload channel; A4, the external controller sends the first frame configuration bit stream file according to the 1024-byte payload; A5. The control management FPGA intercepts the frame header data in the first frame configuration bit stream file, and parses the configuration bit stream file name for this injection, which is recorded as X.bit. A6, control management FPGA compares the information in the current file list area one by one according to the file name X.bit to confirm whether the configuration bit stream file noted above exists. If yes, go to A7; otherwise, go to A8; A7, the control management FPGA first erases the original file data, and marks the block corresponding to the erased original file data as unused, and records it in the free area list area; A8, the control management FPGA determines the minimum storage space required according to the size of the configuration bit stream file; A9, the control management FPGA starts to search the free area list area information in the large-capacity NOR FLASH in turn, and after finding the smallest free block larger than the minimum storage space, it goes to A10; otherwise, it goes to A12; A10, write the configuration bitstream file noted above into the smallest free block found, and when there is excess space in the smallest free block, return the excess space to the free area list area and update the free area list area; otherwise, when there is no excess space, delete the smallest free block record from the free area list area; A11, after all configuration bitstream files are written, update the record information in the existing file list area; A12. Configuration of the bitstream file is completed.

7. The method for managing bitstream files for onboard multi-FPGA refresh and reconstruction according to claim 5, characterized in that: The control management FPGA reads the configuration bit stream file from the large-capacity NOR FLASH in the following manner: B1, the loading control module determines the configuration bit stream file name X.bit required by the target FPGA; B2. The file management system compares the information in the current file list area one by one according to the configuration bit stream file name X.bit to confirm whether the configuration bit stream file to be extracted exists. If yes, go to B3; otherwise, go to B6; B3, determining the location where the configuration bitstream file is stored according to the starting address information of the configuration bitstream file stored in the existing file list area; B4, the file management system drives the FLASH controller to read the configuration bit stream file from the starting address of the configuration bit stream file in the large-capacity NOR FLASH; B5, stop when the amount of data read by the FLASH controller from the large-capacity NOR FLASH is equal to the file size of the configuration bit stream file recorded in the existing file list area; B6. Bitstream file extraction is completed.

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