Processor for superscalar processing and method of operation thereof

Abstract

The invention relates to the field of processors, in particular to a processor for superscale processing and an operation method thereof, and the processor comprises a RAT manager which is used for managing a mapping relation among RAT, RAT storage logic registers and physical registers; a bit matrix manager to manage a bit matrix, rows and columns of the bit matrix indicating the logical registers, coordinate values of the rows and columns of the bit matrix having a first value or a second value; and the controller is in communication connection with the RAT manager and the bit matrix manager and is used for controlling the operation of the RAT manager and the bit matrix manager.

Description

Technical Field

[0001] The present invention relates to the field of processor architecture, and in particular, to a processor for superscalar processing and an operating method thereof. Background Art

[0002] In the design of superscalar processors, effectively managing the allocation and release of physical registers is the key to improving performance. In a superscalar processor, whenever an instruction needs to use a new physical register, the processor's register allocation unit will try to find an unused physical register.

[0003] The move instruction is different from other computing instructions. It does not involve arithmetic or logical operations, but simply copies the value of one register to another. Therefore, the move instruction does not need to allocate a new physical register, but directly maps the destination logical register to the physical register currently mapped by the source logical register. This processing method can reduce register occupancy and achieve zero-delay execution because it avoids additional register allocation and data movement.

[0004] The Register Rename Map Table (RAT) is a key data structure used in superscalar processors to track the mapping of logical registers to physical registers. The RAT allows the processor to dynamically manage register resources and resolve conflicts between registers by renaming.

[0005] When an instruction needs to allocate a new physical register, the processor must check the RAT to determine whether the old physical register has been mapped by another logical register. If the old physical register has a duplicate mapping in the RAT, it means that other instructions depend on the data in this physical register, so the old physical register cannot be released when the current instruction is submitted.

[0006] In the prior art, it is difficult to quickly determine whether there is a duplicate mapping of a physical register, and therefore it is difficult to quickly determine whether an old physical register can be released, which greatly affects the use of physical register resources and reduces the work efficiency of the processor. Summary of the invention

[0007] In view of the problems in the prior art, the present invention provides a processor for superscalar processing and an operating method thereof, which can efficiently optimize the renaming and release process of registers, thereby improving the performance and resource utilization of the processor.

[0008] According to one aspect of the present invention, there is provided an operation method of a processor for superscalar processing, the processor comprising: a RAT manager, for managing a RAT, the RAT storing a mapping relationship between a logical register and a physical register; a bit matrix manager, for managing a bit matrix, the rows and columns of the bit matrix indicating logical registers, the coordinate values ​​of the rows and columns of the bit matrix having a first value or a second value, the first value indicating that the logical registers indicated by the corresponding rows and columns are repeatedly mapped to the same physical register, and the second value indicating that the logical registers indicated by the corresponding rows and columns are not mapped to the same physical register; and a controller, which is communicatively connected with the RAT manager and the bit matrix manager and is used to control the operation of the RAT manager and the bit matrix manager; wherein the method comprises: in a renaming phase of an instruction, controlling the RAT manager to query the RAT according to the destination logical register indicated by the instruction to determine the physical register corresponding to the destination logical register in the RAT; controlling the bit matrix manager to query the bit matrix according to the destination logical register indicated by the instruction to determine the coordinate value related to the destination logical register in the bit matrix; and determining whether the physical register corresponding to the destination logical register can be released based on the determination result of the bit matrix manager.

[0009] Further, based on the determination result of the bit matrix manager, determining whether the physical register corresponding to the destination logical register can be released includes: when the determination result indicates that at least one of the coordinate values ​​related to the destination logical register in the bit matrix has a first value, determining that the physical register corresponding to the destination logical register cannot be released; or when the determination result indicates that all of the coordinate values ​​related to the destination logical register in the bit matrix have a second value, determining that the physical register corresponding to the destination logical register can be released.

[0010] Furthermore, the method further includes: after the instruction is renamed, controlling the RAT manager to update the mapping relationship related to the destination logical register in the RAT; controlling the bit matrix manager to update the coordinate value related to the destination logical register in the bit matrix.

[0011] Further, controlling the RAT manager to update the mapping relationship related to the destination logical register in the RAT includes: when the instruction is a non-move instruction, controlling the RAT manager to map the destination logical register to a newly allocated physical register to update the RAT.

[0012] Further, controlling the RAT manager to update the mapping relationship related to the destination logical register in the RAT includes: when the instruction is a move instruction, controlling the RAT manager to map the destination logical register to an existing allocated physical register to update the RAT.

[0013] Further, controlling the bit matrix manager to update the coordinate values ​​related to the destination logical register in the bit matrix includes: when the instruction is a non-move instruction, controlling the bit matrix manager to update all the coordinate values ​​related to the destination logical register in the bit matrix to the second value.

[0014] Furthermore, controlling the bit matrix manager to update the coordinate values ​​associated with the destination logical register in the bit matrix includes: when the instruction is a move instruction, controlling the bit matrix manager to update one of the coordinate values ​​associated with the destination logical register in the bit matrix to a first value, and updating the remaining coordinate values ​​to coordinate values ​​determined based on the source logical register indicated by the instruction.

[0015] According to one aspect of the present invention, a processor for superscalar processing is provided, comprising: a RAT manager, for managing a RAT, the RAT storing a mapping relationship between a logical register and a physical register; a bit matrix manager, for managing a bit matrix, the rows and columns of the bit matrix indicating logical registers, the coordinate values ​​of the rows and columns of the bit matrix having a first value or a second value, the first value indicating that the logical registers indicated by the corresponding rows and columns are repeatedly mapped to the same physical register, and the second value indicating that the logical registers indicated by the corresponding rows and columns are not mapped to the same physical register; and a controller, connected to the RAT manager and the bit matrix manager, and used to control the operations of the RAT manager and the bit matrix manager; wherein, in the renaming phase of an instruction, the controller: controls the RAT manager to query the RAT according to the destination logical register indicated by the instruction to determine the physical register corresponding to the destination logical register in the RAT; controls the bit matrix manager to query the bit matrix according to the destination logical register indicated by the instruction to determine the coordinate value related to the destination logical register in the bit matrix; and determines whether the physical register corresponding to the destination logical register can be released based on the determination result of the bit matrix manager.

[0016] According to one aspect of the present invention, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the operating method of the processor for superscalar processing are implemented.

[0017] According to one aspect of the present invention, a non-transitory computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the operating method of the processor for superscalar processing are implemented as described above.

[0018] According to an embodiment of the present invention, a processor for superscalar processing and an operating method thereof are provided, which can quickly determine whether a physical register is repeatedly mapped, thereby determining whether it can be released, thereby improving the performance and resource utilization of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The description herein refers to the drawings, wherein like reference numerals refer to like parts throughout.

[0020] Figure 1 FIG. 4 is a schematic diagram of a configuration of a processor for superscalar processing according to an embodiment of the present invention.

[0021] Figure 2 The figure is a flowchart of an operating method of a processor according to an embodiment of the present invention.

[0022] Figure 3 FIG. 4 is a schematic diagram of a configuration of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] Various embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, the elements and features of the present invention may be configured or arranged in different ways to form other embodiments, which may be variations of any disclosed embodiment.

[0024] In the present invention, the terms "comprises", "includes", "has" and "contains" are open-ended. As used in the appended claims, these terms specify the presence of the elements described but do not exclude the presence or addition of one or more other elements. The terms of the claims do not exclude that the device includes additional components, such as interface units, circuits, etc.

[0025] The embodiments will now be described with reference to the drawings, wherein like reference numerals refer to like elements.

[0026] Figure 1 FIG. 1 is a schematic diagram of a configuration of a processor 100 for superscalar processing according to an embodiment of the present invention.

[0027] Reference Figure 1 , the processor 100 may include a RAT manager 110 , a Group bit matrix manager 120 , and a controller 130 .

[0028] The RAT manager 110 may be configured to manage the RAT, such as querying and updating the RAT.

[0029] The RAT may be configured to store a mapping relationship between a logical register and a physical register. In an example, one logical register may be mapped to one physical register, or multiple logical registers may be mapped to one physical register (repeated mapping).

[0030] For ease of description, the structure of the RAT is described below by taking four logical registers and four physical registers as an example.

[0031] Table 1 Example RAT

[0032] Among them, logical registers a0 and a1 are mapped to different physical registers p1 and p2 respectively, and logical registers a2 and a3 are mapped to physical register p3 together (ie, repeated mapping).

[0033] Through the RAT, the RAT manager 110 can quickly determine the physical registers corresponding to the logical registers.

[0034] The Group bit matrix manager 120 may be configured to manage the Group bit matrix, for example, query and update the Group bit matrix.

[0035] When there are n (n is an integer) logical registers, a Group bit matrix implemented by n×n / 2 bit registers can be constructed, that is, half of the n×n matrix.

[0036] The rows and columns of the Group bit matrix may represent logical registers respectively, and the values ​​indicated by the rows and columns (coordinate values ​​of the rows and columns) may represent whether the logical registers indicated by the row and the column are mapped to the same physical register.

[0037] For ease of description, the following uses 4 logic registers as an example to illustrate the construction of the Group bit matrix. When there are 4 logic registers (a0, a1, a2, and a3), a Group bit matrix implemented by 4×4 / 2=8-bit registers can be constructed, as shown below: Table 2 Example Group bit matrix

[0038] Among them, the values ​​indicated by the rows and columns of the matrix (the coordinate values ​​of the rows and columns) may be different. For example, the value (coordinate value) indicated by row a0 and column a3, i.e. ((a0, a3)), is 0, and the value (coordinate value) indicated by row a1 and column a3, i.e. ((a1, a3)), is 1. As described above, the coordinate value may indicate whether the logical registers indicated by the corresponding row and column are mapped to the same physical register. Taking "0" as an example indicating mapping to the same physical register and "1" as an example indicating not mapping to the same physical register, the value of (a0, a3) being 0 may indicate that the logical registers a0 and a3 are mapped to the same physical register. Similarly, the value of (a1, a3) being 1 may indicate that the logical registers a1 and a3 are not mapped to the same physical register.

[0039] Through the Group bit matrix, the Group bit matrix manager 120 can quickly determine whether there is a duplicate mapping between a logical register and other logical registers by querying the value of the coordinate related to the logical register, thereby determining whether the physical register corresponding to the logical register can be released.

[0040] For example, in order to determine whether the physical register corresponding to the logical register a0 can be released, the Group bit matrix manager 120 can query the coordinate value related to the logical register a0 in the Group bit matrix. In this example, the coordinate values ​​related to the logical register a0 include the value "1" of (a0, a0), the value "1" of (a0, a1), the value "1" of (a0, a2), and the value "0" of (a0, a3). Since the value "1" indicates that there is no duplicate mapping, it can be indicated that the logical register a0 does not have a duplicate mapping with the logical registers a1 and a2; and the value "0" indicates that there is a duplicate mapping, which can indicate that the logical register a0 has a duplicate mapping with the logical register a3. Since there is a duplicate mapping between the logical register a0 and the other logical register a3, the physical register corresponding to the logical register a0 cannot be released.

[0041] The controller 130 may be communicatively coupled with the RAT manager 110 and the group bit matrix manager 120 , and the controller 130 may control operations of the RAT manager 110 and the group bit matrix manager 120 .

[0042] For example, in the renaming phase, the controller 130 may control the RAT manager 110 to query the physical register corresponding to the logical register in the RAT according to the logical register indicated by the instruction, and may control the Group bit matrix manager 120 to query the coordinate value related to the logical register in the Group bit matrix according to the logical register indicated by the instruction.

[0043] For example, after the instruction is renamed, the controller 130 can control the RAT manager 110 to query the physical register corresponding to the logical register in the RAT according to the logical register indicated by the instruction, and can control the Group bit matrix manager 120 to query the coordinate value related to the logical register in the Group bit matrix according to the logical register indicated by the instruction, and can determine whether the physical register corresponding to the logical register can be released based on the query result of the Group bit matrix manager 120.

[0044] For another example, after the instruction is renamed, the controller 130 may control the RAT manager 110 to update the mapping relationship related to the logical register in the RAT, and may control the Group bit matrix manager to update the coordinate value related to the logical register in the Group bit matrix.

[0045] Figure 2 The figure is a flowchart of an operating method of a processor according to an embodiment of the present invention.

[0046] Reference Figure 2 , the operating method of the processor according to an embodiment of the present invention comprises the following steps: Step S201: In the renaming phase, the RAT manager is controlled to query the RAT according to the logical register indicated by the instruction to determine the physical register in the RAT corresponding to the logical register; Step S203: The Group bit matrix manager is controlled to query the Group bit matrix according to the logical register indicated by the instruction to determine the coordinate value related to the logical register in the Group bit matrix; Step S205: Based on the determination result of the Group bit matrix manager, it is determined whether the physical register corresponding to the logical register can be released.

[0047] Hereinafter, the operation method of the processor is described by taking the logic registers a0, a1, a2, and a3 as examples.

[0048] During initialization, all logical registers a0, a1, a2, and a3 are mapped to physical register p0. This process is similar to executing (move, a1, a0, move a2, a0, move a3, a0).

[0049] The initialized RAT bit matrix is ​​as shown in Table 3: Table 3 Initialization RAT bit matrix

[0050] Among them, a0 is repeatedly mapped to the same physical register as a1, a2, and a3.

[0051] The initialized RAT is as shown in Table 4: Table 4 Initialization RAT

[0052] Among them, a0, a1, a2, and a3 are all mapped to the same physical register p0.

[0053] In the present invention, the following strategy can be used to update the coordinate points of the matrix.

[0054] for(row = 0, row<4; row++){ for (colum = 0, colum<4; colum++){ if (row>colum) { (colum, row)} else { (row, column) } } } For example, (1) when an instruction requires a destination register, the destination logical register is used to determine the update coordinate point. For example, a1 requires a destination register, and a1 is not a move, so the coordinate points that a1 needs to update are (1, 0), (1, 1), (1, 2), (1, 3); (2) Coordinate point optimization, when the row is larger than the column, convert (row coordinate, column coordinate) into (column coordinate, row coordinate). The coordinates actually updated in (1) are (0, 1), (1, 1), (1, 2), (1, 3).

[0055] As mentioned above, the horizontal axis (row coordinate) and the vertical axis (ordinate coordinate) represent the logical register, and the value corresponding to the coordinate point indicates whether two different logical registers are mapped to the same physical register. In the example, the coordinate value 0 indicates existence, and the coordinate value 1 indicates non-existence.

[0056] As described above, the Group bit matrix is ​​constructed as half of the normal matrix, that is, the coordinate points of the upper half (bold part) are actually used (that is, the registers actually used), as shown in Table 5 below.

[0057] Table 5 Example matrix coordinates

[0058] In the present invention, a register mapping history relationship record table may also be used to record all renaming mapping relationships carried after renaming, as shown in Table 6 below.

[0059] Table 6 Example mapping relationship record table

[0060] Among them, index represents the instruction number, new-pdest represents the new physical register number, old-pdest represents the old physical register number, canRelease represents whether it can be released, value 1 represents it can be released, value 0 represents it cannot be released, and the "canRelease" signal is generated in the rename stage, and is saved to rob along with the pipeline. It is used to generate the release mask value of Freelist deqPtr in the instruction submission stage, where Rob (recoder buffer) is used for instruction scheduling and result reordering structure, and Freelist deqPtr is used in the submission stage to determine whether the old physical register can be released.

[0061] In the present invention, Freelist can also be used to maintain read and write pointers. The Freelist is a queue maintained by an allocation pointer (allocPtr) and a recycle pointer (recyclePtr). The queue stores the numbers of physical registers. In the renaming phase, the queue is read according to allpcPtr to obtain free physical registers, and recyclePtr is used as the write update address in the instruction submission phase.

[0062] It is worth noting that the default value of the Group bit matrix is ​​the RAT bit matrix, and the update of the Group bit matrix belongs to serial logic, which is renamed one by one, but there is no need to wait for the physical register number. It can be updated using isMove and the logical register number. Among them, isMove is determined in the decode stage and is a control signal of the move instruction attribute.

[0063] For example, the first instruction requires the 0th instruction to update the Group bit matrix, and the second instruction requires the 0th and 1st instructions to update the Group bit matrix, that is, each instruction needs to wait until the previous instructions are updated.

[0064] For example, for a move instruction, the source logic register is used to read the Group bit matrix (based on the transfer characteristics of the move), and then the bits are different from the update mask to obtain the final updated result.

[0065] For example, for non-move instructions, all coordinate points determined by the index of the destination logical register are directly updated to "1" because for non-move instructions, the physical register is newly allocated, so there must be no duplication with other logical registers.

[0066] (1.1) Cycle_0 executes the initialization procedure, as shown in Table 7: Table 7 Initialization program instructions

[0067] Among them, index represents the instruction number, and index 0-4 corresponds to different instructions respectively.

[0068] (1.2) Update the Group bit matrix: The Group bit matrix is ​​a wire (wire network type signal), and its default assignment comes from the RAT bit matrix (as shown in Table 3), and some updates come from the update of the rename stage 112 stage.

[0069] Since the instruction at index 0 is not a move instruction, a new physical register needs to be allocated, and the mapping relationship is from (a0, p0) -> (a0, p1); the instruction at index 1 is not a move instruction, and a new physical register needs to be allocated, and the mapping relationship is from (a1, p0) -> (a1, p2); the instruction at index 2 is not a move instruction, and a new physical register needs to be allocated, and the mapping relationship is from (a2, p0) -> (a2, p3); the instruction at index 3 is not a move instruction, and a new physical register needs to be allocated, and the mapping relationship is from (a3, p0) -> (a3, p4).

[0070] The Group bit matrix is ​​updated as shown in Table 8: Table 8 Group bit matrix update results

[0071] For non-move instructions, new physical registers need to be allocated. Since the physical registers are newly allocated, there can be no duplicate mapping. Therefore, all coordinate values ​​of a0, a1, a2, and a3 are updated to "1".

[0072] (1.3) Update the RAT bit matrix: The updated Group bit matrix is ​​assigned to the RAT bit matrix (the RAT bit matrix is ​​updated in this way below), and the updated RAT bit matrix is ​​as shown in Table 9: Table 9 RAT bit matrix update results

[0073] (1.4) Update RAT as shown in Table 10 below: Table 10 RAT update results

[0074] Since none of the instructions shown in Table 7 are move instructions, new physical registers are allocated, and the logical registers indicated by the instructions in the RAT are mapped to the newly allocated physical registers. For example, the physical register to which the logical register a0 indicated by the instruction lui a0 1 is mapped is changed from the original physical register p0 to p1, the physical register to which the logical register a1 indicated by the instruction lui a1 2 is mapped is changed from the original physical register p0 to p2, the physical register to which the logical register a2 indicated by the instruction lui a2 3 is mapped is changed from the original physical register p0 to p3, and the physical register to which the logical register a0 indicated by the instruction lui a0 1 is mapped is changed from the original physical register p0 to p4.

[0075] (1.5) Update the rename mapping as follows:

[0076] Among them, index represents the instruction number, new-pdest represents the new physical register number, old-pdest represents the old physical register number, canRelease represents whether it can be released, 1 represents it can be released, and 0 represents it cannot be released.

[0077] (1.6) Update the Freelist as shown in Table 11 below: Table 11 Freelist update results

[0078] Among them, allocptr indicates the physical register p5.

[0079] (2.1) cycle_1 executes the instruction move a1 a0: As mentioned above, since move a1, a0 is a move instruction, no new physical register will be allocated. Instead, the physical register mapped to a1 will be updated to the physical register mapped to a0, and it will be determined whether there is a duplicate mapping of the physical register currently mapped to a1, thereby determining whether the physical register can be released.

[0080] (2.2) Query RAT: Based on the move a1, a0 instruction, by querying a1 and a0 in the above Table 10, it can be known that the physical register mapped to a1 is p2, and the physical register mapped to a0 is p1.

[0081] (2.3) Query the Group bit matrix: Based on the move a1, a0 instruction, by querying a1 in the above Table 8, it can be known that the coordinates related to a1 and their corresponding values ​​are ((a0, a1), 1), ((a1, a1), 1), ((a1, a2), 1), ((a1, a3), 1), that is, the coordinate values ​​determined by a1 and other logical registers (for example, a0, a2, a3) are all "1", that is, there is no repeated mapping between a1 and other logical registers, and the physical register corresponding to a1 can be released.

[0082] Specifically, the coordinate points (0, 1), (1, 1), (1, 2), (1, 3) in the Group bit matrix can be read by index address 1 (a1); a1-canRelease (i.e., whether the physical register corresponding to a1 can be released) = (0, 1) & (1, 1) & (1, 2) & (1, 3) = 1 & 1 & 1 & 1 = 1 (1 means there is no duplicate mapping). That is, the physical register corresponding to a1 can be released.

[0083] Combined with the result of querying RAT in (2.2), we can know that the physical register corresponding to a1 is p2, so it can be determined that p2 can be released.

[0084] (2.4) Update the Group bit matrix: Based on the move a1, a0 instruction, the physical register p1 to which a0 is mapped is assigned to a1, so after execution, a1 and a0 will be mapped to the physical register p1 together, that is, after execution, a1 and a0 will have duplicate mapping. Therefore, the coordinate value of the coordinate (a0, a1) among the coordinates (a0, a1), (a1, a1), (a1, a2), (a1, a3) of a1 in the Group bit matrix needs to be updated to "0", and the other coordinates (including (a1, a1), (a1, a2), (a1, a3) except the coordinate (a0, a1) among (a0, a1), (a1, a1), (a1, a2), (a1, a3) need to be updated to the coordinate value determined based on the source logical register a0 (updated to "1" in this example) (the following will be explained in conjunction with the transitivity of the move instruction).

[0085] The updated Group bit matrix is ​​shown in Table 12 below: Table 12 Group bit matrix update results

[0086] Among them, the value of the coordinate (a0, a1) is "0", and the values ​​of the coordinates (a1, a1), (a1, a2), and (a1, a3) are "1".

[0087] Specifically, the Group bit matrix may be updated by referring to the following steps in combination with the transitivity of the move instruction.

[0088] Note that the dependency of the move-optimized pdes (destination physical register) is transitive, for example, the physical register is transferred. In the present invention, the dependency determined by the bit matrix is ​​added. And as mentioned above, the bit matrix is ​​optimized, that is, only half of the normal matrix is ​​used, and the coordinates with rows larger than columns are converted to (columns, rows).

[0089] The RAT bit matrix is ​​a hardware resource, similar to a physical register. For the move a1, a0 instruction, the matrix relationship mapped by a0 needs to be passed to a1.

[0090] a. Similar to the transfer of physical registers, the move instruction uses the source logical register a0 to read the RAT and obtain the physical register p1.

[0091] b. Similarly, the move instruction uses the source logical register a0 to read the bit matrix. Accordingly, the coordinates read are (a0, a0), (a0, a1), (a0, a2), and (a0, a3).

[0092] c. Determine the read value through b; determine the coordinate points (a0, a1), (a1, a1), (a1, a2), (a1, a3) of the read bit matrix based on the destination logic register a1, that is, the coordinate address of the write update bit matrix.

[0093] d. Through b, the read coordinate points and coordinate values ​​obtained due to "transitivity" are determined, and the corresponding relationships are ((a0, a0), 1), ((a0, a1), 1), ((a0, a2), 1), ((a0, a3), 1).

[0094] e. Since the move a1, a0 instruction is a move instruction, after the instruction is renamed, a0 and a1 will be repeatedly mapped to the physical register. Therefore, the value of the coordinate point (a1, a0) in the bit matrix needs to be updated to "0" (indicating that there is repeated mapping).

[0095] f. Based on c and e, the coordinate points to be updated are determined based on the logic register a1, and the corresponding mapping relationships and mapping values ​​are ((a0, a1), 1), ((a1, a1), 0), ((a1, a2), 0), ((a1, a3), 0).

[0096] g. Based on d and f, based on the mapping relationship brought by "transitivity" and the mapping relationship that needs to be updated due to move optimization, the two mask bits are XORed to obtain the updated coordinate value.

[0097] h. Based on g, determine the updated coordinate points and updated coordinate values ​​as ((a0, a1), 0), ((a1, a1), 1), ((a1, a2), 1), ((a1, a3), 1).

[0098] The method described in reference ah above can be simplified into the following steps: (1): Use index 0 (a0) to read the Group bit matrix. The coordinate points and values ​​are (0, 0), (0, 1), (0, 2), (0, 3) = (1, 1, 1, 1).

[0099] (2): The coordinate point relationship corresponding to the read data (1, 1, 1, 1) is (a1, a0), (a1, a1), (a1, a2) and (a1, a3).

[0100] (3): The coordinate points and values ​​of the mask to be updated are (abscissa, ordinate, value) -> (a1, a0, 1), (a1, a1, 0), (a1, a2, 0), (a1, a3, 0).

[0101] (4): Perform bitwise XOR operation on the masks of (1) and (3), (1, 1, 1, 1) ^ (1, 0, 0, 0) => (0, 1, 1, 1).

[0102] (5): Update the result of (4) according to the coordinate points of (a1, a0), (a1, a1), (a1, a2), (a1, a3). The actual corresponding coordinate points and values ​​(horizontal coordinate, vertical coordinate, value) -> ((0, 1, 0), (1, 1, 1), (1, 2, 1), (1, 3, 1)). That is, the updated coordinate points and updated coordinate values ​​are ((a0, a1), 0), ((a1, a1), 1), ((a1, a2), 1), ((a1, a3), 1).

[0103] (2.5) Update RAT: Based on the results of querying RAT above (2.2), it can be seen that the physical register mapped to a1 is p2, and the physical register mapped to a0 is p1; based on the move a1, a0 instruction, the physical register p2 mapped to a1 is updated to p1. The update results are shown in Table 13 below: Table 13 RAT update results

[0104] Among them, after updating, the physical register to which a1 is mapped is p1.

[0105] (2.6) Update the mapping history relationship record table, as shown in Table 14 below: Table 14 Mapping history relationship record table

[0106] Among them, for the instruction of index 4 (ie, move a1, a0), the old physical register is p2, the new physical register is p1, and canRelease "1" indicates that the physical register can be released.

[0107] (2.7) Update the Freelist as shown in Table 15 below: Table 15 Freelist update results

[0108] Among them, allocptr indicates the physical register p5.

[0109] (3.1) cycle_2 executes instruction add a1, a0 imm: Since add a1, a0 imm is a non-move instruction, a new physical register will be allocated, a1 will be mapped to the newly allocated physical register, and it will be determined whether there is a duplicate mapping of the physical register currently mapped to a1, so as to determine whether the physical register can be released.

[0110] (3.2) Query RAT: Based on the add a1, a0 imm instruction, by querying a1 in the above Table 13, it can be known that the physical register mapped to a1 is p1.

[0111] (3.3) Query the Group bit matrix: Based on the add a1, a0 imm instruction, by querying a1 in the above Table 12, it can be known that the coordinates related to a1 and their corresponding values ​​are ((a0, a1), 0), ((a1, a1), 1), ((a1, a2), 1), ((a1, a3), 1), that is, the coordinate values ​​determined by a1, a2 and a3 are all "1", that is, there is no repeated mapping between a1 and a2 and a3, but the coordinate values ​​determined by a1 and a0 are "0", that is, there is a repeated mapping between a1 and a0, and the physical register corresponding to a1 cannot be released.

[0112] Specifically, the coordinate points (0, 1), (1, 1), (1, 2), (1, 3) in the Group bit matrix can be read through the index address 1 (a1); a1-canRelease (i.e., whether the physical register corresponding to a1 can be released) = (0, 1) & (1, 1) & (1, 2) & (1, 3) = 0 & 1 & 1 & 1 = 0 (0 indicates that there is a duplicate mapping). That is, the physical register corresponding to a1 cannot be released.

[0113] Combined with the result of querying RAT in (3.2), we can know that the physical register corresponding to a1 is p1, so it can be determined that p1 cannot be released.

[0114] (3.4) Update the Group bit matrix: Since the add a1, a0 imm instruction is a non-move instruction, a new physical register will be allocated. Since the physical register is newly allocated, only a1 will be mapped to the newly allocated physical register, and other logical registers cannot map the newly allocated physical register, so there is no duplicate mapping. That is, the coordinate values ​​of the coordinates (a0, a1), (a1, a1), (a1, a2), and (a1, a3) related to a1 in the Group bit matrix can all be updated to "1". The updated Group bit matrix is ​​shown in Table 16 below: Table 16 Group bit matrix update results

[0115] Among them, the coordinate values ​​of the coordinates (a0, a1), (a1, a1), (a1, a2), and (a1, a3) related to a1 are all updated to "1".

[0116] (3.5) Update RAT: Based on the result of querying RAT in (3.2) above, it can be known that the physical register to which a1 is mapped is p1; based on the add a1, a0imm instruction, a1 is mapped to the newly allocated physical register (for example, p5). The update results are shown in Table 17 below: Table 17 RAT update results

[0117] Among them, after updating, the physical register to which a1 is mapped is p5.

[0118] (3.6) Update the mapping history relationship record table, as shown in Table 18 below: Table 18 Mapping history relationship record table

[0119] Among them, for the instruction with index 5 (i.e., add a1, a0 imm), the old physical register is p1, the new physical register is p1, and canRelease "0" indicates that the physical register cannot be released.

[0120] (3.7) Update the Freelist as shown in Table 19 below: Table 19 Freelist update results

[0121] Among them, allocptr indicates the physical register p6.

[0122] The above example shows that a single instruction is renamed. In the renaming stage, the RAT is queried according to the logical register indicated by the instruction to determine the physical register corresponding to the logical register in the RAT; the Group bit matrix is ​​queried according to the logical register indicated by the instruction to determine the coordinate value related to the logical register in the Group bit matrix; based on the determination result of the Group bit matrix manager, it is determined whether the physical register corresponding to the logical register can be released. In addition, after the instruction is renamed, the mapping relationship related to the logical register in the RAT is updated; the coordinate value related to the logical register in the Group bit matrix is ​​updated.

[0123] The following illustrates a situation where a group of instructions enter renaming at the same time. For ease of description, an example is given where a group of instructions includes 4 instructions.

[0124] Assume that a set of instructions contains 4 instructions, including move instructions and non-move instructions, as shown in Table 20 below: Table 20 Command Description

[0125] Among them, index 0-4 corresponds to different instructions respectively. The instructions corresponding to index 0, index 1, and index 3 are non-move instructions, and the instruction corresponding to index 2 is a move instruction. For non-move instructions, new physical registers need to be allocated; for move instructions, new physical registers do not need to be allocated, but the physical registers corresponding to the source logical registers are used.

[0126] Assume that the RAT before the execution of this group of instructions is as shown in Table 21.

[0127] Table 21 RAT

[0128] Among them, logical registers a0, a1, a2, and a3 correspond to physical registers p1-p4 respectively.

[0129] In combination with the above Table 21, it can be seen that the RAT bit matrix before the execution of this group of instructions is shown in the following Table 22.

[0130] Table 22 RAT bit matrix

[0131] According to Table 21, the logical registers a0, a1, a2, and a3 are mapped to different physical registers p1, p2, p3, and p4, respectively. In Table 22, all coordinate values ​​associated with these logical registers are "1".

[0132] Each instruction in this group of instructions is described separately below.

[0133] (4.1) The first instruction add a2, a1, a0: Since add a2, a1, a0 is a non-move instruction, a new physical register will be allocated, a2 will be mapped to the newly allocated physical register, and it will be determined whether there is a duplicate mapping of the physical register currently mapped to a2, so as to determine whether the physical register can be released.

[0134] (4.2) Query RAT: Based on the add a2, a1, a0 instruction, by querying a2 in the above Table 21, it can be known that the physical register mapped to a2 is p3.

[0135] (4.3) Query the Group bit matrix: Based on the add a2, a1, a0 instruction, query whether the physical register corresponding to a2 can be released in the above Table 22, and combine it with the query result of (4.2), as shown in Table 23.

[0136] Table 23 Group bit matrix query information

[0137] It can be determined that the logical register a2 is not repeatedly mapped to the same physical register as other logical registers, and the physical register p3 corresponding to the logical register a2 can be released.

[0138] (4.4) Update the Group bit matrix: Since the add a2, a1, a0 instruction is a non-move instruction, a new physical register will be allocated. Since the physical register is newly allocated, only a2 will be mapped to the newly allocated physical register, and other logical registers cannot map the newly allocated physical register, so there is no duplicate mapping. That is, the coordinate values ​​of the coordinates (a0, a2), (a1, a2), (a2, a2), and (a2, a3) related to a2 in the Group bit matrix can all be updated to "1". The updated Group bit matrix is ​​shown in Table 24 below: Table 24 Group bit matrix update results

[0139] Among them, the coordinate values ​​of the coordinates (a0, a2), (a1, a2), (a2, a2), and (a2, a3) related to a2 are all updated to "1".

[0140] (4.5) Update RAT: Based on the result of querying RAT above (4.2), it can be known that the physical register to which a2 is mapped is p3; based on the add a2, a1, a0 instruction, a2 is mapped to the newly allocated physical register (for example, p5). The update results are shown in Table 25 below: Table 25 RAT update results

[0141] Among them, after updating, the physical register mapped to by a2 is p5.

[0142] (4.6) Update the mapping history relationship record table, as shown in Table 26 below: Table 26 Mapping history relationship record table

[0143] Among them, for the instruction with index 0 (i.e., add a2, a1, a0), the old physical register is p3, the new physical register is p5, and canRelease "1" indicates that the physical register p3 can be released.

[0144] (5.1) The second instruction add a3, a2, a0: Since add a3, a2, a0 is a non-move instruction, a new physical register will be allocated, a3 will be mapped to the newly allocated physical register, and it will be determined whether there is a duplicate mapping of the physical register currently mapped to a3, so as to determine whether the physical register can be released.

[0145] (5.2) Query RAT: Based on the add a3, a2, a0 instruction, by querying a3 in the above Table 25, it can be known that the physical register mapped to a3 is p4.

[0146] (5.3) Query the Group bit matrix: Based on the add a3, a2, a0 instruction, query whether the physical register corresponding to a3 can be released in the above Table 24, and combine it with the query result of (5.2), as shown in Table 27.

[0147] Table 27 Group bit matrix query information

[0148] It can be determined that the logical register a3 is not repeatedly mapped to the same physical register as other logical registers, and the physical register p4 corresponding to the logical register a3 can be released.

[0149] (5.4) Update the Group bit matrix: Since the add a3, a2, a0 instruction is a non-move instruction, a new physical register will be allocated. Since the physical register is newly allocated, only a3 will be mapped to the newly allocated physical register, and other logical registers cannot map the newly allocated physical register, so there is no duplicate mapping. That is, the coordinate values ​​of the coordinates (a0, a3), (a1, a3), (a2, a3), (a2, a3) related to a3 in the Group bit matrix can all be updated to "1". The updated Group bit matrix is ​​shown in Table 28 below: Table 28 Group bit matrix update results

[0150] Among them, the coordinate values ​​of the coordinates (a0, a3), (a1, a3), (a2, a3), and (a2, a3) related to a3 are all updated to "1".

[0151] (5.5) Update RAT: Based on the result of querying RAT in (5.2) above, it can be known that the physical register to which a3 is mapped is p4; based on the add a3, a2, a0 instruction, a3 is mapped to the newly allocated physical register (for example, p6). The update results are shown in Table 29 below: Table 29 RAT update results

[0152] Among them, after updating, the physical register mapped to by a3 is p6.

[0153] (5.6) Update the mapping history relationship record table, as shown in Table 30 below: Table 30 Mapping history relationship record table

[0154] Among them, for the instruction of index 1 (ie, add a2, a1, a0), the old physical register is p4, the new physical register is p6, and canRelease "1" indicates that the physical register p4 can be released.

[0155] (6.1) The third instruction move a2, a0: Since move a2, a0 is a move instruction, no new physical register will be allocated. It will only update the physical register mapped to a2 to the physical register mapped to a0, and determine whether there is a duplicate mapping of the physical register currently mapped to a2, so as to determine whether the physical register can be released.

[0156] (6.2) Query RAT: Based on the move a2, a0 instruction, by querying a2 and a0 in the above Table 29, it can be known that the physical register mapped to a2 is p5, and the physical register mapped to a0 is p1.

[0157] (6.3) Query the Group bit matrix: Based on the move a2, a0 instruction, query whether the physical register corresponding to a2 can be released in the above Table 28, and combine it with the query result of (6.2), as shown in Table 31.

[0158] Table 31 Group bit matrix query information

[0159] It can be determined that the logical register a2 is not repeatedly mapped to the same physical register as other logical registers, and the physical register p5 corresponding to the logical register a2 can be released.

[0160] (6.4) Update the Group bit matrix: Since the move a2, a0 instruction is a move instruction, based on the transitivity of the move instruction, the value of the coordinate (a0, a2) among the coordinates (a0, a2), (a1, a2), (a2, a2), (a2, a3) related to a2 in the Group bit matrix is ​​updated to "0", and the values ​​of the coordinates (a1, a2), (a2, a2), (a2, a3) among (a0, a2), (a1, a2), (a2, a2), (a2, a3) are updated to the coordinate value "1" determined based on the source logic register a0 (the previous part of this article shows an example of updating the coordinates based on the transitivity of the move instruction, and the process is not repeated here). The updated Group bit matrix is ​​shown in Table 32 below: Table 32 Group bit matrix update results

[0161] Among them, the coordinate values ​​of the coordinate (a0, a2) related to a2 are all updated to "0", and the values ​​of the coordinates (a1, a2), (a2, a2), and (a2, a3) related to a2 are updated to "1".

[0162] (6.5) Update RAT: Based on the results of querying RAT above (6.2), it can be seen that the physical register mapped to a2 is p5, and the physical register mapped to a0 is p1; based on the move a2, a0 instruction, a2 is mapped to p1. The update results are shown in Table 33 below: Table 33 RAT update results

[0163] Among them, after updating, the physical register that a2 is mapped to is p1.

[0164] (6.6) Update the mapping history relationship record table, as shown in Table 34 below: Table 34 Mapping history relationship record table

[0165] Among them, for the instruction of index 2 (ie, move a2, a0), the old physical register is p5, the new physical register is p1, and canRelease "1" indicates that the physical register p5 can be released.

[0166] (7.1) The fourth instruction addi, a2, a0, 2: Since addi,a2,a0,2 is a non-move instruction, a new physical register will be allocated, a2 will be mapped to the newly allocated physical register, and it will be determined whether there is a duplicate mapping of the physical register currently mapped to a2, so as to determine whether the physical register can be released.

[0167] (7.2) Query RAT: Based on the addi, a2, a0, 2 instruction, by querying a2 in the above Table 33, it can be known that the physical register mapped to a2 is p1.

[0168] (7.3) Query the Group bit matrix: Based on the addi, a2, a0, 2 instruction, query whether the physical register corresponding to a2 can be released in the above Table 32, and combine it with the query result of (7.2), as shown in Table 35.

[0169] Table 35 Group bit matrix query information

[0170] It can be determined that the logical register a2 and other logical registers are repeatedly mapped to the same physical register, and the physical register p1 corresponding to the logical register a2 cannot be released.

[0171] (7.4) Update the Group bit matrix: Since the addi, a2, a0, 2 instruction is a non-move instruction, a new physical register will be allocated. Since the physical register is newly allocated, only a2 will be mapped to the newly allocated physical register, and other logical registers cannot map the newly allocated physical register, so there is no duplicate mapping. That is, the coordinate values ​​of the coordinates (a0, a2), (a1, a2), (a2, a2), and (a2, a3) related to a2 in the Group bit matrix can all be updated to "1". The updated Group bit matrix is ​​shown in Table 36 below: Table 36 Group bit matrix update results

[0172] Among them, the coordinate values ​​of the coordinates (a0, a2), (a1, a2), (a2, a2), and (a2, a3) related to a2 are all updated to "1".

[0173] (7.5) Update RAT: Based on the result of querying RAT above (7.2), it can be known that the physical register to which a2 is mapped is p1; based on the addi,a2,a0,2 instruction, a2 is mapped to the newly allocated physical register (for example, p7). The update results are shown in the following Table 37: Table 37 RAT update results

[0174] Among them, after updating, the physical register mapped to by a2 is p7.

[0175] (7.6) Update the mapping history relationship record table, as shown in Table 38 below: Table 38 Mapping history relationship record table

[0176] Among them, for the instruction of index 3 (ie, addi, a2, a0, 2), the old physical register is p1, the new physical register is p7, and canRelease "0" indicates that the physical register p1 cannot be released.

[0177] Figure 3 FIG. 1 is a schematic diagram of a configuration of an electronic device according to an embodiment of the present invention. Figure 3As shown, the electronic device may include: a processor 310, a communication interface 320, a memory 330 and a communication bus 340, wherein the processor 310, the communication interface 320 and the memory 330 communicate with each other through the communication bus 340. The processor 310 may call the logic instructions in the memory 330 to execute the steps of the above methods. No further description is given here.

[0178] According to an embodiment of the present invention, a computer program product is also provided, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, and when the program instructions are executed by a computer, the computer can perform the steps of the above methods. No further description is given here.

[0179] According to an embodiment of the present invention, a non-transitory computer-readable storage medium is further provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above methods are implemented, which will not be described in detail here.

[0180] According to an embodiment of the present invention, a processor for superscalar processing and an operating method thereof are provided, which can efficiently optimize the renaming and release process of registers, thereby improving the performance and resource utilization of the processor.

[0181] Although the present teaching has been described with respect to specific embodiments, it is obvious to those skilled in the art that, according to the present invention, various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, the embodiments may be combined to form other embodiments.

Claims

1. A method for operating a processor for superscalar processing, characterized in that: The processor comprises: A RAT manager, configured to manage a RAT, wherein the RAT stores a mapping relationship between a logical register and a physical register; a bit matrix manager, configured to manage a bit matrix, wherein rows and columns of the bit matrix indicate logical registers, and coordinate values ​​of the rows and columns of the bit matrix have a first value or a second value, wherein the first value indicates that the logical registers indicated by the corresponding rows and columns are repeatedly mapped to the same physical register, and the second value indicates that the logical registers indicated by the corresponding rows and columns are not mapped to the same physical register; and A controller is communicatively coupled to the RAT manager and the bit matrix manager and is used to control operations of the RAT manager and the bit matrix manager; wherein the method comprises: In a renaming phase of the instruction, controlling the RAT manager to query the RAT according to the destination logical register indicated by the instruction to determine a physical register in the RAT corresponding to the destination logical register; Control the bit matrix manager to query the bit matrix according to the destination logical register indicated by the instruction to determine the coordinate value related to the destination logical register in the bit matrix; Based on the determination result of the bit matrix manager, it is determined whether the physical register corresponding to the destination logical register can be released.

2. The method for operating a processor for superscalar processing according to claim 1, characterized in that: Based on the determination result of the bit matrix manager, determining whether the physical register corresponding to the destination logical register can be released includes: When the determination result indicates that at least one of the coordinate values ​​associated with the destination logical register in the bit matrix has the first value, determining that the physical register corresponding to the destination logical register cannot be released; or When the determination result indicates that all of the coordinate values ​​associated with the destination logical register in the bit matrix have the second value, it is determined that the physical register corresponding to the destination logical register can be released.

3. The method for operating a processor for superscalar processing according to claim 1, characterized in that: The method further includes: after the instruction is renamed, controlling the RAT manager to update a mapping relationship related to the destination logical register in the RAT; and controlling the bit matrix manager to update a coordinate value related to the destination logical register in the bit matrix.

4. The method for operating a processor for superscalar processing according to claim 3, characterized in that: Controlling the RAT manager to update the mapping relationship related to the destination logical register in the RAT includes: when the instruction is a non-move instruction, controlling the RAT manager to map the destination logical register to a newly allocated physical register to update the RAT.

5. The method for operating a processor for superscalar processing according to claim 4, characterized in that: Controlling the RAT manager to update the mapping relationship related to the destination logical register in the RAT includes: when the instruction is a move instruction, controlling the RAT manager to map the destination logical register to an existing allocated physical register to update the RAT.

6. The method for operating a processor for superscalar processing according to claim 3, characterized in that: Controlling the bit matrix manager to update the coordinate values ​​related to the destination logical register in the bit matrix includes: when the instruction is a non-move instruction, controlling the bit matrix manager to update all the coordinate values ​​related to the destination logical register in the bit matrix to the second value.

7. The method for operating a processor for superscalar processing according to claim 6, characterized in that: Controlling the bit matrix manager to update the coordinate values ​​associated with the destination logical register in the bit matrix includes: when the instruction is a move instruction, controlling the bit matrix manager to update one of the coordinate values ​​associated with the destination logical register in the bit matrix to the first value, and updating the remaining coordinate values ​​to coordinate values ​​determined based on the source logical register indicated by the instruction.

8. A processor for superscalar processing, characterized in that include: A RAT manager, configured to manage a RAT, wherein the RAT stores a mapping relationship between a logical register and a physical register; A bit matrix manager, configured to manage a bit matrix, wherein rows and columns of the bit matrix indicate logical registers, and coordinate values ​​of the rows and columns of the bit matrix have a first value or a second value, wherein the first value indicates that the logical registers indicated by the corresponding rows and columns are repeatedly mapped to the same physical register, and the second value indicates that the logical registers indicated by the corresponding rows and columns are not mapped to the same physical register; as well as A controller connected to the RAT manager and the bit matrix manager and used to control the operations of the RAT manager and the bit matrix manager; wherein, In the renaming phase of the instruction, the controller: controls the RAT manager to query the RAT according to the destination logical register indicated by the instruction to determine the physical register in the RAT corresponding to the destination logical register; controls the bit matrix manager to query the bit matrix according to the destination logical register indicated by the instruction to determine the coordinate value related to the destination logical register in the bit matrix; Based on the determination result of the bit matrix manager, it is determined whether the physical register corresponding to the destination logical register can be released.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the method for operating a processor for superscalar processing according to any one of claims 1 to 7 are implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for operating a processor for superscalar processing according to any one of claims 1 to 7 are implemented.

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