Scheduling method and device, electronic equipment and computer storage medium

Abstract

The embodiment of the invention discloses a scheduling method which comprises the steps of determining an actual scheduling delay value of a target thread under the condition that the target thread is scheduled, and adjusting the priority level of a group where the target thread is located according to the actual scheduling delay value and a target scheduling delay value corresponding to the priority level of the group where the target thread is located. The embodiment of the invention further provides a scheduling device, electronic equipment and a computer storage medium.

Description

Technical Field

[0001] The present application relates to thread scheduling technology, and in particular to a scheduling method, device, electronic device and computer storage medium. Background Art

[0002] In a computer system, the Central Processing Unit (CPU) scheduler is responsible for managing and allocating the execution time of threads.

[0003] In related technologies, CPU scheduling usually relies on static priority settings or some scheduling algorithms to schedule threads. However, this method may cause some threads to be in a low priority state for a long time or fail to guarantee scheduling delay requirements. Summary of the invention

[0004] The embodiments of the present application provide a scheduling method, device, electronic device and computer storage medium, which can meet the scheduling delay of threads.

[0005] The technical solution of this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a scheduling method, including:

[0007] In the case where the target thread is scheduled, determining an actual scheduling delay value of the target thread;

[0008] The priority level of the group to which the target thread belongs is adjusted according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs.

[0009] In a second aspect, an embodiment of the present application provides a scheduling device, including:

[0010] A determination module, used for determining an actual scheduling delay value of the target thread when the target thread is scheduled;

[0011] The scheduling module is used to adjust the priority level of the group where the target thread is located according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group where the target thread is located.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor and a storage medium storing instructions executable by the processor; the storage medium relies on the processor to perform operations through a communication bus, and when the instructions are executed by the processor, the scheduling method described in one or more of the above embodiments is executed.

[0013] In a fourth aspect, an embodiment of the present application provides a computer storage medium storing executable instructions. When the executable instructions are executed by one or more processors, the processors execute the scheduling method described in one or more of the above embodiments.

[0014] The embodiments of the present application provide a scheduling method, an apparatus, an electronic device, and a computer storage medium. When a target thread is scheduled, an actual scheduling delay value of the target thread is determined, and the priority level of the group to which the target thread belongs is adjusted according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs; that is, in the embodiments of the present application, by determining the actual scheduling delay value of the target thread, the priority level of the group to which the target thread belongs is adjusted together with the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, thereby dynamically adjusting the priority level of the target thread through the actual scheduling delay value and the target scheduling delay value, thereby making the actual scheduling delay value of the target thread close to its target scheduling delay value, so as to meet the scheduling delay of the target thread within the set range, thereby providing delay performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A flowchart of an optional scheduling method provided in an embodiment of the present application;

[0016] Figure 2 A flowchart of an example of an optional scheduling method provided in an embodiment of the present application;

[0017] Figure 3 A schematic diagram of thread scheduling in an optional scheduling method provided in an embodiment of the present application;

[0018] Figure 4 A schematic diagram of the structure of an optional scheduling device provided in an embodiment of the present application;

[0019] Figure 5 A schematic diagram of the structure of an optional electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0021] Currently, thread scheduling mainly relies on static priority scheduling algorithms. In this algorithm, each thread or thread group has a predefined priority when scheduling. The CPU scheduler determines the execution order of threads based on these priorities, and usually threads with higher priorities are scheduled first.

[0022] Among them, common scheduling algorithms also include:

[0023] Fair scheduling algorithms, such as the Completely Fair Scheduler (CFS), dynamically adjust the execution time of threads by using a red-black tree data structure, but do not involve a Proportional-Integration-Differential (PID) controller for real-time adjustment.

[0024] Real-time scheduling algorithms, such as Rate Monotonic Scheduling (RMS) and Earliest Deadline First (EDF), are mainly aimed at real-time systems and perform scheduling by setting the period and deadline of tasks.

[0025] However, the above static priority scheduling algorithm cannot dynamically adjust the priority according to the real-time system requirements, resulting in some thread groups being in a low priority state for a long time, lacking flexibility, and thus affecting system performance. The static priority scheduling algorithm and the fair scheduling algorithm cannot ensure that the scheduling delay of a group of threads is within the set range, that is, the delay target cannot be guaranteed, and it is difficult to meet high performance requirements. Real-time scheduling algorithms (such as RMS and EDF) have large computational complexity and increased complexity when processing complex tasks, which increases system overhead and complexity.

[0026] In addition, the above algorithm does not have a control mechanism based on real-time feedback, and cannot effectively adjust the delay during runtime. The lack of feedback mechanism leads to insufficient scheduling flexibility and responsiveness.

[0027] In a computer system, a CPU scheduler is responsible for managing and allocating the execution time of threads. In related technologies, scheduling usually relies on static priority settings, which cannot be dynamically adjusted to meet the latency requirements of thread groups.

[0028] In order to solve the technical problem that the thread scheduling delay cannot be satisfied within a set range, the embodiment of the present application provides a scheduling method. Figure 1 A flowchart of an optional scheduling method provided in an embodiment of the present application is shown as follows: Figure 1 As shown, the scheduling method may include:

[0029] S101: when a target thread is scheduled, determining an actual scheduling delay value of the target thread;

[0030] The execution subject of the scheduling method provided in the embodiment of the present application can be a CPU scheduler or other devices with scheduling functions. Here, the embodiment of the present application does not make specific limitations on this.

[0031] The target thread may be any one of the created threads, or may be a thread selected from the created threads according to a preset rule, and this embodiment of the present application does not specifically limit this.

[0032] In S101 , when the target thread is scheduled, an actual scheduling delay value of the target thread is determined, wherein the scheduling delay refers to the time period from when the thread is scheduled to when it is actually executed.

[0033] Here, the actual scheduling delay value of the target thread can be determined by recording the actual scheduling delay value of the target thread itself, and the actual scheduling delay value of the target thread can also be determined by recording the actual scheduling delay value of the target thread through other devices. Here, the embodiments of the present application do not make specific limitations on this.

[0034] It should be noted that, when the target thread is scheduled, the thread may be scheduled according to a preset priority so that the target thread is scheduled. Of course, the target thread may also be scheduled when other scheduling algorithms are used to schedule the thread. Here, the embodiment of the present application does not make any specific limitation on this.

[0035] S102: adjusting the priority level of the group to which the target thread belongs according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs.

[0036] The actual scheduling delay value of the target thread can be determined through the above S101. Since the target thread also has a group, which is recorded as the group to which the target thread belongs, and each group is set with a priority level, and each priority level corresponds to a target scheduling delay value, then, after knowing the group to which the target thread belongs, the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs can be known.

[0037] It should be noted that the group to which the target thread belongs can determine the priority of the target thread according to the requirements of the tasks in the target thread, thereby determining the target threads with the same priority level as a group, thereby determining the priority level of the group to which the target thread belongs.

[0038] In S102, after knowing the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, the priority level of the group to which the target thread belongs is adjusted according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, so as to adjust the target scheduling delay value corresponding to the group to which the target thread belongs by dynamically adjusting the priority level of the group to which the target thread belongs, so that the target thread and the threads in its group meet the delay requirements.

[0039] Among them, in the above-mentioned adjustment of the priority level of the target thread group according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the target thread group, the adjustment of the priority level of the target thread group can be achieved by using a preset algorithm, or by using set components to achieve the adjustment of the priority level of the target thread group. Here, the embodiments of the present application do not make specific limitations on this.

[0040] In addition, for the above target thread, in an optional embodiment, the above method may further include:

[0041] When a thread is created, the created thread is determined as a target thread.

[0042] It can be understood that when each thread is created, each created thread is determined as a target thread. In this way, each thread created is used as a target thread, that is, each thread is determined as a target thread, so that the scheduling method provided in the embodiment of the present application is used to adjust the priority level of the group to which the target thread belongs.

[0043] In this way, by taking each created thread as the target thread, determining the group to which each thread belongs, and dynamically adjusting the priority level of the group to which each thread belongs, the actual scheduling delay value of each thread is close to the target scheduling delay value corresponding to the priority level of its group, so as to meet the delay requirements and improve the delay performance.

[0044] In order to determine the target thread, in an optional embodiment, the method may further include:

[0045] Select the target thread from the threads of the created process.

[0046] It can be understood that when creating threads, the created threads are screened to select a target thread from the created threads. Here, a preset rule can be used to select the target thread, or the main thread can be used as the target thread. The embodiment of the present application does not specifically limit this.

[0047] In this way, by selecting a target thread from the created threads, the priority level of the group to which the selected target thread belongs can be dynamically adjusted so that the actual scheduling delay value of the selected target thread is close to the target scheduling delay value corresponding to the priority level of its group, so as to meet the delay requirements and improve the delay performance.

[0048] In order to determine the priority level of the group to which the target thread belongs, in an optional embodiment, the method may further include:

[0049] The priority level of the group to which the target thread belongs is determined based on the importance and urgency of the task in the target thread.

[0050] It can be understood that after determining the target thread, it is necessary to determine the priority level of the group to which the target thread belongs based on the importance and urgency of the tasks in the target thread, wherein the above-mentioned importance is used to characterize the importance requirement of the tasks in the target thread, which can be expressed in level or in numerical value, and the above-mentioned urgency is used to characterize the real-time requirement of the tasks in the target thread, which can be expressed in level or in numerical value.

[0051] After knowing the importance and urgency of the task in the target thread, the priority level of the target thread can be determined by using the preset mapping relationship between the importance, urgency and priority level, and the target thread can be divided into a group corresponding to the priority level, thereby obtaining the priority level of the group to which the target thread belongs; a preset algorithm can also be used to determine the priority level of the target thread, and the target thread can be divided into a group corresponding to the priority level, thereby obtaining the priority level of the group to which the target thread belongs; here, the embodiments of the present application do not make specific limitations on this.

[0052] In this way, the priority level of the target thread is determined based on the importance and real-time performance of the task in the target thread, and then the group to which the target thread belongs is determined to obtain the priority level of the group to which the target thread belongs. In this way, determining a suitable group for the target thread helps to adjust the priority level of the group.

[0053] In order to adjust the priority level of the group to which the target thread belongs, in an optional embodiment, S103 may include:

[0054] Using a PID control algorithm, the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group where the target thread belongs are calculated to obtain a calculation result;

[0055] Determine the priority level corresponding to the operation result;

[0056] The priority level of the group to which the target thread belongs is adjusted to the priority level corresponding to the calculation result.

[0057] It can be understood that the PID control algorithm is used to calculate the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, so as to obtain a calculation result, which can be a numerical value.

[0058] Among them, the basic principle of the above PID control algorithm is to adjust the output signal according to the difference (i.e., error) between the current state of the controlled object and the set value, so that the difference approaches zero. In the embodiment of the present application, the PID control algorithm is used to adjust the calculation result according to the difference (i.e., error) between the actual scheduling delay value of the target thread and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, so that the difference between the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs approaches zero.

[0059] Since the correspondence between the calculation result and the priority level is preset, after obtaining the calculation result, the priority level corresponding to the calculation result can be determined, and then the priority level of the group where the target thread belongs can be adjusted to the priority level corresponding to the calculation result.

[0060] In this way, the PID control algorithm is used to calculate the actual scheduling delay value of the target thread and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, and the priority level of the group to which the target thread belongs is adjusted according to the calculation result, so that the difference between the actual scheduling delay value of the adjusted target thread and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs approaches zero, thereby meeting the delay requirement of the thread.

[0061] In order to achieve the calculation result obtained by using the above PID control algorithm, in an optional embodiment, using the PID control algorithm, calculating the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs to obtain the calculation result, which may include:

[0062] Determine the difference between the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs;

[0063] Perform proportional, integral and differential control operations on the difference to obtain the operation result.

[0064] It can be understood that the difference between the scheduling delay value of the target thread and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs can be calculated first, and the difference can be subjected to proportional control, integral control and differential control, wherein for proportional control, the calculation result is adjusted according to the size of the difference. The larger the difference, the larger the calculation result, thereby speeding up the response speed of the target thread. Proportional control can respond to the difference quickly, but it cannot eliminate the steady-state error (i.e., the error that still exists after the system stabilizes).

[0065] For integral control, past differences are taken into account. It removes steady-state errors by integrating the difference. Integral control helps reduce the difference after the system has stabilized, but it can also cause the system to respond more slowly and may increase overshoot (i.e., a situation where the system output exceeds the reference input).

[0066] For derivative control, the future difference is predicted based on the rate of change of the difference and the control output is adjusted accordingly. Derivative control helps to speed up the system response, reduce overshoot, and increase system stability. However, derivative control is very sensitive to noise because noise often causes sudden changes in the difference, which can be mistaken for the rate of change of the difference.

[0067] In this way, the priority level of the group to which the target thread belongs is adjusted by performing proportional, integral and differential control on the difference, so that the actual scheduling delay value of the target thread is closer to its target scheduling delay value, thereby satisfying the delay performance.

[0068] In addition, other methods may be used to implement PID control. In an optional embodiment, a PID control algorithm is used to calculate the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, and the calculation result may include:

[0069] The actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the target thread group are input into the PID controller corresponding to the target thread group to perform proportional, integral and differential control operations to obtain the operation result.

[0070] It can be understood that a corresponding PID controller is set for each group here. In this way, after determining the actual scheduling delay value of the target thread and the target scheduling delay value corresponding to the priority level of the group where the target thread is located, the two values ​​are input into the PID controller corresponding to the group where the target thread is located, thereby realizing the proportional, integral and differential control of the difference between the actual scheduling delay value of the target thread and the target scheduling delay value corresponding to the priority level of the group where the target thread is located, thereby obtaining the calculation result.

[0071] In this way, by setting a corresponding PID controller in each group and using the corresponding PID controller to adjust the priority level of the group where the target thread is located, the actual scheduling delay value of the target thread is closer to its target scheduling delay value, thereby meeting the delay performance.

[0072] In addition to the above two methods, other methods can also be used to implement PID control. In an optional embodiment, a PID control algorithm is used to calculate the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, and the calculation result is obtained, which may include:

[0073] The actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the target thread group are input into the multi-level PID controller corresponding to the target thread group to perform proportional, integral and differential control operations to obtain the operation result.

[0074] It can be understood that a corresponding multi-stage PID controller is set for each group here. In this way, after determining the actual scheduling delay value of the target thread and the target scheduling delay value corresponding to the priority level of the group where the target thread is located, the two values ​​are input into the multi-stage PID controller corresponding to the group where the target thread is located, thereby realizing proportional, integral and differential control of the difference between the actual scheduling delay value of the target thread and the target scheduling delay value corresponding to the priority level of the group where the target thread is located, thereby obtaining a calculation result.

[0075] In this way, by setting a corresponding multi-stage PID controller in each group and using the corresponding multi-stage PID controller to adjust the priority level of the group where the target thread is located, the actual scheduling delay value of the target thread is closer to its target scheduling delay value, thereby meeting the delay performance.

[0076] The scheduling method described in one or more of the above embodiments is described below with examples.

[0077] This example provides a thread group scheduling method with dynamic priority adjustment based on a PID controller. By introducing a PID controller between the CPU scheduler and the thread group, real-time delay feedback and dynamic priority adjustment are implemented to ensure that the scheduling delay of the thread group meets the preset target.

[0078] Figure 2 A flowchart of an optional scheduling method provided in an embodiment of the present application is shown as follows: Figure 2 As shown, the scheduling method may include:

[0079] S201: The CPU scheduler performs thread grouping;

[0080] Among them, all threads are divided into several thread groups, and the thread groups are divided into multiple levels (such as low, medium, and high) according to the task importance and real-time requirements of the thread groups, and each level corresponds to a target scheduling delay value.

[0081] Here, set the target delay: set a target scheduling delay value for each thread group to ensure that thread groups of different levels have different delay standards.

[0082] S202: The CPU scheduler records the actual scheduling delay value of the thread;

[0083] S203: The CPU scheduler inputs the actual scheduling delay value and the target scheduling delay value into the PID controller corresponding to the group where the thread belongs;

[0084] The CPU scheduler records the actual scheduling delay of the thread group after each scheduling, and passes the recorded actual scheduling delay value and target scheduling delay value to the corresponding PID controller.

[0085] S204: The PID controller feeds back the output signal to the CPU scheduler;

[0086] PID controller adjustment: The PID controller receives the actual scheduling delay and target delay values ​​and calculates the error. The PID controller performs proportional, integral, and differential calculations based on the error value and adjusts the output priority adjustment amount. The PID controller feeds the output signal back to the CPU scheduler.

[0087] S205: The CPU scheduler determines a corresponding priority level based on the output signal;

[0088] S206: The CPU scheduler adjusts the priority level of the group to which the thread belongs to to the priority level corresponding to the output signal, and returns to execute S202.

[0089] Dynamic priority adjustment: The CPU scheduler dynamically adjusts the priority level of the thread group based on the feedback from the PID controller. Thread groups with high priorities are given priority in scheduling, ensuring that their scheduling delay is close to the target scheduling delay value.

[0090] S202 - S206 are executed cyclically to adjust the priorities of the thread groups in real time to ensure that the scheduling delays of all thread groups are within a set range.

[0091] Figure 3 A schematic diagram of thread scheduling in an optional scheduling method provided in an embodiment of the present application, such as Figure 3 As shown, the CPU scheduler schedules thread group 1, thread group 2 and thread group 3. Thread group 1 corresponds to a PID controller 1, thread group 2 corresponds to a PID controller 2, and thread group 3 corresponds to a PID controller 3.

[0092] Figure 3 This is a schematic diagram of the thread group scheduling method based on dynamic priority adjustment of the PID controller, which shows the interaction process between each thread group, the PID controller and the CPU scheduler.

[0093] For example, for thread 1 in thread group 1, when thread 1 in thread group 1 is scheduled, the actual scheduling delay value of thread 1 in thread group 1 is recorded, and it is sent to PID controller 1 together with the target scheduling delay value corresponding to thread group 1, so as to obtain an output signal (equivalent to the above operation result), and the CPU scheduler determines the priority level corresponding to the output signal, and adjusts the priority level of thread group 1 to the priority level corresponding to the output signal, thereby achieving scheduling.

[0094] In this example, different types of tasks can be adapted. For example, the parameter configuration of the PID controller is expanded to enable it to adapt to different types of tasks such as input / output (I / O) intensive and computationally intensive tasks.

[0095] This example may adopt a multi-stage PID controller structure, for example, design a multi-stage PID controller structure to achieve more sophisticated scheduling delay control.

[0096] In this example, dynamic priority adjustment based on PID controller is used. For example, a PID controller is introduced to adjust the priority through real-time feedback to ensure that the scheduling delay of the thread group meets the preset target. Multi-level target delay setting, for example, thread groups are divided into multiple levels according to task importance, and different target delay values ​​are set to meet different real-time requirements. Real-time scheduling delay feedback mechanism, for example, the actual delay is recorded during the scheduling process and fed back to the PID controller to achieve real-time monitoring and adjustment of the delay. Dynamic priority adjustment mechanism, for example, dynamically adjust the priority of the thread group according to the priority adjustment amount output by the PID controller to improve the flexibility and responsiveness of scheduling.

[0097] By using the above example, by dynamically adjusting the thread group priority, critical tasks can be executed in a timely manner, significantly improving the system response speed. It reduces resource competition between thread groups, improves the utilization of CPU resources, and avoids resource waste. The PID controller real-time feedback adjustment mechanism can dynamically adjust the scheduling strategy according to the actual delay situation to improve scheduling flexibility. By setting different levels of target scheduling delay, it can ensure that high-priority tasks are completed within the expected time, improving task performance and reliability.

[0098] An embodiment of the present application provides a scheduling method, which determines the actual scheduling delay value of the target thread when a target thread is scheduled, and adjusts the priority level of the group to which the target thread belongs according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs; that is, in an embodiment of the present application, by determining the actual scheduling delay value of the target thread, the priority level of the group to which the target thread belongs is adjusted together with the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, thereby dynamically adjusting the priority level of the target thread through the actual scheduling delay value and the target scheduling delay value, thereby making the actual scheduling delay value of the target thread close to its target scheduling delay value, so as to meet the scheduling delay of the target thread within the set range, thereby providing delay performance.

[0099] Based on the same inventive concept as the above embodiments, the present application embodiment provides a scheduling device, Figure 4 A schematic diagram of the structure of an optional scheduling device provided in an embodiment of the present application, such as Figure 4As shown, the frequency modulation device includes: a determination module 41 and a scheduling module 42; wherein,

[0100] A determination module 41, used to determine an actual scheduling delay value of the target thread when the target thread is scheduled;

[0101] The scheduling module 42 is used to adjust the priority level of the group where the target thread belongs according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group where the target thread belongs.

[0102] In an optional embodiment, the above device is also used for:

[0103] When a thread is created, the created thread is determined as a target thread.

[0104] In an optional embodiment, the above device is also used for:

[0105] Select the target thread from the threads of the created process.

[0106] In an optional embodiment, the above device is also used for:

[0107] The priority level of the group to which the target thread belongs is determined based on the importance and urgency of the task in the target thread.

[0108] In an optional embodiment, the scheduling module 42 is specifically configured to:

[0109] Using a PID control algorithm, the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group where the target thread belongs are calculated to obtain a calculation result;

[0110] Determine the priority level corresponding to the operation result;

[0111] The priority level of the group to which the target thread belongs is adjusted to the priority level corresponding to the calculation result.

[0112] In an optional embodiment, the scheduling module 42 uses a PID control algorithm to calculate the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, and obtains the calculation result, including:

[0113] Determine the difference between the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs;

[0114] Perform proportional, integral and differential control operations on the difference to obtain the operation result.

[0115] In an optional embodiment, the scheduling module 42 uses a PID control algorithm to calculate the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, and obtains the calculation result, including:

[0116] The actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the target thread group are input into the PID controller corresponding to the target thread group to perform proportional, integral and differential control operations to obtain the operation result.

[0117] In an optional embodiment, the scheduling module 42 uses a PID control algorithm to calculate the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, and obtains the calculation result, including:

[0118] The actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the target thread group are input into the multi-level PID controller corresponding to the target thread group to perform proportional, integral and differential control operations to obtain the operation result.

[0119] In practical applications, the above-mentioned determination module 41 and scheduling module 42 can be implemented by a processor located on the scheduling device, specifically a CPU, a microprocessor (Microprocessor Unit, MPU), a digital signal processor (Digital Signal Processing, DSP) or a field programmable gate array (Field Programmable Gate Array, FPGA) and the like.

[0120] Figure 5 A schematic diagram of the structure of an optional electronic device provided in an embodiment of the present application, such as Figure 5 As shown, an embodiment of the present application provides an electronic device 500, including:

[0121] A processor 51 and a storage medium 52 storing instructions executable by the processor; the storage medium 52 relies on the processor 51 to perform operations through a communication bus 53, and when the instructions are executed by the processor, the scheduling method executed by the processor side in one or more of the above embodiments is executed.

[0122] It should be noted that, in actual application, the various components in the computer device are coupled together via the communication bus 53. It is understandable that the communication bus 53 is used to realize the connection and communication between these components. In addition to the data bus, the communication bus 53 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 5 Various buses are labeled as communication buses 53.

[0123] An embodiment of the present application provides a computer storage medium storing executable instructions. When the executable instructions are executed by one or more processors, the processors execute the scheduling method described in one or more of the above embodiments.

[0124] Among them, the computer-readable storage medium can be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM) and other memories.

[0125] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of hardware embodiments, software embodiments, or embodiments in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.

[0126] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application.

Claims

1. A scheduling method, characterized in that: include: In the case where the target thread is scheduled, determining an actual scheduling delay value of the target thread; The priority level of the group to which the target thread belongs is adjusted according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs.

2. The method according to claim 1, characterized in that The method further comprises: When a thread is created, the created thread is determined as the target thread.

3. The method according to claim 1, characterized in that: The method further comprises: The target thread is selected from the threads of the created process.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: The priority level of the group to which the target thread belongs is determined according to the importance and urgency of the tasks in the target thread.

5. The method according to claim 1, characterized in that: The step of adjusting the priority level of the group to which the target thread belongs according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs comprises: Using a PID control algorithm, the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs are calculated to obtain a calculation result; Determining a priority level corresponding to the operation result; The priority level of the group to which the target thread belongs is adjusted to the priority level corresponding to the calculation result.

6. The method according to claim 5, characterized in that The PID control algorithm is used to calculate the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, and the calculation result is obtained, including: Determine a difference between the actual scheduling delay value and a target scheduling delay value corresponding to the priority level of the group to which the target thread belongs; Proportional, integral and differential control operations are performed on the difference to obtain the operation result.

7. The method according to claim 5, characterized in that The PID control algorithm is used to calculate the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, and the calculation result is obtained, including: The actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group where the target thread is located are input into the PID controller corresponding to the group where the target thread is located to perform proportional, integral and differential control operations to obtain the operation result.

8. The method according to claim 5, characterized in that The PID control algorithm is used to calculate the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group to which the target thread belongs, and the calculation result is obtained, including: The actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group where the target thread is located are input into the multi-stage PID controller corresponding to the group where the target thread is located to perform proportional, integral and differential control operations to obtain the operation result.

9. A scheduling device, characterized in that: include: A determination module, used for determining an actual scheduling delay value of the target thread when the target thread is scheduled; The scheduling module is used to adjust the priority level of the group where the target thread belongs according to the actual scheduling delay value and the target scheduling delay value corresponding to the priority level of the group where the target thread belongs.

10. An electronic device, characterized in that: include: A processor and a storage medium storing instructions executable by the processor; The storage medium relies on the processor to perform operations through a communication bus, and when the instructions are executed by the processor, the scheduling method described in any one of claims 1 to 8 is executed.

11. A computer storage medium, characterized in that: Executable instructions are stored, and when the executable instructions are executed by one or more processors, the processors execute the scheduling method described in any one of claims 1 to 8.

Images