Chip
By designing a chip that includes the monitoring module, monitoring module, and controller during the FPGA chip verification process, the complex and time -consuming of verification processes are solved, and the simplified verification process in high -frequency scenarios is realized.
Patent Information
- Application Number
- CN202411380066.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-01-21
AI Technical Summary
During the verification process of the FPGA chip, as the monitoring time and frequency increase, the true value sequence of the signal to be monitored becomes complicated, resulting in the verification process being complex and time-consuming.
Design a chip, including the module, monitoring module and controller. The monitoring module can be monitored by the number of monitoring signals at different stages through the cumulative collection of testing functions, and switching phases during the level jump. If the cumulative counting value meets the expected conditions, generate trigger signals to determine the monitoring results.
The complexity of the monitoring process is reduced, so that it rely only on the number of fragments of the monitoring signal, rather than the sampling frequency and duration, thereby reducing the verification time in high -frequency scenes.
Smart Images
Figure CN119336558A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip verification, and in particular to a chip. Background Art
[0002] During the verification process of the FPGA chip, it is necessary to monitor whether the signal to be monitored in the chip meets expectations to determine the verification result of the FPGA chip.
[0003] At present, the signal to be monitored is generally sampled continuously at a certain frequency, and the sampled true value sequence is compared with the set expectation. If the comparison is consistent, it is determined that the signal to be monitored meets the expectation. However, as the monitoring time and frequency increase, the sampled true value sequence will become more complex, which will cause the tester to fully understand the relationship between the pulse width and the acquisition frequency to set expectations, making the verification process more complicated and time-consuming.
[0004] In summary, how to reduce the complexity and time of the verification process is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The embodiment of the present invention provides a chip to solve the problem in the prior art that the verification process is relatively complicated and time-consuming.
[0006] In the first aspect, an embodiment of the present invention provides a chip, including a module to be monitored, a monitoring module and a controller; the module to be monitored is provided with a test terminal and a function to be tested; the monitoring module is connected to the monitoring module through the test terminal, and is used to accumulate the number of times the monitored signal of the function to be tested is collected in the i-th stage; when the level of the signal to be monitored jumps, the number of times the monitored signal of the i+1-th stage is collected is accumulated; the monitoring module is also used to compare the level information of the currently collected signal to be monitored with the termination level if the count values accumulated in each stage of the function to be tested meet the expected conditions of the corresponding stage, and if the comparison is successful, generate a trigger signal and send it to the controller; the controller is used to determine the monitoring result of the module to be monitored according to the trigger signal.
[0007] In the above technical scheme, whether to trigger the trigger signal is determined by only monitoring the count values of the set multiple stages of the signal to be monitored and the termination level of the signal to be monitored, thereby determining the monitoring result of the module to be monitored. In this way, the complexity of the monitoring process only depends on the number of changes in the monitored fragments of the signal to be monitored, rather than its sampling frequency and duration. In this way, the complexity of the monitoring process can be reduced in high-frequency scenarios.
[0008] Optionally, the monitoring module includes: an acquisition component, a counting component, a comparison component and a trigger component; the acquisition component and the trigger component are both connected to the module to be monitored; the trigger component is connected to the controller; the acquisition component and the comparison component are both connected to the counting component; the comparison component is connected to the trigger component; the acquisition component is used to acquire the signal to be monitored in the i-th stage from the module to be monitored through the test end, and send the signal to be monitored to the counting component; the counting component is used to count the number of acquisitions of the signal to be monitored in the i-th stage, and when the level of the signal to be monitored jumps, the number of acquisitions in the i+1th stage is counted; the comparison component is used to compare the count value of the signal to be monitored in any stage with the expected conditions of the corresponding stage, and if the comparison is successful, a first notification is generated and sent to the trigger component;
[0009] The trigger component is used to compare the level information of the currently collected signal to be monitored with the termination level after receiving the first notification, and if the comparison is successful, generate a trigger signal and send it to the controller.
[0010] Optionally, the comparison component includes n-1 storage units, a control unit and n comparison units; the comparison unit includes a first comparison unit and a second comparison unit; the first comparison unit is one of the n comparison units; the second comparison unit is any comparison unit other than the first comparison unit among the n comparison units; each storage unit has a one-to-one corresponding second comparison unit; the first comparison unit is connected to the counting component; wherein n is a positive integer greater than or equal to 1; the count value of the counting component is used to characterize the count value in the final stage;
[0011] The counting component is also used for storing the count value in the temporary memory of the counting component when the level of the signal to be monitored changes, clearing the current count value, and collecting the count value of the signal to be monitored in the next stage;
[0012] The counting component is also used to send an update request to the control unit when the count value is greater than a first preset threshold; the update request is used to instruct the control unit to store the count value in the temporary memory of the counting component to the corresponding storage unit; the control unit is used to instruct the i-th storage unit to read the count value from the i-1-th storage unit and update it to its own count value according to the update request; the first storage unit reads the count value from the temporary memory of the counting component and updates it to its own count value; i is a positive integer less than or equal to n; any storage unit is used to store the count value of any stage except the final stage; any storage unit is used to store the count value of any stage except the final stage; the first comparison unit is used to compare the count value of the counting component with the expected conditions of the corresponding stage, and output the comparison result; the second comparison unit is used to compare the count values stored in the one-to-one corresponding storage units with the expected conditions of the corresponding stage, and output the comparison result.
[0013] Optionally, the comparison component also includes a generator; the generator is connected to the output end of each comparison unit; the generator is used to generate a first notification and output it to the trigger component when the comparison result of each comparison unit is a successful comparison.
[0014] Optionally, the comparison component also includes a generator; the generator is connected to the output end of each comparison unit; the generator is used to generate a first notification and output it to the trigger component when the comparison result of each comparison unit is a successful comparison.
[0015] Optionally, the monitoring module is pre-configured with expected conditions for each stage, as well as termination levels.
[0016] Optionally, the expected condition includes an expected value and an expected precision; if the difference between the count value and the expected value is within the expected precision, the comparison is successful.
[0017] Optionally, if the monitored signal corresponding to the function to be tested has k stages, the first expected conditions of the corresponding stages are set in the 1st to kth comparison units respectively; the second expected conditions of the corresponding stages are set in the kth to nth comparison units respectively; n is not less than k; the error value in the second expected condition satisfies the second preset threshold value, so that the kth to nth comparison units always maintain successful comparison.
[0018] Optionally, the counting component is also used to determine whether the count value is greater than a first preset threshold when a level jump occurs in the signal to be monitored. If not, update its own count value to the sum of its own count value and its own temporary memory value plus 1.
[0019] Optionally, the trigger component is further used to send a clear signal to the control unit after the trigger signal is sent to the controller; the control unit is used to clear the count values of n-1 storage units according to the clear signal.
[0020] Optionally, the trigger component is further used to receive a monitoring enable signal; when the monitoring enable signal is a first value, the trigger component switches to a working state. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0022] Figure 1 A schematic diagram of the structure of a chip provided by an embodiment of the present invention;
[0023] Figure 2A schematic diagram of the structure of a monitoring module provided by an embodiment of the present invention;
[0024] Figure 3 A schematic diagram of a pulse signal level change provided by an embodiment of the present invention;
[0025] Figure 4 A schematic diagram of the structure of a chip provided by an embodiment of the present invention;
[0026] Figure 5 A schematic diagram of the structure of another chip provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0027] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0028] In a possible scenario, when a fault occurs in the FPGA chip, it is necessary to check which module in the FPGA chip causes the fault of the FPGA chip. Therefore, the tester first needs to determine which modules have faults that may affect the fault of the FPGA chip, and determine these modules as modules to be monitored, and then check the modules to be monitored in turn. It should be noted that there are two possibilities for the failure of the module to be monitored. The first possibility is to collect the input signal of the module to be monitored. If the input signal meets the set conditions, it means that the module to be monitored cannot enter the working state, thereby causing the module to be monitored to fail. The second possibility is that the module to be monitored has an abnormal fault when entering the working state. In this case, it is first necessary to check whether the module to be monitored has entered the working state. If it enters the working state, collect the internal signal of the module to be monitored or the output signal of the output port in the module to be monitored. If the internal signal of the module to be monitored or the output signal of the output port in the module to be monitored meets the set conditions, it means that the module to be monitored has failed, so as to determine that the failed module to be monitored causes the FPGA chip to fail.
[0029] In one possible case, the commonly used timing monitoring method is to write a timing monitoring module in the form of a shift register. The principle is to continuously sample the signal to be tested at a certain frequency, compare the sampled true value sequence with the expectation, and if they are consistent, it means that the above set conditions are met. However, with the increase of monitoring time and frequency, the monitoring sequence will become more and more complicated. When monitoring a simple rising edge logic, the tester still needs such a lengthy sequence to describe. And when only monitoring a simple pulse, the tester still needs to fully understand the relationship between the pulse width and the acquisition frequency to set expectations. For example, the true value sequence sampled at a certain frequency is "0110", and after the acquisition frequency is halved, it is "0100". This makes it impossible for the tester to detect the process even if the corresponding logic level jump occurs when the acquisition frequency is unreasonable. In many test scenarios, the tester only wants to monitor the edge change of the signal, such as counting the number of changes, and does not need to understand the monitoring of each change. With the increase of the test frequency, the probability of sampling glitches also increases, but this method of truth value comparison will inevitably fail in the case of glitches.
[0030] In summary, the embodiments of the present invention provide a chip to solve the problems that the above method is relatively complicated, time-consuming, and has large errors.
[0031] like Figure 1 As shown, a schematic diagram of the structure of a chip is provided in an embodiment of the present invention, wherein the chip 100 includes a module to be monitored 110, a monitoring module 120 and a controller 130. The module to be monitored 110 is provided with a test terminal and a function to be tested; the monitoring module 120 is connected to the monitoring module 120 through the test terminal, and is used to accumulate the number of times the signal to be monitored of the function to be tested in the i-th stage is collected; when the level jump of the signal to be monitored occurs, the number of times the signal to be monitored in the i+1th stage is collected is accumulated; the monitoring module 120 is also used to compare the level information of the signal to be monitored currently collected with the termination level if the count value accumulated in each stage of the function to be tested meets the expected conditions of the corresponding stage, and if the comparison is successful, a trigger signal is generated and sent to the controller 130; the controller 130 is used to determine the monitoring result of the module to be monitored according to the trigger signal.
[0032] In an embodiment of the present invention, whether to trigger a trigger signal is determined by monitoring only the count values of the set multiple stages of the signal to be monitored and the termination level of the signal to be monitored, thereby achieving determination of the monitoring result of the module to be monitored. In this way, the tester does not need to fully understand the relationship between the pulse width and the acquisition frequency to set expectations. The tolerance for the length of the pulse width can be expanded by expanding the expected accuracy, thereby avoiding the problem that the signal to be monitored has an expected change but cannot be monitored due to overly harsh test conditions.
[0033] like Figure 2As shown, it is a structural schematic diagram of a monitoring module provided by an embodiment of the present invention, the monitoring module 120 includes a collection component 210, a counting component 220, a comparison component 230 and a trigger component 240, wherein the collection component 210 and the trigger component 240 are both connected to the module to be monitored 110; the trigger component 240 is connected to the controller 130; the collection component 210 and the comparison component 230 are both connected to the counting component 220; the comparison component 230 is connected to the trigger component 240.
[0034] The collection component 210 is used to collect the signal to be monitored in the i-th phase from the module to be monitored 110 through the test end, and send the signal to be monitored to the counting component 220 .
[0035] In the embodiment of the present invention, the test end may be the input end of the module to be monitored, and the corresponding signal to be monitored is the input signal of the module to be monitored. The test end may also be the port output end of any port in the module to be monitored, and the corresponding signal to be monitored is the port output signal of any port of the module to be monitored. The test end may also be the test end of the module to be monitored, through which the internal signal in the module to be monitored can be collected, wherein the internal signal may be an intermediate signal generated in the process of converting the input signal into the output signal. The test end may also be other ports, which are not limited here.
[0036] For example, if the signal to be monitored is a pulse signal, the configuration of the test scenario needs to satisfy two consecutive pulse signals lasting 4 seconds, and the trigger signal needs to be triggered in the second half of the second pulse signal. In this case, the monitoring stage is 3 stages, corresponding to 2 level jumps. The configuration of the test scenario should satisfy that in the first stage, the level of the first pulse signal is high, and the high level needs to last for 4 seconds, and then in the second stage, if the high level meets the requirement of lasting 4 seconds, it will jump to a low level, and the duration of the low level is not limited, and then in the third stage, when the low level jumps to a high level, the pulse signal corresponding to the high level is the second pulse signal. If the high level of the second pulse signal lasts for 2 seconds, the trigger signal can be triggered in the subsequent 2s-4s. Please refer to Figure 3 .
[0037] The counting component 220 is used to count the number of acquisitions of the signal to be monitored in the i-th stage. When the level of the signal to be monitored changes, the number of acquisitions in the (i+1)-th stage is counted.
[0038] In an embodiment of the present invention, the counting component 220 is used to count the number of acquisitions of the signal to be monitored in the i-th stage. When the signal to be monitored has a level jump, the number of acquisitions of the signal to be monitored in the i-th stage is stopped, and the number of acquisitions in the i+1-th stage is counted. For example, the signal to be monitored is a pulse signal, and the configuration of the test scenario is required to meet two consecutive pulse signals lasting 4s, and the trigger signal needs to be triggered in the second half of the second pulse signal. If the acquisition frequency is to collect a pulse signal once per second, the counting component counts the number of acquisitions of the signal to be monitored in the first stage. When the signal to be monitored has a level jump, the number of acquisitions of the signal to be monitored in the first stage is stopped. At this time, the count value of the signal to be monitored in the first stage is 4, and the counting component starts to count the number of acquisitions in the second stage. When the signal to be monitored has a level jump, the number of acquisitions of the signal to be monitored in the first stage is stopped. At this time, the count value of the signal to be monitored in the second stage is 3, and the counting component starts to count the number of acquisitions in the third stage.
[0039] The comparison component 230 is used to compare the count value of the signal to be monitored at any stage with the expected condition of the corresponding stage. If the comparison is successful, a first notification is generated and sent to the trigger component 240.
[0040] In an embodiment of the present invention, the comparison component 230 is used to compare the count value of the signal to be monitored at any stage with the expected condition corresponding to the stage. If the count value of the signal to be monitored at all stages is successfully compared with the corresponding expected conditions, a first notification is generated and sent to the trigger component 240.
[0041] The trigger component 240 is used to compare the level information of the signal to be monitored collected in the final stage with the termination level after receiving the first notification, and if the comparison is successful, generate a trigger signal and send it to the controller 130.
[0042] In an embodiment of the present invention, the trigger component 240 continuously collects level information of the signal to be monitored, and after receiving the first notification, compares the level information of the signal to be monitored currently obtained with the termination level. If the comparison is successful, a trigger signal is generated and sent to the controller 130, wherein the termination level is pre-configured by the tester and may also be determined based on the specific situation, which is not limited here.
[0043] Optionally, the comparison component 230 includes n-1 storage units 231, a control unit 232 and n comparison units 233, the comparison unit 233 includes a first comparison unit and a second comparison unit, the first comparison unit is one of the n comparison units; the second comparison unit is any comparison unit among the n comparison units except the first comparison unit; each storage unit 231 has a one-to-one corresponding second comparison unit; the first comparison unit is connected to the counting component 220; wherein n is a positive integer greater than or equal to 1.
[0044] Optionally, the counting component 220 counts the number of collection times of the signal to be monitored in the i-th stage. When the level of the signal to be monitored jumps, the number of collection times of the i-th stage is stored in the temporary memory of the counting component, and the number of collection times of the i+1-th stage is counted. When the count value is greater than the first preset threshold, an update request is sent to the control unit, wherein the update request is used to instruct the control unit to store the count value in the temporary memory of the counting component to the corresponding storage unit.
[0045] Optionally, after receiving the update request, the control unit 232 sequentially instructs the i-th storage unit to update the count value read from the i-1-th storage unit to its own count value according to the update request, where i is a positive integer less than or equal to n.
[0046] For example, see Figure 4, if the signal to be monitored is a pulse signal, the configuration of the test scenario is to meet the requirements of two consecutive pulse signals lasting 4s, and to meet the requirement of triggering the trigger signal in the second half of the second pulse signal. In this case, the monitoring stage is 3 stages, corresponding to 2 level jumps. The counting component 220 counts the number of acquisitions of the signal to be monitored in the first stage. When the signal to be monitored has a level jump, at this time, the count value of the signal to be monitored in the first stage is 4, and the counting of the signal to be monitored in the first stage is stopped, and the count value is temporarily stored in the temporary memory of the counting component 220, the current count value of the counting component 220 is cleared, and the number of acquisitions in the second stage is started. When the count of the second stage is greater than the first preset threshold, an update request is sent to the control unit 232, and after the counting component 220 sends the update request, the control unit 232 writes the count value of the signal to be monitored in the first stage stored in the temporary memory by the counting component 220 into the first storage unit according to the update request. Then, when the signal to be monitored jumps again, at this time, the count value of the signal to be monitored in the second stage is 3, and the counting of the second stage is stopped, the count value is temporarily stored in the temporary memory of the counting component, the current count value of the counting component 220 is cleared, and the number of acquisitions in the third stage is counted. When the count of the third stage is greater than the first preset threshold, an update request is sent to the control unit 232, and after the counting component 220 sends the update request, the control unit 232 instructs the second storage unit to read the count value from the first storage unit, that is, 4, and update it to its own count value according to the update request, and clears the count value of the first storage unit, and instructs the counting component 220 to write the value of the temporary memory, that is, 3, into the first storage unit. The count value of the third stage is stored in the counting component 220.
[0047] Optional, see Figure 4 , the first comparison unit is Figure 4 The first comparison unit in the comparison is Figure 4 Any one of the 2nd to nth comparison units in the storage unit, wherein the 2nd to nth comparison units correspond to n-1 storage units one by one. According to the above example, the 1st comparison unit is connected to the counting component 220, and is used to compare the count value in the counting component 220 with the expected condition of the third stage, and output the comparison result. The 2nd comparison unit is connected to the 1st storage unit, and is used to compare the count value of the 1st storage unit with the expected condition of the second stage, and output the comparison result. The 3rd comparison unit is connected to the 2nd storage unit, and is used to compare the count value of the 2nd storage unit with the expected condition of the first stage, and output the comparison result.
[0048] Optionally, the expected condition includes an expected value and an expected accuracy. If the difference between the count value and the expected value is within the expected accuracy, the comparison is successful. Specifically, the expected condition is (expected value - expected accuracy) < count value < (expected value + expected accuracy). By comparing the count value with the expected condition, if the count value successfully compares with the expected condition, it means that the signal meets expectations. For example, for analog circuits that are more susceptible to voltage and temperature, the conversion process of their output will also change to a certain extent with voltage and temperature. During use, as long as it is within a certain range, it is reasonable. By setting the expected conditions to a reasonable range of working conditions, when monitoring signals that are directly or indirectly affected by these analog signals, it can be avoided to a large extent that the signal works reasonably but fails the test.
[0049] Optionally, since it is possible to determine how many stages of the monitored signal need to be monitored according to the configuration of the test scenario, if the monitored signal corresponding to the function to be tested has k stages, the first expected condition of the corresponding stage is set in the 1st to the kth comparison units respectively; the second expected condition is set in the kth to the nth comparison units respectively; n is not less than k; the error value in the second expected condition satisfies the second preset threshold value, so that the kth to the nth comparison units always maintain successful comparison. For example, if there are 3 stages in total, the first expected condition of the corresponding stage is set in the 1st comparison unit, the 2nd comparison unit and the 3rd comparison unit respectively, wherein the first expected condition of the 3rd stage is set in the 1st comparison unit, the first expected condition of the 2nd stage is set in the 2nd comparison unit, and the first expected condition of the 1st stage is set in the 3rd comparison unit. The second expected condition is set in the 4th to the nth comparison units respectively, so that the comparison results of the 4th to the nth comparison units are always successful.
[0050] Optionally, the comparison component also includes a generator 234, see Figure 4 , wherein the generator 234 is connected to the output end of each comparison unit, and the generator 234 is used to generate a first notification and output it to the trigger component 240 when the comparison result of each comparison unit is a successful comparison.
[0051] Optionally, since it is possible to determine how many stages of the monitored signal need to be monitored based on the configuration of the test scenario, if the monitored signal corresponding to the function to be tested has k stages, the first expected conditions of the corresponding stages are set in the 1st to kth comparison units respectively; the kth to nth comparison units are turned off, and it is set in the generator 234 to generate a first notification only after receiving the successful comparisons sent by the 1st to kth comparison units respectively.
[0052] For example, if the signal to be monitored is a pulse signal, the configuration of the test scenario requires two consecutive pulse signals lasting 4 seconds, and the trigger signal needs to be triggered in the second half of the second pulse signal. In this case, the monitoring stage is 3 stages. Since the configuration of the test scenario requires two consecutive pulse signals lasting 4 seconds, if the frequency of collecting the signal to be monitored is once per second, if the configuration is expected, the first stage of the signal to be monitored will have the first pulse signal lasting 4 seconds, and then after lasting 4 seconds, it will be converted from a high level to a low level. The second stage of the signal to be monitored will have a negligible low level duration. When the low level jumps to a high level, the third stage of the signal to be monitored is to continue to monitor the second pulse signal of the signal to be monitored. When the second pulse signal continues at a high level for more than 2 seconds, if the first pulse signal lasts for 4 seconds and the second pulse signal lasts for more than 2 seconds, the trigger signal will be triggered within 2s-4s of the second pulse signal. Therefore, the expected value in the first expected condition of the first stage is 4, and the expected accuracy is 0. The expected value in the first expected condition of the second stage is 0. If the second preset threshold is the maximum value of the expected value, where the expected accuracy is the maximum value of the expected value, denoted as C, then the expected accuracy satisfies the second preset threshold. Therefore, this stage satisfies the expected condition of (expected value-expected accuracy)<count value<(expected value+expected accuracy), so the comparison result of the comparison unit corresponding to this stage is a successful comparison. The expected value in the first expected condition of the third stage is 3, and the expected accuracy is 1.
[0053] In this case, see Figure 4, the third comparison unit reads the count value of the first stage from the second storage unit, and determines whether the comparison is successful according to the first expected condition of the first stage. Since the count value of the first stage is 4, which meets the first expected condition, it means that the comparison is successful, and the third comparison unit sends a notification that the comparison result is successful to the generator 234. Similarly, the second comparison unit reads the count value of the second stage from the first storage unit, and determines whether the comparison is successful according to the first expected condition of the second stage. Since the count value of the second stage is 3, which meets the first expected condition, it means that the comparison is successful, and the second comparison unit sends a notification that the comparison result is successful to the generator 234. Similarly, the first comparison unit reads the count value of the third stage from the counting component 220, and determines whether the comparison is successful according to the first expected condition of the third stage. When the count value in the counting component 220 is 2, which meets the first expected condition of the third stage, it means that the comparison is successful, and the first comparison unit sends a notification that the comparison result is successful to the generator 234. Since the first comparison unit, the second comparison unit and the third comparison unit all send comparison success notifications to the generator 234, when the generator 234 simultaneously receives the comparison success results of each comparison unit, the generator 234 generates a first notification and outputs it to the trigger component 240, wherein the first notification is used to notify the trigger component 240 that the comparison results of each comparison unit are all comparison successes. If the generator 234 only receives the comparison success notifications sent by the first comparison unit and the second comparison unit, and does not receive the comparison success notification sent by the third comparison unit, the generator 234 will not generate the first notification.
[0054] Optionally, each second comparison unit reads the count value from the corresponding storage unit in real time and compares the count value with the corresponding second expected condition to determine the comparison result. Similarly, the first comparison unit reads the count value from the counting component 220 in real time and compares the count value with the first expected condition to determine the comparison result.
[0055] For example, if the signal to be monitored is a pulse signal, the configuration of the test scenario requires two consecutive pulse signals lasting 4 seconds, and the trigger signal needs to be triggered in the second half of the second pulse signal. Since the monitoring stage is 3 stages, the first expected condition corresponding to the first comparison unit is compared with the count value of the third stage, the first expected condition corresponding to the second comparison unit is compared with the count value of the second stage, and the first expected condition corresponding to the third comparison unit is compared with the count value of the first stage.
[0056] However, during the monitoring process, the counting component 220 counts the number of times the monitored signal is collected in the first stage. Since each comparison unit compares the corresponding storage unit in real time, although the count value collected by the current counting component 220 is the count value of the first stage, which is different from the stage of the count value required to be compared by the first comparison component, the first comparison component will always read the count value from the counting component 220 in real time and compare the count value with the first expected condition of the third stage until the read count value is successfully compared with the first expected condition of the third stage. When an update request occurs, the count value of the first stage is 4, and the counting component 220 will first store the count value of the first stage in the first storage unit. Although the count value currently stored in the first storage unit is the count value of the first stage, which is different from the stage of the count value required to be compared by the second comparison component, the second comparison component will read the count value from the first storage component in real time and compare the count value with the first expected condition of the second stage until the read count value is successfully compared with the first expected condition of the second stage. Since no count value is currently stored in the second storage component, the comparison result of the third comparison unit corresponding to the second storage unit is that the comparison is unsuccessful. When an update request occurs again, the count value of the second stage is 3, wherein the second comparison unit reads the count value of the first stage from the first storage unit and updates it to its own count value, and the first storage unit reads the count value of the second stage from the counting component 220 and updates it to its own count value. At this time, the third comparison unit reads the count value of the second stage from the second storage unit, the second comparison unit reads the count value of the first stage from the first storage unit, and the first comparison unit reads the count value of the third stage from the counting component 220. Since the acquisition frequency of the monitored signal is once per second, the counting component 220 acquires once every 1 second until the current count value of the counting component 220 is greater than or equal to 2. If the comparisons of the first to third comparison units are successful and notifications of successful comparison are sent to the generator 234 respectively, the generator 234 will generate a first notification and send it to the trigger component 240.
[0057] In the embodiment of the present invention, the counting value corresponding to each stage can be determined by the counting component 220, wherein the level information of the signal to be monitored corresponding to the same stage is the same, i.e., a high level or a low level. Then, only by comparing the counting value with the corresponding comparison unit, it can be quickly determined whether the comparison is successful. In the process of comparison, only the counting value is compared, and there is no need to determine the level information of the signal to be monitored, nor is there a need to determine the true value sequence of the signal to be monitored, so that it can be simply and quickly determined whether each comparison unit is successful. In order to ensure the accuracy of triggering the generation of the trigger signal, after the comparison is successful, considering that although the counting value meets the corresponding expected conditions, the situation that the corresponding level information is in the opposite state to the expected level information, therefore, by comparing whether the current level information of the signal to be monitored is consistent with the termination level, it can be demonstrated whether each level information collected in the monitoring stage is consistent with the expected level information, so it can be more accurately and quickly determined whether the trigger signal is satisfied.
[0058] Optionally, the trigger component 240 is preset with a termination level. After receiving the first notification, the trigger component 240 in the working state compares the level information of the currently collected signal to be monitored with the termination level, and if the comparison is successful, generates a trigger signal and sends it to the controller.
[0059] Optionally, if the trigger component 240 receives a monitoring enable signal, when the monitoring enable signal is a first value, the trigger component 240 switches to a working state.
[0060] In a possible case, the trigger component is also used to receive the comparison results sent by each comparison unit when in a working state, and then if the comparison results sent by each comparison unit are all successful, the level information of the currently collected signal to be monitored is compared with the termination level, and if the comparison is successful, a trigger signal is generated and sent to the controller. Figure 5 .
[0061] Optional, see Figure 4, the first comparison unit compares the final stage, that is, the count value in the counting component 220, and the first storage unit stores the count value in the current counting component 220 when the level jumps. For example, if the signal to be monitored is a pulse signal, the configuration of the test scenario needs to satisfy two consecutive pulse signals lasting 4s, and needs to satisfy the trigger signal in the second half of the second pulse signal. In this case, the monitoring stage is 3 stages. If the count value of the signal to be monitored in the first stage is 2, the count value of the signal to be monitored in the second stage is 4, and the count value of the signal to be monitored in the third stage is 3, wherein the count value of the first stage is stored in the second storage unit, the count value of the second stage is stored in the first storage unit, and the count value of the third stage is stored in the counting component 220. The comparison is performed through the corresponding comparison components, wherein the comparison in the first stage is unsuccessful, and the comparisons in the second and third stages are successful, then the generator 234 cannot generate the first notification, and needs to continue counting the signal to be monitored. When the current count value of the counting component is greater than the first preset threshold after the level jumps, the control unit When the element 232 receives the update request, it will instruct the i-th storage unit to read the count value from the i-1-th storage unit and update it to its own count value, and the first storage unit will read the count value from the temporary memory of the counting component and update it to its own count value. In this way, the count value of the first stage is stored in the third storage unit, the count value of the second stage is stored in the second storage unit, the count value of the third stage is stored in the first storage unit, and the count value of the fourth stage is stored in the counting component 220, wherein the count value of the fourth stage is 3, and the corresponding comparison components are compared, wherein all comparisons are successful, wherein although the comparisons of the 1st to 3rd stages of the signal to be monitored are not successful, see Figure 4It can be seen that the placement order of each comparison unit corresponds to the progressive order of the count values of each storage unit, so that if there are n stages, the first comparison unit compares the count value of the nth stage, the second comparison unit compares the count value of the n-1th stage, the third comparison unit compares the count value of the n-2th stage, and so on. The nth comparison unit corresponds to the count value of the first stage. Since the count value is greater than the first preset threshold after each level jump, thereby triggering an update request to the control unit, the control unit will instruct the count values of each storage unit to be transmitted in a progressive manner. In this way, it can be ensured that the count value of the nth stage stored in the counting component 220, the first storage unit stores the count value of the n-1th stage, the second storage unit stores the count value of the n-2th stage, and so on. The n-1th storage unit stores the count value of the first stage. Before the comparison is successful, the counting component 220 will still count, and when the count value is greater than the first preset threshold, the count value will be stored in the corresponding storage unit in a progressive manner, so that each comparison unit compares the three most recent stages of collecting the signal to be monitored. Therefore, in this example, the comparison of the 2nd to 4th stages of the signal to be monitored is successful.
[0062] For example, if the signal to be monitored is a pulse signal, the test scenario is configured to trigger only at a high level. In other words, in this test scenario, no corresponding expected condition is set, and only the termination level is set to a high level. In this case, the expected accuracy in the expected condition corresponding to each comparison unit is C.
[0063] Optionally, after the trigger component 240 generates a trigger signal and sends it to the controller, a clear signal is sent to the control unit 232, and the control signal clears the count values of n-1 storage units according to the clear signal.
[0064] In one possible case, as the test frequency increases, the probability of sampling glitches also increases. In order to reduce the impact of glitches on subsequent comparison results, the counting component 220 determines whether the count value is greater than a first preset threshold when a level jump occurs in the signal to be monitored. If not, it is considered that the level jump is caused by the glitch rather than a normal level jump of the signal to be monitored. Therefore, its own count value is updated to the sum of its own count value and its own temporary memory value plus 1, thereby preventing the glitches from affecting subsequent comparison results.
[0065] For example, when counting the first stage, if the first preset threshold is 4 and the current count value is 6, a level jump occurs at this time. The counting component will think that the first stage is over and store the count value 6 in the temporary memory, and clear the current count value. In the process of counting the second stage, when the count value is 3, a level jump occurs again. The counting component believes that it should not enter the third stage and the second stage is invalid, so it gives up generating an update request, updates its own count value to 11, and continues to count stage 1 to shield pulses with a duration that is too short. The advantage of this is that there are a lot of glitches in the process of the monitored signal changing. The probability of sampling glitches can only be avoided by reducing the frequency. It is necessary to reconfigure the expected parameters according to the sampling frequency. This method can shield the glitches without changing the sampling frequency. For another example, if the signal to be monitored changes logically exactly as expected. When the expected value of the final stage is set to 0, the expected accuracy is set to C, and the first preset threshold is set to 4, the first comparison unit will always pass. At the last level jump, the counting component starts to count the final stage. Since the count value of the counting component will increase with the acquisition time, when the count value of the counting component for the final stage is less than the first preset threshold, no update request is generated. Except for the first comparison unit, other comparison units will fail to pass the comparison. Therefore, when the count value of the counting component is less than the first preset threshold, although the count value meets the expected conditions of the final stage, the first notification cannot be generated. When the count value of the counting component is greater than the first preset threshold, that is, 4, the counting component generates an update request. In this case, considering that the expected value of the final stage is less than the first preset threshold, if the final stage is directly determined to be successfully compared according to the expected conditions, it will lead to the problem of mistakenly determining the burr as meeting the expected conditions of the final stage. Therefore, by considering whether the count value of the final stage meets the first preset threshold and then judging whether the corresponding expected conditions are met, it is possible to avoid the burr from affecting the accuracy of the monitoring results.
[0066] In one possible case, in order to improve the efficiency of monitoring the signal to be monitored, since the expected conditions corresponding to each stage are configurable, the tolerance of the expected conditions corresponding to the first stage can be set larger, that is, the expected accuracy can be set greater than the third preset threshold. In this way, the first stage can be entered quickly, and it is only necessary to determine whether the subsequent stages meet the corresponding expected conditions. If they are all met, the signal to be monitored can trigger the trigger signal.
[0067] Optionally, in a test scenario, it is necessary to configure the monitoring enable signal to be a first value, a first preset threshold, a collection frequency, a termination level, and expected conditions corresponding to each comparison unit.
[0068] Optionally, the trigger signal is used to characterize the monitoring result of the module to be monitored. In one possible case, if the module to be monitored fails, the input signal of the module to be monitored is used as the signal to be monitored. In the monitoring environment, the configured expected conditions and termination levels are used to monitor whether the signal to be monitored is abnormal. If, during the process of monitoring the signal to be monitored, the trigger component generates a trigger signal and sends it to the controller, it means that the input signal is abnormal, and the module to be monitored cannot enter the working state due to the input signal.
[0069] In another possible situation, if the module to be monitored is monitored for faults, the output signal or internal signal of the module to be monitored is used as the signal to be monitored. Under the monitoring environment, the configured expected conditions and termination levels are used to monitor whether the signal to be monitored is abnormal. If, during the process of monitoring the signal to be monitored, the trigger component generates a trigger signal and sends it to the controller, it means that the output signal or the internal signal is abnormal, and it can be inferred that the module to be monitored has failed in the working state.
[0070] There is another possible situation, if the module to be monitored is monitored to be working normally, if a trigger signal is generated and sent to the controller, it means that the module to be monitored is in a normal working state.
Claims
1. A chip, characterized in that: It includes a module to be monitored, a monitoring module and a controller; The module to be monitored is provided with a test terminal and a function to be tested; The monitoring module is connected to the monitoring module via the test terminal, and is used to accumulate the number of times the signal to be monitored of the function to be tested in the i-th stage is collected; When the level of the signal to be monitored changes, the number of times the signal to be monitored in the i+1th stage is collected is accumulated; The monitoring module is also used to compare the level information of the signal to be monitored in the final stage with the termination level if the count values accumulated in each stage of the function to be tested meet the expected conditions of the corresponding stage, and if the comparison is successful, generate a trigger signal and send it to the controller; The controller is used to determine the monitoring result of the module to be monitored according to the trigger signal.
2. The chip according to claim 1, characterized in that: The monitoring module includes: a collection component, a counting component, a comparison component and a trigger component; the collection component and the trigger component are both connected to the module to be monitored; the trigger component is connected to the controller; the collection component and the comparison component are both connected to the counting component; the comparison component is connected to the trigger component; The acquisition component is used to collect the signal to be monitored in the i-th stage from the module to be monitored through the test end, and send the signal to be monitored to the counting component; The counting component is used to count the number of acquisitions of the signal to be monitored in the i-th stage, and when the level of the signal to be monitored jumps, the number of acquisitions in the i+1-th stage is counted; The comparison component is used to compare the count value of the signal to be monitored at any stage with the expected condition of the corresponding stage, and if the comparison is successful, generate a first notification and send it to the trigger component; The trigger component is used to compare the level information of the currently collected signal to be monitored with the termination level after receiving the first notification, and if the comparison is successful, generate a trigger signal and send it to the controller.
3. The chip according to claim 2, characterized in that: The comparison component includes n-1 storage units, a control unit and n comparison units; the comparison units include a first comparison unit and a second comparison unit; the first comparison unit is one of the n comparison units; the second comparison unit is any comparison unit other than the first comparison unit among the n comparison units; each storage unit has a one-to-one corresponding second comparison unit; the first comparison unit is connected to the counting component; wherein n is a positive integer greater than or equal to 1; the count value of the counting component is used to represent the count value in the final stage; The counting component is also used for storing the count value in the temporary memory of the counting component when the level of the signal to be monitored changes, clearing the current count value, and collecting the count value of the signal to be monitored in the next stage; The counting component is also used to send an update request to the control unit when the count value is greater than a first preset threshold; the update request is used to instruct the control unit to store the count value in the temporary memory of the counting component to the corresponding storage unit; The control unit is used to instruct the i-th storage unit to update the count value read from the i-1-th storage unit to its own count value in sequence according to the update request; The first storage unit reads the count value from the temporary memory of the counting component and updates it into its own count value, wherein i is a positive integer less than or equal to n; Any one of the storage units is used to store the count value of any stage except the final stage; The first comparison unit is used to compare the count value of the counting component with the expected condition of the corresponding stage and output a comparison result; The second comparison unit is used to compare the count values stored in the one-to-one corresponding storage units with the expected conditions of the corresponding stages, and output the comparison result.
4. The chip according to claim 3, characterized in that: The comparison component further comprises a generator; the generator is connected to the output end of each comparison unit; The generator is used for generating a first notification and outputting the notification to the trigger component when the comparison result of each comparison unit is successful.
5. The chip according to any one of claims 1 to 4, characterized in that: The monitoring module is pre-configured with the expected conditions for each stage, as well as the termination level.
6. The chip according to claim 5, characterized in that: The expected conditions include an expected value and an expected accuracy; if the difference between the count value and the expected value is within the expected accuracy, the comparison is successful.
7. The chip according to claim 5, characterized in that: If the monitored signal corresponding to the function to be tested has k stages, the first expected conditions of the corresponding stages are set in the 1st to the kth comparison units respectively; the second expected conditions of the corresponding stages are set in the kth to the nth comparison units respectively; n is not less than k; the error value in the second expected condition satisfies the second preset threshold value, so that the kth to the nth comparison units always maintain successful comparison.
8. The chip according to claim 5, characterized in that The counting component is also used to determine whether the count value is greater than a first preset threshold when the level of the signal to be monitored jumps. If not, update its own count value to the sum of its own count value and its own temporary memory value plus 1.
9. The chip according to claim 5, characterized in that: The trigger component is also used to send a clear signal to the control unit after the trigger signal is sent to the controller; The control unit is used to clear the count values of the n-1 storage units according to the clear signal.
10. The chip according to claim 5, characterized in that: The trigger component is also used to receive a monitoring enable signal; when the monitoring enable signal is a first value, the trigger component switches to a working state.