System and method for cache filtering

Abstract

A method for filtering an address from a cache includes receiving, by a filter, a data request including an address specifying a memory location of the requested data; querying a filter to determine whether the address is cacheable or non-cacheable; and in response to determining that the address is not cacheable, blocking caching of the data and the address associated with the data. Other example methods, systems, and non-transitory computer-readable media for filtering addresses from a cache are also provided.

Description

Technical Field

[0001] One or more example embodiments relate to systems, methods, and / or non-transitory computer-readable storage media for cache filtering. Background Art

[0002] Computing systems typically include a cache and a main memory. A cache is a memory implemented using hardware and / or software that is used to provide recently and / or more frequently accessed data to a requester in or associated with a computer system. When data is requested, the cache is queried to see if the requested data is available. If so, the data is retrieved and provided to the requester. This scenario is typically referred to as a "cache hit." If the requested data is not found in the cache (e.g., referred to as a "cache miss"), the data is retrieved from the main memory and provided to the requester. In such a scenario, the requested data found in the main memory can be copied to the cache (e.g., via the cache). If the cache is full, other data in the cache is evicted to make room for the new data.

[0003] Eviction of data in a cache may be determined based on different replacement or caching algorithms. For example, eviction of data in a cache may be based on a least frequently used algorithm that tracks how often data is accessed and then evicts entries with the lowest counts first. Other algorithms include a least recently used algorithm that evicts the least recently accessed entries first and a most recently used algorithm that evicts the most recently accessed entries first. Summary of the invention

[0004] The independent claims define the scope of protection sought by various example embodiments. Example embodiments and / or features described in this specification that do not fall within the scope of the independent claims, if any, are to be construed as examples that aid in understanding the various embodiments.

[0005] According to one or more example embodiments, a system for filtering addresses from a cache is provided. The system includes a filter in communication with a memory. The filter includes a filter data structure. The filter is configured to receive a data request including an address that specifies a memory location of the requested data, query the filter data structure to determine whether the address is cacheable or not cacheable, and in response to determining that the address is not cacheable, prevent caching of the data and an address associated with the data.

[0006] In various embodiments, the system may include a cache memory and a cache controller in communication with the cache memory. The cache controller may be configured to receive a data request including an address, query the cache memory to determine whether the cache memory includes the address, and in response to determining that the address is present in the cache memory, update a cache state of the cache memory based on the received data request. Additionally and / or alternatively, the cache controller may be configured to receive a data request including the address, query the cache memory to determine whether the cache memory includes the address, and in response to determining that the address is not present in the cache memory and the address is cacheable, cache the data and the address in the cache memory.

[0007] In various embodiments, the filter can be configured to compare an address associated with a received data request to a set of addresses in a filter data structure, identify the address as cacheable in response to the address matching one of the addresses in the set of addresses, and identify the address as uncacheable in response to the address not matching any of the addresses in the set of addresses.

[0008] In various embodiments, the filter may be a Bloom filter.

[0009] In various embodiments, the filter may be configured to insert the address of the received data request into a filter data structure.

[0010] In various embodiments, the filter may be configured to determine a number of addresses in a filter data structure and, in response to the number of addresses exceeding a defined threshold, purge the addresses from the filter data structure.

[0011] In various embodiments, the filter data structure includes a bit array having bit values, and the filter may be configured to generate hash values ​​for the addresses based on a plurality of hash functions and set a bit value of the bit array associated with each hash value to 1.

[0012] In various embodiments, the filter may be configured to determine a fill level of the bit array and, in response to the fill level exceeding a defined threshold, clear at least a portion of the bit values ​​of the bit array to zero.

[0013] At least one other example embodiment provides a method for filtering addresses from a cache, the method comprising receiving, by a filter, a data request including an address that specifies a memory location of requested data; querying the filter to determine whether the address is cacheable or not cacheable; and in response to determining that the address is not cacheable, preventing caching of the data and an address associated with the data.

[0014] In various embodiments, the method may also include receiving, by the cache, a data request including the address, querying the cache to determine whether the cache includes the address, and in response to determining that the address is present in the cache, updating a cache state of the cache based on the received data request.

[0015] In various embodiments, the method may also include receiving, by the cache, a data request including the address, querying the cache to determine whether the cache includes the address, and caching the data and the address in the cache in response to determining that the address is not present in the cache and the address is cacheable.

[0016] In various embodiments, querying a filter to determine whether the address is cacheable or not cacheable may include comparing an address associated with a received data request to a set of addresses in the filter, identifying the address as cacheable in response to the address matching one of the addresses in the set of addresses, and identifying the address as not cacheable in response to the address not matching any of the addresses in the set of addresses.

[0017] In various embodiments, the method may further include inserting an address associated with the received data request into the filter.

[0018] In various embodiments, inserting the address associated with the received data request into the filter may include inserting the address into the filter in response to preventing caching of the data and the address associated with the data.

[0019] In various embodiments, the method may further include determining a number of addresses in the filter, and in response to the number of addresses exceeding a defined threshold, removing the address from the filter.

[0020] In various embodiments, the filter includes a bit array having bit values, and inserting the address associated with the received data request into the filter may include generating hash values ​​of the address based on multiple hash functions and setting the bit value of the bit array associated with each hash value to 1.

[0021] In various embodiments, the method may further include determining a fill level of the bit array, and clearing at least a portion of the bit values ​​of the bit array to zero in response to the fill level exceeding a defined threshold.

[0022] At least one other example embodiment provides a non-transitory computer-readable medium storing computer-readable instructions that, when executed by a processing circuit system, cause the processing circuit system to: receive a data request including an address that specifies a memory location of requested data; query a filter to determine whether an address associated with the received data request is cacheable or non-cacheable; and in response to determining that the address is not cacheable, prevent caching of the data and an address associated with the data.

[0023] In various embodiments, the processing circuitry may be further caused to query the cache to determine whether the cache includes the address, and in response to determining that the address is present in the cache, update a cache state of the cache based on the received data request.

[0024] In various embodiments, the processing circuitry may be further caused to query the cache to determine whether the cache includes the address, and in response to determining that the address is not present in the cache and the address is cacheable, cache the data and the address in the cache.

[0025] At least one other example embodiment provides a system for filtering addresses from a cache memory. The system includes: a component for caching data and an address associated with the data; and a component for: receiving a data request including an address, the address specifying a memory location of the requested data, querying a filter (e.g., a filter data structure) to determine whether the address is cacheable or not cacheable, and in response to determining that the address is not cacheable, preventing caching of the data and the address associated with the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Example embodiments will become more fully understood by understanding the detailed description and accompanying drawings given below, in which like elements are represented by like reference numerals, which are given by way of illustration only and thus do not limit the present disclosure.

[0027] Figure 1 is a block diagram of a computing system including a cache and a filter for filtering addresses from the cache according to an example embodiment;

[0028] Figure 2 According to an example embodiment Figure 1 A block diagram of an example computing device of a system;

[0029] Figure 3 is a flow chart of a control method for filtering addresses from a cache according to an example embodiment;

[0030] Figure 4is a flow chart of another control method for filtering addresses from a cache according to an example embodiment;

[0031] Figure 5 is a flow chart of a control method for inserting addresses into a filter and maintaining a desired fill level of the filter according to an example embodiment; and

[0032] Figure 6 is a flow chart of a control method for filtering addresses from a cache according to an example embodiment.

[0033] It should be noted that these drawings are intended to illustrate the general characteristics of methods, structures, and / or materials used in certain example embodiments and to supplement the written description provided below. However, these drawings are not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values ​​or characteristics encompassed by the example embodiments. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0034] Various example embodiments will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown.

[0035] Detailed illustrative embodiments are disclosed herein. However, the specific structural and functional details disclosed herein are representative only for the purpose of describing the exemplary embodiments. However, the exemplary embodiments may be embodied in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0036] It should be understood that there is no intent to limit example embodiments to the particular forms disclosed. On the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.

[0037] It should be understood that various example embodiments described herein may be used in combination.

[0038] Computing systems typically include caches and main memory. In some cases, caches may be polluted with rarely used data. For example, in conventional cache implementations, requested data is indiscriminately passed to the cache even if the data is rarely used or will never be used again. This may cause cache entries to be evicted before any cache hits are generated based on conventional cache replacement algorithms. Therefore, with conventional cache implementations, space in the cache may be wasted on rarely used data, thereby reducing cache performance and increasing cache power consumption.

[0039] According to one or more example embodiments of the present disclosure, computing systems, methods, and non-transitory computer-readable storage media effectively filter data entries from a cache by preventing the cache from caching entries that are unlikely to be needed in the near future. In various embodiments, and as further explained herein, these systems and methods may employ a filter having a data structure for summarizing addresses associated with data seen in the past to select data items to be copied and / or not copied to the cache. For example, a cache filter may be employed to receive a data request including an address that specifies a memory location of the requested data, query a filter data structure to determine whether the address is cacheable or not cacheable, and in response to determining that the address is not cacheable, prevent the associated cache from caching the data and the address associated with the data. In this way, the filter can effectively prevent the cache from being polluted by rarely used data. Therefore, the size of the cache can be more efficient, thereby reducing the amount of data written to the cache by, for example, up to 90%. Furthermore, the cache can experience improved (e.g., significantly improved) cache performance and / or reduced power consumption compared to conventional cache implementations.

[0040] Figure 1 An example computing system 100 for filtering addresses from a cache is illustrated in accordance with at least one example embodiment. Figure 1 As shown, computing system 100 includes filter 102, cache 106 for caching data and specific addresses associated with the data, main memory 112, and data requester 114 in communication with filter 102, cache 106, and main memory 112. Filter 102 includes data structure 104, and cache 106 includes cache memory 108 and cache controller 110. In various embodiments, system 100 may include and / or be associated with one or more suitable computing devices, including routers, switches, computers, etc., for receiving and / or processing data. Although Figure 1 The system 100 is shown as including one data requester, one filter, one cache and one main memory, but it should be understood that the system 100 may include multiple data requesters, multiple filters, multiple caches and multiple memories if necessary. Figure 1 Controller 110 is shown as being part of cache 106, but it is understood that controller 110 may be external to cache 106 and / or part of another controller in system 100, if desired.

[0041] In various embodiments, data requester 114 may send data requests to filter 102, cache 106, and / or main memory 112. In such examples, each data request may include an address that specifies a memory location of the requested data. For example, Figure 1 The filter 102 may receive one or more data requests from the data requester 114. In turn, the filter 102 may insert the address provided with each data request into the data structure 104.

[0042] Figure 1 The data requester 114 and / or other data requesters herein may be any suitable cache client requesting data. For example, the data requester 114 may be one or more controllers (e.g., CPUs, etc.), software applications, state machines, operating systems, web browsers, etc.

[0043] In various embodiments, the filter 102 may query the filter data structure 104 to determine whether an address in a received data request is cacheable or non-cacheable in the cache 106 (e.g., in the cache memory 108). For example, the filter 102 may compare an address associated with the received data request with previously inserted addresses (e.g., a set of addresses) in the filter data structure 104. If the new address matches one of the previously inserted addresses, the filter 102 may identify the address as cacheable. In such an example, because the address has been seen by the filter 102 and inserted into the filter data structure 104, the address will likely generate a cache hit with respect to the cache memory 108. Therefore, in the event that the address is requested multiple times (e.g., twice, etc.) in a short period of time, the address may be repeatedly repeated in the future. For example, this situation often occurs in elephant flow scenarios.

[0044] However, if the new address does not match any previously inserted address, the filter 102 may identify the address as uncacheable. For example, the filter 102 may insert the previously seen address into the data structure 104. If the address does not exist in the data structure 104, the new address is identified as uncacheable because the new address may generate a cache miss with respect to the cache memory 106. Although the new address may be considered uncacheable, the filter 102 may continue to insert the new address into the filter data structure 104. Therefore, if the new address is seen again (e.g., in a subsequent data request from the data requester 114), the filter 102 may identify the address as cacheable.

[0045] Then, in response to determining that the address is not cacheable, the filter 102 may prevent the cache 106 from caching the data and the associated address. For example, the filter 102 may generate a signal indicating that the particular address is not cacheable and then send the signal to the cache 106 (e.g., the cache controller 110). In response to the signal, the cache controller 110 may not cache the particular address and data in the cache memory 108 when the address is not in the cache memory 108, and / or the cache controller 110 may not update the cache state of the cache memory 108 when the address is in the cache memory 108.

[0046] In such an example, if the uncacheable signal is not received, the cache 106 may cache the address and the associated data. For example, and as explained herein, the cache 106 may receive a data request from the data requester 114 and determine that the received address does not exist in the cache memory 108 (e.g., a cache miss). In such a scenario, if the uncacheable signal associated with the address is not received within a time period defined by receiving the data request, the cache controller 110 may communicate with the main memory 112 and cache the data and the address in the cache memory 108.

[0047] In some embodiments, the filter 102 may generate a signal for a particular address and send it to the cache 106, regardless of whether the address is uncacheable or cacheable. For example, when an address with a data request is received, the filter 102 may set the cacheable value associated with the address to 1 (e.g., a default value). If the filter 102 determines that the address is cacheable, the cacheable value remains unchanged (e.g., remains at 1). However, in response to determining that the address is not cacheable, the filter 102 may change the cacheable value associated with the address to 0 to indicate an uncacheable event. The filter 102 then transmits a signal with a cacheable value of 1 or 0 to the cache 106 (e.g., the cache controller 110). In response to the signal with a cacheable value of 1, the cache controller 110 may cache the address and data in the cache memory 108, and / or update the cache state of the cache memory 108 when the address is in the cache memory 108. Alternatively, if the cacheable value is 0, cache controller 110 may not cache the address and data and / or may not update the cache status of cache memory 108 .

[0048] In various embodiments, filter 102 can be any suitable type of filter having a data structure for tracking addresses and detecting address duplication and / or associated with the data structure. For example, filter 102 can be implemented using a Bloom filter, a cuckoo filter, a ternary content addressable memory (TCAM) filter, a filter with an associated dictionary data structure, and the like. In such an example, a Bloom filter can insert multiple hash values ​​for each received address (as further explained below), and therefore each address requires several bits of data. However, as further explained below, since each address has multiple hash values, when querying the filter, the Bloom filter may provide false positives. Unlike a Bloom filter, a TCAM filter can insert an actual address (rather than a hash value), so each address uses more data bits than a Bloom filter. In addition, a dictionary data structure can use more data bits per address than a Bloom filter, but rarely provides false positives. Although the example of filter 102 is explained below as being about a Bloom filter, it should be understood that any other suitable type of filter (e.g., a TCAM filter, a cuckoo filter, a dictionary data structure, etc.) can be used without departing from the scope of the present disclosure.

[0049] For example, when a Bloom filter is employed, the Bloom filter can provide sufficient indication of whether an address has been seen recently. In some examples, the Bloom filter can function in a conventional manner. For example, the Bloom filter can include a space-efficient and probabilistic data structure (e.g., data structure 104) that uses a hash function to insert entries into a bit array of the data structure. More specifically, the Bloom filter can be composed of a set A={a1, a2, ..., a ... n} and a set of K cryptographic hash functions H = {h1, h2, ..., h k In such an example, these elements may correspond to the inserted addresses.

[0050] For example, the bit values ​​of the bit array in the data structure may be initially set to 0. When the Bloom filter receives an address (a) for insertion into the data structure, the filter may generate a hash value for the address (a) based on a plurality of hash functions (e.g., a set of cryptographic hash functions or a set of cyclic redundancy check (CRC) functions). In such an example, each hash function (h1, h2, ..., h k ) can receive an address (a) as input and generate hash values ​​(h1(a), h2(a), ..., h1(a), h2(a), ..., h2(a)) within a range of defined sizes based on bit arrays (e.g., a range of [1 to m] for m-bit arrays). k(a)). The Bloom filter may then set the bit value of the bit array associated with each hash value to 1, thereby inserting the address (a) into the data structure. For example, if one hash function (h1) generates a hash value of 2 based on address (a), the bit value at the second index position in the bit array is set to 1. Similarly, if another hash function (h2) generates another hash value of 4 based on address (a), the bit value at the fourth index position in the bit array is also set to 1.

[0051] The Bloom filter repeats such a function for each received address. For example, as described above, when the Bloom filter receives another address (a2) for insertion into the data structure, the filter generates a hash value (a2) for the address based on each hash function, and then sets the bit value of the bit array associated with each hash value to 1. For example, if the hash function (h1) generates a hash value of 3 based on address (a2), the bit value at the third index position in the bit array is set to 1. If the bit array is already set to 1 due to another inserted address, the bit value remains at 1. For example, the hash function can generate a hash value of 4 based on address (a2). In this case, the bit value at the fourth index position is already set to 1 due to the insertion of address (a), and therefore does not change.

[0052] The Bloom filter can also query the address (a) in the data structure to determine whether the address is cacheable or not. For example, after each hash function generates a hash value based on address (a), the hash value can be compared to the value at the index position in the bit array. For example, if a hash function (h1) generates a hash value 2 based on address (a) as described above, the value (0 or 1) at the second index position in the bit array can be used to determine whether the address is cacheable or not. This can be done for each generated hash value of address (a) and its associated value at the index position. If all values ​​at the index position are set to 1, then address (a) is an element in set A (e.g., a∈A). In other words, address (a) has most likely been previously seen by the Bloom filter and inserted into the filter data structure as described above. In such an example, address (a) can be identified as cacheable. However, if any value at the index position is 0, then address (a) is not an element in set A (e.g., ). In this case, address (a) may be identified as uncacheable. As described herein, the Bloom filter may then prevent cache 106 from caching the data and the associated address in response to determining that the address is uncacheable.

[0053] Continue to refer Figure 1, the filter 102 can have a false positive hit probability associated with the address received in the data request. This is particularly the case for Bloom filters and / or other filters of similar functionality. For example, when using a Bloom filter, a false positive hit may occur if all index positions corresponding to a particular address (a) are set to 1 because other addresses (rather than a) are inserted into the array. In such an example, the Bloom filter can indicate that address (a) is an element in set A and is therefore cacheable even if address (a) has not been previously inserted into the array. In such an example, the probability of a false positive hit typically increases with the number of addresses stored in the Bloom filter. Therefore, in some embodiments, it is desirable to control the filter fill level to reduce the chance of a false positive hit.

[0054] In various embodiments, the filter 102 may implement a maintenance strategy to control its fill level. For example, when a defined time period is met, the filter 102 may clear all or a portion of the addresses, the bit values ​​associated with the addresses, etc. from the filter data structure 104. In such an example, the defined time period may be 100 microseconds, 1 second, two seconds, three seconds, and / or another suitable time period based on the cache size, the expected number of addresses stored, etc. In other examples, the filter 102 may determine the number of addresses in the filter data structure 104, and then clear all or a portion of the addresses from the filter data structure 104 in response to the number of addresses exceeding a defined threshold. In such an example, the number of addresses may be determined by, for example, summing the inserted addresses. If the determined number of addresses exceeds a defined threshold, all or a portion of the addressed addresses may be removed from the data structure 104. In such an example, the defined threshold may be based on the cache size, the expected number of stored addresses, etc. For example, the defined threshold may be 10,000 addresses, 15,000 addresses, 20,000 addresses, 25,000 addresses, 30,000 addresses, more than 30,000 addresses, less than 10,000 addresses, and the like.

[0055] In other examples, when, for example, a Bloom filter or another similar functional filter is used, the maintenance strategy can be based on the fill level of the bit array. For example, as described above, when a Bloom filter is used, the Bloom filter inserts the address into its filter data structure by setting the bit value of the index position in the bit array associated with each hash value to 1. In such an example, the number of 1s in the bit array corresponds to the fill level of the bit array. In connection with this, the Bloom filter can determine the fill level of the bit array in a data structure (e.g., data structure 104), and then clear all or a portion of the bit values ​​of the bit array to 0 in response to the fill level exceeding a defined threshold. In such an example, the defined threshold can be based on, for example, any expected number of storage addresses, the number of hash functions used, the cache size, etc.

[0056] Continue to refer Figure 1 , filter 102 and / or cache 106 may be partially or completely implemented in hardware. For example, data structure 104 and / or cache memory 108 may be a data structure on one or more chips, such as a chip associated with and / or in communication with data requester 114. In some examples, cache memory 108 may be referred to as a high-speed static random access memory (SRAM). In other examples, filter 102 and / or cache 106 may be partially or completely implemented in software (e.g., a software-managed filter and / or cache).

[0057] Regardless of whether the cache 106 is implemented in hardware and / or software, the cache 106 can temporarily store recently and / or frequently accessed data and provide it to the data requestor 114, update the cache state, etc. For example, the cache controller 110 can receive a data request including an address from the data requestor 114 as described above, and then query the cache memory 108 to determine whether the cache memory 108 includes the received address. If the received address exists in the cache memory 108 (e.g., a cache hit), the cache controller 110 can provide the data associated with the address to the data requestor 114. In response to determining that the address exists in the cache memory 108, the cache controller 110 can update the cache state of the cache memory 108 based on the received data request. This can affect when the address and data associated with the cache hit are evicted from the cache 106 depending on the specific replacement or caching algorithm employed by the cache controller 110.

[0058] In other scenarios, the cache controller 110 may determine that the received address does not exist in the cache memory 108 (e.g., a cache miss). In such a scenario, the main memory (e.g., dynamic random access memory (DRAM)) 112 may provide data associated with the address to the data requester 114. In addition, in response to the received address not being present in the cache memory 108, if the filter 102 deems the address cacheable, the cache controller 110 may communicate with the main memory 112 and cache the data and address in the cache memory 108 (as explained herein). For example, if the received address does not exist in the cache memory 108 and the address is cacheable, the cache controller 110 may receive the data and the associated address from the main memory 112 and insert such information into the cache memory 108.

[0059] Although the above examples are described as implementing the filter 102 and the cache 106 in hardware, it should be understood that the filter 102 and / or the cache 106 can achieve similar functions when implemented in software. For example, when implemented in software, the cache 106 can receive a data request including an address and then determine whether the address is included in the cache. In such an example, as described above, the cache 106 can then update the cache state, cache data and address, etc. Such embodiments and other embodiments discussed herein can be performed by one or more processors (or processing circuit systems) at an applicable device. For example, according to one or more example embodiments, at least one memory may include or store computer-readable instructions that, when executed by at least one processor, cause the processor or applicable device to perform one or more operations discussed herein.

[0060] For example, Figure 2 The diagram shows that it can be achieved Figure 1 An example embodiment of a device 200 that implements the functionality of a data requester 114, a filter 102, and / or a cache 106. Figure 2 As shown, the device 200 includes a processor (e.g., processing circuit system) 202, a memory 204 connected to the processor 202, and a network interface 206 for receiving data from / sending data to other network devices, systems, etc. As will be appreciated, depending on the implementation of the device 200, the device may include more than one Figure 2 Further components are shown, including one or more additional processors, memories, network interfaces, etc.

[0061] exist Figure 2In the example of , memory 204 can be a computer-readable storage medium, which typically includes random access memory (RAM), read-only memory (ROM) and / or a permanent mass storage device, such as a disk drive. Memory 204 can also store an operating system and any other routines / modules / applications for providing the functions of the device to be executed by processor 202. These software components can also be loaded into memory 204 from a separate computer-readable storage medium using a drive mechanism (not shown). Such a separate computer-readable storage medium may include an optical disk, a magnetic tape, a DVD / CD-ROM drive, a memory card, or other similar computer-readable storage medium (not shown). In some example embodiments, the software components can be loaded into memory 204 via interface 206.

[0062] The processor 202 may be configured to execute computer-executable instructions of a computer program by performing arithmetic, logical, and input / output operations of the system. The instructions may be provided to the processor 202 by the memory 204.

[0063] Figure 3 A control method 300 for filtering addresses from a cache is illustrated in accordance with at least one example embodiment. In various embodiments, the example control method 300 may represent a "filter before cache" scenario, where the filter may be independent of the cache. In such an example, the cache does not provide feedback to the filter. As further explained below, Figure 3 The control method 300 generally includes, for example, querying a filter to determine cacheability of an address, updating a filter state, querying a cache (e.g., causing a cache hit or a cache miss), and inserting the address and associated data into the cache or preventing insertion of the address and associated data based on the determined cacheability of the address and the cache query.

[0064] As shown, method 300 begins at 302 where a data request with an address is received from a data requester (eg, a processor, etc.) by a cache and filter (such as a Bloom filter described herein or another suitable filter). Control then proceeds to 304 .

[0065] At 304, the filter queries the address of the received data request. For example, a previously seen address or a representation thereof may be inserted into the filter as described above. The filter may search the newly received address to see if the address was previously inserted. For example, the filter may compare the newly received address or one or more representations thereof with previously inserted addresses (e.g., a set of addresses). In various embodiments, a cacheability attribute (e.g., a cacheability value) associated with the address may be determined and stored until needed. For example, if the new address matches one of the previously inserted addresses, the filter may identify the address as cacheable. In such an example, the filter may set the attribute associated with the address to 1 (e.g., a default value), or if the address is cacheable, keep the attribute at 1. Alternatively, if the new address does not match one of the previously inserted addresses in the filter, the address is not cacheable, and the filter may set the attribute associated with the address to 0, or keep the attribute at 0. Control then proceeds to 306.

[0066] At 306, the filter state is updated. For example, the filter can insert the address of the received data request into the filter. In such an example, for example, if the address does not exist in the filter, the filter can insert the address. Control then proceeds to 308.

[0067] At 308, control queries the cache for the address of the received data request to determine whether the address exists therein. For example, the cache may determine whether the address is stored therein by implementing conventional methods. If the address exists in the cache (e.g., a cache hit), control proceeds to 310. If the address does not exist in the cache (e.g., a cache miss), control proceeds to 316.

[0068] At 310, control updates the cache state of the cache associated with the address. For example, the internal cache state may be updated based on a particular replacement or caching algorithm employed by the cache (e.g., a least recently used (LRU) algorithm, etc.). In turn, this may have an impact when the address and data associated with the cache hit are evicted from the cache. Control then proceeds to 312.

[0069] At 312, control retrieves the requested data from the cache and returns the cached data to the data requester. In various embodiments, the retrieval and return of the requested data can be accomplished by conventional methods. Control then proceeds to 314, where the next data request is received from the data requester. Control then returns to 304.

[0070] As described above, if it is determined at 308 that the address does not exist in the cache, control proceeds to 316. At 316, control retrieves the address from main memory (e.g., Figure 1 The main memory 112 of the data requester) extracts the requested data and returns the data to the data requester. In various embodiments, retrieving and returning the requested data from the main memory can be achieved by conventional methods. Control then proceeds to 318.

[0071] At 318, if cacheability has not been determined, for example, at 304, control may determine whether the address of the received data request is cacheable. For example, if the cacheability attribute associated with the address is determined at 304, the received data request may be considered cacheable (e.g., previously considered cacheable at 304). If not, the received data request may be considered non-cacheable. In other examples, if the new address does not match one of the addresses previously inserted in the filter, the filter may identify the address as non-cacheable as described above. However, if the new address matches one of the addresses previously inserted, the filter may identify the address as cacheable. If the address is determined to be cacheable at 318 (or at 304), control proceeds to 320. However, if the address is determined to be non-cacheable at 318 (or at 304), control proceeds to 322.

[0072] At 320, control inserts the address and associated data into the cache. In such an example, if the cacheable value associated with the address is at a defined value (e.g., 1, etc.), the cache may insert the address. In various embodiments, the insertion of the cacheable address and associated data may be accomplished by conventional methods. Control then proceeds to 314, where the next data request is received from the data requestor as described above.

[0073] At 322, control blocks the request from being inserted into the cache. For example, as described above, if the cacheable value of the address is at another defined value (e.g., 0, etc.), the cache may be blocked from caching the address and the data associated with the address. Control then proceeds to 314, where the next data request is received from the data requestor as described above.

[0074] Figure 4 Another control method 400 for filtering addresses from a cache is illustrated in accordance with at least one example embodiment. In various embodiments, the example control method 400 may represent a "cache lookup before filter update" scenario, where a filter state update may depend on a cache lookup result. As further explained below, Figure 4The control method 400 generally includes, for example, querying a cache (e.g., causing a cache hit or a cache miss), querying a filter to determine the cacheability of an address, inserting the address and associated data into the cache or preventing the insertion of the address and data based on the determined cacheability of the address and the cache query, and updating the filter state based on the cache query. In such an example, if a cache miss scenario occurs for a certain address, the address is inserted into the filter. However, if a cache hit scenario occurs for the address, the address is removed from the filter. Through this implementation, the filter can be prevented from being polluted by addresses currently stored in the cache.

[0075] As shown, method 400 begins at 402, where a data request with an address is received from a data requester by a filter and cache as described herein. In such an example, the filter may be a Bloom filter or another suitable filter explained herein. Control then proceeds to 404.

[0076] At 404, control determines whether the address of the received data request exists in the cache by querying the cache for the address. For example, the cache can determine whether the address is stored therein by implementing a conventional method. If the address exists in the cache (e.g., a cache hit), control proceeds to 406.

[0077] At 406, control updates the cache state of the cache associated with the address. For example, as described above, the internal cache state may be updated according to a particular replacement or caching algorithm employed by the cache. Control then proceeds to 408.

[0078] At 408, control retrieves the requested data from the cache and returns the cached data to the data requester. In various embodiments, the retrieval and return of the requested data can be accomplished by conventional methods. Control then proceeds to 410, where the next data request is received from the data requester. Control then returns to 404.

[0079] If it is determined at 404 that the address does not exist in the cache, control proceeds to 412. At 412, control retrieves the requested data from the main memory and returns the data to the data requester, as described above. Retrieving and returning the requested data from the main memory can be accomplished by conventional methods. Control then proceeds to 414.

[0080] At 414, the filter queries the address of the received data request as described above. For example, a previously seen address or a representation thereof may be inserted into the filter as described above. The filter may search the newly received address to see if the address was previously inserted as described above. Control then proceeds to 416.

[0081] At 416, control determines whether the address of the received data request is cacheable. For example, if the new address matches one of the previously inserted addresses in the filter, the filter can identify the address as cacheable (e.g., set the cacheability value of the address to a first value) as described above. However, if the new address does not match one of the previously inserted addresses in the filter, the filter can identify the address as non-cacheable (e.g., set the cacheability value of the address to a second value) as described above. If it is determined at 416 that the address is cacheable, control proceeds to 418.

[0082] At 418, control inserts the address and associated data into the cache. In such an example, if the cacheable value associated with the address is at a defined value as described above, the cache may insert the address. In various embodiments, the insertion of the cacheable address and associated data may be accomplished by conventional methods. Control then proceeds to 420.

[0083] At 420, control may update a filter state of a filter associated with the address based on, for example, inserting the address into a cache. For example, in response to determining at 416 that the address is cacheable and / or inserting the address into a cache at 418, control may remove the address from the filter. Thus, in this example, the filter is prevented from being polluted by an address that has been inserted into the cache. Control then proceeds to 410, where a next data request is received from the data requestor as described above.

[0084] If it is determined at 416 that the address is not cacheable, control proceeds to 422. At 422, control prevents the request from being inserted into the cache as described herein. Control then proceeds to 424.

[0085] At 424, control may update the filter state of the filter associated with the address based on not inserting the address into the cache. For example, in response to determining at 416 that the address is not cacheable and / or preventing the requested address from being inserted into the cache at 422, control may insert the address into the filter. Control then proceeds to 410, where a next data request is received from the data requestor as described above.

[0086] Figure 5 A control method 500 for inserting addresses into a filter and maintaining a desired fill level of the filter is illustrated according to an example embodiment, and Figure 6 A control method 600 for filtering addresses from a cache is illustrated according to an example embodiment. Figure 5 and Figure 6In the example of , the filter includes a Bloom filter having a data structure implementing a hash function for inserting entries into a bit array of the data structure as described above. Although the control methods 500, 600 are described with respect to a Bloom filter, it should be understood that the control methods 500 and 600 may be implemented using any other suitable type of filter if desired.

[0087] refer to Figure 5 , method 500 begins at 502, where a Bloom filter sets all bit values ​​in a bit array to 0. For example, as described above, at least some bit values ​​in the bit array may be set to 1 based on a previously inserted address. In such an example, the Bloom filter clears the bit array to a default setting by forcing all bit values ​​to 0. Control then proceeds to 504, where the Bloom filter receives a data request with an address from a data requester as described herein.

[0088] At 506, the Bloom filter generates a hash value for the received address based on a plurality of hash functions. For example, as described above, each hash function of the Bloom filter receives the address as input and generates a hash value that falls within the size of the bit array. For example, if the size of the bit array is 10, each hash function generates a hash value that is between 1 and 10. Control then proceeds to 508.

[0089] At 508, the Bloom filter sets the bit value in the bit array associated with each hash value generated at 506 to 1. For example, if one hash function generates a hash value of 10 based on the received address, the bit value at the tenth index position in the bit array is set to 1. Additionally, if a different hash function generates a hash value of 6 based on the received address, the bit value at the sixth index position in the bit array is set to 1. This process continues for each hash function and resulting hash value. If multiple hash functions generate the same hash value, the bit value at that index position in the bit array is set to 1. Control then proceeds to 510.

[0090] At 510, the Bloom filter determines whether the fill level of the bit array in the data structure is greater than a defined threshold as described above. For example, the number of 1s in the bit array (set based on the hash value) can correspond to the fill level of the bit array. In such an example, the Bloom filter can determine the fill level by summing the number of 1s in the bit array. The number of addresses stored in the Bloom filter can be approximated as a function of the stored addresses. In various embodiments, the probability of a false positive hit from the Bloom filter generally increases with an increase in the fill level of the bit array (e.g., the number of 1s). This is because any one or more hash functions may generate the same hash value for different addresses. Therefore, a balance between the maximum capacity of the Bloom filter and the probability of a false positive can be achieved.

[0091] If the fill level of the bit array at 510 is greater than the defined threshold, control proceeds to 512. Otherwise, control proceeds to 514. At 512, the Bloom filter clears each bit value of the bit array to 0. In other words, the Bloom filter clears the bit array to the default setting as described above. This effectively resets the Bloom filter. Control then proceeds to 514. In other embodiments, the Bloom filter may clear a portion of the bit values ​​of the bit array. In such an example, the Bloom filter may clear a certain percentage (e.g., 25%, 50%, 75%, etc.) of the bit values. In this way, the Bloom filter may not completely reset the bit array whenever the filter has an overfill level (e.g., exceeding the defined threshold). Instead, the Bloom filter may clear multiple index positions where the bit value is set to 1 to move the fill level back below the defined threshold. Other maintenance methods may include removing addresses from the filter based on when the address was inserted into the filter. For example, the oldest entry may be removed first. In the case of a Bloom filter, such a scheme may typically include regenerating the entire array. In other embodiments, the maintenance method can implement a sliding Bloom filter (e.g., sometimes referred to as a rolling Bloom filter), in which the Bloom filter bit array can be divided into portions to be populated with addresses in sequence. The portions can be reset independently of each other as needed. Regardless of whether the Bloom filter clears every bit value or a portion of the bit values ​​of the bit array to 0, keeping the fill level below a defined threshold can improve and / or maximize the performance of the filter.

[0092] At 514, control determines whether the data requester makes any additional data requests. If so, control proceeds to 516, where the Bloom filter receives the next data request and address. Otherwise, control ends.

[0093] like Figure 6As shown, method 600 begins at 602, where a Bloom filter receives a data request having an address from a data requester as described herein. Control then proceeds to 604, where the Bloom filter generates a hash value for the received address based on a plurality of hash functions. For example, as described above, each hash function of the Bloom filter generates a hash value that falls within the size of a bit array. Control then proceeds to 606.

[0094] At 606, the Bloom filter identifies the bit value in the bit array associated with each generated hash value. Figure 1 and Figure 5 The bit array of the data structure includes index positions with bit values. If three hash functions in the filter generate hash values ​​2, 6, and 10 based on the received address, the bit values ​​at the second index position, the sixth index position, and the tenth index position are identified. Control then proceeds to 608.

[0095] At 608, the Bloom filter determines whether all bit values ​​identified at 606 are set to 1. For example, as described above with respect to Figure 1 and Figure 5 As described, the Bloom filter inserts the previously received address into the data structure by setting the bit value associated with the generated hash value to 1. For example, the bit values ​​at the second index position, the sixth index position, and the tenth index position of the bit array can be set to 1 based on the previously received address. In this example, all bit values ​​identified at 606 are set to 1 to indicate that the Bloom filter has likely seen the address previously (e.g., to take into account the possibility of false positives). If all bit values ​​identified at 606 are set to 1, control proceeds to 610, where the Bloom filter sets the address to be cacheable as described above. Control then proceeds to 614.

[0096] In other examples, the bit values ​​at the second index position and the tenth index position of the bit array may be set to 1 based on a previously received address, and the bit value at the sixth index position of the bit array may be set to 0. In this case, not all of the bit values ​​identified at 606 are set to 1, indicating that the Bloom filter has not seen the address previously. If not all of the bit values ​​identified at 606 are set to 1 (e.g., any of the identified bit values ​​are set to 0), control proceeds to 612, where the Bloom filter sets the address to uncacheable, as described above. Control then proceeds to 614.

[0097] At 614, control determines whether the data requester makes any additional data requests. If so, control proceeds to 616, where the Bloom filter receives the next data request and address. Otherwise, control ends.

[0098] Various example embodiments herein are directed to improved devices, systems, methods, and / or non-transitory computer-readable media for filtering addresses from a cache. For example, in various embodiments, a filter may be implemented (in hardware and / or software) to track past addresses and / or representatives of addresses to select specific addresses to place in the cache when requests for addresses are likely to be repeated. Using this technique, one-time addresses are filtered out by the filter without polluting the cache, while frequently repeated addresses are promoted to the cache and can stay there longer.

[0099] The filtered cache solutions in this article may always outperform traditional cache methods. For example, by adopting any of the filtered cache solutions in this article, cache evictions can be reduced by one-tenth compared to traditional cache methods. In addition, cache hit rates can be increased by 10 to 20 percentage points compared to traditional cache methods. Due to the increased cache hit rate and reduced cache evictions, the cache consumes less power and has less cache thrashing than traditional caches.

[0100] For example, an example filter cache solution and a conventional cache of the same size (e.g., 256) receiving a 50,000 long address sequence were tested. The sequence consisted of addresses obtained by sampling a weighted distribution having, for example, 256 high-weighted addresses (e.g., frequently occurring addresses) and 1,792 low-weighted addresses (e.g., rarely repeated addresses). The weights were such that the high-weighted addresses accounted for 70% of the resulting input sequence (see fitness = 0.7 described below). In this example, the filter included a bit array size (m) of 2048, a maximum number of stored addresses (N) of 213, and 7 hash functions (K). As shown in Table 1 below, the filter cache solution had a cache hit rate of 55%, a score of 0.78 (e.g., cache hit rate % / fitness), an efficiency of 80%, and 2,000 cache evictions, while the conventional cache had a cache hit rate of 41%, a score of 0.59, an efficiency of 57%, and 29,000 cache evictions. In addition, a lower probability of false positives was observed. In such an example, the efficiency can be the sum of the weights of the cached addresses divided by the sum of the weights of all possible addresses. The weight used in this article can refer to the frequency with which an address appears in a request (e.g., the higher the weight, the more frequently the address appears). In addition, fitness can be the proportion of addresses with higher weights. For example, if fitness is equal to 0.7, addresses with higher weights appear as input 70% of the time. Although the tests described above refer to specific metrics, other metrics as well as different test cases can be defined to establish the performance of the filter cache in this article compared to a traditional cache. In general, by using a filtered cache in this article instead of a traditional cache, the cache hit rate is improved and the number of evictions is reduced.

[0101] Table 1

[0102] result Traditional Cache Filter Cache Cache Hit Rate % 41％ 55％ Score 0.59 0.78 efficiency 57％ 80％ Cache eviction Approx. 29,000 Approx. 2,000

[0103] In addition, the cache filters herein can be designed to maximize the results with respect to their associated caches. For example, for a particular cache size, the filter can be set to give an expected score. In such an example, the score is the fitness of the average cache hit rate divided by the number of iterations defined (e.g., 10,000 iterations). For example, the tests performed take into account the cache and filter time windows. If the address repeats itself before the filter (e.g., Bloom filter) is erased during maintenance (e.g., the fill level exceeds a defined threshold), the address is cached; if the address repeats itself before being evicted from the cache (e.g., based on a replacement or cache algorithm), a cache hit occurs. If the filter time window is much larger than the cache time window, cache thrashing occurs because the filter allows addresses that are not repeated before being evicted to enter. Conversely, if the filter time window is much smaller than the cache time window, only frequently repeated addresses are cached, resulting in slow cache filling. Therefore, the tests show that ideal results occur when the time windows of the cache and the filter are the same (or when the time window of the filter is slightly larger).

[0104] Testing has also shown that filters (e.g., Bloom filters) can be set up so that they can accommodate the same or similar number of elements as the number of entries in their corresponding cache. For example, an optimal Bloom filter for a given cache can store the maximum number of addresses (N) around the size of the cache, with a small probability of false positives. In such an example, if two filters have similar values ​​of N but different bit array sizes (m), the larger size filter can perform significantly better due to the lower number of false positives.

[0105] In addition, testing has shown that it is feasible to implement a filter cache solution on a chip (e.g., silicon die). For example, the performance of a filter cache solution generally increases with the size of the filter, but levels off at a certain point. In some filter implementations, it is desirable to have a Bloom filter size that is larger (approximately 8 to 16 times) than the size of the cache, and to implement the Bloom filter using three hash functions. With such a design, a filtered cache solution can be implemented on a chip while also improving the average cache hit rate by 8% to 14% and reducing evictions by a factor of ten compared to a conventional cache.

[0106] Furthermore, adding a filter sized according to the above example (e.g., a Bloom filter) can double the effective size of the cache. For example, testing has shown that the cache hit rate of a smaller cache with a Bloom filter is similar to the cache hit rate of a cache twice the size without a Bloom filter, and the number of cache evictions is about one-tenth less when the Bloom filter is implemented. In various embodiments, if space on the chip is limited, the Bloom filter size can be reduced to about one-quarter the cache size while still achieving the desired results.

[0107] In addition, in some embodiments, various example filters are tested to analyze the impact of cache size, which limits the number of addresses that can be physically stored in the cache. In such an example, the test includes input distributions where the number of frequently repeated addresses is lower, higher, or equal to the number of addresses that can be stored in the cache. Each input distribution can be referred to as a conversion. For example, the test shows that, compared to a conventional cache, when the conversion is less than 1, only a few cache addresses can be used to obtain improved results. If the conversion exceeds 1, it is easier to cache the addresses that will produce cache hits. However, the results may be slightly reduced because the cache can also receive cacheable addresses, resulting in more evictions. In such an example, the test has shown that a conversion equal to 1 (e.g., the number of frequently repeated addresses is the same as the number of addresses that can be stored in the cache) may be more challenging to obtain the desired cache scenario than when the conversion is greater than or less than 1. This is because over time, only one unique cache content combination will produce the best performance (e.g., in an ideal case, every high-weight address is in the cache, and nothing else). Therefore, one can experiment with a transformed input distribution equal to 1 when optimizing the filter size and cache size for the implementation.

[0108] Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0109] When an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "immediately adjacent," etc.).

[0110] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" shall also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of the features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0111] It should also be noted that in some alternative implementations, the functions / actions described may not occur in the order shown in the figures. For example, two figures shown in succession may actually be performed substantially simultaneously, or may sometimes be performed in reverse order, depending on the functions / actions involved.

[0112] Specific details are provided in the following description to provide a comprehensive understanding of the example embodiments. However, one of ordinary skill in the art will appreciate that the example embodiments may be practiced without these specific details. For example, the system may be shown in a block diagram so as not to obscure the example embodiments with unnecessary details. In other cases, well-known processes, structures, and techniques may be shown without unnecessary details in order to avoid obscuring the example embodiments.

[0113] As described herein, illustrative embodiments will be described with reference to actions and symbolic representations of operations (e.g., in the form of flow charts, flowcharts, data flow diagrams, structure diagrams, block diagrams, etc.), which operations may be implemented as program modules or functional processes that include routines, programs, objects, components, data structures, etc. for performing specific tasks or implementing specific abstract data types, and may be implemented using, for example, existing hardware at existing user equipment or other network elements and / or hardware. Such existing hardware may be a processing or control circuit system, such as, but not limited to, one or more processors, one or more central processing units (CPUs), one or more controllers, one or more arithmetic logic units (ALUs), one or more digital signal processors (DSPs), one or more microcomputers, one or more field programmable gate arrays (FPGAs), one or more systems on chips (SoCs), one or more programmable logic units (PLUs), one or more microprocessors, one or more application specific integrated circuits (ASICs), or any other device or devices capable of responding to and executing instructions in a defined manner.

[0114] Although a flowchart may describe operations as a sequential process, many operations may be performed in parallel, simultaneously, or synchronously. In addition, the order of operations may be rearranged. A process may terminate when its operations are completed, but may also have other steps not included in the diagram. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0115] As disclosed herein, the terms "storage media", "computer-readable storage media", or "non-transitory computer-readable storage media" may represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), magnetic RAM, core memory, magnetic disk storage media, optical storage media, flash memory devices, and / or other tangible machine-readable media for storing information. The term "computer-readable medium" may include, but is not limited to, portable or fixed storage devices, optical storage devices, and various other media capable of storing, containing, or carrying (multiple) instructions and / or data.

[0116] In addition, the example embodiments can be implemented by hardware, software, firmware, middleware, microcode, hardware description language or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segment for performing the necessary tasks can be stored in a machine or computer readable medium (e.g., a computer readable storage medium). When implemented in software, one or more processors will perform the necessary tasks. For example, as described above, according to one or more example embodiments, at least one memory may include or store a computer program code, and at least one memory and the computer program code may be configured to, together with at least one processor, cause a network element or network device to perform the necessary tasks. In addition, the processor, memory and example algorithm encoded as a computer program code are used as components for providing or causing the execution of the operations discussed herein.

[0117] The code segment of a computer program code can represent any combination of a process, function, subprogram, program, routine, subroutine, module, software package, class, or instruction, data structure, or program statement. A code segment can be coupled to another code segment or hardware circuit by transmitting and / or receiving information, data, independent variables, parameters, or memory contents. Information, independent variables, parameters, data, etc. can be transmitted, forwarded, or sent by any suitable technology, including memory sharing, message passing, token passing, network transmission, etc.

[0118] As used herein, the terms "including" and / or "having" are defined as comprising (i.e., open language). The term "coupled," as used herein, is defined as connected, although not necessarily directly and not necessarily mechanically. Terms derived from the word "indicating" (e.g., "indicates" and "indication") are intended to cover all of the various techniques used to transmit or reference the indicated object / information. Some, but not all, examples of techniques that may be used to transmit or reference the indicated object / information include communication of the indicated object / information, communication of an identifier of the indicated object / information, communication of information used to generate the indicated object / information, communication of a part or portion of the indicated object / information, communication of some derivative of the indicated object / information, and communication of some symbol representing the indicated object / information.

[0119] The above has described benefits, other advantages and solutions to problems with respect to the embodiments of the present disclosure. However, benefits, advantages, solutions to problems, and any (multiple) elements that may make or result in such benefits, advantages or solutions, or make such benefits, advantages or solutions more obvious should not be construed as key, required or essential features or elements of any or all claims.

Claims

1. A system for filtering addresses from a cache memory, the system comprising: a filter in communication with the cache memory, the filter comprising a filter data structure, the filter configured to: receive a data request including an address specifying a memory location of the requested data; querying the filter data structure to determine whether the address is cacheable or non-cacheable; And in response to determining that the address is not cacheable, preventing caching of the data and the address associated with the data.

2. The system of claim 1 , further comprising the cache memory and a cache controller in communication with the cache memory, the cache controller being configured to: receiving said data request including said address, querying the cache memory to determine whether the cache memory includes the address, and In response to determining that the address exists in the cache memory, a cache state of the cache memory is updated based on the received data request.

3. The system of claim 1 , further comprising the cache memory and a cache controller, the cache controller communicating with the cache memory and the filter, the cache controller being configured to: receiving said data request including said address, querying the cache memory to determine whether the cache memory includes the address, and In response to determining that the address does not exist in the cache memory and the address is cacheable, the data and the address are cached in the cache memory.

4. The system according to any one of the preceding claims, wherein the filter is configured to: comparing the address associated with the received data request with a set of addresses in the filter data structure, In response to the address matching an address in the set of addresses, identifying the address as cacheable, and In response to the address not matching any address in the set of addresses, the address is identified as uncacheable.

5. The system according to any of the preceding claims, wherein the filter is a Bloom filter.

6. The system of any preceding claim, wherein the filter is configured to insert the address of the received data request into the filter data structure.

7. A system according to any one of the preceding claims, wherein the filter is configured to: determining the number of addresses in the filter data structure, and In response to the number of addresses exceeding a defined threshold, the addresses are cleared from the filter data structure.

8. A system according to any one of the preceding claims, wherein: The filter data structure comprises a bit array having bit values, and The filter is configured to generate hash values ​​of the addresses based on a plurality of hash functions and set a bit value of the bit array associated with each hash value to 1.

9. The system of claim 8, wherein the filter is configured to: determining a fill level of the bit array, and In response to the fill level exceeding a defined threshold, at least a portion of the bit values ​​of the bit array are cleared to zero.

10. A method for filtering addresses from a cache, the method comprising: receiving, by the filter, a data request including an address specifying a memory location of the requested data; querying the filter to determine whether the address is cacheable or non-cacheable; as well as In response to determining that the address is not cacheable, caching of the data and the address associated with the data is prevented.

11. The method according to claim 10, further comprising: receiving, by the cache, the data request including the address, querying the cache to determine whether the cache includes the address, and In response to determining that the address is present in the cache, a cache state of the cache is updated based on the received data request.

12. The method according to claim 10, further comprising: receiving, by the cache, the data request including the address, querying the cache to determine whether the cache includes the address, and In response to determining that the address is not present in the cache and the address is cacheable, the data and the address are cached in the cache.

13. The method of claim 10, wherein querying the filter to determine whether the address is cacheable or not cacheable comprises: comparing the address associated with the received data request with a set of addresses in the filter, In response to the address matching an address in the set of addresses, identifying the address as cacheable, and In response to the address not matching any address in the set of addresses, the address is identified as uncacheable.

14. The method according to any one of claims 10 to 13, further comprising: The address associated with the received data request is inserted into the filter.

15. A non-transitory computer-readable medium storing computer-readable instructions that, when executed by a processing circuit system, cause the processing circuit system to: receiving a data request including an address specifying a memory location of the requested data; querying a filter to determine whether the address associated with the received data request is cacheable or non-cacheable; as well as In response to determining that the address is not cacheable, caching of the data and the address associated with the data is prevented.

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