Chip system and communication equipment

Abstract

The invention provides a chip system and communication equipment, relates to the technical field of communication, and is used for improving the data communication efficiency between non-storage bare chips while ensuring the functions of the non-storage bare chips. The chip system includes: a memory die; the at least two non-storage bare chips comprise a first non-storage bare chip and a second non-storage bare chip; wherein the first non-storage bare chip comprises a first controller, the second non-storage bare chip comprises a second controller, and the first controller and the second controller are used for controlling access of the storage bare chip.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a chip system and communication equipment. Background Art

[0002] As the scale of system on chip (SoC) increases, the area of ​​SoC also continues to grow, but the manufacturing yield of the chip will deteriorate with the increase of area. If the area of ​​a complete SoC is too large, it is necessary to spread the SoC over multiple dies for implementation. The multiple dies usually include two types of dies, namely storage dies and non-storage dies. For example, the storage die may include dynamic random access memory (DRAM), and the non-storage die may include a central processing unit (CPU) and a modem, etc.

[0003] Currently, most of the non-storage dies in the plurality of dies need to use the storage dies to complete their respective functions. Therefore, how to arrange the plurality of dies to improve the data communication efficiency between the non-storage dies while ensuring the functions of each non-storage dies is a problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a chip system and a communication device, which are used to ensure the function of each non-storage die when multiple dies are set, while improving the data communication efficiency between non-storage dies.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a chip system is provided, which includes: a storage die, which may be a die with a storage function, such as the storage die may include a DRAM; at least two non-storage die, including a first non-storage die and a second non-storage die, which may be a die with a data processing function or a computing function, and the non-storage die can access the storage die; the first non-storage die includes a first controller, the second non-storage die includes a second controller, and the first controller and the second controller are used to control access to the storage die.

[0007] In the above technical solution, both the first non-storage die and the second non-storage die can access the storage die through their respective controllers, so that the first non-storage die and the second non-storage die can use the storage die to complete their respective functions; both the first non-storage die and the second non-storage die can access the storage die, that is, different non-storage die can access the same storage die, so that the first non-storage die and the second non-storage die can use the storage die to achieve data communication, so as to improve the data communication efficiency between different non-storage die, and can also save storage die and reduce costs.

[0008] In a possible implementation of the first aspect, at least two interfaces of the storage die are coupled with the first interface of the first non-storage die and the first interface of the second non-storage die, respectively, and are used by the first controller and the second controller to control access to the storage die, so that the first non-storage die can access the storage die through the first interface of the first non-storage die, and the second non-storage die can access the storage die through the first interface of the second non-storage die; the second interface of the first non-storage die is coupled with the second interface of the second non-storage die, and is used by the first controller and the second controller to communicate, so that the first non-storage die and the second non-storage die can communicate directly through the second interface, for example, the first non-storage die and the second non-storage die can negotiate the control right of the storage die through the second interface. In the above possible implementation, the first controller of the first non-storage die and the second controller of the second non-storage die can negotiate the control right of the storage die through the corresponding second interface, so that there is no need to make major improvements to the storage die, and the storage density and flexibility of the storage die will not be reduced.

[0009] In a possible implementation of the first aspect, the at least two non-storage dies access the storage die through time-division multiplexing, that is, the at least two non-storage dies can access the storage die at different times; illustratively, when the at least two non-storage dies include a first non-storage die and a second non-storage die, the first non-storage die and the second non-storage die can access the storage die through time-division multiplexing. In the above possible implementation, each of the at least two non-storage dies can access the storage die at a different time, so that there is no need to make major improvements to the storage die, and the storage density and flexibility of the storage die will not be reduced.

[0010] In a possible implementation of the first aspect, the first controller is used to: send first indication information through a second interface of the first non-storage die, the first indication information is used to instruct the first non-storage die to access the storage die; and / or the second controller is used to: send second indication information through a second interface of the second non-storage die, the second indication information is used to instruct the second non-storage die to access the storage die. In the above possible implementation, the first controller of the first non-storage die and the second controller of the second non-storage die can negotiate the control right of the storage die through the second interface, so that there is no need to make major improvements to the storage die, and the storage density and flexibility of the storage die will not be reduced.

[0011] In a possible implementation of the first aspect, the at least two non-storage chips further include a third non-storage chip, the third non-storage chip includes a third controller, and the third controller is used to control access to the storage chip. In the above possible implementation, the third non-storage chip can access the storage chip through the third controller, so that the third non-storage chip can use the storage chip to complete its own functions; in addition, different non-storage chips can access the same storage chip, so that the third non-storage chip and other non-storage chips can use the storage chip to achieve data communication, so as to improve the data communication efficiency between different non-storage chips, and can also save storage chips and reduce costs.

[0012] In a possible implementation of the first aspect, at least two interfaces of the storage die are also coupled to the first interface of the third non-storage die, so that the third controller controls access to the storage die, so that the third non-storage die can use the storage die to complete the function of the third non-storage die, and any two of the at least two non-storage die can use the storage die to achieve data communication, so as to improve the data communication efficiency between the non-storage die; the second interface of the third non-storage die is coupled to the second interface of the first non-storage die and the second interface of the second non-storage die, so that the third controller communicates with the first controller and the second controller, so that the third non-storage die can negotiate the control right of the storage die with other non-storage die through the second interface, so as to achieve access to the storage die in a time-division multiplexing manner.

[0013] In a possible implementation of the first aspect, the third controller is used to: send third indication information through the second interface of the third non-storage die, and the third indication information is used to instruct the third non-storage die to access the storage die. In the above possible implementation, the third non-storage die can negotiate the control right of the storage die through the second interface, so that there is no need to make major improvements to the storage die, and thus the storage density and flexibility of the storage die will not be reduced.

[0014] In a possible implementation of the first aspect, the storage die and some of the at least two non-storage dies are packaged together; or, the storage die and the at least two non-storage dies are packaged together. In the above possible implementations, by packaging the storage die with the at least two non-storage dies or some of the at least two non-storage dies together, the integration of the chip system can be improved and the area of ​​the chip system can be reduced.

[0015] In a possible implementation of the first aspect, each of the at least two non-storage dies includes a controller, and the controller is used to control access to the storage die. In the above possible implementation, each of the at least two non-storage dies can access the storage die through its own controller without integrating the controller into the storage die, thereby not affecting the flexibility of the storage die.

[0016] In a possible implementation of the first aspect, the at least two non-storage dies include at least one of the following: a central processing unit CPU, a modem modem, an image signal processor ISP, a digital signal processor DSP, a graphics processor GPU, a neural network processor NPU, a tensor processing unit TPU, and a network card. The above possible implementation can improve the diversity of non-storage dies and the flexibility of selection.

[0017] In a second aspect, a communication device is provided, the communication device comprising: a printed circuit board, and a chip system provided on the printed circuit board as provided in the first aspect or any possible implementation of the first aspect. Optionally, the communication device comprises a mobile terminal, for example, the mobile terminal may include a mobile phone, a tablet computer, a laptop computer, a video camera, a camera, a wearable device, a vehicle-mounted device, etc.

[0018] It can be understood that the beneficial effects that can be achieved by any of the communication devices provided above can correspond to the beneficial effects in the chip system provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of a dual-port DRAM;

[0020] Figure 2 It is a schematic diagram of the structure of another dual-port DRAM;

[0021] Figure 3 A schematic diagram of the structure of a terminal device provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of the structure of a chip system provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of the structure of another chip system provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of the structure of another chip system provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the structure of another chip system provided in an embodiment of the present application;

[0026] Figure 8 A schematic diagram of the structure of another chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided by this application can be implemented in a variety of specific environments. The specific embodiments discussed are only illustrative of specific ways to implement and use this description and this technology, and do not limit the scope of this application.

[0028] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0029] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when the specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuits that perform an operation, etc.

[0030] The technical solution in the embodiment of the present application will be described below in conjunction with the drawings in the embodiment of the present application. In the description of the present application, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship, for example, A / B can represent A or B; "and / or" in the present application is only a description of the association relationship of the associated objects, indicating that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0031] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0032] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference.

[0033] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0034] Before introducing the embodiments of the present application, the relevant background involved in the present application is first introduced and explained.

[0035] As the scale of system on chip (SoC) increases, the area of ​​SoC also continues to grow, but the manufacturing yield of the chip will deteriorate with the increase of area. If the area of ​​a complete SoC is too large, the SoC needs to be distributed to multiple dies for implementation. The multiple dies usually include two types of dies, namely storage dies and non-storage dies. Most of the non-storage dies in the multiple dies need to use storage dies to complete their respective functions. Therefore, how to set the multiple dies to improve the data communication efficiency between non-storage dies while ensuring the functions of each non-storage die is a problem that needs to be solved urgently.

[0036] In the related art, the storage die is usually improved, that is, the storage die is implemented using a dual-port DRAM, which has two access ports, allowing two non-storage dies to access simultaneously, thereby ensuring the functions of the non-storage die while improving the data communication efficiency between the non-storage die.

[0037] Figure 1The schematic diagram of the structure of a dual-port DRAM is shown. The dual-port DRAM allows two ports to be accessed simultaneously, so that two non-storage bare chips can access the DRAM simultaneously through the dual ports. In the dual-port DRAM, a storage unit (i.e., a capacitor C) is coupled with two transistors (represented as T1 and T2) respectively, and each transistor is coupled with a bit line (BL) and a word line (WL), for example, transistor T1 is coupled with bit line BL1 and word line WL1, and transistor T2 is coupled with bit line BL2 and word line WL2. Figure 1 / BL1 in FIG. 8 represents the inversion of the bit line BL1, and / BL2 represents the inversion of the bit line BL2.

[0038] Figure 2 The schematic diagram of the structure of another dual-port DRAM is shown. The dual-port DRAM also allows two ports to be accessed simultaneously, so that two non-storage bare chips can access the DRAM simultaneously through the dual ports. The dual-port DRAM is integrated with a DRAM controller, and a dual-port controller is added. The dual-port controller is used to sort the access requests received by the two ports, and send the access requests to the DRAM controller for processing in the sorted order to prevent timing conflicts when the two ports are accessed simultaneously. In addition, the dual-port DRAM can also include I / O buffers, inductive amplifiers and I / O circuits, storage arrays and serial shift registers and other related devices for data input, output and cache. Figure 2 CLK in the figure represents the clock signal of the serial shift register, and SD represents the output data of the serial shift register.

[0039] When the above two dual-port DRAMs are used as storage dies for SoC distributed dies, although they can improve the data communication efficiency between non-storage dies, they still have certain problems, which limits their use. Figure 1 The dual-port DRAM shown in the figure introduces additional bit lines BL and word lines WL, which will lead to a decrease in the storage density of the dual-port DRAM; Figure 2 An additional dual-port controller is introduced into the dual-port DRAM shown, and the dual-port controller and the DRAM controller need to be integrated into the dual-port DRAM, so the flexibility is poor.

[0040] Based on this, an embodiment of the present application provides a chip system, which can ensure the functions of non-storage chips without reducing the storage density and flexibility of storage chips, while improving the data communication efficiency between non-storage chips.

[0041] The technical solution of the present application can be applied to various communication devices, for example, the communication device can be a terminal device. The terminal device can include but is not limited to: a mobile phone, a tablet computer, a computer, a laptop computer, a video camera, a camera, a wearable device, an on-board device (for example, a car, a bicycle, an electric car, an airplane, a ship, a train, a high-speed train, etc.), a virtual reality (VR) device, an augmented reality (AR) device, or an intelligent robot, etc.

[0042] Figure 3 The schematic diagram of the structure of a terminal device provided in an embodiment of the present application is shown in FIG. The terminal device is a mobile phone as an example, and the mobile phone includes: a radio frequency (RF) circuit 110, a memory 120, an input unit 130, a display unit 140, a sensor component 150, an audio circuit 160, a processor 170, and a power supply 180. Figure 3 The following is a detailed introduction to the various components of the mobile phone:

[0043] The RF circuit 110 can be used for receiving and sending information or receiving and sending signals during a call. Generally, the RF circuit 110 includes, but is not limited to, an antenna, an amplifier, a transceiver, a coupler, a low noise amplifier (LNA), a duplexer, etc. Optionally, the antenna may include multiple receiving antennas and multiple transmitting antennas. In addition, the RF circuit 110 can also communicate with a network and other devices through wireless communication, such as communicating with an access device through a WiFi network.

[0044] The memory 120 can be used to store software programs and modules. The processor 170 executes various functional applications and data processing of the mobile phone by running the software programs and modules stored in the memory 120. The memory 120 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function, etc.; the data storage area can store data created according to the use of the mobile phone (for example, audio data, image data, phone book, etc.). In addition, the memory 120 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0045] The input unit 130 can be used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the mobile phone. Specifically, the input unit 130 may include a touch screen 131 and other input devices 132. The touch screen 131, also known as a touch panel, can collect user touch operations on or near it (such as operations performed by the user using any suitable object or accessory such as a finger, stylus, etc. on or near the touch screen 131), and drive the corresponding connection device according to a pre-set program. Other input devices 132 may include, but are not limited to, one or more of a physical keyboard, function keys (such as a volume control button, a power switch button, etc.), a trackball, a mouse, a joystick, etc.

[0046] The display unit 140 can be used to display information input by the user or information provided to the user and various menus of the mobile phone. The display unit 140 may include a display panel 141. Optionally, the display panel 141 may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc. Further, the touch screen 131 may cover the display panel 141. When the touch screen 131 detects a touch operation on or near it, it is transmitted to the processor 170 to determine the type of touch event. Subsequently, the processor 170 provides a corresponding visual output on the display panel 141 according to the type of touch event. Although in Figure 3 In the embodiment, the touch screen 131 and the display panel 141 are used as two independent components to implement the input and output functions of the mobile phone, but in some embodiments, the touch screen 131 and the display panel 141 can be integrated to implement the input and output functions of the mobile phone.

[0047] The sensor assembly 150 includes one or more sensors for providing status evaluation of various aspects of the mobile phone. The sensor assembly 150 may include a temperature sensor, an acceleration sensor, a gyroscope sensor, a magnetic sensor or a pressure sensor, and the sensor assembly 150 may detect the temperature change of the mobile phone, the acceleration / deceleration, orientation, open / closed state of the mobile phone, or the relative positioning of components. In addition, the sensor assembly 150 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications.

[0048] The audio circuit 160, the speaker 161, and the microphone 162 can provide an audio interface between the user and the mobile phone. The audio circuit 160 can transmit the received audio data to the speaker 161 after converting the received audio data into an electrical signal, which is converted into a sound signal for output; on the other hand, the microphone 162 converts the collected sound signal into an electrical signal, which is received by the audio circuit 160 and converted into audio data, and then the audio data is output to the RF circuit 110 to be sent to, for example, another mobile phone, or the audio data is output to the memory 120 for further processing.

[0049] The processor 170 is the control center of the mobile phone. It uses various interfaces and lines to connect various parts of the entire mobile phone. By running or executing software programs and / or modules stored in the memory 120, and calling data stored in the memory 120, it executes various functions of the mobile phone and processes data, thereby monitoring the mobile phone as a whole. Optionally, the processor 170 may include one or more processing units. Exemplarily, the processor 170 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 170.

[0050] The mobile phone also includes a power supply 180 (such as a battery) for supplying power to various components. Optionally, the power supply can be logically connected to the processor 170 through a power management system, so that the power management system can manage charging, discharging, power consumption and other functions.

[0051] Furthermore, the mobile phone may also include a connectivity chip 190, in which a wireless fidelity (WiFi) chip may be integrated, and in the embodiment of the present application, an antenna for receiving or sending multiple data streams or a single data stream may be an antenna of the WiFi chip. In addition, the chip 190 may also integrate one or more of a Bluetooth module, a near field communication (NFC) module, a global navigation satellite system (GNSS) module, or a frequency modulation (FM) module, which will not be described in detail in the present application.

[0052] It can be understood by those skilled in the art that Figure 3 The mobile phone structure shown in the figure does not constitute a limitation on the mobile phone, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0053] Figure 4 A schematic diagram of the structure of a chip system provided in an embodiment of the present application, which can be applied to the communication device provided above. The chip system may include: a storage die 210 and at least two non-storage die 220. The at least two non-storage die 220 may include a first non-storage die 221 and a second non-storage die 222. The first non-storage die 221 includes a first controller, and the second non-storage die includes a second controller, and the first controller and the second controller are used to control access to the storage die 210.

[0054] In a possible embodiment, at least two interfaces of the storage die 210 are coupled with the first interface of the first non-storage die 221 and the first interface of the second non-storage die 222, respectively, and are used by the first controller and the second controller to control access to the storage die 210, respectively; the second interface of the first non-storage die 221 is coupled with the second interface of the second non-storage die 222, and is used for communication between the first controller and the second controller.

[0055] The die may also be referred to as a crystal grain, a bare crystal, a particle or a core grain, etc., and may specifically refer to a crystal grain cut from a wafer. The storage die 210 may be a die with a storage function. The non-storage die may be a die with a data processing function or a computing function, and the non-storage die may access the storage die 210.

[0056] Optionally, the storage die 210 may include but is not limited to: DRAM, static random access memory (SRAM), synchronous dynamic random-access memory (SDRAM), double data rate SDRAM (DDR), etc.

[0057] Optionally, the at least two non-storage bare chips 220 may include, but are not limited to: a central processing unit CPU, a modem, an image signal processor (ISP), a digital signal processor (DSP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU), a network card, and various accelerators, etc.

[0058] In addition, the at least two interfaces of the storage die 210 may include two or more interfaces. The first interface and the second interface of the first non-storage die 221 may each include one or more interfaces. The first interface and the second interface of the second non-storage die 222 may also each include one or more interfaces. The first interface of the first non-storage die 221 and the first interface of the second non-storage die 222 may be coupled to different interfaces of the at least two interfaces of the storage die 210.

[0059] Exemplarily, the storage die 210 includes 4 interfaces and are represented as I1 to I4, the first interface of the first non-storage die 221 and the first interface of the second non-storage die 222 each include 2 interfaces and are represented as J1 to J2 and K1 to K2, respectively, the second interface of the first non-storage die 221 and the second interface of the second non-storage die 222 each include 1 interface and are represented as J3 and K3, respectively. The interfaces I1 to I2 of the storage die 210 can be coupled with the interfaces J1 to J2 of the first non-storage die 221, the interfaces I3 to I4 of the storage die 210 can be coupled with the interfaces K1 to K2 of the second non-storage die 222, and the interface J3 of the first non-storage die 221 can be coupled with the interface K3 of the second non-storage die 222.

[0060] In the chip system, part of the interface of the storage die is coupled with the first interface of the first non-storage die 221, so that the first non-storage die 221 can access the storage die 210 through the first interface of the first non-storage die 221. Similarly, part of the interface of the storage die is coupled with the first interface of the second non-storage die 222, so that the second non-storage die 222 can access the storage die 210 through the first interface of the second non-storage die 222. The second interface of the first non-storage die 221 is coupled with the second interface of the second non-storage die 222, so that the first non-storage die 221 and the second non-storage die 222 can directly communicate with each other through the second interface, for example, the first non-storage die 221 and the second non-storage die 222 can negotiate the control right (or access right) of the storage die 210 through the second interface.

[0061] In the embodiment of the present application, both the first non-storage die 221 and the second non-storage die 222 can access the storage die 210, so that the first non-storage die 221 and the second non-storage die 222 can use the storage die 210 to complete their respective functions. In addition, both the first non-storage die 221 and the second non-storage die 222 can access the storage die 210, that is, different non-storage die can access the same storage die, so that the first non-storage die 221 and the second non-storage die 222 can use the storage die 210 to achieve data communication, so as to improve the data communication efficiency between the first non-storage die 221 and the second non-storage die 222, and can also save the storage die 210 to reduce costs. For example, the first non-storage die 221 writes data to the storage die 210 , and the second non-storage die 222 reads the data from the storage die 210 ; or, the second non-storage die 222 writes data to the storage die 210 , and the first non-storage die 221 reads the data from the storage die 210 .

[0062] Optionally, the at least two non-storage dies 220 access the storage die 210 through time-division multiplexing, that is, the at least two non-storage dies 220 can access the storage die 210 at different times. When the at least two non-storage dies 220 include a first non-storage die 221 and a second non-storage die 222, the first non-storage die 221 and the second non-storage die 222 can access the storage die 210 through time-division multiplexing. At this time, the storage die 210 can also be called a dual-port storage die, for example, the storage die 210 can be a dual-port DRAM.

[0063] In a possible embodiment, when the first non-storage die 221 needs to access the storage die 210, the first controller of the first non-storage die 221 may be used to: send first indication information through the second interface of the first non-storage die 221, and the first indication information is used to instruct the first non-storage die 221 to access the storage die 210. In this way, when the second non-storage die 222 receives the first indication information through the second interface of the second non-storage die 222, the second non-storage die 222 may not access the storage die 210, so as to transfer the control right of the storage die 210 to the first non-storage die 221. Optionally, the second non-storage die 222 may also send first response information through the second interface of the second non-storage die 222, and the first response information may be used to confirm that the first non-storage die 221 accesses the storage die 210.

[0064] Similarly, when the second non-storage die 222 needs to access the storage die 210, the second controller of the second non-storage die 222 may be used to: send second indication information through the second interface of the second non-storage die 222, and the second indication information is used to instruct the second non-storage die 222 to access the storage die 210. In this way, when the first non-storage die 221 receives the second indication information through the second interface of the first non-storage die 221, the first non-storage die 221 may not access the storage die 210, so as to transfer the control right of the storage die 210 to the second non-storage die 222. Optionally, the first non-storage die 221 may also send second response information through the second interface of the first non-storage die 221, and the second response information may be used to confirm that the second non-storage die 222 accesses the storage die 210.

[0065] In an embodiment of the present application, the at least two non-storage die 220 access the storage die 210 through time-division multiplexing, so that each of the at least two non-storage die 220 can access the storage die 210 at a different time, that is, only one non-storage die accesses the storage die 210 at the same time, thereby eliminating the need for major improvements to the storage die 210 and thereby not reducing the storage density and flexibility of the storage die 210.

[0066] Further, such as Figure 5 As shown, the at least two non-storage die 220 further include a third non-storage die 223 . The third non-storage die 223 includes a third controller. The third controller is used to control access to the storage die 210 .

[0067] In a possible embodiment, at least two interfaces of the storage die 210 are also coupled to the first interface of the third non-storage die 223, so that the third controller controls access to the storage die 210; the second interface of the third non-storage die 223 is coupled to the second interface of the first non-storage die 221 and the second interface of the second non-storage die 222, so that the third controller communicates with the first controller and the second controller.

[0068] Among them, at least two interfaces of the storage die 210 are also coupled to the first interface of the third non-storage die 223, so that the third non-storage die 223 can access the storage die 210 through the first interface of the third non-storage die 223, so that the third non-storage die 223 can use the storage die 210 to complete the function of the third non-storage die 223.

[0069] In addition, the first non-storage die 221, the second non-storage die 222 and the third non-storage die 223 can all access the storage die 210, that is, different non-storage die can access the same storage die, so that any two of the above three non-storage die can use the storage die 210 to achieve data communication, so as to improve the data communication efficiency between non-storage die.

[0070] Furthermore, the second interface of the third non-storage die 223 is coupled to the second interface of the first non-storage die 221 and the second interface of the second non-storage die 222, so that the three non-storage die can directly communicate with each other through the second interface. For example, the first non-storage die 221, the second non-storage die 222 and the third non-storage die 223 can negotiate the control right of the storage die 210 through the second interface to access the storage die 210 in a time-division multiplexing manner.

[0071] In a possible embodiment, when the third non-storage die 223 needs to access the storage die 210, the third memory of the third non-storage die 223 may be used to: send third indication information through the second interface of the third non-storage die 223, and the third indication information is used to instruct the third non-storage die 223 to access the storage die 210. In this way, when the first non-storage die 221 and the second non-storage die 222 both receive the third indication information through their respective second interfaces, the first non-storage die 221 and the second non-storage die 222 may not access the storage die 210, so as to transfer the control right of the storage die 210 to the third non-storage die 223. Optionally, the first non-storage die 221 and the second non-storage die 222 may also send third response information through their respective second interfaces, and the third response information may be used to confirm that the third non-storage die 223 accesses the storage die 210.

[0072] It is understandable that the above description is only based on the example that the at least two non-storage dies 220 include three non-storage dies. In practical applications, the at least two non-storage dies 220 may also include a larger number of non-storage dies, which may be coupled with the storage die 210 and other non-storage dies in a manner similar to the third non-storage die 223, and time-division multiplexing of the storage die 210 may be achieved by negotiating the control right of the storage die 210. The embodiment of the present application does not specifically limit the number of non-storage dies included in the at least two non-storage dies 220.

[0073] Further, each of the at least two non-storage dies 220 may include a controller, which may be used to control access to the storage die 210. For example, the storage die 210 may include a storage array, and the controller may be used to write data to the storage array, or read data stored in the storage array.

[0074] For ease of understanding, the following description is made by taking the example that the at least two non-storage die 220 include a first non-storage die 221 and a second non-storage die 222, the storage die 210 is a DRAM, and the controller is a DRAM controller. Figure 6 As shown, the first non-storage die 221 includes a DRAM controller 1, and the second non-storage die 222 includes a DRAM controller 2. The DRAM controller 1 can access the storage die 210 through the first interface of the first non-storage die 221, and the DRAM controller 2 can access the storage die 210 through the first interface of the second non-storage die 222. The DRAM controller 1 and the DRAM controller 2 can also communicate through the second interfaces of their respective non-storage die.

[0075] It is understandable that the above Figure 6 In the example, each of the at least two non-storage dies 220 includes a controller. In practical applications, each of the at least two non-storage dies 220 may not have an integrated controller. For example, a controller may be integrated in the storage die 210, or an independent controller may be provided between the storage die 210 and the at least two non-storage dies 220. Figure 6 The examples in the description do not limit the embodiments of the present application.

[0076] Further, in the chip system, the storage die 210 and the at least two non-storage die 220 may be packaged together, or the storage die 210 and some of the at least two non-storage die 220 may be packaged together. For ease of understanding, the following description is made by taking the at least two non-storage die 220 including a first non-storage die 221 and a second non-storage die 222 as an example.

[0077] In a possible embodiment, Figure 7 As shown, the chip system includes the memory die 210 , a first non-memory die 221 , and a second non-memory die 222 . The memory die 210 , the first non-memory die 221 , and the second non-memory die 222 are packaged together. Figure 7 The first controller of the first non-memory die 221 and the second controller of the second non-memory die 222 are not shown.

[0078] In another possible embodiment, Figure 8 As shown, the chip system includes the memory die 210 , a first non-memory die 221 , and a second non-memory die 222 . The memory die 210 and the first non-memory die 221 are packaged together. Figure 8 The first controller of the first non-memory die 221 and the second controller of the second non-memory die 222 are not shown.

[0079] In an embodiment of the present application, by packaging the storage die 210 and the at least two non-storage die 220 together, or packaging the storage die 210 and some of the at least two non-storage die 220 together, the integration of the chip system can be improved and the area of ​​the chip system can be reduced.

[0080] Based on this, an embodiment of the present application also provides a communication device, which may include a printed circuit board (PCB) and a chip system arranged on the printed circuit board PCB, and the chip system may be any of the chip systems provided above.

[0081] Optionally, the communication device may be a mobile terminal. For example, the mobile terminal may include but is not limited to: a mobile phone, a tablet computer, a laptop computer, a video camera, a camera, a wearable device, a vehicle-mounted device, etc., and the present embodiment of the application does not impose specific restrictions on this.

[0082] It should be noted that the above detailed descriptions about the chip system can all be referred to in the corresponding embodiments of the communication device, and the embodiments of the present application will not be repeated here.

[0083] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip system, characterized in that: include: Storage die; at least two non-storage die, including a first non-storage die and a second non-storage die; The first non-storage die includes a first controller, the second non-storage die includes a second controller, and the first controller and the second controller are used to control access to the storage die.

2. The chip system according to claim 1, characterized in that: At least two interfaces of the storage die are respectively coupled to the first interface of the first non-storage die and the first interface of the second non-storage die, and are used for the first controller and the second controller to control access to the storage die; The second interface of the first non-storage die is coupled to the second interface of the second non-storage die for communication between the first controller and the second controller.

3. The chip system according to claim 1 or 2, characterized in that: The at least two non-storage dies access the storage die through time-division multiplexing.

4. The chip system according to claim 2 or 3, characterized in that: The first controller is used to send first indication information through the second interface of the first non-storage die, where the first indication information is used to instruct the first non-storage die to access the storage die; and / or, The second controller is used to send second indication information through the second interface of the second non-storage die, where the second indication information is used to instruct the second non-storage die to access the storage die.

5. The chip system according to any one of claims 1 to 4, characterized in that: The at least two non-storage die further include a third non-storage die including a third controller for controlling access to the storage die.

6. The chip system according to claim 5, characterized in that: The at least two interfaces of the storage die are also coupled to the first interface of the third non-storage die for the third controller to control access to the storage die; The second interface of the third non-storage die is coupled to both the second interface of the first non-storage die and the second interface of the second non-storage die for the third controller to communicate with the first controller and the second controller.

7. The chip system according to claim 6, characterized in that: The third controller is used to send third indication information through the second interface of the third non-storage die, where the third indication information is used to instruct the third non-storage die to access the storage die.

8. The chip system according to any one of claims 1 to 7, characterized in that: The memory die and some of the at least two non-memory die are packaged together.

9. The chip system according to any one of claims 1 to 7, characterized in that: The memory die and the at least two non-memory die are packaged together.

10. The chip system according to any one of claims 1 to 9, characterized in that: The memory die includes a dynamic random access memory DRAM.

11. The chip system according to any one of claims 1 to 10, characterized in that: The at least two non-storage bare chips include at least one of the following: a central processing unit CPU, a modem modem, an image signal processor ISP, a digital signal processor DSP, a graphics processor GPU, a neural network processor NPU, a tensor processing unit TPU, and a network card.

12. A communication device, characterized in that: The communication device comprises: a printed circuit board, and a chip system according to any one of claims 1 to 11 arranged on the printed circuit board.

13. The communication device according to claim 12, characterized in that The communication device includes a mobile terminal.

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