Memory reconstruction system and method

Abstract

The invention discloses a memory reconstruction system and method. The system comprises a target chip and a calibration tool, a memory, a data coding system and a data sending module are arranged in the target chip, and a memory, a data decoding system and a data receiving module are arranged in the calibration tool; the data coding system comprises a kernel write operation interface, a filtering module, a compression module, a packaging module and a data buffer area. According to the embodiment of the invention, the input signal variable and the output control variable of the control algorithm model in the chip can be quickly and accurately acquired based on the memory, the data coding system and the data sending module of the chip and the memory, the data decoding system and the data receiving module of the calibration tool; and the collected input signal variable and the output control variable of the control algorithm model in the chip are provided for the user, so that the complexity is low, the efficiency is high, and the high-speed calibration scene requirement can be met.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory reconstruction system and method. Background Art

[0002] Automobiles are usually equipped with chips for automobile control. Chips for automobile control include, but are not limited to: electronic control unit (ECU) chips located inside the anti-lock braking system (ABS) installed on the automobile, and motor control chips installed on the automobile. The ECU chip inside the ABS needs to collect the tire speed signal of the automobile at high speed, and issue a brake control command after calculation and processing to help the automobile achieve body stability during braking. The motor control chip needs to collect the rotation position and motor speed signal of the motor rotor of the automobile at high speed, and calculate and output the next motor drive signal through the control algorithm. In the process of automobile development, calibration engineers usually need to collect and observe the input signal variables and output control variables of the control algorithm model inside the chip at high speed to evaluate and optimize the control algorithm model. The input signal variables of the control algorithm model can be the input parameters of the control algorithm model. The output control variables of the control algorithm model can be the calculation results of the control algorithm model.

[0003] In the related technology, calibration engineers usually collect the input signal variables and output control variables of the control algorithm model inside the chip based on the chip's debugging protocol. This is highly complex and cannot quickly and accurately collect the input signal variables and output control variables of the control algorithm model inside the chip. It is inefficient and cannot meet the needs of high-speed calibration scenarios. Summary of the invention

[0004] The present invention provides a memory reconstruction system and method to solve the problems that the related technology is highly complex, cannot quickly and accurately collect the input signal variables and output control variables of the control algorithm model inside the chip, has low efficiency, and cannot meet the requirements of high-speed calibration scenarios.

[0005] According to one aspect of the present invention, there is provided a memory reconstruction system, comprising: a target chip and a calibration tool;

[0006] The target chip is provided with a memory, a data encoding system and a data sending module, and the calibration tool is provided with a memory, a data decoding system and a data receiving module;

[0007] The data encoding system includes a kernel write operation interface, a filtering module, a compression module, a packaging module and a data buffer;

[0008] After the data encoding system obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface, the filtering module determines whether the value is valid data. If so, the compression module compresses the original memory address according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address, and the encapsulation module encodes the compressed memory address and the value according to the memory operation message encoding format to obtain a memory operation message, and caches the memory operation message to the data buffer;

[0009] The data sending module sends the message in the data buffer to the data receiving module;

[0010] The data receiving module sends the received message to the data decoding system;

[0011] The data decoding system decodes the received memory operation message according to the memory operation message encoding format to obtain the compressed memory address and numerical value corresponding to the memory operation message, determines the original memory address corresponding to the compressed memory address based on the previous original memory address, stores the original memory address and the numerical value in the memory of the calibration tool and provides them to the target user.

[0012] After caching a preset number of memory operation messages, the data encoding system encodes a preset value and a data buffer identifier according to a synchronization information encoding format through the encapsulation module to obtain synchronization information, and caches the synchronization information in the data buffer.

[0013] The data decoding system decodes the received synchronization information according to the synchronization information encoding format to obtain a preset value and a data buffer identifier, and stores the preset value and the data buffer identifier in the memory of the calibration tool.

[0014] According to another aspect of the present invention, a memory reconstruction method is provided, which is applied to the memory reconstruction system according to any embodiment of the present invention, comprising:

[0015] After the data encoding system obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface, the filtering module determines whether the value is valid data. If so, the compression module compresses the original memory address according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address, and the encapsulation module encodes the compressed memory address and the value according to the memory operation message encoding format to obtain a memory operation message, and caches the memory operation message to the data buffer;

[0016] The data sending module sends the message in the data buffer to the data receiving module;

[0017] The data receiving module sends the received message to the data decoding system;

[0018] The data decoding system decodes the received memory operation message according to the memory operation message encoding format to obtain the compressed memory address and numerical value corresponding to the memory operation message, determines the original memory address corresponding to the compressed memory address based on the previous original memory address, stores the original memory address and the numerical value in the memory of the calibration tool and provides them to the target user.

[0019] It also includes: after caching a preset number of memory operation messages, the data encoding system encodes the preset value and the data buffer identifier through the encapsulation module according to the synchronization information encoding format to obtain synchronization information, and caches the synchronization information to the data buffer.

[0020] It also includes: a data decoding system decodes the received synchronization information according to the synchronization information encoding format to obtain a preset value and a data buffer identifier, and stores the preset value and the data buffer identifier in the memory of the calibration tool.

[0021] The data encoding system determines whether the value is valid data through the filtering module, including:

[0022] The data encoding system determines whether the value is valid data according to the target memory address range, the target data source identifier and / or the target bus attribute through the filtering module.

[0023] The data encoding system compresses the original memory address according to the last original memory address through the compression module to obtain a compressed memory address corresponding to the original memory address, including:

[0024] The data encoding system compares the bytes at the same position in the original memory address and the previous original memory address through the compression module to see whether they are the same, and determines the compressed memory address corresponding to the original memory address based on the comparison result.

[0025] The data encoding system encodes the compressed memory address and the value according to the memory operation message encoding format through the encapsulation module to obtain a memory operation message, including:

[0026] The data encoding system performs the following operations through the encapsulation module:

[0027] Sort the bytes in the compressed memory address in order from low byte to high byte to obtain the encoded compressed memory address;

[0028] Determining the encoded address length information of the compressed memory address;

[0029] Sort the bytes in the value from low byte to high byte to obtain the encoded value;

[0030] Determine the data length information of the encoded value;

[0031] Determining identification information corresponding to the compressed memory address and the value;

[0032] The identification information, the address length information, the data length information, the encoded compressed memory address and the encoded numerical value are concatenated to obtain a memory operation message.

[0033] The data decoding system decodes the received memory operation message according to the memory operation message encoding format to obtain a compressed memory address and a value corresponding to the memory operation message, including:

[0034] The data decoding system determines the encoded compressed memory address and the encoded value in the memory operation message according to the sorting order of each component in the memory operation message and the data length, and extracts the encoded compressed memory address and the encoded value in the memory operation message;

[0035] The data decoding system sorts the bytes in the encoded compressed memory address in order from high byte to low byte to obtain a compressed memory address corresponding to the memory operation message;

[0036] The data decoding system sorts the bytes in the encoded value in order from high byte to low byte to obtain a value corresponding to the memory operation message.

[0037] In the technical solution of the embodiment of the present invention, after the data encoding system of the target chip obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface, it determines whether the value is valid data through the filtering module. If so, the original memory address is compressed by the compression module according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address, and the compressed memory address and value are encoded by the encapsulation module according to the memory operation message encoding format to obtain a memory operation message, and the memory operation message is cached in the data buffer; the data sending module of the target chip sends the message in the data buffer to the data receiving module of the calibration tool; the data receiving module of the calibration tool receives the received message The received message is sent to the data decoding system of the calibration tool; the data decoding system of the calibration tool decodes the received memory operation message according to the memory operation message encoding format, obtains the compressed memory address and value corresponding to the memory operation message, determines the original memory address corresponding to the compressed memory address according to the previous original memory address, stores the original memory address and value in the memory of the calibration tool and provides them to the target user, which solves the problem that the related technology is highly complex, cannot quickly and accurately collect the input signal variables and output control variables of the control algorithm model inside the chip, has low efficiency, and cannot meet the needs of high-speed calibration scenarios. Based on the data encoding system and data sending module of the chip, The input signal variable or output control variable of the control algorithm model and the storage address of the input signal variable or output control variable of the control algorithm model are filtered out from the corresponding original memory addresses and values, the storage address of the input signal variable or output control variable of the control algorithm model is compressed, the input signal variable or output control variable of the control algorithm model and the storage address of the input signal variable or output control variable of the control algorithm model after compression are encoded, and the encoded information is sent to the data receiving module of the calibration tool. Based on the data receiving module and the data decoding module of the calibration tool, the encoded information can be received, and the encoded information can be decoded to obtain the input signal of the control algorithm model. The storage address of the input signal variables or output control variables, the input signal variables or output control variables of the control algorithm model, and the storage address of the input signal variables or output control variables of the control algorithm model are provided to the user. During the operation of the chip, based on the chip's memory, data encoding system and data sending module, the calibration tool's memory, data decoding system and data receiving module, the input signal variables and output control variables of the control algorithm model inside the chip can be quickly and accurately collected, and the collected input signal variables and output control variables of the control algorithm model inside the chip can be provided to the user. It has low complexity and high efficiency, and can meet the needs of high-speed calibration scenarios.

[0038] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of the structure of a memory reconstruction system provided by an embodiment of the present invention.

[0041] Figure 2 A flowchart of a method for compressing an original memory address provided by an embodiment of the present invention.

[0042] Figure 3 A schematic diagram of a memory operation message encoding format provided in an embodiment of the present invention.

[0043] Figure 4 A schematic diagram of an encoded compressed memory address provided by an embodiment of the present invention.

[0044] Figure 5 A schematic diagram of a synchronization information encoding format provided by an embodiment of the present invention.

[0045] Figure 6 A schematic diagram of a data processing flow in a target chip provided by an embodiment of the present invention.

[0046] Figure 7 A flowchart of a memory reconstruction method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "target", "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprise", "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] Figure 1 This is a schematic diagram of the structure of a memory reconstruction system provided by an embodiment of the present invention. This embodiment is applicable to the case where the input signal variables and output control variables of the control algorithm model inside the chip are collected during the operation of the chip and provided to the calibration engineer. Figure 1 As shown, the memory reconstruction system may specifically include: a target chip 101 and a calibration tool 102, and the structure and function thereof are described below.

[0050] The target chip 101 is provided with a memory 103 , a data encoding system 104 and a data sending module 105 , and the calibration tool 102 is provided with a memory 106 , a data decoding system 107 and a data receiving module 108 .

[0051] The data encoding system 104 includes a kernel write operation interface 1041 , a filtering module 1042 , a compression module 1043 , a packaging module 1044 and a data buffer 1045 .

[0052] After the data encoding system 104 obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface 1041, it determines whether the value is valid data through the filtering module 1042. If so, the compression module 1043 compresses the original memory address according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address. The encapsulation module 1044 encodes the compressed memory address and the value according to the memory operation message encoding format to obtain a memory operation message, and caches the memory operation message to the data buffer 1045.

[0053] The data sending module 105 sends the message in the data buffer 1045 to the data receiving module 108 .

[0054] The data receiving module 108 sends the received message to the data decoding system 107 .

[0055] The data decoding system 107 decodes the received memory operation message according to the memory operation message encoding format to obtain the compressed memory address and numerical value corresponding to the memory operation message, determines the original memory address corresponding to the compressed memory address based on the previous original memory address, stores the original memory address and the numerical value in the memory 106 of the calibration tool 102 and provides them to the target user.

[0056] Optionally, the target chip 101 is a chip that needs to collect and observe the input signal variables and output control variables of the control algorithm model inside the chip. The target chip 101 is provided with a control algorithm model inside. The control algorithm model inside the target chip 101 may be a model for executing the control algorithm of the target chip 101. The input signal variables of the control algorithm model may be input parameters of the control algorithm model. The input parameters of the control algorithm model may be vehicle parameters input into the control algorithm model. The output control variables of the control algorithm model may be the calculation results of the control algorithm model. The calculation results of the control algorithm model may be instructions or signals output by the control algorithm model after calculation according to the input parameters. The target chip 101 is a chip for controlling the vehicle. Exemplarily, the target chip 101 may be an ECU chip inside the ABS provided on the vehicle, the input signal variables of the control algorithm model inside the target chip 101 include but are not limited to the tire speed signal of the vehicle, and the output control variables of the control algorithm model inside the target chip 101 include but are not limited to the braking control instructions. The target chip 101 can also be a motor control chip installed in a car. The input signal variables of the control algorithm model inside the target chip 101 include but are not limited to the rotation position of the motor rotor and the motor speed signal of the car, and the output control variables of the control algorithm model inside the target chip 101 include but are not limited to the motor drive signal.

[0057] Optionally, the target chip 101 includes multiple cores. During the operation of the target chip 101, one or more cores among the cores will call the control algorithm model to execute the control algorithm of the target chip 101. In the process of calling the control algorithm model to execute the control algorithm of the target chip 101, each core will write the input signal variable or output control variable of the control algorithm model into the memory 103 of the target chip 101.

[0058] Optionally, the calibration tool 102 may be a terminal device used by a target user, who may be a calibration engineer who needs to collect and observe input signal variables and output control variables of the control algorithm model inside the target chip 101 at high speed, and evaluate and optimize the control algorithm model.

[0059] Optionally, the target chip 101 is provided with a memory 103, a data encoding system 104, and a data sending module 105. The memory 103 may be a memory provided in the target chip 101 for storing data. The data encoding system 104 may be a hardware system or software system provided in the target chip 101 for encoding the input signal variables or output control variables and their memory addresses of the control algorithm model written by each core to the memory 103 of the target chip 101. The data sending module 105 may be a hardware module or software module provided in the target chip 101 for sending the encoded input signal variables or output control variables and their memory addresses of the control algorithm model to the data receiving module 108 in the calibration tool 102.

[0060] Optionally, the data encoding system 104 includes a kernel write operation interface 1041, a filtering module 1042, a compression module 1043, a packaging module 1044 and a data buffer 1045. A kernel write operation interface 1041 is provided in each kernel. The kernel write operation interface 1041 may be an interface provided in the kernel for sending the original memory address and value corresponding to the memory write operation behavior to the filtering module 1042 after the kernel performs a memory write operation behavior. The memory write operation behavior may be an operation behavior in which the kernel writes data into the memory 103 of the target chip 101. The original memory address corresponding to the memory write operation behavior is the storage address of the storage unit where the written data is located. The value corresponding to the memory write operation behavior is the written data. During the operation of the target chip 101, the kernel may send the original memory address and value corresponding to the memory write operation behavior to the filtering module 1042 through the kernel write operation interface 1041 after each memory write operation behavior. The filtering module 1042 may be a hardware module or a software module for determining whether the value corresponding to the memory write operation behavior is valid data. The valid data includes the input signal variables and output control variables of the control algorithm model of the target chip 101. The control algorithm model of the target chip 101 is the control algorithm model inside the target chip 101. Judging whether a numerical value is valid data refers to judging whether a numerical value is an input signal variable or an output control variable of the control algorithm model inside the target chip 101. The compression module 1043 can be a hardware module or software module for compressing the original memory address according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address. The encapsulation module 1044 can be a hardware module or software module for encoding the compressed memory address and the numerical value according to the memory operation message encoding format to obtain a memory operation message. The data buffer 1045 can be an area set in the target chip 101 for caching the memory operation message that needs to be sent to the calibration tool 102.

[0061] Optionally, the calibration tool 102 is provided with a memory 106, a data decoding system 107, and a data receiving module 108. The memory 106 may be a memory provided in the calibration tool 102 for storing data. The data decoding system 107 may be a hardware system or software system provided in the calibration tool 102 for decoding a received memory operation message according to the memory operation message encoding format, obtaining a compressed memory address and a value corresponding to the memory operation message, determining an original memory address corresponding to the compressed memory address according to the last original memory address, storing the original memory address and the value in the memory 106 of the calibration tool 102, and providing them to the target user. The data receiving module 108 may be a hardware module or a software module provided in the calibration tool 102 for receiving a message sent by the data sending module 105.

[0062] Optionally, the memory 103 is connected to the data encoding system 104, the data encoding system 104 is connected to the data sending module 105, the data sending module 105 is connected to the data receiving module 108 via a high-speed serial bus, the data receiving module 108 is connected to the data decoding system 107, and the data decoding system 107 is connected to the memory 106. The kernel write operation interface 1041 is connected to the filtering module 1042, the filtering module 1042 is connected to the compression module 1043, the compression module 1043 is connected to the encapsulation module 1044, and the encapsulation module 1044 is connected to the data buffer 1045.

[0063] Optionally, the kernel write operation interface 1041 is a parallel bus interface. The kernel write operation interface 1041 includes an address bus and a data bus. The address bus can be 32 bits or 64 bits. The data bus can be 32 bits, 64 bits or 128 bits.

[0064] Optionally, after the data encoding system 104 obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface 1041, the data encoding system 104 determines whether the value is valid data through the filtering module 1042. The data encoding system 104 determines whether the value is valid data through the filtering module 1042, including: the data encoding system 104 determines whether the value is valid data according to the target memory address range, the target data source identifier and / or the target bus attribute through the filtering module 1042.

[0065] Optionally, the filter module 1042 determines whether the value is valid data according to the target memory address range, the target data source identifier and / or the target bus attribute after receiving the original memory address and value corresponding to the memory write operation behavior sent by the kernel through the kernel write operation interface 1041 each time, that is, after obtaining the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface 1041 each time. The filter module 1042 stores the target memory address range, the target data source identifier and the target bus attribute.

[0066] Optionally, the target memory address range is the address range in which the storage addresses of the storage units of the input signal variables or output control variables that will be written into the control algorithm model will be located. The target memory address range is limited by a lower boundary address and an upper boundary address. If the numerical value is valid data, the original memory address collected together with the numerical value will be in the target memory address range. If the numerical value is not valid data, the original memory address collected together with the numerical value will not be in the target memory address range. The original memory address collected together with the numerical value being in the target memory address range may mean that the original memory address collected together with the numerical value is greater than or equal to the lower boundary address of the target memory address range and less than or equal to the upper boundary address of the target memory address range. The original memory address collected together with the numerical value is not in the target memory address range may mean that the original memory address collected together with the numerical value is less than the lower boundary address of the target memory address range or greater than the upper boundary address of the target memory address range.

[0067] Optionally, the target data source identification is composed of identification information of all kernels that will not write the input signal variables or output control variables of the control algorithm model into the memory 103 of the target chip 101. Each kernel is provided with unique corresponding identification information. The identification information of the kernel can be a digital number or a string of kernels used for unique identification. If the value is valid data, the target data source identification will not include the identification information of the kernel that writes the value into the memory 103 of the target chip 101. If the value is not valid data, the target data source identification will include the identification information of the kernel that writes the value into the memory 103 of the target chip 101.

[0068] Optionally, the target bus attribute is composed of the types of buses that will be used when all kernels that will not write the input signal variables or output control variables of the control algorithm model into the memory 103 of the target chip 101 access the memory. If the value is valid data, the target bus attribute will not include the type of bus used when the kernel writes the value. If the value is not valid data, the target bus attribute will include the type of bus used when the kernel writes the value. Exemplarily, the type of bus that the kernel will use when accessing the memory can be an AXI bus, an ATCM bus, a BTCM bus, a CTCM bus, or a LLPP bus.

[0069] Optionally, the filtering module 1042 can obtain the data source identifier and bus attribute corresponding to the memory write operation behavior from the kernel each time after receiving the original memory address and value corresponding to the memory write operation behavior sent by the kernel through the kernel write operation interface 1041. The data source identifier corresponding to the memory write operation behavior is the identification information of the kernel that writes the data. The bus attribute corresponding to the memory write operation behavior is the type of bus used by the kernel when writing data.

[0070] Optionally, judging whether the numerical value is valid data based on the target memory address range includes: judging whether the original memory address collected together with the numerical value is within the target memory address range; if so, determining that the numerical value is valid data; if not, determining that the numerical value is not valid data.

[0071] Optionally, judging whether the numerical value is valid data based on the target data source identifier includes: judging whether the target data source identifier includes a data source identifier collected together with the numerical value; if so, determining that the numerical value is not valid data; if not, determining that the numerical value is valid data.

[0072] Optionally, judging whether the numerical value is valid data according to the target bus attributes includes: judging whether the target bus attributes include bus attributes collected together with the numerical value; if so, determining that the numerical value is not valid data; if not, determining that the numerical value is valid data.

[0073] Optionally, judging whether the numerical value is valid data according to the target memory address range, the target data source identifier and the target bus attribute includes: judging whether the target data source identifier includes the data source identifier collected together with the numerical value; if the target data source identifier includes the data source identifier collected together with the numerical value, determining that the numerical value is not valid data; if the target data source identifier does not include the data source identifier collected together with the numerical value, judging whether the target bus attribute includes the bus attribute collected together with the numerical value; if the target bus attribute includes the bus attribute collected together with the numerical value, determining that the numerical value is not valid data; if the target bus attribute does not include the bus attribute collected together with the numerical value, judging whether the original memory address collected together with the numerical value is within the target memory address range; if the original memory address collected together with the numerical value is within the target memory address range, determining that the numerical value is valid data; if the original memory address collected together with the numerical value is not within the target memory address range, determining that the numerical value is not valid data.

[0074] Optionally, if the value is valid data, the filtering module 1042 outputs the value and the original memory address collected together with the value to the compression module 1043, so that the compression module 1043 compresses the original memory address according to the last original memory address to obtain a compressed memory address corresponding to the original memory address. The last original memory address is the original memory address processed by the compression module 1043 last time.

[0075] Optionally, the data encoding system 104 compresses the original memory address according to the previous original memory address through the compression module 1043 to obtain a compressed memory address corresponding to the original memory address, including: the data encoding system 104 compares whether the bytes at the same position in the original memory address and the previous original memory address are the same through the compression module 1043, and determines the compressed memory address corresponding to the original memory address based on the comparison result.

[0076] Optionally, after receiving the numerical value output by the filtering module 1042 and the original memory address collected together with the numerical value, the compression module 1043 can compare whether the bytes at the same position in the original memory address and the previous original memory address are the same, and determine the compressed memory address corresponding to the original memory address based on the comparison result, and then output the compressed memory address and the numerical value to the encapsulation module 1044, so that the encapsulation module 1044 encodes the compressed memory address and the numerical value according to the memory operation message encoding format to obtain a memory operation message, and caches the memory operation message to the data buffer 1045.

[0077] Optionally, the original memory address is a 32-bit address containing four bytes. The four bytes in the original memory address are the highest byte, the third byte, the second byte, and the first byte. The highest byte is the byte at the highest position in the original memory address. The third byte is the byte adjacent to the highest byte after the highest byte. The second byte is the byte adjacent to the third byte after the third byte. The first byte is the byte adjacent to the second byte after the second byte. Exemplarily, the original memory address is 0x10002001, the highest byte in the original memory address is 0x10, the third byte is 0x00, the second byte is 0x20, and the first byte is 0x01.

[0078] Optionally, when the kernel performs a series of memory write operations, the original memory addresses corresponding to the respective memory write operations have local characteristics. The local characteristics of the respective original memory addresses may refer to that the respective original memory addresses may change in the low byte portion and remain relatively unchanged in the high byte portion. Thus, the compression module 1043 may compress the original memory address currently being processed according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address currently being processed. The compressed memory address corresponding to the original memory address is information in the original memory address retained during the process of compressing the original memory address. The compressed memory address corresponding to the original memory address may be the low byte change portion in the original memory address, or may be the complete original memory address. For the subsequent original memory address, the original memory address is compressed according to the change of the original memory address relative to the previous original memory address to obtain a compressed memory address corresponding to the original memory address. If the original memory address changes in the low byte portion relative to the previous original memory address and remains relatively unchanged in the high byte portion, only the low byte change portion in the original memory address is retained.

[0079] Optionally, if the original memory address is the same as the previous original memory address in the highest byte and different in the third byte, only the low byte change part of the original memory address is retained: the third byte, the second byte, and the first byte, and the third byte, the second byte, and the first byte are determined as the compressed memory address corresponding to the original memory address. If the original memory address is the same as the previous original memory address in the highest byte and the third byte, and different in the second byte, only the low byte change part of the original memory address is retained: the second byte and the first byte, and the second byte and the first byte are determined as the compressed memory address corresponding to the original memory address. If the original memory address is the same as the previous original memory address in the highest byte, the third byte, and the second byte, and different in the first byte, only the low byte change part of the original memory address is retained: the first byte, and the first byte is determined as the compressed memory address corresponding to the original memory address. If the original memory address is also different from the previous original memory address in the highest byte, the complete original memory address containing four bytes is retained, and the complete original memory address containing four bytes is determined as the compressed memory address corresponding to the original memory address.

[0080] Optionally, comparing whether the bytes at the same position in the original memory address and the previous original memory address are the same, and determining the compressed memory address corresponding to the original memory address according to the comparison result, includes: after the original memory address is obtained for the first time, determining the original memory address as the compressed memory address corresponding to the original memory address; after the original memory address is obtained for the second time, comparing whether the bytes at the same position in the original memory address obtained for the second time and the original memory address obtained for the first time are the same, and determining the compressed memory address corresponding to the original memory address obtained for the second time according to the comparison result; after the original memory address is obtained for the third time, comparing whether the bytes at the same position in the original memory address obtained for the third time and the original memory address obtained for the second time are the same, and determining the compressed memory address corresponding to the original memory address obtained for the third time according to the comparison result; and so on, after the original memory address is obtained for the Nth time, comparing whether the bytes at the same position in the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are the same, and determining the compressed memory address corresponding to the original memory address obtained for the Nth time according to the comparison result. N is an integer greater than or equal to 2.

[0081] Optionally, after the original memory address is obtained for the Nth time, compare whether the bytes at the same position in the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are the same, and determine the compressed memory address corresponding to the original memory address obtained for the Nth time based on the comparison result, including: after the original memory address is obtained for the Nth time, compare whether the highest bytes in the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are different; if the highest bytes in the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are different, determine the original memory address obtained for the Nth time as the compressed memory address corresponding to the original memory address obtained for the Nth time; if the highest bytes in the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are the same, compare whether the third bytes in the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are different; if the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are the same, -1 times are not the same, the third byte, the second byte and the first byte of the original memory address obtained for the Nth time are determined as the compressed memory address corresponding to the original memory address obtained for the Nth time; if the third byte of the original memory address obtained for the Nth time is the same as the third byte of the original memory address obtained for the Nth time, then compare whether the second bytes of the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are different; if the second bytes of the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are not the same, then the second byte and the first byte of the original memory address obtained for the Nth time are determined as the compressed memory address corresponding to the original memory address obtained for the Nth time; if the second bytes of the original memory address obtained for the Nth time and the original memory address obtained for the N-1th time are the same, then the first byte of the original memory address obtained for the Nth time is determined as the compressed memory address corresponding to the original memory address obtained for the Nth time.

[0082] Optional, Figure 2 A flowchart of a method for compressing an original memory address provided by an embodiment of the present invention. Figure 2 As shown, the method specifically includes:

[0083] Step 1001, start.

[0084] Step 1002: When the original memory address containing four bytes output by the filtering module is obtained for the first time, the original memory address is determined as a compressed memory address corresponding to the original memory address, and the compressed memory address containing four bytes is output.

[0085] Step 1003: Update the original memory address containing four bytes to the previous original memory address corresponding to the next original memory address.

[0086] Step 1004: Wait for the filtering module to output the next original memory address.

[0087] Step 1005, determine whether to continue the operation: if so, execute step 1006; if not, determine that this process is terminated.

[0088] Step 1006: Compare the differences between the next original memory address output by the filtering module and the bytes in the corresponding previous original memory address.

[0089] Step 1007, determine whether the highest byte in the next original memory address is different from the highest byte in the corresponding previous original memory address; if so, execute step 1008; if not, execute step 1009.

[0090] Step 1008: determine the next original memory address as the compressed memory address corresponding to the next original memory address, and output the compressed memory address containing four bytes.

[0091] Step 1009, determine whether the third byte in the next original memory address is different from the third byte in the corresponding previous original memory address; if so, execute step 1010; if not, execute step 1011.

[0092] Step 1010: determine the third byte, the second byte, and the first byte in the next original memory address as the compressed memory address corresponding to the next original memory address, and output the compressed memory address containing three bytes.

[0093] Step 1011, determine whether the second byte in the next original memory address is different from the second byte in the corresponding previous original memory address; if so, execute step 1012; if not, execute step 1013.

[0094] Step 1012: determine the second byte and the first byte in the next original memory address as the compressed memory address corresponding to the next original memory address, and output the compressed memory address containing two bytes.

[0095] Step 1013: determine the first byte in the next original memory address as the compressed memory address corresponding to the next original memory address, and output the compressed memory address containing one byte.

[0096] Optionally, if the next original memory address output by the filtering module is received, it is determined to continue the operation. If the next original memory address output by the filtering module is not received, it is determined not to continue the operation.

[0097] Optionally, the data encoding system 104 encodes the compressed memory address and the numerical value according to the memory operation message encoding format through the encapsulation module 1044 to obtain a memory operation message, including: the data encoding system 104 performs the following operations through the encapsulation module 1044: sorting each byte in the compressed memory address in order from low byte to high byte to obtain the encoded compressed memory address; determining the address length information of the encoded compressed memory address; sorting each byte in the numerical value in order from low byte to high byte to obtain the encoded numerical value; determining the data length information of the encoded numerical value; determining the identification information corresponding to the compressed memory address and the numerical value; splicing the identification information, the address length information, the data length information, the encoded compressed memory address and the encoded numerical value to obtain a memory operation message.

[0098] Optionally, the memory operation message is information containing data related to the memory write operation behavior. The memory write operation behavior may be an operation behavior in which the kernel writes data into the memory of the target chip. The memory operation message encoding format may be information used to characterize the names, sorting order, and data length of each component in the memory operation message. Exemplarily, the memory operation message encoding format may be a table used to characterize the names, sorting order, and data length of each component in the memory operation message. For each memory write operation behavior, the memory operation message containing data related to the memory write operation behavior is composed of five components: the encoded compressed memory address corresponding to the memory write operation behavior, the encoded value corresponding to the memory write operation behavior, the identification information corresponding to the memory write operation behavior, the address length information of the encoded compressed memory address, and the data length information of the encoded value. The sorting order of the five components in the memory operation message is identification information, address length information, data length information, encoded compressed memory address, and encoded value. The identification information is ranked first, the address length information is ranked second, the data length information is ranked third, the encoded compressed memory address is ranked fourth, and the encoded value is ranked fifth. The data length of the identification information is usually 4 bits. The data length of the address length information is usually 2 bits. The data length of the data length information is usually 2 bits. The data length of the encoded compressed memory address is usually 1-4 bytes. The data length of the encoded value is usually 1-8 bytes.

[0099] Optional, Figure 3 A schematic diagram of a memory operation message encoding format provided by an embodiment of the present invention. Figure 3As shown, the memory operation message containing data related to the memory write operation behavior consists of five components. The order of the five components in the memory operation message is identification information, address length information, data length information, encoded compressed memory address, and encoded numerical value. The identification information is ranked first, the address length information is ranked second, the data length information is ranked third, the encoded compressed memory address is ranked fourth, and the encoded numerical value is ranked fifth. The data length of the identification information is usually 4 bits. The data length of the address length information is usually 2 bits. The data length of the data length information is usually 2 bits. The data length of the encoded compressed memory address is usually 1-4 bytes. The data length of the encoded numerical value is usually 1-8 bytes.

[0100] Optionally, the encoded value may be a byte sequence obtained by reordering the bytes in the value in order from low byte to high byte. Exemplarily, the value is 0x90000000. The bytes in the compressed memory address are reordered in order from low byte to high byte to obtain a byte sequence: 0x00, 0x00, 0x00, 0x90. The obtained byte sequence is the encoded value.

[0101] Optionally, the compressed memory address corresponding to the memory write operation behavior is a compressed memory address obtained by compressing the original memory address corresponding to the memory write operation behavior. The encoded compressed memory address can be a byte sequence obtained by reordering the bytes in the compressed memory address in order from low byte to high byte. Exemplarily, the compressed memory address is 0x300000. The byte sequence is obtained by reordering the bytes in the compressed memory address in order from low byte to high byte: 0x00, 0x00, 0x30. The obtained byte sequence is the encoded compressed memory address.

[0102] Optional, Figure 4 A schematic diagram of an encoded compressed memory address provided by an embodiment of the present invention. Figure 4As shown, the original memory address obtained for the first time is 0x10000000. The original memory address obtained for the first time is the compressed memory address corresponding to the original memory address obtained for the first time. The compressed memory addresses after encoding are 0x00, 0x00, 0x00, 0x10. The original memory address obtained for the second time is 0x10002000. The original memory address obtained for the second time is the same as the original memory address obtained for the first time in the highest byte, the third byte is the same, and the second byte is different. The second byte and the first byte of the original memory address obtained for the second time are determined as the compressed memory address corresponding to the original memory address obtained for the second time. The compressed memory address is 0x20, 0x00. The compressed memory address after encoding is 0x00, 0x20. The original memory address obtained for the third time is 0x10002001. The original memory address obtained for the third time is the same as the original memory address obtained for the second time in the highest byte, the third byte is the same, and the second byte is the same. The first byte of the original memory address obtained for the third time is determined as the compressed memory address corresponding to the original memory address obtained for the third time. The compressed memory address is 0x01. The compressed memory address after encoding is 0x01. The original memory address obtained for the fourth time is 0x10300000. The original memory address obtained for the fourth time has the same highest byte as the original memory address obtained for the third time, but the third byte is different. The third byte, the second byte, and the first byte of the original memory address obtained for the fourth time are determined as the compressed memory address corresponding to the original memory address obtained for the fourth time. The compressed memory address is 0x30, 0x00, 0x00. The compressed memory address after encoding is 0x00, 0x00, 0x30. The original memory address obtained for the fifth time is 0x30300000. The original memory address obtained for the fifth time has the same highest byte as the original memory address obtained for the fourth time. The highest byte, the third byte, the second byte, and the first byte of the original memory address obtained for the fifth time are determined as the compressed memory address corresponding to the original memory address obtained for the fifth time. The compressed memory address is 0x30, 0x30, 0x00, 0x00. The encoded compressed memory addresses are 0x00, 0x00, 0x30, 0x30.

[0103] Optionally, the data length information of the encoded numerical value may be information used to characterize the data length of the encoded numerical value corresponding to the memory write operation behavior. The data length information of the encoded numerical value may be 0b00, 0b01, 0b10, or 0b11. The data length information of the encoded numerical value is 0b00, indicating that the data length of the encoded numerical value corresponding to the memory write operation behavior is 1 byte. The data length information corresponding to the memory write operation behavior is 0b01, indicating that the data length of the encoded numerical value corresponding to the memory write operation behavior is 2 bytes. The data length information corresponding to the memory write operation behavior is 0b10, indicating that the data length of the encoded numerical value corresponding to the memory write operation behavior is 4 bytes. The data length information corresponding to the memory write operation behavior is 0b11, indicating that the data length of the encoded numerical value corresponding to the memory write operation behavior is 8 bytes.

[0104] Optionally, the address length information of the encoded compressed memory address may be information used to characterize the data length of the encoded compressed memory address corresponding to the memory write operation behavior. The address length information of the encoded compressed memory address may be 0b00, 0b01, 0b10, or 0b11. The address length information of the encoded compressed memory address is 0b00, indicating that the data length of the encoded compressed memory address corresponding to the memory write operation behavior is 1 byte. The address length information of the encoded compressed memory address is 0b01, indicating that the data length of the encoded compressed memory address corresponding to the memory write operation behavior is 2 bytes. The address length information of the encoded compressed memory address is 0b10, indicating that the data length of the encoded compressed memory address corresponding to the memory write operation behavior is 3 bytes. The address length information of the encoded compressed memory address is 0b11, indicating that the data length of the encoded compressed memory address corresponding to the memory write operation behavior is 4 bytes.

[0105] Optionally, the identification information corresponding to the memory write operation behavior may be a data source identifier corresponding to the memory write operation behavior, or a bus attribute corresponding to the memory write operation behavior, or a preset specific value for identifying the memory write operation behavior, or XOR data obtained by performing an XOR operation on the address length information and the data length information in the memory operation message. The encapsulation module 1044 stores a preset specific value for identifying the memory write operation behavior. The XOR data can be used to verify the correctness of the address length information and the data length information. When the identification function of the identification information is not enabled, the default value of the identification information is 4 bits of 0.

[0106] Optionally, determining the address length information of the encoded compressed memory address includes: detecting the data length of the encoded compressed memory address; if the data length of the encoded compressed memory address is 1 byte, determining the address length information of the encoded compressed memory address to be 0b00; if the data length of the encoded compressed memory address is 2 bytes, determining the address length information of the encoded compressed memory address to be 0b01; if the data length of the encoded compressed memory address is 3 bytes, determining the address length information of the encoded compressed memory address to be 0b10; if the data length of the encoded compressed memory address is 4 bytes, determining the address length information of the encoded compressed memory address to be 0b11.

[0107] Optionally, determining the data length information of the encoded value includes: detecting the data length of the encoded value; if the data length of the encoded value is 1 byte, determining the data length information of the encoded value to be 0b00; if the data length of the encoded value is 2 bytes, determining the data length information of the encoded value to be 0b01; if the data length of the encoded value is 4 bytes, determining the data length information of the encoded value to be 0b10; if the data length of the encoded value is 8 bytes, determining the data length information of the encoded value to be 0b11.

[0108] Optionally, the identification information corresponding to the compressed memory address and the numerical value is the identification information corresponding to the memory write operation behavior to which the compressed memory address and the numerical value belong. Determining the identification information corresponding to the compressed memory address and the numerical value includes: determining the data source identifier corresponding to the memory write operation behavior to which the compressed memory address and the numerical value belong, which is sent by the kernel write operation interface 1041, as the identification information corresponding to the compressed memory address and the numerical value; or determining the bus attribute corresponding to the memory write operation behavior to which the compressed memory address and the numerical value belong, which is sent by the kernel write operation interface 1041, as the identification information corresponding to the compressed memory address and the numerical value; or determining a preset specific value for identifying the memory write operation behavior as the identification information corresponding to the compressed memory address and the numerical value; or performing an XOR operation on the encoded address length information of the compressed memory address and the encoded data length information of the numerical value to obtain XOR data, and determining the XOR data as the identification information corresponding to the compressed memory address and the numerical value.

[0109] Optionally, the spliced ​​data obtained by splicing the identification information, the address length information, the data length information, the encoded compressed memory address and the encoded value is a memory operation message carrying data related to the memory write operation behavior to which the compressed memory address and the value belong. After encoding the compressed memory address and the value according to the memory operation message encoding format to obtain the memory operation message, the encapsulation module 1044 caches the memory operation message to the data buffer 1045.

[0110] Optionally, the data sending module 105 may send each memory operation message in the data buffer 1045 to the data receiving module 108 in sequence according to the order in which each memory operation message is cached in the data buffer 1045. The memory operation message cached first is sent to the data receiving module 108 first. The memory operation message cached later is sent to the data receiving module 108 later. After receiving each memory operation message, the data receiving module 108 sends the received memory operation message to the data decoding system 107.

[0111] Optionally, after receiving each memory operation message, the data decoding system 107 will decode the received memory operation message according to the memory operation message encoding format to obtain a compressed memory address and a value corresponding to the memory operation message. Then, based on the last original memory address, the original memory address corresponding to the compressed memory address is determined, and the original memory address and the value are provided to the target user. The compressed memory address before encoding corresponding to the compressed memory address after encoding in the memory operation message is the compressed memory address corresponding to the memory write operation behavior to which the memory operation message belongs. The value before encoding corresponding to the encoded value in the memory operation message is the value corresponding to the memory write operation behavior to which the memory operation message belongs. The last original memory address is the original memory address processed by the data encoding system 104 last time, and is also the original memory address obtained after the data decoding system 107 processes the memory operation message received last time.

[0112] Optionally, the data decoding system 107 decodes the received memory operation message according to the memory operation message encoding format to obtain a compressed memory address and a numerical value corresponding to the memory operation message, including: the data decoding system 107 determines the encoded compressed memory address and the encoded numerical value in the memory operation message according to the sorting order of each component in the memory operation message and the data length, and extracts the encoded compressed memory address and the encoded numerical value in the memory operation message; the data decoding system 107 sorts each byte in the encoded compressed memory address in order from high byte to low byte to obtain the compressed memory address corresponding to the memory operation message; the data decoding system 107 sorts each byte in the encoded numerical value in order from high byte to low byte to obtain the numerical value corresponding to the memory operation message.

[0113] Optionally, the bytes in the encoded compressed memory address are sorted in order from high byte to low byte to obtain the compressed memory address before encoding, and the compressed memory address before encoding is the compressed memory address corresponding to the memory operation message. The bytes in the encoded value are sorted in order from high byte to low byte to obtain the value before encoding, and the value before encoding is the value corresponding to the memory operation message.

[0114] Optionally, determining the original memory address corresponding to the compressed memory address based on the previous original memory address includes: if the compressed memory address contains four bytes, determining that the fourth byte in the compressed memory address is the highest byte in the original memory address corresponding to the compressed memory address, the third byte in the compressed memory address is the third byte in the original memory address corresponding to the compressed memory address, the second byte in the compressed memory address is the second byte in the original memory address corresponding to the compressed memory address, and the first byte in the compressed memory address is the first byte in the original memory address corresponding to the compressed memory address, and performing the above steps on the first byte, the second byte, the second byte, and the first byte. The bytes are spliced ​​to obtain the original memory address corresponding to the compressed memory address; if the compressed memory address contains three bytes, it is determined that the highest byte in the previous original memory address is the highest byte in the original memory address corresponding to the compressed memory address, the third byte in the compressed memory address is the third byte in the original memory address corresponding to the compressed memory address, the second byte in the compressed memory address is the second byte in the original memory address corresponding to the compressed memory address, and the first byte in the compressed memory address is the first byte in the original memory address corresponding to the compressed memory address, and the highest byte, the third byte, the second byte and the first byte are spliced ​​to obtain the original memory address corresponding to the compressed memory address. the original memory address corresponding to the compressed memory address; if the compressed memory address contains two bytes, then determine that the highest byte in the previous original memory address is the highest byte in the original memory address corresponding to the compressed memory address, the third byte in the previous original memory address is the third byte in the original memory address corresponding to the compressed memory address, the second byte in the compressed memory address is the second byte in the original memory address corresponding to the compressed memory address, and the first byte in the compressed memory address is the first byte in the original memory address corresponding to the compressed memory address, and concatenate the highest byte, the third byte, the second byte and the first byte to obtain the address corresponding to the compressed memory address. the original memory address of the compressed memory address; if the compressed memory address contains a byte, determine that the highest byte in the previous original memory address is the highest byte in the original memory address corresponding to the compressed memory address, the third byte in the previous original memory address is the third byte in the original memory address corresponding to the compressed memory address, the second byte in the previous original memory address is the second byte in the original memory address corresponding to the compressed memory address, and one byte in the compressed memory address is the first byte in the original memory address corresponding to the compressed memory address, and concatenate the highest byte, the third byte, the second byte and the first byte to obtain the original memory address corresponding to the compressed memory address.

[0115] Optionally, providing the original memory address and the numerical value to the target user includes: displaying the original memory address and the numerical value in an information display page. The information display page may be a page set in the calibration tool 102 for interacting with the user and displaying the input signal variable and output control variable of the control algorithm model of the chip to the user. After the original memory address and the numerical value are displayed in the information display page, the target user may browse the original memory address and the numerical value displayed in the information display page. The numerical value is the input signal variable or output control variable of the control algorithm model of the target chip 101. The original memory address is the storage address of the storage unit storing the numerical value. The data decoding system 107 may display the original memory address and the numerical value in the information display page, thereby providing the input signal variable or output control variable of the control algorithm model of the target chip 101 acquired each time, and the storage address of the storage unit storing the input signal variable or output control variable of the control algorithm model of the target chip 101 acquired each time to the target user.

[0116] Optionally, the encapsulation module 1044 is further used to encode the preset value and the data buffer identifier according to the synchronization information encoding format to obtain synchronization information, and cache the synchronization information in the data buffer 1045. After caching a preset number of memory operation messages, the data encoding system 104 encodes the preset value and the data buffer identifier according to the synchronization information encoding format through the encapsulation module 1044 to obtain synchronization information, and caches the synchronization information in the data buffer 1045.

[0117] Optionally, after the encapsulation module 1044 caches the preset number of memory operation messages to the data buffer 1045, the data encoding system 104 can control the encapsulation module 1044 to encode the preset value and the data buffer identifier according to the synchronization information encoding format to obtain synchronization information, and cache the synchronization information to the data buffer 1045, so that the data sending module 105 can send the synchronization information to the data receiving module 108. The synchronization information can be information used to synchronize with the calibration tool 102. The preset number can be set according to business needs. Exemplarily, the preset number is 64. The synchronization information contains two components: a preset value and a data buffer identifier. The preset value can be 15 bytes of 0. The data buffer identifier is 0x10 or 0x11. If the data buffer identifier is 0x10, the highest bit 1 in the data buffer identifier is used to identify the synchronization message, and the lowest bit 0 in the data buffer identifier is used to indicate that no data buffer overflow has occurred. If the data buffer identifier is 0x11, the highest bit 1 in the data buffer identifier is used to identify the synchronization message, and the lowest bit 1 in the data buffer identifier is used to indicate that a data buffer overflow has occurred. The synchronization information encoding format may be a table used to characterize the name, sorting order, and data length of each component in the synchronization information. Figure 5 A schematic diagram of a synchronization information encoding format provided by an embodiment of the present invention. Figure 5 As shown, the synchronization information consists of two components. The order of the two components in the synchronization information is the preset value and the data buffer identifier. The preset value is ranked first, and the data buffer identifier is ranked second. The preset value is 15 bytes. The data length of the data buffer identifier is 1 byte.

[0118] Optionally, the data decoding system 107 decodes the received synchronization information according to the synchronization information encoding format to obtain a preset value and a data buffer identifier, and stores the preset value and the data buffer identifier in the memory 106 of the calibration tool 102. Decoding the received synchronization information according to the synchronization information encoding format to obtain a preset value and a data buffer identifier includes: determining the preset value and the data buffer identifier in the received synchronization information according to the sorting order of each component in the synchronization information encoding format and the data length, and extracting the preset value and the data buffer identifier in the received synchronization information.

[0119] In the technical solution of the embodiment of the present invention, after the data encoding system of the target chip obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface, it determines whether the value is valid data through the filtering module. If so, the original memory address is compressed by the compression module according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address, and the compressed memory address and value are encoded by the encapsulation module according to the memory operation message encoding format to obtain a memory operation message, and the memory operation message is cached in the data buffer; the data sending module of the target chip sends the message in the data buffer to the data receiving module of the calibration tool; the data receiving module of the calibration tool receives the received message The received message is sent to the data decoding system of the calibration tool; the data decoding system of the calibration tool decodes the received memory operation message according to the memory operation message encoding format, obtains the compressed memory address and value corresponding to the memory operation message, determines the original memory address corresponding to the compressed memory address according to the previous original memory address, stores the original memory address and value in the memory of the calibration tool and provides them to the target user, which solves the problem that the related technology is highly complex, cannot quickly and accurately collect the input signal variables and output control variables of the control algorithm model inside the chip, has low efficiency, and cannot meet the needs of high-speed calibration scenarios. Based on the data encoding system and data sending module of the chip, The input signal variable or output control variable of the control algorithm model and the storage address of the input signal variable or output control variable of the control algorithm model are filtered out from the corresponding original memory addresses and values, the storage address of the input signal variable or output control variable of the control algorithm model is compressed, the input signal variable or output control variable of the control algorithm model and the storage address of the input signal variable or output control variable of the control algorithm model after compression are encoded, and the encoded information is sent to the data receiving module of the calibration tool. Based on the data receiving module and the data decoding module of the calibration tool, the encoded information can be received, and the encoded information can be decoded to obtain the input signal of the control algorithm model. The storage address of the input signal variables or output control variables, the input signal variables or output control variables of the control algorithm model, and the storage address of the input signal variables or output control variables of the control algorithm model are provided to the user. During the operation of the chip, based on the chip's memory, data encoding system and data sending module, the calibration tool's memory, data decoding system and data receiving module, the input signal variables and output control variables of the control algorithm model inside the chip can be quickly and accurately collected, and the collected input signal variables and output control variables of the control algorithm model inside the chip can be provided to the user. It has low complexity and high efficiency, and can meet the needs of high-speed calibration scenarios.

[0120] In an optional implementation of the embodiment of the present invention, optionally, Figure 6 A schematic diagram of a data processing flow in a target chip provided by an embodiment of the present invention. The target chip includes two cores: a first core and a second core. The first core and the second core are Cortex-R52 cores. A core write operation interface MRP is provided in each core. The first core and the second core can send the original memory address and value corresponding to the memory write operation behavior to the data encoding system through the core write operation interface MRP after each memory write operation behavior. The core write operation interface MRP belongs to a parallel bus interface. The data encoding system can encode the original memory address and value corresponding to the memory write operation behavior of each core into a corresponding memory operation message, thereby encoding the memory write operation behavior into a data stream mode. The data encoding system can gather the memory operation messages corresponding to the memory write operation behavior of each core together through the trace funnel component in the target chip and cache them in the data cache area. The embedded trace FIFO trace buffer in the target chip can be used as a data cache area. The data cache area can avoid data loss caused by data peaks. The Embedded Trace Substrate (ETS) component in the target chip can convert the data stream consisting of memory operation messages corresponding to the memory write operation behavior of each core into the AXI-Stream format. The High Speed ​​Serial Trace Probe PHY component in the target chip can be used as a data transmission module. The data transmission module can package the memory operation messages into Aurora high-speed serial data packets and send them out of the chip.

[0121] Figure 7 Flow chart of a memory reconstruction method provided by an embodiment of the present invention. The method can be executed by the memory reconstruction system provided by the above embodiment of the present invention. Figure 7 As shown, the method of this embodiment specifically includes:

[0122] Step 201, after the data encoding system obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface, the filtering module determines whether the value is valid data. If so, the compression module compresses the original memory address according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address, and encodes the compressed memory address and the value according to the memory operation message encoding format through the encapsulation module to obtain a memory operation message, and caches the memory operation message to the data buffer.

[0123] Optionally, the data encoding system determines whether the value is valid data through a filtering module, including: the data encoding system determines whether the value is valid data according to a target memory address range, a target data source identifier and / or a target bus attribute through a filtering module.

[0124] Optionally, the data encoding system compresses the original memory address according to the previous original memory address through a compression module to obtain a compressed memory address corresponding to the original memory address, including: the data encoding system compares the bytes at the same position in the original memory address and the previous original memory address through a compression module to see whether they are the same, and determines the compressed memory address corresponding to the original memory address based on the comparison result.

[0125] Optionally, the data encoding system encodes the compressed memory address and the numerical value according to the memory operation message encoding format through the encapsulation module to obtain a memory operation message, including: the data encoding system performs the following operations through the encapsulation module: sorting each byte in the compressed memory address in order from low byte to high byte to obtain the encoded compressed memory address; determining the address length information of the encoded compressed memory address; sorting each byte in the numerical value in order from low byte to high byte to obtain the encoded numerical value; determining the data length information of the encoded numerical value; determining the identification information corresponding to the compressed memory address and the numerical value; splicing the identification information, the address length information, the data length information, the encoded compressed memory address and the encoded numerical value to obtain a memory operation message.

[0126] Step 202: The data sending module sends the message in the data buffer to the data receiving module.

[0127] Step 203: The data receiving module sends the received message to the data decoding system.

[0128] Step 204: The data decoding system decodes the received memory operation message according to the memory operation message encoding format to obtain a compressed memory address and a numerical value corresponding to the memory operation message, determines the original memory address corresponding to the compressed memory address according to the previous original memory address, stores the original memory address and the numerical value in the memory of the calibration tool and provides them to the target user.

[0129] Optionally, the data decoding system decodes the received memory operation message according to the memory operation message encoding format to obtain a compressed memory address and a numerical value corresponding to the memory operation message, including: the data decoding system determines the encoded compressed memory address and the encoded numerical value in the memory operation message according to the sorting order of each component in the memory operation message and the data length, and extracts the encoded compressed memory address and the encoded numerical value in the memory operation message; the data decoding system sorts each byte in the encoded compressed memory address in order from high byte to low byte to obtain the compressed memory address corresponding to the memory operation message; the data decoding system sorts each byte in the encoded numerical value in order from high byte to low byte to obtain the numerical value corresponding to the memory operation message.

[0130] Optionally, it also includes: after caching a preset number of memory operation messages, the data encoding system encodes the preset value and the data buffer identifier according to the synchronization information encoding format through the encapsulation module to obtain synchronization information, and caches the synchronization information to the data buffer.

[0131] Optionally, it also includes: a data decoding system decodes the received synchronization information according to the synchronization information encoding format to obtain a preset value and a data buffer identifier, and stores the preset value and the data buffer identifier in the memory of the calibration tool.

[0132] In the technical solution of the embodiment of the present invention, after the data encoding system obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface, the filtering module determines whether the value is valid data. If so, the compression module compresses the original memory address according to the previous original memory address to obtain the compressed memory address corresponding to the original memory address, and the encapsulation module encodes the compressed memory address and value according to the memory operation message encoding format to obtain the memory operation message, and caches the memory operation message to the data buffer; the data sending module sends the message in the data buffer to the data receiving module; the data receiving module sends the received message to the data decoding system; the data decoding system decodes the received memory operation message according to the memory operation message encoding format to obtain the compressed memory address and value corresponding to the memory operation message, determines the original memory address corresponding to the compressed memory address according to the previous original memory address, stores the original memory address and value in the memory of the calibration tool and provides them to the target user, and can filter out the input signal variables or output control variables of the control algorithm model and the input signal variables of the control algorithm model from the original memory address and value corresponding to the memory write operation behavior based on the data encoding system and the data sending module of the chip. Or the storage address of the output control variable, compress the storage address of the input signal variable or output control variable of the control algorithm model, encode the input signal variable or output control variable of the control algorithm model and the storage address of the input signal variable or output control variable of the compressed control algorithm model, and send the encoded information to the data receiving module of the calibration tool. Based on the data receiving module and the data decoding module of the calibration tool, the encoded information can be received, the encoded information can be decoded to obtain the input signal variable or output control variable of the control algorithm model and the storage address of the input signal variable or output control variable of the control algorithm model, and the input signal variable or output control variable of the control algorithm model and the storage address of the input signal variable or output control variable of the control algorithm model are provided to the user. During the operation of the chip, based on the chip memory, the data encoding system and the data sending module, the calibration tool memory, the data decoding system and the data receiving module, the input signal variables and output control variables of the control algorithm model inside the chip can be quickly and accurately collected, and the collected input signal variables and output control variables of the control algorithm model inside the chip are provided to the user. The complexity is low and the efficiency is high, which can meet the needs of high-speed calibration scenarios.

[0133] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0134] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory reconstruction system, characterized in that: include: Target chips and calibration tools; The target chip is provided with a memory, a data encoding system and a data sending module, and the calibration tool is provided with a memory, a data decoding system and a data receiving module; The data encoding system includes a kernel write operation interface, a filtering module, a compression module, a packaging module and a data buffer; After the data encoding system obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface, the filtering module determines whether the value is valid data. If so, the compression module compresses the original memory address according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address, and the encapsulation module encodes the compressed memory address and the value according to the memory operation message encoding format to obtain a memory operation message, and caches the memory operation message to the data buffer; The data sending module sends the message in the data buffer to the data receiving module; The data receiving module sends the received message to the data decoding system; The data decoding system decodes the received memory operation message according to the memory operation message encoding format to obtain the compressed memory address and numerical value corresponding to the memory operation message, determines the original memory address corresponding to the compressed memory address based on the previous original memory address, stores the original memory address and the numerical value in the memory of the calibration tool and provides them to the target user.

2. The memory reconstruction system according to claim 1, characterized in that: After caching a preset number of memory operation messages, the data encoding system encodes a preset value and a data buffer identifier according to a synchronization information encoding format through the encapsulation module to obtain synchronization information, and caches the synchronization information in the data buffer.

3. The memory reconstruction system according to claim 2, characterized in that: The data decoding system decodes the received synchronization information according to the synchronization information encoding format to obtain a preset value and a data buffer identifier, and stores the preset value and the data buffer identifier in the memory of the calibration tool.

4. A memory reconstruction method, applied to the memory reconstruction system as claimed in claim 1, characterized in that: include: After the data encoding system obtains the original memory address and value corresponding to the memory write operation behavior through the kernel write operation interface, the filtering module determines whether the value is valid data. If so, the compression module compresses the original memory address according to the previous original memory address to obtain a compressed memory address corresponding to the original memory address, and the encapsulation module encodes the compressed memory address and the value according to the memory operation message encoding format to obtain a memory operation message, and caches the memory operation message to the data buffer; The data sending module sends the message in the data buffer to the data receiving module; The data receiving module sends the received message to the data decoding system; The data decoding system decodes the received memory operation message according to the memory operation message encoding format to obtain the compressed memory address and numerical value corresponding to the memory operation message, determines the original memory address corresponding to the compressed memory address based on the previous original memory address, stores the original memory address and the numerical value in the memory of the calibration tool and provides them to the target user.

5. The memory reconstruction method according to claim 4, characterized in that: Also includes: After caching a preset number of memory operation messages, the data encoding system encodes the preset value and the data buffer identifier according to the synchronization information encoding format through the encapsulation module to obtain synchronization information, and caches the synchronization information in the data buffer.

6. The memory reconstruction method according to claim 5, characterized in that: Also includes: The data decoding system decodes the received synchronization information according to the synchronization information encoding format to obtain a preset value and a data buffer identifier, and stores the preset value and the data buffer identifier in the memory of the calibration tool.

7. The memory reconstruction method according to claim 4, characterized in that: The data encoding system determines whether the value is valid data through the filtering module, including: The data encoding system determines whether the value is valid data according to the target memory address range, the target data source identifier and / or the target bus attribute through the filtering module.

8. The memory reconstruction method according to claim 4, characterized in that: The data encoding system compresses the original memory address according to the last original memory address through the compression module to obtain a compressed memory address corresponding to the original memory address, including: The data encoding system compares the bytes at the same position in the original memory address and the previous original memory address through the compression module to see whether they are the same, and determines the compressed memory address corresponding to the original memory address based on the comparison result.

9. The memory reconstruction method according to claim 4, characterized in that: The data encoding system encodes the compressed memory address and the value according to the memory operation message encoding format through the encapsulation module to obtain a memory operation message, including: The data encoding system performs the following operations through the encapsulation module: Sort the bytes in the compressed memory address in order from low byte to high byte to obtain the encoded compressed memory address; Determining the encoded address length information of the compressed memory address; Sort the bytes in the value from low byte to high byte to obtain the encoded value; Determine the data length information of the encoded value; Determining identification information corresponding to the compressed memory address and the value; The identification information, the address length information, the data length information, the encoded compressed memory address and the encoded numerical value are concatenated to obtain a memory operation message.

10. The memory reconstruction method according to claim 4, characterized in that: The data decoding system decodes the received memory operation message according to the memory operation message encoding format to obtain a compressed memory address and a value corresponding to the memory operation message, including: The data decoding system determines the encoded compressed memory address and the encoded value in the memory operation message according to the sorting order of each component in the memory operation message and the data length, and extracts the encoded compressed memory address and the encoded value in the memory operation message; The data decoding system sorts the bytes in the encoded compressed memory address in order from high byte to low byte to obtain a compressed memory address corresponding to the memory operation message; The data decoding system sorts the bytes in the encoded value in order from high byte to low byte to obtain a value corresponding to the memory operation message.

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