Method for fusing section contours of multiple process files of three-dimensional integrated circuit chip

Abstract

A method for fusing section contours of multiple process files of a three-dimensional integrated circuit chip comprises the following steps: respectively generating a new data class of each process file according to input process files and fusion relation parameters; according to the new data class of each process file, generating a two-dimensional plane graph of the process file; respectively generating three-dimensional data corresponding to each process file according to the new data class of each process file and the two-dimensional plane graph, and converting the three-dimensional data into two-dimensional plane data; keeping the two-dimensional plane data of the lower-layer process file unchanged, overturning and translating the two-dimensional plane data of the upper-layer process file, and translating the two-dimensional plane data of the connecting-layer process file; connecting the two-dimensional plane data of the overturned and translated upper-layer process file, the connection-layer process file and the lower-layer process file according to a fusion connection relationship to obtain fused complete two-dimensional data; and displaying the complete two-dimensional data on an interface to obtain a multi-process file section contour fusion image.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit automated design, and in particular to a method for fusing cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip. Background Art

[0002] When performing layout design and parasitic parameter extraction in the field of integrated circuit design, it is necessary to master the connection relationship between each layer in the process file and the actual stacking effect of each film layer in the process file, so as to facilitate back-end layout design and circuit simulation. At present, in order to pursue a smaller chip size, chip developers and designers will use 3D IC (three-dimensional integrated circuit) chip stacking process, involving SOC (System on Chip, System on Chip), MEM (Memory Enhanced Processing, Memory Enhanced Computing Technology) and other different fab (fabrication, manufacturing process), and the integration between multiple different process chips. 3D IC platform is a new type of integrated circuit technology, which stacks multiple chips together and realizes interconnection through vertical connection. Therefore, when designing 3D IC chips, the fusion of cross-sectional profiles of multiple process files becomes an indispensable part of 3D IC stacking development and design. There is currently no method for realizing cross-sectional profile fusion for multiple process files. In this regard, the present invention proposes a method for fusion of cross-sectional profiles of multiple process files of three-dimensional integrated circuit chips. Summary of the invention

[0003] In order to solve the defects of the prior art, the purpose of the present invention is to provide a method for fusing the cross-sectional contours of multiple process files of a three-dimensional integrated circuit chip, which can enable 3D IC developers to see the actual effect of stacking multiple process files after 3D IC design before designing, thereby improving design efficiency and accelerating development iterations.

[0004] In order to achieve the above object, the method for fusing the cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip provided by the present invention comprises the following steps:

[0005] Generate new data classes for each process file according to the input process files and fusion relationship parameters; the fusion relationship parameters include the fusion connection relationship between the process files;

[0006] Generate a two-dimensional plane diagram of the process file according to the new data class of each process file;

[0007] According to the new data class of each process file and the two-dimensional plane diagram of the process file, three-dimensional data corresponding to each process file is generated respectively, and the three-dimensional data is converted into two-dimensional plane data;

[0008] Keep the two-dimensional plane data of the lower-layer process file unchanged, flip and translate the two-dimensional plane data of the upper-layer process file, translate the two-dimensional plane data of the connection-layer process file, and connect the flipped and translated two-dimensional plane data of the upper-layer process file, the connection-layer process file, and the lower-layer process file according to the fusion connection relationship to obtain the fused complete two-dimensional data;

[0009] The complete two-dimensional data is displayed on a computer interface to obtain a fusion diagram of the cross-sectional profile of a three-dimensional integrated circuit chip multi-process file.

[0010] Furthermore, the process files that need to be fused are stacked in the order of upper layer process file, connection layer process file, and lower layer process file from top to bottom; the fusion relationship parameters are used to specify the connection layer between the upper layer process file and the connection layer process file, and the connection layer between the connection layer process file and the lower layer process file; wherein, in the connection layer process file, at least one process film layer located in the upper half needs to be fused into a process film layer in the upper layer, and at least one process film layer located in the lower half needs to be fused into a process film layer in the lower layer process file.

[0011] Furthermore, the process file that needs to be merged also includes an epitaxial process file, and the process film layer in the epitaxial process file is a process film layer epitaxially customized in the connection layer process file, which needs to be merged into the conductor layer specified in the lower half of the lower layer process file; the connection layer layer between the epitaxial process file and the lower layer process file is specified by the fusion relationship parameters.

[0012] Furthermore, each of the process files contains process information of at least one process layer;

[0013] The process layer includes: a dielectric layer, a conductor layer and a through-hole layer;

[0014] The process information represents basic information of each process layer, including: process layer thickness, process layer size and connection relationship between process layers, wherein the connection relationship between the dielectric layer and the conductor layer is determined by the process layer sequence in the process file, and the connection relationship between the conductor layer and the through-hole layer is determined by the attributes of the through-hole layer in the process file, and the attributes of the through-hole layer include the upper connecting conductor layer and the lower connecting conductor layer in the through-hole layer definition in the process file.

[0015] Furthermore, the step of generating a new data class for each process file according to the input process file and fusion relationship parameters further includes:

[0016] The input process file is parsed and data processed, and the process information corresponding to the fusion connection relationship is added to the process information of the corresponding process file according to the fusion relationship parameters, so as to obtain a new data class for each process file, wherein the new data class contains the process information of the original process file and the process information added by the fusion connection relationship.

[0017] Furthermore, the step of generating a two-dimensional plan view of the process file according to the new data class of each process file further comprises:

[0018] Obtain process information after adding fusion connection relationship;

[0019] Establish a plane rectangular coordinate system, the plane rectangular coordinate system includes a first coordinate axis and a second coordinate axis, and the first coordinate axis is perpendicular to the second coordinate axis, wherein the plane where the plane rectangular coordinate system is located is a plane where each process layer extends; according to the process information and the relative position relationship between the process layers, determine the first coordinate on the first coordinate axis and the second coordinate on the second coordinate axis of each key point in the process layers; and generate a two-dimensional plane diagram according to the first coordinate and the second coordinate.

[0020] Furthermore, the step of generating three-dimensional data of each process file according to the new data class of each process file and the two-dimensional plane diagram, and converting the three-dimensional data into two-dimensional plane data further includes:

[0021] Obtain process information after adding fusion connection relationship;

[0022] According to the process information, a three-dimensional structure diagram composed of various process layers is constructed: a spatial rectangular coordinate system is established, and according to the basic information and stacking order of each process layer in the process information, the three-dimensional coordinates of the key points of each process layer in the spatial rectangular coordinate system are determined, and the three-dimensional coordinates of the key points of each process layer are marked in the spatial rectangular coordinate system. Each process layer is drawn in turn according to the three-dimensional coordinates to draw a three-dimensional structure diagram composed of various process layers;

[0023] The three-dimensional structure diagram is intercepted using a preset cross section to obtain a planar cross-sectional contour diagram, wherein the preset cross section is a cross section extending along the stacking direction of each process layer, and two-dimensional plane data is obtained from the planar cross-sectional contour diagram.

[0024] Furthermore, the step of generating three-dimensional data of each process file according to the new data class of each process file and the two-dimensional plane diagram, and converting the three-dimensional data into two-dimensional plane data further includes:

[0025] Obtain process information after adding fusion connection relationship;

[0026] Establishing a spatial rectangular coordinate system, the spatial rectangular coordinate system includes a third coordinate axis, the third coordinate axis is respectively perpendicular to the first coordinate axis and the second coordinate axis of the plane rectangular coordinate system, wherein the third coordinate axis extends along the stacking direction of each process layer; determining the third coordinate of each key point in each process layer on the third coordinate axis according to the thickness of each process layer; converting the two-dimensional plane diagram into the three-dimensional structure diagram according to the third coordinate;

[0027] The three-dimensional structure diagram is intercepted using a preset cross section to obtain a planar cross-sectional contour diagram, wherein the preset cross section is a cross section extending along the stacking direction of each process layer, and two-dimensional plane data is obtained from the planar cross-sectional contour diagram.

[0028] Furthermore, the step of generating a two-dimensional plan view of the process files according to the new data class of each process file is to generate a two-dimensional plan view containing all the process files or to generate a two-dimensional plane for each process file separately; in the two-dimensional plan view containing all the process files, the layers of each process file maintain consistent upper and lower widths.

[0029] The method for fusing the cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip provided by the present invention has the following beneficial effects compared with the prior art:

[0030] By specifying the connection relationship of multiple process files through fusion relationship parameters, the data of the process files after adding the fusion process information is obtained, the two-dimensional plane diagram corresponding to the process file is generated, and then the three-dimensional data corresponding to the process file is generated, and the three-dimensional data is converted into two-dimensional plane data. After flipping and translating the corresponding two-dimensional plane data, the complete two-dimensional data after fusion is obtained, and the complete two-dimensional data is displayed on the computer interface to obtain the cross-sectional contour fusion diagram of the multi-process files of the 3D IC chip, so that the designer can see the actual effect of the stacking of multiple process files after 3D IC design before designing, thereby improving design efficiency and accelerating development iterations.

[0031] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0033] Figure 1 It is a flow chart of a method for fusing cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to the first embodiment of the present invention;

[0034] Figure 2A schematic diagram of a connection layer designation interface according to the first embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the connection relationship defined in hb according to the first embodiment of the present invention;

[0036] Figure 4 A schematic diagram of a TSV process setting in HB according to Embodiment 1 of the present invention;

[0037] Figure 5 It is a schematic diagram of the fusion of cross-sectional profiles of multiple process files of a 3D IC according to an embodiment of the present invention;

[0038] Figure 6 is a schematic diagram of a cross-sectional profile of a top according to an embodiment of the present invention;

[0039] Figure 7 is a schematic cross-sectional profile diagram of hb according to an embodiment of the present invention;

[0040] Figure 8 is a schematic cross-sectional profile diagram of a bot according to an embodiment of the present invention;

[0041] Fig. 9 It is a schematic diagram of the fusion of cross-section profiles of multiple process files of a 3D IC chip according to the first embodiment of the present invention. DETAILED DESCRIPTION

[0042] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0043] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

[0044] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0045] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.

[0046] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0047] Example 1

[0048] In the development and design of integrated circuits, developers and designers are very concerned about the actual effect of the cross-sectional profile after stacking multiple process files of 3D IC chips. In an embodiment of the present invention, a method for fusing the cross-sectional profile of multiple process files of a three-dimensional integrated circuit chip is provided, comprising: inputting at least three process files and fusion relationship parameters to be fused, wherein the process files are divided into upper process files, connection layer process files and lower process files; generating new data classes for each process file according to the input process files and fusion relationship parameters, wherein the new data classes contain process information of the original process files and process information after the fusion connection relationship is added; generating an actual layout containing all process files according to the new data classes of each process file; generating three-dimensional data of each process file according to the new data classes of each process file and the actual layout, and converting the three-dimensional data into two-dimensional plane data; keeping the two-dimensional plane data of the lower process file unchanged, flipping and translating the two-dimensional plane data of the upper layer, translating the two-dimensional plane data of the connection layer process file, and connecting them together to obtain the complete two-dimensional data after fusion; displaying the complete two-dimensional data on a computer interface to obtain a fusion diagram of the cross-sectional profile of multiple process files of a 3D IC chip. The following takes an actual 3D IC multi-process file cross-section contour fusion as an example to illustrate the method for fusion of multi-process file cross-section contours of a three-dimensional integrated circuit chip of the present invention.

[0049] For the sake of convenience, in this example, the four process files that need to be merged are named top (upper layer process file), hb (connection layer process file), bot (lower layer process file), and tsv (epitaxial process file), and each process file contains process information of at least one process layer. Among them, when the process files are stacked, the stacking order of the four process files is top, hb, bot, and tsv from top to bottom; the placement of the process film layers of the four process files is: the process film layers of top and tsv are both inverted, and the process film layers of hb and bot are both forward. The fusion connection relationship of the four process files is: among the process film layers of hb, at least one process film layer located in the upper half needs to be merged into a process film layer in top; at least one process film layer located in the lower half needs to be merged into a process film layer in bot. The process film layer in tsv is a small number of film layers customized for epitaxy in hb, which needs to be merged into the conductor layer specified in the lower half of bot.

[0050] It should be noted that in some other exemplary embodiments of the present invention, the placement of the TSV may also be forward placement, which is determined by the film layer definition of the process file of the TSV. In addition, in some other exemplary embodiments, the forward or reverse placement of the above-mentioned process files is not limited to the method described in this example.

[0051] The process layer represents a semiconductor process film layer. In one example, each process layer includes a dielectric layer, a conductor layer and a via layer, wherein the conductor layer can also be called a metal layer. The process information represents the basic information of each process layer, and the process information of each process layer is obtained from the process file. In one example, the process information includes the process layer thickness, the process layer size and the connection relationship between the process layers, wherein the connection relationship between the dielectric layer and the conductor layer is determined by the process layer sequence in the process file, and the connection relationship between the conductor layer and the via layer is determined by the attributes of the via layer in the process file, and the attributes of the via layer include the upper connecting conductor layer and the lower connecting conductor layer in the via layer definition in the process file.

[0052] Figure 1 The flowchart of the method for merging the cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to the first embodiment of the present invention is as follows. Figure 1 The specific embodiments of the present invention are described in further detail.

[0053] In step 101, the process files and fusion relationship parameters to be fused are input.

[0054] In the embodiment of the present invention, the fusion connection relationship of specific layers between each process file is specified by the input fusion relationship parameters, including: the connection layer between top and hb, the connection layer between hb and bot, and the connection layer between bot and tsv. Figure 2 The "Top File" column indicates the acquisition path of the upper process file (top), the "Bottom File" column indicates the acquisition path of the lower process file (bot is the abbreviation of bottom) connected to the upper process file, the "TopMerge Layer in Hb" column indicates that the specified upper process file is to be merged with the process film layer (such as MET3) of the connection layer process file, the "Bottom Merge Layer in Hb" column indicates that the specified lower process file is to be merged with the process film layer (such as MET1) of the connection layer process file, the "Hb Merge Layer in Top" column indicates that the process film layer of the specified connection layer process file is connected to a metal layer (such as metal8) of the upper process file, and the "Hb Merge Layer in Bottom" column indicates that the process film layer of the connection layer process file is connected to a metal layer (such as metal8) of the lower process file.

[0055] The connection relationship between the process film layer in the epitaxial process file (tsv) and the lower process file (bot) is defined in the connection layer process file (hb). Figure 3 , here exemplarily defines that the process film layer BMT of the epitaxial process file (tsv) is connected to the metal layer metal3 in the lower process file (bot). In another example, refer to Figure 4 , you can also completely define the connection relationship between the process film layers that need to be merged in each process file in hb. Figure 5 The example is a graphical representation of the fusion of the cross-sectional profiles of the 3D IC multi-process files according to the above fusion connection relationship.

[0056] It should be noted that the embodiment of this article is an example of the fusion of multiple process files including TSV (epitaxial process file). In some other implementations, the fusion of multiple process files may not include TSV, then the fusion method for other process files (i.e., TOP, BOT and HB) remains unchanged.

[0057] In step 102, the input process files are parsed and data processed to generate new data classes for each process file.

[0058] In this embodiment, data processing refers to adding the process information corresponding to the fusion connection relationship to the process information of the corresponding process file according to the input fusion relationship parameters, and obtaining a new data class for each process file, that is, the new data class contains the process information of the original process file and the process information after the fusion connection relationship is added.

[0059] In step 103, according to the new data class of each process file, an actual layout including all process files is generated, that is, a two-dimensional plane diagram including all process files is generated. The purpose of generating an overall two-dimensional plane diagram is mainly to ensure that the layers of each process file in the layout maintain the same width from top to bottom.

[0060] In an embodiment of the present invention, the steps of generating a two-dimensional plane diagram are as follows: obtaining process information after adding a fusion connection relationship; establishing a plane rectangular coordinate system, the plane rectangular coordinate system includes a first coordinate axis and a second coordinate axis, and the first coordinate axis and the second coordinate axis are perpendicular, wherein the plane where the plane rectangular coordinate system is located is the plane where each process layer extends; according to the relative position relationship between the process information and the process layers, determining the first coordinate on the first coordinate axis and the second coordinate on the second coordinate axis of each key point in the process layer; according to the first coordinate and the second coordinate, generating the two-dimensional plane diagram. Among them, the key point of each process layer is a preset point, which is a point in each process layer that can reflect the position change, such as each vertex of each process layer. A two-dimensional plane diagram of all process files is generated according to the above method.

[0061] In step 104, four sets of three-dimensional data are generated according to the new data classes of the four process files and the actual layout, and the three-dimensional data are converted into two-dimensional plane data.

[0062] In this embodiment, the step of generating four sets of three-dimensional data according to the new data class of four process files and the actual layout refers to obtaining the process information after adding the fusion connection relationship; according to the process information, constructing a three-dimensional structure diagram composed of each process layer, and obtaining the three-dimensional data of each process file. Specifically, in any application with a three-dimensional mapping function, a spatial rectangular coordinate system is established, and the three-dimensional coordinates of the key points of each process layer in the spatial rectangular coordinate system are determined according to the basic information of each process layer in the process information and the expected stacking effect (stacking order), and the three-dimensional coordinates of the key points of each process layer are marked in the spatial rectangular coordinate system. Each process layer is drawn in turn according to the three-dimensional coordinates, and a three-dimensional structure diagram composed of each process layer can be drawn. Among them, the key points of each process layer are preset points, which are points in each process layer that can reflect the position change, such as each vertex of each process layer. The three-dimensional structure diagram can clearly show the actual stacking effect of each process layer, and the three-dimensional structure diagram can also be regarded as a simple actual layout.

[0063] In an embodiment of the present invention, the method of generating three-dimensional data may also be: determining the thickness of each process layer according to process information; converting the two-dimensional plane diagram into the three-dimensional structure diagram according to the thickness of each process layer. Specifically, a spatial rectangular coordinate system is established, the spatial rectangular coordinate system includes a third coordinate axis, the third coordinate axis is respectively perpendicular to the first coordinate axis and the second coordinate axis of the plane rectangular coordinate system, wherein the third coordinate axis extends along the stacking direction of each process layer; determining the third coordinate of each key point in each process layer on the third coordinate axis according to the thickness of each process layer; converting the two-dimensional plane diagram into the three-dimensional structure diagram according to the third coordinate, thereby obtaining the three-dimensional data of the process file.

[0064] In this embodiment, the step of converting three-dimensional data into two-dimensional plane data is: use a preset cross section to intercept the three-dimensional structure, and the obtained plane diagram is the contour diagram of each process layer on the preset cross section. The preset cross section is a cross section extending along the stacking direction of each process layer, that is, a straight cross section where the height of the three-dimensional structure geometry is located. For example, by using a preset cross section to intercept the above three-dimensional structure diagram, a cross-sectional contour diagram of the plane can be accurately and quickly generated, and two-dimensional plane data can be obtained from the cross-sectional contour diagram of the plane. The actual stacking effect of each process layer can be clearly seen from the cross-sectional contour diagram, which is used for design conception before designing the real layout. Reference Figures 6 to 8 , which correspond to the cross-sectional profile diagrams of the top, hb, and bot single process files, respectively. Figure 7 Only one process membrane layer in hb to be connected to the upper process file, one process membrane layer to be connected to the lower process file, and the process membrane layer in the connecting layer process file between the two are illustrated (only one layer is illustrated here, and there may actually be multiple layers).

[0065] In step 105, the two-dimensional plane data of bot remains unchanged, the two-dimensional plane data of top and tsv are flipped and translated, and the two-dimensional plane data of hb is translated, and connected together to obtain the fused complete two-dimensional data. That is, the flipped and translated two-dimensional plane data of top, hb, bot and tsv are connected according to the fusion connection relationship to obtain the fused complete two-dimensional data.

[0066] In the embodiment of the present invention, since the top process layer in the fusion of multiple process files needs to be connected backwards, the top two-dimensional plane data needs to be flipped when the fusion is performed. If the source of the two-dimensional plane data is the overall layout of each process file generated as described above, no translation is required, that is, the translation amount is zero; on the contrary, since the two-dimensional plane data generated by each process file respectively only know the fusion connection relationship and two-dimensional plane data of the process layers between different process files, when performing combined connection, the positions of the process layers may not correspond, so it is necessary to generate a connection after translation.

[0067] In step 106, the complete two-dimensional data is displayed on a computer interface to obtain a 3D IC chip multi-process file cross-sectional profile fusion diagram. Fig. 9 It is a schematic diagram of the fusion of cross-section profiles of multiple process files of a 3D IC chip according to the first embodiment of the present invention.

[0068] The method for fusing the cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip provided by the present invention solves the problem of fusing the cross-sectional profiles of multiple process files in 3DIC chip design, and enables 3D IC developers to see the actual effect of stacking multiple process files after 3DIC design before designing, which is beneficial to improving design efficiency and accelerating development iterations.

[0069] Example 2

[0070] The difference between this embodiment and Embodiment 1 is that after generating a new data class for each process file, a preliminary two-dimensional plane diagram corresponding to each process file is generated according to the new data class of each process file to display the two-dimensional data structure, and then according to the stacking order of each process file and the placement of the process film layer, the two-dimensional data of the corresponding process file is mirrored (i.e. flipped) and translated and combined together to obtain complete two-dimensional data.

[0071] In this embodiment, after inputting the original process file and the fusion connection relationship, each original process file is first parsed and data processed, that is, according to the fusion connection relationship defined in the process file or the fusion connection relationship specified by the input fusion relationship parameters, the process information setting corresponding to the fusion connection relationship is added to each process file, and then a new data class is generated for each process file, and then according to the new data class of each process file, a preliminary two-dimensional plane map corresponding to each process file is generated to display the two-dimensional data structure, and then according to the stacking order of each process file and the arrangement of the process film layers (that is, the placement method: the process film layers of top and tsv are placed inverted, and the process film layers of hb and bot are placed forward), the two-dimensional data of the corresponding process file is mirrored (that is, flipped) and translated and combined together to obtain complete two-dimensional data.

[0072] Among them, the process film layer of top is mirrored to obtain the process film layer structure after top is inverted, and the two-dimensional plane data of bot is kept unchanged. According to the fusion connection relationship, the position relationship between top and hb, bot, and tsv, the translation amount of top, hb, and tsv is determined, and the process film layer of the process file corresponding to the translation amount is translated, and the mirrored and translated top, translated hb and tsv are combined with bot to form a complete fused two-dimensional data. Finally, the final complete two-dimensional data is displayed on the interface program to obtain a schematic diagram of the cross-sectional contour fusion of multiple process files of the 3D IC chip.

[0073] Those skilled in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for merging the cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip, characterized in that: The following steps are involved: Generate new data classes for each process file according to the input process file and fusion relationship parameters; The fusion relationship parameters include the fusion connection relationship between the process files; Generate a two-dimensional plane diagram of the process file according to the new data class of each process file; According to the new data class of each process file and the two-dimensional plane diagram of the process file, three-dimensional data corresponding to each process file is generated respectively, and the three-dimensional data is converted into two-dimensional plane data; Keep the two-dimensional plane data of the lower-layer process file unchanged, flip and translate the two-dimensional plane data of the upper-layer process file, translate the two-dimensional plane data of the connection-layer process file, and connect the flipped and translated two-dimensional plane data of the upper-layer process file, the connection-layer process file, and the lower-layer process file according to the fusion connection relationship to obtain the fused complete two-dimensional data; The complete two-dimensional data is displayed on a computer interface to obtain a fusion diagram of the cross-sectional profile of a three-dimensional integrated circuit chip multi-process file.

2. The method for merging cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to claim 1, characterized in that: The input process files are stacked in the order of upper layer process files, connection layer process files, and lower layer process files from top to bottom; The fusion relationship parameters are used to specify the connection layers between the upper layer process file and the connection layer process file, and the connection layers between the connection layer process file and the lower layer process file; wherein, in the connection layer process file, at least one process film layer located in the upper half needs to be fused into a process film layer in the upper layer, and at least one process film layer located in the lower half needs to be fused into a process film layer in the lower layer process file.

3. The method for merging cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to claim 1, characterized in that: The process file that needs to be merged also includes an epitaxial process file. The process film layer in the epitaxial process file is a process film layer epitaxially customized in the connection layer process file, which needs to be merged into the conductor layer specified in the lower half of the lower layer process file; the connection layer between the epitaxial process file and the lower layer process file is specified by the fusion relationship parameters.

4. The method for merging cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to claim 1, characterized in that: Each of the process files contains process information of at least one process layer; The process layer includes: a dielectric layer, a conductor layer and a through-hole layer; The process information represents basic information of each process layer, including: process layer thickness, process layer size and connection relationship between process layers, wherein the connection relationship between the dielectric layer and the conductor layer is determined by the process layer sequence in the process file, and the connection relationship between the conductor layer and the through-hole layer is determined by the attributes of the through-hole layer in the process file, and the attributes of the through-hole layer include the upper connecting conductor layer and the lower connecting conductor layer in the through-hole layer definition in the process file.

5. The method for merging cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to claim 1, characterized in that: The step of generating a new data class for each process file according to the input process file and fusion relationship parameters further includes: The input process file is parsed and data processed, and the process information corresponding to the fusion connection relationship is added to the process information of the corresponding process file according to the fusion relationship parameters, so as to obtain a new data class for each process file, wherein the new data class contains the process information of the original process file and the process information added by the fusion connection relationship.

6. The method for merging cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to claim 1, characterized in that: The step of generating a two-dimensional plan view of the process file according to the new data class of each process file further comprises: Obtain process information after adding fusion connection relationship; Establish a plane rectangular coordinate system, the plane rectangular coordinate system includes a first coordinate axis and a second coordinate axis, and the first coordinate axis is perpendicular to the second coordinate axis, wherein the plane where the plane rectangular coordinate system is located is a plane where each process layer extends; according to the process information and the relative position relationship between the process layers, determine the first coordinate on the first coordinate axis and the second coordinate on the second coordinate axis of each key point in the process layers; and generate a two-dimensional plane diagram according to the first coordinate and the second coordinate.

7. The method for merging cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to claim 1, characterized in that: The step of generating three-dimensional data of each process file according to the new data class of each process file and the two-dimensional plane diagram, and converting the three-dimensional data into two-dimensional plane data, further comprises: Obtain process information after adding fusion connection relationship; According to the process information, a three-dimensional structure diagram composed of various process layers is constructed: a spatial rectangular coordinate system is established, and according to the basic information and stacking order of each process layer in the process information, the three-dimensional coordinates of the key points of each process layer in the spatial rectangular coordinate system are determined, and the three-dimensional coordinates of the key points of each process layer are marked in the spatial rectangular coordinate system. Each process layer is drawn in turn according to the three-dimensional coordinates to draw a three-dimensional structure diagram composed of various process layers; The three-dimensional structure diagram is intercepted using a preset cross section to obtain a planar cross-sectional contour diagram, wherein the preset cross section is a cross section extending along the stacking direction of each process layer, and two-dimensional plane data is obtained from the planar cross-sectional contour diagram.

8. The method for merging cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to claim 1, characterized in that: The step of generating three-dimensional data of each process file according to the new data class of each process file and the two-dimensional plane diagram, and converting the three-dimensional data into two-dimensional plane data, further comprises: Obtain process information after adding fusion connection relationship; Establishing a spatial rectangular coordinate system, the spatial rectangular coordinate system includes a third coordinate axis, the third coordinate axis is respectively perpendicular to the first coordinate axis and the second coordinate axis of the plane rectangular coordinate system, wherein the third coordinate axis extends along the stacking direction of each process layer; determining the third coordinate of each key point in each process layer on the third coordinate axis according to the thickness of each process layer; converting the two-dimensional plane diagram into the three-dimensional structure diagram according to the third coordinate; The three-dimensional structure diagram is intercepted using a preset cross section to obtain a planar cross-sectional contour diagram, wherein the preset cross section is a cross section extending along the stacking direction of each process layer, and two-dimensional plane data is obtained from the planar cross-sectional contour diagram.

9. The method for merging cross-sectional profiles of multiple process files of a three-dimensional integrated circuit chip according to claim 1, characterized in that: The step of generating a two-dimensional plane diagram of the process files according to the new data class of each process file is to generate a two-dimensional plane diagram containing all process files or to generate a two-dimensional plane diagram of each process file separately; In the two-dimensional plane diagram containing all the process files, the layers of each process file maintain the same width from top to bottom.

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