Method and device for generating chip bus layout mode, equipment and storage medium
By obtaining the bandwidth requirement information and physical design rules of the chip bus, the architecture and data flow direction of the chip bus layout are automatically determined, which solves the problem of low efficiency in generating chip bus layout methods in the existing technology and achieves efficient automated design.
Patent Information
- Application Number
- CN202411464192.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-01-21
AI Technical Summary
The existing chip bus layout methods are inefficient and require manual design, resulting in inefficient design.
By obtaining the bandwidth requirement information and physical design rules of the chip bus layout, the architecture and data flow direction of the chip bus layout are determined based on the preset initial bus, and the initial bus layout method is determined based on this information, and finally the chip bus layout results are generated.
The layout of automation generation chip bus is realized, the design efficiency is improved, and the chip bus layout that meets the needs of bandwidth and physical design rules can be quickly generated.
Smart Images
Figure CN119337808A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of chip technology, and in particular, relates to a method, device, equipment and storage medium for generating a chip bus layout. Background Art
[0002] The layout of the chip bus usually refers to the placement of the various devices that make up the chip bus and the connection relationship between the various devices. This layout has a great impact on the performance of the chip bus. Therefore, determining a reasonable chip bus layout helps improve the performance of the chip bus, and thus improve the performance of the chip.
[0003] Currently, the layout of chip buses is usually generated through manual design, which has the problem of low efficiency. Summary of the invention
[0004] In view of this, the embodiments of the present application provide a method, apparatus, device and storage medium for generating a chip bus layout to solve the technical problem that the existing method for generating a chip bus layout is inefficient.
[0005] In a first aspect, an embodiment of the present application provides a method for generating a chip bus layout, comprising:
[0006] Obtain bandwidth requirement information and physical design rules for chip bus layout;
[0007] According to the bandwidth requirement information and the physical design rules, determining the architecture and data flow of the chip bus layout based on a preset initial bus;
[0008] Determining a layout of the initial bus according to the bandwidth requirement information, the data flow direction, and the physical design rule;
[0009] A chip bus layout result is generated according to the layout mode of the initial bus and the architecture.
[0010] Optionally, the initial bus includes a plurality of pairs of bidirectional ring structures, each pair of the bidirectional ring structures includes two ring structures, each pair of the bidirectional ring structures includes a plurality of topological nodes, each of the topological nodes includes a plurality of cells, and each of the cells includes a plurality of standard cells;
[0011] The determining the layout of the initial bus according to the bandwidth requirement information, the data flow direction and the physical design rule includes:
[0012] The placement of each of the cells and each of the standard cells, the connection between each of the cells, and the connection between each of the standard cells are determined according to the bandwidth requirement information, the data flow direction, and the physical design rules.
[0013] Optionally, after generating a chip bus layout result according to the layout mode of the initial bus and the architecture, the method further includes:
[0014] Performing timing analysis on the chip bus layout result;
[0015] If it is determined according to the result of the timing analysis that the chip bus layout result will cause a timing violation caused by noise, the relative positions of each clockwise node standard cell and each counterclockwise node standard cell in each standard cell of the chip bus layout result are adjusted until the chip bus layout result does not cause a timing violation caused by noise;
[0016] If it is determined based on the result of the timing analysis that the chip bus layout result will cause timing violations due to excessive routing density, the volume of each cell of the chip bus layout result is increased and the routing spacing of the chip bus layout result is increased until the chip bus layout result does not cause timing violations due to excessive routing density.
[0017] Optionally, also include:
[0018] After the result of the timing analysis meets the preset requirements, judging whether the chip bus layout result will cause congestion of the wiring according to the physical design rules;
[0019] If the chip bus layout result will cause congestion in the wiring, the volume of each cell of the chip bus layout result is increased and the wiring spacing of the chip bus layout result is improved until the chip bus layout result does not cause congestion in the wiring.
[0020] Optionally, also include:
[0021] After determining that the chip bus layout result will not cause congestion of the wiring, determining whether the chip bus layout result will cause a voltage drop risk;
[0022] If the chip bus layout result will cause a voltage drop risk, the volume of each unit cell of the chip bus layout result is increased and the spacing between each standard unit is increased until the chip bus layout result does not cause a voltage drop risk.
[0023] Optionally, before generating a chip bus layout result according to the layout mode of the initial bus and the architecture, the method further includes:
[0024] Determining an expected area of the architecture based on the bandwidth requirement information;
[0025] The architecture is adjusted according to the expected area.
[0026] Optionally, determining the expected area of the architecture according to the bandwidth requirement information includes:
[0027] Determining the required quantity of the standard units according to the bandwidth requirement information;
[0028] The expected area is determined according to the number of metal layers and the manufacturing process of the chip corresponding to the chip bus, as well as the required quantity.
[0029] In a second aspect, an embodiment of the present application provides a device for generating a chip bus layout, including:
[0030] An information acquisition unit, used to acquire bandwidth requirement information and physical design rules of chip bus layout;
[0031] A first determining unit, configured to determine the architecture and data flow of the chip bus layout based on a preset initial bus according to the bandwidth requirement information and the physical design rule;
[0032] A second determining unit, configured to determine a layout of the initial bus according to the bandwidth requirement information, the data flow direction, and the physical design rule;
[0033] The bus layout generation unit is used to generate a chip bus layout result according to the layout mode of the initial bus and the architecture.
[0034] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the processor implements each step of the method for generating a chip bus layout as described in any one of the first aspects above.
[0035] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements each step in the method for generating a chip bus layout as described in any one of the first aspects above.
[0036] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on a terminal device, the terminal device executes each step of the method for generating a chip bus layout as described in any one of the first aspects above.
[0037] The method, device, equipment and storage medium for generating a chip bus layout provided by the embodiments of the present application have the following beneficial effects:
[0038] In the method for generating a chip bus layout provided in an embodiment of the present application, the bandwidth requirement information and physical design rules of the chip bus layout are first obtained, and then the architecture and data flow of the chip bus layout are determined based on the preset initial bus according to the bandwidth requirement information and the physical design rules, and then the layout of the initial bus is determined according to the bandwidth requirement information, the data flow and the physical design rules, and finally the chip bus layout result is generated according to the layout and architecture of the initial bus. By the method of the present application, the layout of the chip bus can be automatically generated by simply inputting the bandwidth requirement information and the physical design rules of the chip bus layout into the electronic device. Compared with the method of generating the chip bus layout by artificial design, the present application can improve the efficiency of generating the layout of the chip bus. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0040] Figure 1 A flowchart of a method for generating a chip bus layout provided in an embodiment of the present application;
[0041] Figure 2 A schematic diagram of a typical bidirectional ring topology bus structure provided in an embodiment of the present application;
[0042] Figure 3 A schematic diagram of the structure of an initial bus provided in an embodiment of the present application;
[0043] Figure 4 A schematic diagram of the structure of a device for generating a chip bus layout mode provided in an embodiment of the present application;
[0044] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0045] It should be noted that the terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. In the description of the embodiments of the present application, unless otherwise specified, "multiple" refers to two or more than two, and "at least one", "one or more" refers to one, two or more. The terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, it is defined that the "first" and "second" features can explicitly or implicitly include one or more of the features.
[0046] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.
[0047] The execution subject of the method for generating a chip bus layout provided in an embodiment of the present application can be an electronic device, and the electronic device can include but is not limited to an apparatus for generating a chip bus layout, a mobile phone, a tablet computer, a laptop computer, a desktop computer and other devices.
[0048] The method for generating a chip bus layout provided in an embodiment of the present application can be applied to any application scenario that requires generating a chip bus layout. For example, when it is necessary to generate a chip bus layout, the steps of the method for generating a chip bus layout provided in an embodiment of the present application can be performed by an electronic device, so that the chip bus layout can be automatically generated by the electronic device.
[0049] See also Figure 1 , Figure 1 A flowchart of a method for generating a chip bus layout is provided in an embodiment of the present application. The method for generating a chip bus layout may include S101 to S104, which are described in detail as follows:
[0050] In S101, bandwidth requirement information and physical design rules of chip bus layout are obtained.
[0051] In an embodiment of the present application, when it is necessary to generate a chip bus layout, the user can input the bandwidth requirement information and physical design rules of the chip bus layout into an electronic device so that the electronic device can obtain the bandwidth requirement information and physical design rules of the chip bus layout.
[0052] The bandwidth requirement information of the chip bus layout can be used to describe the user's bandwidth requirement for the chip bus. In other words, the bandwidth requirement described by the bandwidth requirement information can be achieved after the chip bus layout is completed according to the obtained chip bus layout result.
[0053] The physical design rules of the chip bus layout may be rules that the user specifies, based on actual requirements and relevant knowledge of the chip bus layout, that the electronic device needs to comply with when generating a layout of the chip bus.
[0054] In S102 , according to the bandwidth requirement information and the physical design rules, the architecture and data flow of the chip bus layout are determined on the basis of the preset initial bus.
[0055] In an embodiment of the present application, after obtaining the bandwidth requirement information and physical design rules of the chip bus layout, the electronic device can determine the architecture and data flow of the chip bus layout based on a preset initial bus according to the bandwidth requirement information and the physical design rules.
[0056] The preset initial bus can be set according to actual needs. The following describes an initial bus provided in an embodiment of the present application.
[0057] See also Figure 2 , Figure 2 The schematic diagram of a typical bidirectional ring topology bus provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, a typical bidirectional ring topology bus may include four topology nodes (Node1, Node2, Node3 and Node4), each of which may transmit data via a ring structure. The data flows of the two ring structures included in the typical bidirectional ring topology bus are counterclockwise and clockwise, respectively.
[0058] The initial bus provided by this application is improved on the basis of the typical bidirectional ring topology bus. Figure 3 , Figure 3 A schematic diagram of the structure of an initial bus provided in an embodiment of the present application.
[0059] like Figure 3As shown, the initial bus may include several pairs of bidirectional ring structures, each of which may include two ring structures, and the data flow directions of the two ring structures included in each bidirectional ring structure may be counterclockwise and clockwise, respectively, and each pair of bidirectional ring structures may include several topological nodes ( Figure 3 Each pair of bidirectional ring structures shown includes 4 topological nodes), and each topological node may include several cells, and each cell may include several standard cells.
[0060] Based on this, electronic devices can obtain bandwidth demand information and physical design rules. Figure 3 Based on the initial bus shown, determine the architecture and data flow of the chip bus layout.
[0061] Among them, the architecture of the chip bus layout may include but is not limited to the number of bidirectional ring structures, the distance between each pair of bidirectional ring structures, the distance between two ring structures in a bidirectional ring structure, the number of topological nodes included in each pair of bidirectional ring structures, the number of cells included in each topological node, the number of standard cells included in each cell, and the total number of standard cells, etc.
[0062] The data flow direction of the chip bus layout may include but is not limited to the data flow direction of two ring structures in the bidirectional ring structure, and the data flow direction between each pair of bidirectional ring structures.
[0063] Specifically, the electronic device can generate a chip bus layout architecture and data flow that can simultaneously meet the bandwidth demand information and the physical design rules through a preset architecture generation algorithm and a data flow generation algorithm according to the bandwidth demand information and the physical design rules. The specific architecture generation algorithm and the data flow generation algorithm can be set according to actual needs and are not specifically limited here.
[0064] In a possible implementation, after the electronic device determines the architecture of the chip bus layout and before step S104, the electronic device may adjust the architecture of the chip bus layout through steps a to b.
[0065] In step a, the expected area of the architecture is determined based on the bandwidth requirement information.
[0066] In this implementation, the electronic device can determine the required number of standard units based on the bandwidth requirement information, and then determine the expected area of the chip bus layout architecture based on the number of metal layers and manufacturing process of the chip corresponding to the chip bus and the required number of standard units.
[0067] Specifically, the height of the array for placing each component in the corresponding chip can be determined according to the manufacturing process of the corresponding chip, and then the total number of winding resources can be determined according to the height of the array for placing each component in the corresponding chip and the number of metal layers of the corresponding chip. Then, the number of winding resources required for the power module and the clock module in the corresponding chip can be subtracted from the total number of winding resources to obtain the number of effective winding resources. Finally, the expected area of the architecture of the chip bus layout can be determined based on the number of effective winding resources, the number of standard units that can be placed on each winding, and the required number of standard units.
[0068] In step b, the architecture is adjusted according to the expected area.
[0069] In this implementation, after determining the expected area of the architecture, it can be determined whether the expected area of the architecture meets the preset requirements. If the expected area of the architecture does not meet the preset requirements, the architecture can be adjusted until the expected area of the architecture meets the preset requirements.
[0070] In S103, the layout of the initial bus is determined according to the bandwidth requirement information, data flow direction and physical design rules.
[0071] In the embodiment of the present application, after determining the architecture and data flow of the chip bus layout based on the preset initial bus, the electronic device can also determine the architecture and data flow of the chip bus layout based on the bandwidth requirement information, data flow and physical design rules. Figure 3 Based on the initial bus shown, determine the layout of the initial bus.
[0072] Specifically, the electronic device can determine the placement of each unit cell and each standard unit in the initial bus, the connection relationship between each unit cell in the initial bus, and the connection relationship between each standard unit in the initial bus according to bandwidth demand information, data flow direction, and physical design rules.
[0073] In S104, a chip bus layout result is generated according to the layout mode and architecture of the initial bus.
[0074] In an embodiment of the present application, after determining the layout mode of the initial bus and the architecture of the chip bus layout, the electronic device can use the determined layout mode of the initial bus and the architecture of the chip bus layout together as the chip bus layout result.
[0075] In a possible implementation, after the chip bus layout result is generated, the timing violation that may be caused by the chip bus layout result may be eliminated through steps c to e, as described in detail as follows:
[0076] In step c, a timing analysis is performed on the chip bus layout result.
[0077] In this implementation, after generating the chip bus layout result, the electronic device may perform a timing analysis on the generated chip bus layout result to obtain a timing analysis result.
[0078] In step d, if it is determined based on the results of the timing analysis that the chip bus layout result will cause timing violations caused by noise, the relative positions of each clockwise node standard cell and each counterclockwise node standard cell in each standard cell of the chip bus layout result are adjusted until the chip bus layout result does not cause timing violations caused by noise.
[0079] In this implementation, after obtaining the result of the timing analysis, the electronic device can determine whether the chip bus layout result will cause a timing violation caused by noise according to the result of the timing analysis.
[0080] If it is determined that the chip bus layout result will cause timing violations caused by noise, the relative positions of each clockwise node standard cell and each counterclockwise node standard cell in each standard cell of the chip bus layout result can be adjusted until the chip bus layout result does not cause timing violations caused by noise.
[0081] Among them, the clockwise node standard cell is a standard cell whose corresponding ring structure has a clockwise data flow direction; the counterclockwise node standard cell is a standard cell whose corresponding ring structure has a counterclockwise data flow direction.
[0082] In step e, if it is determined based on the results of the timing analysis that the chip bus layout result will cause timing violations due to excessive routing density, the volume of each cell of the chip bus layout result is increased and the routing spacing of the chip bus layout result is increased until the chip bus layout result does not cause timing violations due to excessive routing density.
[0083] In this implementation, after obtaining the result of the timing analysis, the electronic device can determine whether the chip bus layout result will cause a timing violation caused by excessive routing density based on the result of the timing analysis.
[0084] If it is determined that the chip bus layout result will cause timing violations due to excessive routing density, the volume of each cell of the chip bus layout result can be increased and the routing spacing of the chip bus layout result can be increased until the chip bus layout result does not cause timing violations due to excessive routing density.
[0085] After the electronic device determines that the chip bus layout result will neither cause timing violations caused by noise nor timing violations caused by excessive routing density, the electronic device can determine that the result of the timing analysis of the chip bus layout result meets the preset requirements.
[0086] After determining that the result of the timing analysis of the chip bus layout result meets the preset requirements, the electronic device can eliminate the congestion phenomenon of the wiring that may be caused by the chip bus layout result through steps f to g, as detailed below:
[0087] In step f, after the result of the timing analysis meets the preset requirements, it is determined whether the chip bus layout result will cause congestion in the wiring according to the physical design rules.
[0088] In this implementation, after determining that the result of the timing analysis meets the preset requirements, the electronic device can also determine whether the chip bus layout result will cause congestion in the wiring according to the physical design rules.
[0089] In step g, if the chip bus layout result will cause congestion in the wiring, the volume of each cell of the chip bus layout result can be increased and the wiring spacing of the chip bus layout result can be increased until the chip bus layout result does not cause congestion in the wiring.
[0090] In this implementation, if the electronic device determines that the chip bus layout result will cause congestion in the winding, the volume of each cell of the chip bus layout result can be increased and the routing spacing of the chip bus layout result can be increased until the chip bus layout result does not cause congestion in the winding.
[0091] After the electronic device determines that the chip bus layout result will not cause congestion of the winding, the electronic device can eliminate the voltage drop risk that may be caused by the chip bus layout result through steps h to i, as detailed below:
[0092] In step h, after determining that the chip bus layout result will not cause congestion of the wiring, it is determined whether the chip bus layout result will cause a voltage drop risk.
[0093] In this implementation, after determining that the chip bus layout result will not cause congestion in the wiring, the electronic device can determine whether the chip bus layout result will cause a voltage drop risk through power reliability analysis.
[0094] In step i, if the chip bus layout result will cause voltage drop risk, the volume of each unit cell of the chip bus layout result is increased and the spacing between each standard unit is increased until the chip bus layout result does not cause voltage drop risk.
[0095] In this implementation, if it is determined that the chip bus layout result will cause voltage drop risk, the electronic device can increase the volume of each cell of the chip bus layout result and increase the spacing between each standard cell until the chip bus layout result does not cause voltage drop risk.
[0096] After adjusting the chip bus layout result to ensure that the chip bus layout result will neither cause timing violations nor cause congestion in the windings nor cause voltage drop risks, the adjusted chip bus layout result can be determined as the final chip bus layout result, thereby obtaining a chip bus layout method based on the initial bus.
[0097] It can be seen from the above that in the method for generating a chip bus layout provided in an embodiment of the present application, the bandwidth requirement information and physical design rules of the chip bus layout are first obtained, and then the architecture and data flow of the chip bus layout are determined based on the preset initial bus according to the bandwidth requirement information and the physical design rules, and then the layout of the initial bus is determined according to the bandwidth requirement information, the data flow and the physical design rules, and finally the chip bus layout result is generated according to the layout and architecture of the initial bus. Through the method of the present application, the layout of the chip bus can be automatically generated by simply inputting the bandwidth requirement information and the physical design rules of the chip bus layout into the electronic device. Compared with the method of generating the chip bus layout by artificial design, the present application can improve the efficiency of generating the layout of the chip bus.
[0098] Based on the method for generating a chip bus layout provided in the above embodiment, the present application further provides a device for generating a chip bus layout to implement the above method embodiment, please refer to Figure 4 , Figure 4 A schematic diagram of a structure of a device for generating a chip bus layout mode provided in an embodiment of the present application. Figure 4 As shown, the device 40 for generating a chip bus layout may include: an information acquisition unit 41, a first determination unit 42, a second determination unit 43, and a bus layout generation unit 44. Among them:
[0099] The information acquisition unit 41 is used to acquire bandwidth requirement information and physical design rules of chip bus layout.
[0100] The first determining unit 42 is used to determine the architecture and data flow of the chip bus layout based on the preset initial bus according to the bandwidth requirement information and the physical design rules.
[0101] The second determining unit 43 is used to determine the layout of the initial bus according to the bandwidth requirement information, data flow direction and physical design rules.
[0102] The bus layout generation unit 44 is used to generate a chip bus layout result according to the layout mode and architecture of the initial bus.
[0103] Optionally, the initial bus includes several pairs of bidirectional ring structures, each pair of bidirectional ring structures includes two ring structures, each pair of bidirectional ring structures includes several topological nodes, each topological node includes several cells, and each cell includes several standard cells; the second determining unit 43 is specifically used to:
[0104] According to the bandwidth requirement information, data flow direction and physical design rules, the placement of each unit cell and each standard unit, the connection method between each unit cell and the connection method between each standard unit are determined.
[0105] Optionally, the device 40 for generating a chip bus layout mode may further include a timing checking unit, wherein:
[0106] The timing check unit is specifically used for:
[0107] Perform timing analysis on chip bus layout results;
[0108] If it is determined according to the result of the timing analysis that the chip bus layout result will cause a timing violation caused by noise, then the relative positions of each clockwise node standard cell and each counterclockwise node standard cell in each standard cell of the chip bus layout result are adjusted until the chip bus layout result does not cause a timing violation caused by noise;
[0109] If it is determined based on the results of the timing analysis that the chip bus layout result will cause timing violations due to excessive routing density, the volume of each cell of the chip bus layout result is increased and the routing spacing of the chip bus layout result is increased until the chip bus layout result does not cause timing violations due to excessive routing density.
[0110] Optionally, the device 40 for generating a chip bus layout mode may further include a congestion phenomenon checking unit, wherein:
[0111] The congestion phenomenon detection unit is specifically used for:
[0112] After the timing analysis results meet the preset requirements, determine whether the chip bus layout results will cause congestion in the routing according to the physical design rules;
[0113] If the chip bus layout result will cause congestion in the wiring, the volume of each cell of the chip bus layout result will be increased and the wiring spacing of the chip bus layout result will be increased until the chip bus layout result will not cause congestion in the wiring.
[0114] Optionally, the device 40 for generating a chip bus layout mode may further include a voltage drop risk checking unit, wherein:
[0115] The voltage drop risk check unit is specifically used for:
[0116] After determining that the chip bus layout result will not cause congestion of the wiring, determine whether the chip bus layout result will cause voltage drop risk;
[0117] If the chip bus layout result will cause a voltage drop risk, the volume of each unit cell of the chip bus layout result will be increased and the spacing between each standard unit will be increased until the chip bus layout result will not cause a voltage drop risk.
[0118] Optionally, the device 40 for generating a chip bus layout mode may further include an architecture adjustment unit, wherein:
[0119] The architecture adjustment unit is specifically used to:
[0120] Based on the bandwidth requirement information, determine the expected area of the architecture;
[0121] Adjust the architecture according to the expected area.
[0122] Optionally, the architecture adjustment unit is specifically used for:
[0123] Determine the required number of standard units based on bandwidth requirement information;
[0124] Determine the expected area based on the number of metal layers and manufacturing process of the chip corresponding to the chip bus, as well as the required quantity.
[0125] See also Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 5 As shown, the electronic device 5 provided in this embodiment may include: a processor 50, a memory 51, and a computer program 52 stored in the memory 51 and executable on the processor 50, such as a program corresponding to the method for generating a chip bus layout. When the processor 50 executes the computer program 52, the steps in the above-mentioned method embodiment for generating a chip bus layout are implemented, such as Figure 1 Alternatively, when the processor 50 executes the computer program 52, the functions of each module / unit in the above-mentioned device for generating a chip bus layout are realized, for example Figure 4 The functions of the units 41 to 44 are shown.
[0126] Exemplarily, the computer program 52 may be divided into one or more modules / units, one or more modules / units are stored in the memory 51, and are executed by the processor 50 to complete the present application. The one or more modules / units may be a series of computer program instruction segments that can complete specific functions, and the instruction segments are used to describe the execution process of the computer program 52 in the electronic device 5. For example, the computer program 52 may be divided into an information acquisition unit 41, a first determination unit 42, a second determination unit 43, and a bus layout generation unit 44. For the specific functions of each unit, please refer to Figure 4 The relevant descriptions in the corresponding embodiments are not repeated here.
[0127] Those skilled in the art will understand that Figure 5 The electronic device 5 is merely an example and does not constitute a limitation on the electronic device 5 , and may include more or less components than those shown in the figure, or may combine certain components, or may have different components.
[0128] The processor 50 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.
[0129] The memory 51 may be an internal storage unit of the electronic device 5, such as a hard disk or memory of the electronic device 5. The memory 51 may also be an external storage device of the electronic device 5, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, or a flash card, etc., equipped on the electronic device 5. Further, the memory 51 may also include both an internal storage unit of the electronic device 5 and an external storage device. The memory 51 is used to store computer programs and other programs and data required by the electronic device. The memory 51 may also be used to temporarily store data that has been output or is to be output.
[0130] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional units is used as an example for illustration. In actual applications, the above-mentioned function allocation can be completed by different functional units as needed, that is, the internal structure of the device for generating the chip bus layout mode can be divided into different functional units to complete all or part of the functions described above. The functional units in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.
[0131] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.
[0132] An embodiment of the present application provides a computer program product. When the computer program product is executed on a terminal device, the terminal device implements the steps in the above-mentioned various method embodiments.
[0133] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0134] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0135] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.
Claims
1. A method for generating a chip bus layout, characterized in that: include: Obtain bandwidth requirement information and physical design rules for chip bus layout; According to the bandwidth requirement information and the physical design rules, determining the architecture and data flow of the chip bus layout based on a preset initial bus; Determining a layout of the initial bus according to the bandwidth requirement information, the data flow direction, and the physical design rule; A chip bus layout result is generated according to the layout mode of the initial bus and the architecture.
2. The method according to claim 1, characterized in that The initial bus includes a plurality of pairs of bidirectional ring structures, each pair of the bidirectional ring structures includes two ring structures, each pair of the bidirectional ring structures includes a plurality of topological nodes, each of the topological nodes includes a plurality of cells, and each of the cells includes a plurality of standard cells; The determining the layout of the initial bus according to the bandwidth requirement information, the data flow direction and the physical design rule includes: The placement of each of the cells and each of the standard cells, the connection between each of the cells, and the connection between each of the standard cells are determined according to the bandwidth requirement information, the data flow direction, and the physical design rules.
3. The method according to claim 2, characterized in that After generating a chip bus layout result according to the layout mode of the initial bus and the architecture, the method further includes: Performing timing analysis on the chip bus layout result; If it is determined according to the result of the timing analysis that the chip bus layout result will cause a timing violation caused by noise, then the relative positions of each clockwise node standard cell and each counterclockwise node standard cell in each of the standard cells of the chip bus layout result are adjusted until the chip bus layout result does not cause a timing violation caused by noise; If it is determined based on the result of the timing analysis that the chip bus layout result will cause timing violations due to excessive routing density, the volume of each cell of the chip bus layout result is increased and the routing spacing of the chip bus layout result is increased until the chip bus layout result does not cause timing violations due to excessive routing density.
4. The method according to claim 3, characterized in that Also includes: After the result of the timing analysis meets the preset requirements, judging whether the chip bus layout result will cause congestion of the wiring according to the physical design rules; If the chip bus layout result will cause congestion in the wiring, the volume of each cell of the chip bus layout result is increased and the wiring spacing of the chip bus layout result is improved until the chip bus layout result does not cause congestion in the wiring.
5. The method according to claim 4, characterized in that Also includes: After determining that the chip bus layout result will not cause congestion of the wiring, determining whether the chip bus layout result will cause a voltage drop risk; If the chip bus layout result will cause a voltage drop risk, the volume of each unit cell of the chip bus layout result is increased and the spacing between each standard unit is increased until the chip bus layout result does not cause a voltage drop risk.
6. The method according to any one of claims 2 to 5, characterized in that: Before generating a chip bus layout result according to the layout mode of the initial bus and the architecture, the method further includes: Determining an expected area of the architecture based on the bandwidth requirement information; The architecture is adjusted according to the expected area.
7. The method according to claim 6, characterized in that The determining, according to the bandwidth requirement information, an expected area of the architecture includes: Determining the required quantity of the standard units according to the bandwidth requirement information; The expected area is determined according to the number of metal layers and the manufacturing process of the chip corresponding to the chip bus, as well as the required quantity.
8. A device for generating a chip bus layout, characterized in that: include: An information acquisition unit, used to acquire bandwidth requirement information and physical design rules of chip bus layout; A first determining unit, configured to determine the architecture and data flow of the chip bus layout based on a preset initial bus according to the bandwidth requirement information and the physical design rule; A second determining unit, configured to determine a layout of the initial bus according to the bandwidth requirement information, the data flow direction, and the physical design rule; The bus layout generation unit is used to generate a chip bus layout result according to the layout mode of the initial bus and the architecture.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the processor implements the steps in the method for generating a chip bus layout as described in any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, each step of the method for generating a chip bus layout as claimed in any one of claims 1 to 7 is implemented.