Chip verification method and chip verification device

Abstract

The present application provides a chip verification method and a chip verification device, and relates to the field of chip verification technology. The present application can adaptively generate multiple random input parameter test cases based on the test item content customized by the user considering various factors to cover the chips to be mass-produced, and perform chip data analysis based on the chip test result data according to user needs, so as to quickly derive the optimal input parameter distribution data required for the chips to be mass-produced when they are formally mass-produced, so as to quickly find the optimal input settings of the chips in terms of safety, environmental protection and energy saving, and effectively reduce the relevant requirements for chip testers and reduce the manpower loss in the chip verification process.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a chip verification method and a chip verification device. Background Art

[0002] With the rapid development of chip design and manufacturing technology, the complexity of chip functions is increasing, and safety, environmental protection and energy saving are becoming more and more important for chips. As a result, more and more factors need to be considered in various stages such as chip tuning and mass production preparation. This has brought more severe challenges to the verification work before chip mass production. The corresponding verification work has put forward higher requirements on the professional skills and knowledge reserves of the operators, and the time required to test the ideal working parameters of the chip is also getting longer and longer.

[0003] However, the paradox is that the current chip launch cycle is required to be shorter and shorter, and there is a huge gap in chip R&D talent, which often leads to the inability to find the optimal input settings for the chip in terms of safety, environmental protection and energy saving within the specified time during chip verification (for example, measuring the optimal input parameter value range of the chip in the minimum power consumption state, the most stable output state or the minimum noise state). Usually, it can only be barely adjusted to the function pass state within the specified time. At the same time, during the preparation for chip mass production, experienced testing experts are required to manually set the chip mass production test items, chip input parameter coverage and chip input parameter values ​​based on their experience. Junior technicians cannot complete the chip verification work. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a chip verification method and a chip verification device, which can adaptively generate multiple random input parameter test cases based on the test item content customized by the user considering various factors, to cover the chips to be mass-produced, and perform chip data analysis based on the chip test result data according to user needs, so as to quickly derive the optimal input parameter distribution data required for the chips to be mass-produced when they are formally mass-produced, so as to quickly find the optimal input settings of the chip in terms of safety, environmental protection and energy saving, while effectively reducing the relevant requirements for chip testers and reducing manpower loss in the chip verification process.

[0005] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, the present application provides a chip verification method, the method comprising:

[0007] Obtaining a test item definition file configured by a user for a chip to be mass-produced, wherein the test item definition file includes a value distribution range and a value coverage of at least one chip input parameter matching a target test item parameter type, and a chip output parameter type matching the target test item parameter type;

[0008] Generate multiple random input parameter test cases according to the numerical coverage and the numerical distribution range of the at least one chip input parameter, and obtain chip test result data corresponding to the chip output parameter type after the multiple random input parameter test cases are respectively run on multiple sample chips of the chip to be mass-produced;

[0009] Perform data preprocessing on the acquired chip test result data to obtain and display the result data to be analyzed;

[0010] Based on the result data to be analyzed and the multiple random input parameter test cases, chip data analysis is performed on the chip to be mass-produced according to the analysis objectives specified by the user, and the expected distribution results of at least one chip input parameter of the chip to be mass-produced when achieving the analysis objectives are obtained and displayed.

[0011] In an optional embodiment, the step of generating a plurality of random input parameter test cases according to the numerical coverage and the numerical distribution range of the at least one chip input parameter includes:

[0012] For each chip input parameter of the at least one chip input parameter, randomly select a plurality of input parameter values ​​within a value distribution range of the chip input parameter according to the value coverage rate;

[0013] Test case combinations are performed on multiple input parameter values ​​corresponding to each of the at least one chip input parameters to obtain multiple random input parameter test cases, wherein each random input parameter test case is composed of an input parameter value of each of the at least one chip input parameters.

[0014] In an optional embodiment, the step of obtaining chip test result data corresponding to the chip output parameter type after the multiple random input parameter test cases are respectively run on multiple sample chips of the chip to be mass-produced includes:

[0015] For each random input parameter test case in the multiple random input parameter test cases, calling the chip hardware test platform to respectively supply input parameters to multiple sample chips of the chip to be mass-produced according to the random input parameter test case;

[0016] Collecting actual chip output parameter values ​​corresponding to the chip output parameter type of each of the plurality of sample chips under the action of the random input parameter test case;

[0017] The actual chip output parameter values ​​of each of the plurality of sample chips corresponding to the plurality of random input parameter test cases are sorted to obtain the chip test result data.

[0018] In an optional embodiment, the step of performing data preprocessing on the acquired chip test result data to obtain and display the result data to be analyzed includes:

[0019] For each sample chip, according to the actual chip output parameter values ​​of the sample chip under the action of the multiple random input parameter test cases, a sample stability analysis is performed on the sample chip to obtain a stability analysis result of the sample chip;

[0020] When the corresponding stability analysis results indicate that the sample chip is running stably, data cleaning is performed on the actual chip output parameter values ​​of the sample chip under the action of the multiple random input parameter test cases, and the valid output parameter values ​​of the sample chip corresponding to the multiple random input parameter test cases in the result data to be analyzed are obtained and displayed.

[0021] In an optional embodiment, the step of performing chip data analysis on the chip to be mass-produced according to the result data to be analyzed and the multiple random input parameter test cases according to the analysis target specified by the user, and obtaining and displaying the expected distribution result of the at least one chip input parameter of the chip to be mass-produced when achieving the analysis target includes:

[0022] Constructing an eye diagram according to the result data to be analyzed and the multiple random input parameter test cases to obtain multiple test eye diagrams of the chip to be mass-produced during the verification process;

[0023] Based on the multiple test eye diagrams, construct an initial eye diagram tuning parameter set associated with the analysis target, and iteratively optimize the initial eye diagram tuning parameter set based on a particle swarm optimization algorithm to obtain an optimal eye diagram tuning parameter set required to achieve the analysis target;

[0024] According to the parameter conversion relationship between the expected distribution parameter type pointed to by the analysis target and the eye diagram tuning parameter type, the expected distribution result of the at least one chip input parameter matching the optimal eye diagram tuning parameter set is calculated and displayed.

[0025] In an optional implementation, the step of iteratively optimizing the initial eye diagram tuning parameter set based on a particle swarm optimization algorithm to obtain an optimal eye diagram tuning parameter set required to achieve the analysis objective includes:

[0026] For each iterative optimization operation in the multiple iterative optimization operations, the actual inertia weight of the iterative optimization operation is calculated according to the preset weight parameter, and the ideal particle movement speed set of the iterative optimization operation is calculated according to the actual inertia weight and the eye diagram tuning parameter set to be output and the actual particle movement speed set determined in the previous iterative optimization operation;

[0027] According to the ideal particle movement speed set and the eye diagram tuning parameter set to be output of the previous iterative optimization operation, the eye diagram tuning parameter set to be output that meets the eye diagram tuning parameter constraint conditions of this iterative optimization operation is calculated, and the actual particle movement speed set required for calculating the corresponding eye diagram tuning parameter set to be output in this iterative optimization operation;

[0028] Calculate the eye diagram tuning index of this iterative optimization operation according to the eye diagram tuning parameter set to be outputted in this iterative optimization operation, and update the individual optimal tuning parameter and the group optimal tuning parameter of this iterative optimization operation according to the eye diagram tuning index of this iterative optimization operation;

[0029] Check whether the eye diagram tuning index of this iterative optimization operation meets the iterative optimization end condition;

[0030] If it is detected that the eye diagram tuning index of this iterative optimization operation meets the iterative optimization end condition, the eye diagram tuning parameter set to be outputted by this iterative optimization operation is directly used as the optimal eye diagram tuning parameter set, otherwise the next iterative optimization operation is performed.

[0031] In an optional implementation, the step of calculating the eye diagram tuning parameter set to be output that satisfies the eye diagram tuning parameter constraint condition for the current iterative optimization operation according to the ideal particle movement speed set and the eye diagram tuning parameter set to be output for the previous iterative optimization operation comprises:

[0032] The ideal particle moving speed set is used as the target particle moving speed set, and the target eye diagram tuning parameter set for this iterative optimization operation is calculated according to the target particle moving speed set and the eye diagram tuning parameter set to be outputted in the previous iterative optimization operation;

[0033] Detecting whether the target eye diagram tuning parameter set meets the eye diagram tuning parameter constraint condition;

[0034] If it is detected that the target eye diagram tuning parameter set satisfies the eye diagram tuning parameter constraint condition, the target eye diagram tuning parameter set is used as the eye diagram tuning parameter set to be output for this iterative optimization operation; otherwise, the target particle movement speed set is subjected to a speed progressive modification, and then based on the target particle movement speed set after the speed progressive modification, the step of calculating the target eye diagram tuning parameter set for this iterative optimization operation is jumped to continue execution.

[0035] In an optional embodiment, when the analysis target is optimal input parameter coverage, the expected distribution parameter type is input parameter coverage, the eye diagram tuning parameter type is eye diagram offset, and the eye diagram tuning indicator is eye diagram overlap opening;

[0036] When the analysis target is the optimal chip mass production input parameter value, the expected distribution parameter type is the parameter value interval of each of the at least one chip input parameters, the eye diagram tuning parameter type is the eye diagram mask vertex coordinates, and the eye diagram tuning indicator is the eye diagram area covered by the eye diagram mask.

[0037] In an optional embodiment, the method further comprises:

[0038] In response to the user's definition file adjustment operation based on the result data to be analyzed and / or the expected distribution result of the at least one chip input parameter, the chip input parameter composition, the numerical distribution range and / or the numerical coverage of each chip input parameter in the test item definition file are updated, and the step of generating multiple random input parameter test cases based on the numerical coverage and the numerical distribution range of the at least one chip input parameter is jumped to continue execution.

[0039] In a second aspect, the present application provides a chip verification device, including a processor and a memory, wherein the memory stores a computer program that can be executed by the processor, and the processor can execute the computer program to implement the chip verification method described in any one of the aforementioned embodiments.

[0040] In this case, the beneficial effects of the embodiments of the present application may include the following:

[0041] After obtaining the test item definition file configured by the user for the chip to be mass-produced, the present application will generate multiple random input parameter test cases according to the numerical distribution range and numerical coverage of at least one chip input parameter that matches the target test item parameter type included in the test item definition file, and obtain chip test result data corresponding to the chip output parameter type after the multiple random input parameter test cases are respectively run on multiple sample chips of the chip to be mass-produced, and then perform data preprocessing on the obtained chip test result data to obtain and display the result data to be analyzed, and then perform analysis on the chip to be mass-produced according to the analysis target specified by the user based on the result data to be analyzed and the multiple random input parameter test cases. The chip performs chip data analysis to obtain and display the expected distribution result of at least one chip input parameter of the chip to be mass-produced when achieving the analysis goal, thereby adaptively generating multiple random input parameter test cases based on the test item content customized by the user considering various factors to perform coverage testing on the chip to be mass-produced, and performing chip data analysis based on the chip test result data according to user needs to quickly derive the optimal input parameter distribution data required for the chip to be mass-produced when it is officially mass-produced, so as to quickly find the optimal input settings of the chip in terms of safety, environmental protection and energy saving, while effectively reducing the relevant requirements for chip testers and reducing manpower loss in the chip verification process.

[0042] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A schematic diagram of the composition of a chip verification device provided in an embodiment of the present application;

[0045] Figure 2 One of the flowcharts of the chip verification method provided in the embodiment of the present application;

[0046] Figure 3 for Figure 2 A schematic flow chart of the sub-steps included in step S230;

[0047] Figure 4 for Figure 2 A schematic flow chart of the sub-steps included in step S240;

[0048] Figure 5 for Figure 4 Schematic diagram of the step execution flow of sub-step S242 in FIG.

[0049] Figure 6 for Figure 5 Schematic diagram of the step execution flow of sub-step S2422 in FIG.

[0050] Figure 7 The second flowchart of the chip verification method provided in the embodiment of the present application.

[0051] Icons: 10 - chip verification device; 11 - memory; 12 - processor; 13 - communication unit. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0053] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0054] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0055] In the description of the present application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0056] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0057] In addition, in the description of the present application, it is understood that the relational terms such as the term "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood by specific circumstances.

[0058] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0059] Please refer to Figure 1 , Figure 1 : is a schematic diagram of the composition of the chip verification device 10 provided in the embodiment of the present application. In the embodiment of the present application, the chip verification device 10 can be connected to the user terminal held by the chip tester in communication, so as to obtain the test item content customized by the chip tester for the chip to be mass-produced considering various factors, and adaptively generate multiple random input parameter test cases to cover the chip to be mass-produced, and then perform chip data analysis based on the chip test result data according to the data analysis purpose specified by the chip tester, so as to quickly derive the optimal input parameter distribution data required for the chip to be mass-produced when it is formally mass-produced, so as to facilitate the chip tester to observe the optimal input parameter distribution data derived by the chip verification device 10 through the user terminal, and there is no need for the chip tester to manually find the optimal input settings of the chip to be mass-produced in terms of safety, environmental protection and energy saving, so as to achieve the effect of quickly finding the optimal input settings of the chip in terms of safety, environmental protection and energy saving, and effectively reduce the relevant requirements for chip testers, and reduce the manpower loss in the chip verification process. Among them, the chip verification device 10 can be a computer device independent of the user terminal, and the computer device can be but is not limited to a personal computer, a cloud server, a laptop computer, a tablet computer, etc.; the chip verification device 10 can also be a physical hardware device integrated with the user terminal.

[0060] In this embodiment, the test item content may include, but is not limited to: one or several target IP (Intellectual Property) cores that need to be verified on the mass-produced chip specified by the chip tester, the test item parameter type composition that needs to be tested and verified for one or several target IP cores specified by the chip tester (for example, any one or more combinations of test item parameter types such as minimum power consumption, most stable output, and minimum noise), the numerical distribution range of at least one chip input parameter configured by the chip tester considering various factors associated with the test item parameter type composition, the numerical coverage of each chip input parameter specified by the chip tester in the chip verification process, and the chip output parameter type that needs to be collected and is associated with the test item parameter type composition specified by the chip tester. The expected distribution parameter types of the optimal input parameter distribution data corresponding to different data analysis purposes are different. For example, when the data analysis purpose is "optimal input parameter coverage", the corresponding expected distribution parameter type is "input parameter coverage (that is, the sampling coverage degree of the corresponding chip input parameter when numerical sampling is performed within the numerical distribution range)"; when the data analysis purpose is "optimal chip mass production input parameter value", the corresponding expected distribution parameter type is "the parameter value range of each of the at least one chip input parameter".

[0061] In the embodiment of the present application, the chip verification device 10 may include a memory 11, a processor 12, and a communication unit 13. The memory 11, the processor 12, and the communication unit 13 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, the memory 11, the processor 12, and the communication unit 13 may be electrically connected to each other via one or more communication buses or signal lines.

[0062] In the embodiment of the present application, the memory 11 may be, but not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc. The memory 11 is used to store a computer program, and the processor 12 may execute the computer program accordingly after receiving an execution instruction.

[0063] In the embodiment of the present application, the processor 12 may be an integrated circuit chip with signal processing capability. The processor 12 may be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc., which may implement or execute the disclosed methods, steps, and logic block diagrams in the embodiment of the present application.

[0064] In the embodiment of the present application, the communication unit 13 is used to establish a communication connection between the chip verification device 10 and other electronic devices through a network, and to send and receive data through the network, wherein the network includes a wired communication network and a wireless communication network. For example, the chip verification device 10 can obtain the test item content customized by the chip tester for the chip to be mass-produced through the communication unit 13, and display at least one of the generated multiple random input parameter test cases, the chip test result data of the multiple random input parameter test cases tested by the chip to be mass-produced, and the optimal input parameter distribution data required for the chip to be mass-produced when it is officially mass-produced to the user terminal held by the chip tester through the communication unit 13.

[0065] In an embodiment of the present application, the chip verification device 10 may pre-store a specific computer program related to the chip verification function in the memory 11, and by driving the processor 12 to execute the specific computer program stored in the memory 11, based on the test item content customized by the user (i.e., chip tester) considering various factors, adaptively generate multiple random input parameter test cases to cover the mass-produced chips, and perform chip data analysis based on the chip test result data according to user needs (i.e., the data analysis purpose specified by the chip tester) to quickly derive the optimal input parameter distribution data required for the mass-produced chips when they are officially mass-produced, so as to quickly find the optimal input settings of the chip in terms of safety, environmental protection, and energy saving, while effectively reducing the relevant requirements for chip testers and reducing manpower loss in the chip verification process.

[0066] Understandably, Figure 1 The block diagram shown is only a schematic diagram of a composition of the chip verification device 10. The chip verification device 10 may also include Figure 1More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0067] In this application, in order to ensure that the chip verification device 10 can perform adaptive coverage testing and chip data analysis on the chips to be mass-produced according to the chip verification requirements of the chip testers, so as to quickly find the optimal input settings of the chips to be mass-produced in terms of safety, environmental protection and energy saving, and effectively reduce the manpower loss and talent requirements required for chip verification operations, the embodiment of this application provides a chip verification method applied to the aforementioned chip verification device 10 to achieve the aforementioned purpose. The chip verification method provided by this application is described in detail below.

[0068] Please refer to Figure 2 , Figure 2 It is one of the flow charts of the chip verification method provided in the embodiment of the present application. In the embodiment of the present application, Figure 2 The chip verification method shown may include steps S210 to S240.

[0069] Step S210, obtaining a test item definition file configured by the user for the chip to be mass-produced, the test item definition file including a numerical distribution range and numerical coverage of at least one chip input parameter matching the target test item parameter type, and a chip output parameter type matching the target test item parameter type.

[0070] In this embodiment, the test item definition file is used to represent the test item content customized by the user (i.e., chip tester) for one or several target IP cores of the chip to be mass-produced after considering various influencing factors in terms of safety, environmental protection, and energy saving during the chip verification process; the target test item parameter type is the test item parameter type composition specified by the user for the one or several target IP cores that need to be tested and verified.

[0071] The chip verification device 10 can construct a test item file database at the memory 11, and store the test item definition file configured by any chip tester for any chip to be mass-produced through the test item file database, so that the chip tester can search for the stored test item definition file that he wants to browse by accessing the test item file database. Therefore, when the chip verification device 10 obtains an externally input test item definition file, it will store the test item definition file in the test item file database, and establish an association relationship between the test item definition file and the chip to be mass-produced at the test item file database, so as to facilitate the chip tester to search for the test item definition file later.

[0072] Step S220, generating multiple random input parameter test cases based on the numerical coverage and the numerical distribution range of at least one chip input parameter, and obtaining chip test result data corresponding to the chip output parameter type after the multiple random input parameter test cases are run on multiple sample chips of the chip to be mass-produced.

[0073] In this embodiment, the chip verification device 10 can pre-construct a test case generator in the memory 11, and generate multiple random input parameter test cases for the chip to be mass-produced based on the numerical coverage specified by the user and the numerical distribution range of at least one chip input parameter by calling the test case generator, wherein each random input parameter test case is composed of a random input parameter value of the at least one chip input parameter that is within the corresponding numerical distribution range, and the multiple random input parameter test cases collaboratively cover the numerical distribution range of the at least one chip input parameter according to the numerical coverage.

[0074] Then, the chip verification device 10 can perform coverage testing on the chip to be mass-produced by applying the generated multiple random input parameter test cases to multiple sample chips of the chip to be mass-produced for trial operation, and then obtain chip test result data of the chip to be mass-produced by collecting actual chip output parameter values ​​of the multiple sample chips of the chip to be mass-produced under different random input parameter test cases.

[0075] In addition, the chip verification device 10 can also call a visualization component that matches the input parameter test case, and display the generated multiple random input parameter test cases to the user through the user terminal, so that the user can test the chip to be mass-produced by himself according to the displayed multiple random input parameter test cases, and then receive the chip test result data imported by the user through the user terminal.

[0076] It can be understood that the chip verification device 10 can construct a test case database and a test result database in the memory 11, so as to store the multiple random input parameter test cases generated through the test case database, and store the chip test result data of any chip to be mass-produced when trial-running the multiple random input parameter test cases through the test result database, so that chip testers can find the stored input parameter test cases and stored chip test result data they want to browse by accessing the test case database and the test result database.

[0077] Therefore, after the chip verification device 10 generates multiple random input parameter test cases for the chip to be mass-produced and obtains the chip test result data of the chip to be mass-produced under the action of the multiple random input parameter test cases, the multiple random input parameter test cases will be stored in the test case database, and an association relationship between the multiple random input parameter test cases and the chip to be mass-produced will be established in the test case database, so as to facilitate the chip tester to subsequently search for input parameter test cases. At the same time, the chip test result data corresponding to the chip to be mass-produced and the multiple random input parameter test cases will also be stored in the test result database, so as to facilitate the chip tester to subsequently search for test result data.

[0078] Optionally, in an implementation of this embodiment, the step of “generating multiple random input parameter test cases according to the numerical coverage and the numerical distribution range of at least one chip input parameter” may include:

[0079] For each chip input parameter of the at least one chip input parameter, randomly select a plurality of input parameter values ​​within a value distribution range of the chip input parameter according to the value coverage rate;

[0080] Test case combinations are performed on the multiple input parameter values ​​corresponding to each of the at least one chip input parameters to obtain multiple random input parameter test cases, wherein each random input parameter test case is composed of an input parameter value of each of the at least one chip input parameter, and an input parameter value of the same chip input parameter may appear in multiple random input parameter test cases.

[0081] Optionally, in an implementation of this embodiment, the step of "obtaining chip test result data corresponding to chip output parameter types after multiple random input parameter test cases are respectively run on multiple sample chips of chips to be mass-produced" may include:

[0082] For each random input parameter test case in the multiple random input parameter test cases, calling the chip hardware test platform to respectively supply input parameters to multiple sample chips of the chip to be mass-produced according to the random input parameter test case;

[0083] Collecting actual chip output parameter values ​​corresponding to the chip output parameter type of each of the plurality of sample chips under the action of the random input parameter test case;

[0084] The actual chip output parameter values ​​of each of the plurality of sample chips corresponding to the plurality of random input parameter test cases are sorted to obtain the chip test result data.

[0085] Step S230, preprocessing the acquired chip test result data to obtain and display the result data to be analyzed.

[0086] In this embodiment, the chip verification device 10 can search for a batch of chip test result data or multiple batches of chip test result data that match the chip to be mass-produced from the test result database, and perform data preprocessing on the found chip test result data to filter out invalid data from the found chip test result data to obtain the result data to be analyzed. At this time, the visualization component that matches the chip output parameter type can be called to display the result data to be analyzed to the user through the user terminal. Among them, the same batch of chip test result data corresponds to multiple random input parameter test cases generated in the same batch; the visualization component that matches the chip output parameter type can be associated with the visualization component that matches the input parameter test case, so as to improve the visualization effect of the chip verification operation.

[0087] Optionally, in an implementation of this embodiment, the chip verification device 10 may directly perform data cleaning on the found chip test result data to obtain the result data to be analyzed.

[0088] Optionally, see Figure 3 , Figure 3 yes Figure 2 In another implementation of this embodiment, to ensure that the result data to be analyzed can represent the effective output parameter data when the chip to be mass-produced is running stably, the step S230 may include sub-steps S231 to S232.

[0089] Sub-step S231, for each sample chip, according to the actual chip output parameter values ​​of the sample chip under the action of the multiple random input parameter test cases, a sample stability analysis is performed on the sample chip to obtain a stability analysis result of the sample chip.

[0090] In this embodiment, the chip verification device 10 can determine whether the corresponding sample chip can currently operate stably, that is, whether the corresponding sample chip is currently a good product, by performing a sample stability analysis on the sample chip.

[0091] Sub-step S232, when the corresponding stability analysis results indicate that the sample chip is running stably, data cleaning is performed on the actual chip output parameter values ​​of the sample chip under the action of multiple random input parameter test cases, and the effective output parameter values ​​of the sample chip corresponding to the multiple random input parameter test cases in the result data to be analyzed are obtained and displayed.

[0092] In this embodiment, the chip verification device 10 only cleans the chip output parameter data for the sample chips that are judged to be stable in operation (i.e., good products), ensuring that the final result data to be analyzed is composed of the effective output parameter values ​​of the good sample chips under different random input parameter test cases, thereby ensuring that the final result data to be analyzed can represent the effective output parameter data of the chip to be mass-produced when it is running stably.

[0093] Therefore, the present application can ensure that the result data to be analyzed finally obtained can represent the effective output parameter data when the chip to be mass-produced is running stably by executing the above sub-steps S231 to S232.

[0094] Step S240, based on the result data to be analyzed and multiple random input parameter test cases, chip data analysis is performed on the chip to be mass-produced according to the analysis target specified by the user, and the expected distribution result of at least one chip input parameter of the chip to be mass-produced when achieving the analysis target is obtained and displayed.

[0095] In this embodiment, after determining the result data to be analyzed and multiple random input parameter test cases matching the result data to be analyzed, the chip verification device 10 will respond to the analysis target designation operation made by the user through the user terminal, call the optimal input parameter distribution data solver adapted to the specified analysis target, and perform chip data analysis based on the result data to be analyzed and the multiple random input parameter test cases, so as to quickly derive the optimal input parameter distribution data (i.e., the expected distribution result of at least one chip input parameter when achieving the analysis target) of the chip to be mass-produced during formal mass production to ensure that multiple finished chips are running stably, thereby quickly finding the effect of the optimal input setting of the chip in terms of safety, environmental protection, and energy saving, and effectively reducing the manpower loss and talent requirements required for chip verification operations. Among them, as the analysis target specified by the user is different, the expected distribution parameter type of the corresponding expected distribution result will also be different.

[0096] Optionally, see Figure 4 , Figure 4 yes Figure 2 Schematic diagram of the flow of sub-steps included in step S240. In the embodiment of the present application, step S240 may include sub-steps S241 to S243 to achieve different optimal input settings for different analysis objectives.

[0097] Sub-step S241 , constructing an eye diagram according to the result data to be analyzed and a plurality of random input parameter test cases, to obtain a plurality of test eye diagrams of the chip to be mass-produced during the verification process.

[0098] In this embodiment, in the early stage of chip mass production, it is usually necessary to find an input parameter setting range in which multiple finished chips can operate stably. In order to find this input parameter setting range, it is necessary to generate an eye diagram based on the result data to be analyzed corresponding to the chip to be mass-produced and multiple random input parameter test cases, and by superimposing the multiple test eye diagrams generated, find the best eye diagram overlap range of these multiple test eye diagrams, and then calculate the optimal input parameter distribution data that meets the analysis objectives specified by the user based on the found best eye diagram overlap range.

[0099] Sub-step S242, based on multiple test eye diagrams, construct an initial eye diagram tuning parameter set associated with the analysis target, and iteratively optimize the initial eye diagram tuning parameter set based on the particle swarm optimization algorithm to obtain the optimal eye diagram tuning parameter set required to achieve the analysis target.

[0100] In this embodiment, the existing method of finding the best eye diagram overlap interval usually requires the chip tester to manually display multiple test eye diagrams on the oscilloscope, and adjust the eye diagram position of each test eye diagram by pressing various buttons on the oscilloscope, so that the multiple eye diagrams reach the maximum overlap rate after the position is moved, and then determine the best eye diagram overlap interval by naked eye observation. It is worth noting that this method is time-consuming and laborious, and it is difficult to find the real best eye diagram overlap interval, resulting in the final determination of the optimal input parameter distribution data to substantially guarantee that the multiple finished chips of the mass-produced chip can run stably after mass production.

[0101] In this case, the present application can use a particle swarm optimization algorithm to perform real-time tuning on multiple test eye diagrams based on the eye diagram characteristics, so as to accurately find the optimal eye diagram overlap interval of multiple test eye diagrams, and achieve the optimal eye diagram tuning parameter set for the optimal eye diagram overlap interval, thereby saving a lot of working time of chip testers.

[0102] In this embodiment, as different analysis targets are different, the eye diagram tuning parameter types corresponding to the eye diagram tuning parameter sets are different from each other, and the eye diagram tuning indicators associated with the eye diagram tuning parameter sets are also different from each other.

[0103] Take the analysis target "optimal input parameter coverage" as an example to illustrate: eye opening is an important indicator of eye diagram quality. In the process of real-time tuning of the multiple test eye diagrams, not only is the eye opening of each test eye diagram required to be as large as possible, but more importantly, the eye opening of the overlapping area of ​​the multiple test eye diagrams after superposition is required to be as large as possible. However, as the number of eye diagrams increases, it is difficult for the superimposed multiple test eye diagrams to have a large eye overlap opening (i.e., the eye opening of the eye overlap area). Therefore, in the real-time tuning of the eye diagram, the center position of a single test eye diagram can be adjusted by adjusting the eye offset to ensure that the eye overlap opening of the eye overlap area between the multiple test eye diagrams after final superposition is the largest, and the maximum overlap rate of the multiple test eye diagrams related to the input parameter coverage is obtained. Therefore, when the analysis target is "optimal input parameter coverage", the expected distribution parameter type associated with the analysis target is "input parameter coverage", the eye diagram tuning parameter type of the corresponding eye diagram tuning parameter set is "eye diagram offset", and the eye diagram tuning indicator associated with the eye diagram tuning parameter type is "eye diagram overlap opening". At this time, the initial eye diagram tuning parameter set is composed of the initial eye diagram offsets of each of the multiple test eye diagrams, and the optimal eye diagram tuning parameter set is composed of the optimal eye diagram offsets of each of the multiple test eye diagrams when achieving the analysis target.

[0104] Take the analysis target "optimal chip mass production input parameter value" as an example to illustrate: eye diagram mask test is an important inspection test in the early stage of chip mass production. It can effectively improve the chip mass production yield by selecting a suitable eye diagram mask. The eye diagram mask can be represented by a mask vertex coordinate set. During the real-time eye diagram tuning process, the eye diagram mask needs to ensure that the eye area of ​​the eye diagram overlapping area covered by it is maximized to find the optimal eye diagram overlap interval between multiple test eye diagrams. Therefore, when the analysis target is "the best chip mass production input parameter value", the expected distribution parameter type associated with the analysis target is "the parameter value range of each of the at least one chip input parameter", and the eye diagram tuning parameter type corresponding to the eye diagram tuning parameter set is "the eye diagram mask vertex coordinates for the eye diagram overlapping area", and the eye diagram tuning indicator associated with the eye diagram tuning parameter type is "the eye diagram area covered by the eye diagram mask in the eye diagram overlapping area". At this time, the initial eye diagram tuning parameter set is the initial eye diagram mask vertex coordinate set for the eye diagram overlapping area after the multiple test eye diagrams are superimposed, and the optimal eye diagram tuning parameter set is the optimal eye diagram mask vertex coordinate set when achieving the analysis target.

[0105] Optionally, see Figure 5 , Figure 5 yes Figure 4Schematic diagram of the step execution flow of sub-step S242 in the embodiment of the present application, the step of "iteratively optimizing the initial eye diagram tuning parameter set based on the particle swarm optimization algorithm to obtain the optimal eye diagram tuning parameter set required to achieve the analysis goal" in the sub-step S242 may include sub-steps S2421 to S2426 to achieve the automatic iterative optimization effect of the optimal eye diagram tuning parameter set.

[0106] Sub-step S2421, for each iterative optimization operation in multiple iterative optimization operations, calculate the actual inertia weight of this iterative optimization operation according to the preset weight parameters, and calculate the ideal particle movement speed of this iterative optimization operation according to the actual inertia weight and the eye diagram tuning parameter set to be output and the actual particle movement speed set determined by the previous iterative optimization operation.

[0107] In this embodiment, the preset weight parameters may include information such as the maximum weight value, the minimum weight value, and the maximum number of iteration optimizations; the chip verification device 10 may use any one of the inertia weight calculation strategies such as the typical linear decreasing strategy and the linear differential decreasing strategy to calculate the actual inertia weight of each iteration optimization operation in multiple iteration optimization operations. For the dth iteration optimization operation, the ideal particle moving speed set V d It can be calculated using the following formula:

[0108]

[0109] in, The ideal particle moving speed set V used to represent the dth iteration optimization operation d The flying speed of the i-th particle in d It is used to represent the actual inertia weight of the d-th iteration optimization operation, The actual particle moving speed set V used to represent the d-1th iteration optimization operation d-1 The flying speed of the i-th particle in 1 is the first learning factor used to represent the particle's self-awareness ability, c 2 is the second learning factor used to represent the global cognitive ability of particles, and A random number used to represent the dth iteration of the optimization operation, It is used to represent the individual best tuning parameters of the i-th particle in the d-1th iteration optimization operation, gBest d-1 It is used to represent the optimal tuning parameters of the group for the d-1th iteration optimization operation, It is used to represent the output eye diagram tuning parameter set X of the i-th particle in the d-1th iteration optimization operation d-1The actual eye diagram tuning parameter value in . Among them, when the eye diagram tuning parameter type of the eye diagram tuning parameter set is "eye diagram offset", the corresponding particle is "test eye diagram"; when the eye diagram tuning parameter type of the eye diagram tuning parameter set is "eye diagram mask vertex coordinate", the corresponding particle is "eye diagram mask vertex"; for the first iterative optimization operation, the particle moving speed set V 0 The flying speed of each particle in is 0, and the corresponding eye diagram tuning parameter set X 0 That is the initial eye diagram tuning parameter set.

[0110] Sub-step S2422, based on the ideal particle movement speed set and the eye diagram tuning parameter set to be output of the previous iterative optimization operation, calculate the eye diagram tuning parameter set to be output that meets the eye diagram tuning parameter constraint conditions of this iterative optimization operation, and the actual particle movement speed set required for calculating the corresponding eye diagram tuning parameter set to be output in this iterative optimization operation.

[0111] In this embodiment, after the ideal particle movement speed set of a certain iterative optimization operation is determined, the speed is progressively modified based on the ideal particle movement speed set for the purpose of satisfying the eye diagram tuning parameter constraint condition, and then a new eye diagram tuning parameter set is calculated according to the modified particle movement speed set and the eye diagram tuning parameter set to be output of the previous iterative optimization operation, and it is determined whether the new eye diagram tuning parameter set satisfies the eye diagram tuning parameter constraint condition, and then when the eye diagram tuning parameter constraint condition is not satisfied, the speed of the particle movement speed set modified at that time is progressively modified, and then the step of calculating the new eye diagram tuning parameter set is jumped to continue execution, until the eye diagram tuning parameter set to be output that satisfies the eye diagram tuning parameter constraint condition is finally determined, and the actual particle movement speed set required for calculating the eye diagram tuning parameter set to be output is calculated. Among them, when the analysis target is "optimal input parameter coverage", the corresponding eye diagram tuning parameter constraint condition can be "the eye diagram offset of each test eye diagram in the corresponding eye diagram tuning parameter set is within the preset offset range"; when the analysis target is "optimal chip mass production input parameter value", the corresponding eye diagram tuning parameter constraint condition can be "all mask vertex coordinates of the corresponding eye diagram mask are within the eye diagram overlap area". For the dth iteration optimization operation, an eye diagram tuning parameter set X′ obtained by the dth iteration optimization operation d It can be calculated using the following formula:

[0112] X′ d =X d-1 +V′ d ;

[0113] Among them, X d-1 It is used to represent the output eye diagram tuning parameter set for the d-1th iteration optimization operation, V′ dA particle movement speed set used to represent the d-th iterative optimization operation (which may be an ideal particle movement speed set for the d-th iterative optimization operation, or a particle movement speed set obtained by a speed progressive modification process for the d-th iterative optimization operation).

[0114] Optionally, see Figure 6 , Figure 6 yes Figure 5 In this embodiment, the sub-step S2422 may include sub-steps S24221 to S24225, so as to ensure that the output eye diagram tuning parameter set obtained by one iterative optimization operation can meet the eye diagram tuning parameter constraint condition through the speed progressive modification operation.

[0115] Sub-step S24221, taking the ideal particle movement speed set as the target particle movement speed set.

[0116] Sub-step S24222, calculating the target eye diagram tuning parameter set for this iterative optimization operation according to the target particle moving speed set and the eye diagram tuning parameter set to be outputted in the previous iterative optimization operation.

[0117] The target eye diagram tuning parameter set may adopt the eye diagram tuning parameter set X′ of the dth iteration optimization operation. d The calculation formula is used for calculation.

[0118] Sub-step S24223, detecting whether the target eye diagram tuning parameter set meets the eye diagram tuning parameter constraint condition.

[0119] Among them, when it is detected that the target eye diagram tuning parameter set calculated at that time meets the eye diagram tuning parameter constraint conditions, the target eye diagram tuning parameter set can be used as the eye diagram tuning parameter set to be output for the corresponding iterative optimization operation, and the corresponding sub-step S24224 will be executed at this time; when it is detected that the target eye diagram tuning parameter set calculated at that time does not meet the eye diagram tuning parameter constraint conditions, it means that the target particle movement speed set at that time is not sufficient to achieve the analysis goal. At this time, it is necessary to execute sub-step S24225 to perform a speed progressive modification on the target particle movement speed set at that time, and then use the modified target particle movement speed set as the new target particle movement speed set, and jump to the above-mentioned sub-step S24222 to continue execution until the target particle movement speed set finally determined can ensure that the corresponding target eye diagram tuning parameter set meets the eye diagram tuning parameter constraint conditions.

[0120] Sub-step S24224, using the target eye diagram tuning parameter set as the eye diagram tuning parameter set to be output for this iterative optimization operation.

[0121] Sub-step S24225, performing a speed progressive modification on the target particle moving speed set.

[0122] Among them, the k-th speed progressive modification operation of the d-th iterative optimization operation can be expressed by the following formula:

[0123]

[0124] in, It is used to represent the target particle moving speed set after the kth speed progressive modification operation of the dth iteration optimization operation. The int function is used to represent the floor rounding function. It is used to represent the target particle moving speed set after the k-1th speed progressive modification operation of the dth iterative optimization operation, and S is used to represent the progressive coefficient, where That is, the ideal particle moving speed set V for the dth iteration optimization operation d .

[0125] Therefore, the present application can ensure that the eye diagram tuning parameter set to be output obtained by one iterative optimization operation can meet the eye diagram tuning parameter constraint conditions by executing the above sub-steps S24221 to S24225 through a speed progressive modification operation.

[0126] Sub-step S2423, calculates the eye diagram tuning index of this iterative optimization operation according to the eye diagram tuning parameter set to be outputted for this iterative optimization operation, and updates the individual optimal tuning parameters and the group optimal tuning parameters of this iterative optimization operation according to the eye diagram tuning index of this iterative optimization operation.

[0127] Sub-step S2424, detecting whether the eye diagram tuning index of this iterative optimization operation meets the iterative optimization end condition.

[0128] In this embodiment, the iterative optimization termination condition may be "the number of iterative optimizations corresponding to this iterative optimization operation exceeds the maximum number of iterative optimizations", or "the eye diagram tuning index of this iterative optimization operation reaches the maximum effect". If it is detected that the eye diagram tuning index of this iterative optimization operation meets the iterative optimization termination condition, it indicates that the eye diagram tuning parameter set to be outputted in this iterative optimization operation can be used as the optimal eye diagram tuning parameter set, and sub-step S2425 will be executed accordingly; if it is detected that the eye diagram tuning index of this iterative optimization operation does not meet the iterative optimization termination condition, it indicates that the optimal eye diagram tuning parameter set is not actually solved in this iterative optimization operation, and sub-step S2421 will be jumped to continue execution to start the next iterative optimization operation until the optimal eye diagram tuning parameter set is finally determined.

[0129] Sub-step S2425 , directly taking the eye diagram tuning parameter set to be output in this iterative optimization operation as the best eye diagram tuning parameter set.

[0130] Therefore, the present application can achieve the automatic iterative optimization effect of the best eye diagram tuning parameter set by executing the above sub-steps S2421 to S2425.

[0131] Sub-step S243, according to the parameter conversion relationship between the expected distribution parameter type pointed to by the analysis target and the eye diagram tuning parameter type, calculate and display the expected distribution result of at least one chip input parameter that matches the optimal eye diagram tuning parameter set.

[0132] In this embodiment, after determining the optimal eye diagram tuning parameter set related to the optimal eye diagram overlap interval of multiple test eye diagrams, the optimal input parameter distribution data of the optimal eye diagram overlap interval when achieving the analysis target (that is, the expected distribution result of the at least one chip input parameter) can be calculated according to the parameter conversion relationship between the expected distribution parameter type pointed to by the analysis target and the eye diagram tuning parameter type, and then by calling the visualization component matching the expected distribution parameter type, the expected distribution result of the at least one chip input parameter is displayed to the user through the user terminal, so that the user can intuitively understand the optimal input setting result of the chip that is adapted to the customized test item content, and there is no need for chip testers to manually search for the optimal input settings of the mass-produced chips in terms of safety, environmental protection, energy saving, etc., thereby achieving the effect of quickly finding the optimal input settings of the chip in terms of safety, environmental protection, energy saving, etc., and effectively reducing the relevant requirements for chip testers and reducing manpower loss in the chip verification process.

[0133] Therefore, the present application can implement different optimal input setting automated solution functions for different analysis objectives by executing the above sub-steps S241 to S243.

[0134] The present application can execute the above steps S210 to S240, based on the test item content customized by the user considering various factors, and adaptively generate multiple random input parameter test cases to cover the chips to be mass-produced, and perform chip data analysis based on the chip test result data according to user needs (i.e., the data analysis purpose specified by the chip tester) to quickly derive the optimal input parameter distribution data required for the chips to be mass-produced when they are officially mass-produced, so as to quickly find the optimal input settings of the chip in terms of safety, environmental protection, and energy saving, while effectively reducing the relevant requirements for chip testers and reducing manpower loss in the chip verification process.

[0135] Optionally, see Figure 7 , Figure 7This is the second flow chart of the chip verification method provided in the embodiment of the present application. Figure 2 Compared with the chip verification method shown, Figure 7 The chip verification method shown may further include step S250 to further study and verify the chip characteristic area of ​​the chip to be mass-produced, so as to obtain the optimal input setting that meets the user's expectations.

[0136] Step S250, in response to the user's definition file adjustment operation based on the result data to be analyzed and / or the expected distribution result of at least one chip input parameter, the chip input parameter composition, the numerical distribution range and / or the numerical coverage of each chip input parameter in the test item definition file are updated.

[0137] In this embodiment, when the user observes the result data to be analyzed displayed by the chip verification device 10 for the chip to be mass-produced (i.e., the effective output parameter data when the chip to be mass-produced is running stably), and / or the expected distribution result of the at least one chip input parameter when it meets the analysis target specified by the user, the user can adjust the content of the test item definition file originally customized according to the observation content, so that the adjusted test item definition file can further meet the research scope of the chip characteristic area that the user is interested in. Among them, the definition file adjustment operation made by the user may include but is not limited to: adjusting the chip input parameter composition corresponding to the chip to be mass-produced, adjusting the numerical coverage of each chip input parameter according to the expected distribution result of the at least one chip input parameter corresponding to the analysis target "optimal input parameter coverage", reducing or enlarging the numerical coverage of each chip input parameter according to the result data to be analyzed, reducing or expanding the numerical distribution range of each chip input parameter according to the result data to be analyzed, and adjusting the numerical distribution range of each chip input parameter according to the expected distribution result of the at least one chip input parameter corresponding to the analysis target "optimal chip mass production input parameter value".

[0138] After completing the content update operation of the test item definition file, the chip verification device 10 will repeat the above steps S220 to S240 according to the updated test item definition file to ensure that the optimal chip input settings finally solved can further meet the user's expected chip characteristic area research needs. Among them, when the numerical distribution range and numerical coverage of at least one chip input parameter are updated using the expected distribution result obtained in step S240, the optimal chip input settings solved by the chip verification device 10 can be further verified by repeating the above steps S220 to S240 to confirm the accuracy of the optimal chip input settings, which is conducive to the realization of chip mass production.

[0139] Therefore, the present application can further study and verify the chip characteristic area of ​​the chip to be mass-produced through the mutual cooperation of the above-mentioned step S250 and steps S210 to S240, and obtain the optimal input setting that meets the user's expectations.

[0140] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic, for example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to the embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0141] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0142] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a readable storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned readable storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0143] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip verification method, characterized in that: The method comprises: Obtaining a test item definition file configured by a user for a chip to be mass-produced, wherein the test item definition file includes a numerical distribution range and a numerical coverage of at least one chip input parameter matching a target test item parameter type, and a chip output parameter type matching the target test item parameter type; Generate multiple random input parameter test cases according to the numerical coverage and the numerical distribution range of the at least one chip input parameter, and obtain chip test result data corresponding to the chip output parameter type after the multiple random input parameter test cases are respectively run on multiple sample chips of the chip to be mass-produced; Perform data preprocessing on the acquired chip test result data to obtain and display the result data to be analyzed; Based on the result data to be analyzed and the multiple random input parameter test cases, chip data analysis is performed on the chip to be mass-produced according to the analysis target specified by the user, and the expected distribution result of the at least one chip input parameter of the chip to be mass-produced when achieving the analysis target is obtained and displayed, wherein the expected distribution result is used to represent the optimal input parameter distribution data of the at least one chip input parameter when ensuring that multiple finished chips of the chip to be mass-produced are all running stably.

2. The method according to claim 1, characterized in that The step of generating a plurality of random input parameter test cases according to the numerical coverage and the numerical distribution range of the at least one chip input parameter comprises: For each chip input parameter of the at least one chip input parameter, randomly select a plurality of input parameter values ​​within a value distribution range of the chip input parameter according to the value coverage rate; Test case combinations are performed on multiple input parameter values ​​corresponding to each of the at least one chip input parameters to obtain multiple random input parameter test cases, wherein each random input parameter test case is composed of an input parameter value of each of the at least one chip input parameters.

3. The method according to claim 1, characterized in that The step of obtaining chip test result data corresponding to the chip output parameter type after the multiple random input parameter test cases are respectively run on multiple sample chips of the chip to be mass-produced comprises: For each random input parameter test case in the multiple random input parameter test cases, calling the chip hardware test platform to respectively supply input parameters to multiple sample chips of the chip to be mass-produced according to the random input parameter test case; Collecting actual chip output parameter values ​​corresponding to the chip output parameter type of each of the plurality of sample chips under the action of the random input parameter test case; The actual chip output parameter values ​​of each of the plurality of sample chips corresponding to the plurality of random input parameter test cases are sorted to obtain the chip test result data.

4. The method according to claim 3, characterized in that The step of preprocessing the acquired chip test result data to obtain and display the result data to be analyzed includes: For each sample chip, according to the actual chip output parameter values ​​of the sample chip under the action of the multiple random input parameter test cases, a sample stability analysis is performed on the sample chip to obtain a stability analysis result of the sample chip; When the corresponding stability analysis results indicate that the sample chip is running stably, data cleaning is performed on the actual chip output parameter values ​​of the sample chip under the action of the multiple random input parameter test cases, and the valid output parameter values ​​of the sample chip corresponding to the multiple random input parameter test cases in the result data to be analyzed are obtained and displayed.

5. The method according to claim 1, characterized in that The step of performing chip data analysis on the chip to be mass-produced according to the result data to be analyzed and the multiple random input parameter test cases according to the analysis target specified by the user, and obtaining and displaying the expected distribution result of the at least one chip input parameter of the chip to be mass-produced when achieving the analysis target, includes: Constructing an eye diagram according to the result data to be analyzed and the multiple random input parameter test cases to obtain multiple test eye diagrams of the chip to be mass-produced during the verification process; Based on the multiple test eye diagrams, construct an initial eye diagram tuning parameter set associated with the analysis target, and iteratively optimize the initial eye diagram tuning parameter set based on a particle swarm optimization algorithm to obtain an optimal eye diagram tuning parameter set required to achieve the analysis target; According to the parameter conversion relationship between the expected distribution parameter type pointed to by the analysis target and the eye diagram tuning parameter type, the expected distribution result of the at least one chip input parameter matching the optimal eye diagram tuning parameter set is calculated and displayed.

6. The method according to claim 5, characterized in that The step of iteratively optimizing the initial eye diagram tuning parameter set based on the particle swarm optimization algorithm to obtain the optimal eye diagram tuning parameter set required to achieve the analysis goal includes: For each iterative optimization operation in the multiple iterative optimization operations, the actual inertia weight of the iterative optimization operation is calculated according to the preset weight parameter, and the ideal particle movement speed of the iterative optimization operation is calculated according to the actual inertia weight and the eye diagram tuning parameter set to be output and the actual particle movement speed set determined in the previous iterative optimization operation; According to the ideal particle movement speed set and the eye diagram tuning parameter set to be output of the previous iterative optimization operation, the eye diagram tuning parameter set to be output that meets the eye diagram tuning parameter constraint conditions of this iterative optimization operation is calculated, and the actual particle movement speed set required for calculating the corresponding eye diagram tuning parameter set to be output in this iterative optimization operation; Calculate the eye diagram tuning index of this iterative optimization operation according to the eye diagram tuning parameter set to be outputted in this iterative optimization operation, and update the individual optimal tuning parameter and the group optimal tuning parameter of this iterative optimization operation according to the eye diagram tuning index of this iterative optimization operation; Check whether the eye diagram tuning index of this iterative optimization operation meets the iterative optimization end condition; If it is detected that the eye diagram tuning index of this iterative optimization operation meets the iterative optimization end condition, the eye diagram tuning parameter set to be outputted by this iterative optimization operation is directly used as the optimal eye diagram tuning parameter set, otherwise the next iterative optimization operation is performed.

7. The method according to claim 6, characterized in that The step of calculating the eye diagram tuning parameter set to be output that meets the eye diagram tuning parameter constraint condition of the current iterative optimization operation according to the ideal particle moving speed set and the eye diagram tuning parameter set to be output of the previous iterative optimization operation comprises: The ideal particle moving speed set is used as the target particle moving speed set, and the target eye diagram tuning parameter set for this iterative optimization operation is calculated according to the target particle moving speed set and the eye diagram tuning parameter set to be outputted in the previous iterative optimization operation; Detecting whether the target eye diagram tuning parameter set meets the eye diagram tuning parameter constraint condition; If it is detected that the target eye diagram tuning parameter set satisfies the eye diagram tuning parameter constraint condition, the target eye diagram tuning parameter set is used as the eye diagram tuning parameter set to be output for this iterative optimization operation; otherwise, the target particle movement speed set is subjected to a speed progressive modification, and then based on the target particle movement speed set after the speed progressive modification, the step of calculating the target eye diagram tuning parameter set for this iterative optimization operation is jumped to continue execution.

8. The method according to claim 6, characterized in that When the analysis target is the best input parameter coverage, the expected distribution parameter type is the input parameter coverage, the eye diagram tuning parameter type is the eye diagram offset, and the eye diagram tuning indicator is the eye diagram overlap opening; When the analysis target is the optimal chip mass production input parameter value, the expected distribution parameter type is the parameter value interval of each of the at least one chip input parameters, the eye diagram tuning parameter type is the eye diagram mask vertex coordinates, and the eye diagram tuning indicator is the eye diagram area covered by the eye diagram mask.

9. The method according to any one of claims 1 to 8, characterized in that: The method further comprises: In response to the user's definition file adjustment operation based on the result data to be analyzed and / or the expected distribution result of the at least one chip input parameter, the chip input parameter composition, the numerical distribution range and / or the numerical coverage of each chip input parameter in the test item definition file are updated, and the step of generating multiple random input parameter test cases based on the numerical coverage and the numerical distribution range of the at least one chip input parameter is jumped to continue execution.

10. A chip verification device, characterized in that: It comprises a processor and a memory, wherein the memory stores a computer program executable by the processor, and the processor can execute the computer program to implement the chip verification method described in any one of claims 1 to 9.

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