Abnormal position hotspot map generation method and device for chip packaging, equipment and medium
By obtaining and analyzing the test results information and substrate position coordinates of the chip packaging, the hot spot of the abnormal position is generated, and the problem that the chip defect cannot be accurately positioned in existing technology can be solved, and the positioning efficiency is improved.
Patent Information
- Application Number
- CN202411463432.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-01-21
AI Technical Summary
The existing chip package heat map generation method cannot accurately generate heat maps when chip defects occasionally occur at low frequency, making it difficult for engineers to quickly find the location of the defect.
By obtaining the test result information and substrate position coordinates of the test chips of each packaging batch, the failure information corresponding to the failure mode is extracted, the location of the abnormal substrate is determined, and a heat map of the abnormal location is generated.
When the chip defects occasionally occasionally occur, the defect position is quickly and accurately found by a large amount of historical data and the position coordinates of the substrate, which improves the positioning efficiency of engineers.
Smart Images
Figure CN119338945A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of chip packaging detection technology, and in particular to a method, device, equipment and storage medium for generating an abnormal position heat map of a chip package. Background Art
[0002] The integrated circuit production line process is extremely precise and complex. A large number of wafer tests and verification studies are required before the new process can be put into formal mass production. By accurately locating defects and detecting mechanisms on the test wafers, the systematic causes of manufacturing process defects can be found. At the same time, a suitable layout design rule system is established to ensure the yield during formal production.
[0003] The heat maps currently used to locate defects are generated only through limited historical data from a single packaging batch. However, when chip defects occur occasionally with low frequency, the existing heat map generation method cannot generate a correct heat map due to the small number of abnormal errors, making it impossible for engineers to accurately find the location of the defect. Summary of the invention
[0004] The embodiments of the present invention provide a method, device, equipment and storage medium for generating an abnormal position heat map of chip packaging. When chip defects occur occasionally with low frequency, an abnormal position heat map is generated through a large amount of historical data and substrate position coordinates, so that engineers can quickly and accurately find the location of the defect.
[0005] In a first aspect, an embodiment of the present invention provides a method for generating a heat map of abnormal locations of a chip package, comprising:
[0006] Acquire test result information and substrate position coordinates of test chips of each packaging batch; wherein each packaging batch uses multiple substrates with the same specifications;
[0007] Extracting failure information corresponding to each failure mode in the test result information;
[0008] determining an abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information;
[0009] For each of the failure modes, an abnormal position heat map is generated according to the abnormal substrate positions corresponding to the failure mode.
[0010] In a second aspect, an embodiment of the present invention further provides a device for generating a heat map of abnormal positions of chip packages, the device comprising:
[0011] An information acquisition module, used to acquire test result information and substrate position coordinates of test chips of each packaging batch; wherein each packaging batch uses multiple substrates of the same specification;
[0012] An information extraction module, used to extract failure information corresponding to each failure mode in the test result information;
[0013] an abnormal substrate position determination module, configured to determine the abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information;
[0014] The heat map generation module is used to generate an abnormal position heat map according to the abnormal substrate position corresponding to each failure mode.
[0015] In a third aspect, an embodiment of the present disclosure further provides an electronic device, the electronic device comprising:
[0016] one or more processors;
[0017] a storage device for storing one or more programs,
[0018] When the one or more programs are executed by the one or more processors, the one or more processors implement the method for generating an abnormal location heat map of a chip package provided in an embodiment of the present disclosure.
[0019] In a fourth aspect, the embodiments of the present disclosure further provide a storage medium comprising computer executable instructions, which, when executed by a computer processor, are used to implement the method for generating an abnormal location hot spot map of a chip package provided by the embodiments of the present disclosure.
[0020] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the method for generating an abnormal position hotspot map of a chip package provided in the embodiment of the first aspect.
[0021] The present invention discloses a method, device, equipment and storage medium for generating an abnormal position heat map of chip packaging, including: obtaining test result information and substrate position coordinates of test chips of each packaging batch; wherein each packaging batch uses multiple substrates of the same specification; extracting failure information corresponding to each failure mode in the test result information; determining the abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information; and generating an abnormal position heat map for each failure mode according to the abnormal substrate position corresponding to the failure mode. Using this method: when a chip defect occurs occasionally with a low frequency, an abnormal position heat map is generated through a large amount of historical data and substrate position coordinates, so that engineers can quickly and accurately find the location of the defect. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.
[0023] Figure 1 A flow chart of a method for generating a heat map of abnormal locations of a chip package provided by an embodiment of the present disclosure;
[0024] Figure 2 An example diagram of an abnormal location heat map provided by an embodiment of the present disclosure;
[0025] Figure 3 A schematic diagram of the structure of a device for generating an abnormal position heat map of a chip package provided by an embodiment of the present disclosure;
[0026] Figure 4 A schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0027] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.
[0028] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.
[0029] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.
[0030] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.
[0031] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".
[0032] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.
[0033] It is understandable that before using the technical solutions disclosed in the embodiments of the present disclosure, the types, scope of use, usage scenarios, etc. of the personal information involved in the present disclosure should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with relevant laws and regulations.
[0034] For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly prompt the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can autonomously choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present disclosure according to the prompt message.
[0035] As an optional but non-limiting implementation, in response to receiving an active request from the user, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. In addition, the pop-up window may also carry a selection control for the user to choose "agree" or "disagree" to provide personal information to the electronic device.
[0036] It is understandable that the above notification and the process of obtaining user authorization are merely illustrative and do not constitute a limitation on the implementation of the present disclosure. Other methods that meet the relevant laws and regulations may also be applied to the implementation of the present disclosure.
[0037] It is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and relevant provisions.
[0038] Figure 1 A flowchart for generating a heat map of abnormal positions of a chip package provided in an embodiment of the present disclosure is applicable to providing a solution to the problem of when chip defects occur occasionally with low frequency and there is no way to determine the defect position based on big data. The method can be executed by a device for generating a heat map of abnormal positions of a chip package, which can be implemented in the form of software and / or hardware, and optionally, by an electronic device, which can be a mobile terminal, a PC or a server, etc.
[0039] like Figure 1As shown, a method for generating a heat map of abnormal locations of chip packages provided in an embodiment of the present disclosure may specifically include the following steps:
[0040] S110 , obtaining test result information and substrate position coordinates of the test chips of each packaging batch.
[0041] Among them, each packaging batch uses multiple substrates with the same specifications;
[0042] The test result information includes: the packaging batch number of the test chip, the chip failure mode number and the positioning information on the substrate. The substrate position coordinates include: the tracking serial number of the substrate, the position code on the substrate, the row number on the substrate and the column number on the substrate.
[0043] In this embodiment, the packaging batch may refer to a batch of integrated circuit chips that are packaged at the same time and for the same product in a packaging plant. The number of the chip failure mode defines the number of the failure mode of the test parameters of the defective product corresponding to a certain defect. The substrate may be a printed circuit board. The substrate position coordinates may be position codes on all substrates, and the position codes are decoded into corresponding row and column numbers according to the two-dimensional code coding rules of the integrated circuit chip. The positioning information on the substrate may be the position information of the chip on the substrate.
[0044] Specifically, the test result information and substrate position coordinates of all test chips of each packaging batch are obtained, wherein each packaging batch uses multiple substrates with the same specifications.
[0045] S120: Extract failure information corresponding to each failure mode in the test result information.
[0046] In this embodiment, the failure information may be location information of the chip on the substrate in each failure mode.
[0047] Specifically, failure information corresponding to each failure mode in the test result information is extracted.
[0048] S130, determining the abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information
[0049] In this embodiment, the abnormal substrate position may be that the substrate fails to be accurately positioned at the expected processing or testing position.
[0050] Specifically, the number of times each position coordinate in the substrate position coordinates appears in the failure information is queried, the number is used as the abnormal value of each position coordinate, and the abnormal substrate position is determined from the position coordinate according to the ratio of the abnormal value to the sum of the abnormal values.
[0051] Based on the above embodiment, determining the abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information may include the following steps:
[0052] a1) Query the number of times each position coordinate in the substrate position coordinate appears in the failure information, and use the number as the abnormal value of each position coordinate.
[0053] b1) Determine the abnormal substrate position from the position coordinates based on the abnormal value.
[0054] In this embodiment, the failure information includes the chip position where an abnormality occurs in each failure mode.
[0055] Specifically, by querying the number of times each position coordinate in the substrate position coordinate appears in the failure information, the number is used as the abnormal value of each position coordinate, and the abnormal substrate position is determined according to the ratio of the abnormal value of each position coordinate to the sum of the abnormal values.
[0056] Based on the above embodiment, determining the abnormal substrate position from the position coordinates according to the abnormal value may include the following steps:
[0057] b11) taking the ratio of the abnormal value of each position coordinate to the sum of the abnormal values as the abnormal percentage of each position coordinate;
[0058] b12) Take the average of the anomaly percentages as the average percentage of the location coordinates
[0059] b13) If the ratio of the abnormal percentage to the average percentage is greater than a preset threshold, the position coordinates corresponding to the ratio are used as the abnormal substrate position.
[0060] In this embodiment, the preset threshold value can be set according to actual conditions and is not specifically limited in the embodiment of the present invention.
[0061] Exemplarily, the sum of each failure mode at each location, the percentage of failure modes at each location, and the ratio of the percentage of failure modes at each location to the average percentage are calculated once a week. When the ratio exceeds a preset threshold, it is considered an abnormal point.
[0062] S140 . For each failure mode, generate an abnormal position heat map according to the abnormal substrate position corresponding to the failure mode.
[0063] In this embodiment, the position coordinate template diagram is a diagram generated by decoding the position code on the substrate into corresponding row and column numbers according to the two-dimensional code coding rules.
[0064] Specifically, a position coordinate template map of the substrate is obtained, and abnormal substrate positions under different failure modes are mapped into the position coordinate template map to generate an abnormal position hotspot map of each failure mode.
[0065] On the basis of the above embodiments, for each failure mode, generating an abnormal position heat map according to the abnormal substrate position corresponding to the failure mode may include the following steps:
[0066] a2) Obtain the position coordinate template map of the substrate.
[0067] b2) Mapping the abnormal substrate positions under different failure modes to the position coordinate template map to generate an abnormal position hotspot map of each failure mode.
[0068] Figure 2 This is an example diagram of an abnormal position heat map provided by an embodiment of the present disclosure. As shown in the figure, the red and yellow points on the figure are possible abnormal points, and the red and yellow colors represent different degrees of abnormality. The program script is developed using the statistical software JMP programming language and the SQL server data query language to connect to the database, and all the information in the data table storing the test result information and substrate position coordinates for a specified time period is downloaded to a JMP software data table; the JMP script is developed using the data content in JMP to generate an abnormal position heat map based on the row and column coordinates of the substrate.
[0069] For example, in a chip product, 15 batches of 414 test batches failed during testing; the common point is the same failure mode, and the result shows that the pin is cracked. By using the above big data JMP to capture historical data, an abnormal position point map of the failure mode is generated, as shown above Figure 2 66% of the failed chips come from the 10 abnormal protruding points in the figure. Based on these 10 abnormal points, the packaging engineers analyzed and believed that the pins cracked due to uneven force on the substrate when it was washed before plastic packaging. After experimental verification, the problem was solved by reducing the pressure of water washing while ensuring the water washing effect.
[0070] The present invention discloses a method for generating an abnormal position heat map of chip packaging, comprising: obtaining test result information and substrate position coordinates of test chips of each packaging batch; wherein the substrates used in each packaging batch are the same; extracting failure information corresponding to each failure mode in the test result information; determining the abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information; and generating an abnormal position heat map according to the abnormal substrate position corresponding to each failure mode for each failure mode. Using this method: when a chip defect occurs occasionally with a low frequency, an abnormal position heat map is generated through historical data and substrate position coordinates, so that engineers can quickly and accurately find the location of the defect.
[0071] Figure 3 The present invention also provides a schematic diagram of a chip package abnormal position heat map generating device structure, such as Figure 3As shown, the device includes: an information acquisition module 210, an information extraction module 220, an abnormal substrate position determination module 230 and a heat map generation module 240.
[0072] The information acquisition module 210 is used to acquire the test result information and substrate position coordinates of the test chips of each packaging batch; wherein each packaging batch uses multiple substrates with the same specifications;
[0073] An information extraction module 220 is used to extract failure information corresponding to each failure mode in the test result information;
[0074] An abnormal substrate position determination module 230, configured to determine the abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information;
[0075] The heat map generating module 240 is used to generate an abnormal position heat map according to the abnormal substrate position corresponding to each failure mode.
[0076] The technical solution provided by the embodiment of the present disclosure generates an abnormal position hot spot map through historical data and substrate position coordinates when chip defects occur occasionally at a low frequency, so that engineers can quickly and accurately find the location of the defect.
[0077] Furthermore, the abnormal substrate position determination module 230 may be used to:
[0078] querying the number of times each position coordinate in the substrate position coordinate appears in the failure information, and taking the number as an abnormal value of each position coordinate;
[0079] The abnormal substrate position is determined from the position coordinates according to the abnormal value.
[0080] Furthermore, the abnormal substrate position determination module 230 may be used to:
[0081] Taking the ratio of the abnormal value of each position coordinate to the sum of the abnormal values as the abnormal percentage of each position coordinate;
[0082] The average value of the abnormal percentage is taken as the average percentage of the position coordinates
[0083] If the ratio of the abnormal percentage to the average percentage is greater than a preset threshold, the position coordinate corresponding to the ratio is used as the abnormal substrate position.
[0084] Furthermore, the heat map generation module 240 may be used to:
[0085] Obtaining a position coordinate template diagram of the substrate;
[0086] The abnormal substrate positions under different failure modes are mapped to the position coordinate template map to generate the abnormal position heat map of each failure mode.
[0087] Furthermore, the information acquisition module 210 may be used to:
[0088] The test result information includes: the packaging batch number of the test chip and the number of the chip failure mode.
[0089] Furthermore, the information acquisition module 210 may be used to:
[0090] The substrate position coordinates include: a tracking serial number of the substrate, a position code on the substrate, a row number on the substrate, and a column number on the substrate.
[0091] The above device can execute the methods provided by all the above embodiments of the present invention, and has the corresponding functional modules and beneficial effects of executing the above methods. For technical details not described in detail in this embodiment, please refer to the methods provided by all the above embodiments of the present invention.
[0092] Figure 4 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is given. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.
[0093] like Figure 4 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0094] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.
[0095] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a method for generating a heat map of abnormal locations of chip packages.
[0096] In some embodiments, the method for generating a heat map of abnormal locations of chip packages may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the method for generating a heat map of abnormal locations of chip packages described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the method for generating a heat map of abnormal locations of chip packages in any other appropriate manner (e.g., by means of firmware).
[0097] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
[0098] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.
[0099] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0100] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).
[0101] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.
[0102] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.
[0103] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0104] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A method for generating a heat map of abnormal locations of chip packaging, characterized in that: include: Acquire test result information and substrate position coordinates of test chips of each packaging batch; wherein each packaging batch uses multiple substrates with the same specifications; Extracting failure information corresponding to each failure mode in the test result information; determining an abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information; For each of the failure modes, an abnormal position heat map is generated according to the abnormal substrate positions corresponding to the failure mode.
2. The method according to claim 1, characterized in that The determining the abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information includes: querying the number of times each position coordinate in the substrate position coordinate appears in the failure information, and taking the number as an abnormal value of each position coordinate; The abnormal substrate position is determined from the position coordinates according to the abnormal value.
3. The method according to claim 2, characterized in that The step of determining the abnormal substrate position from the position coordinates according to the abnormal value comprises: Taking the ratio of the abnormal value of each position coordinate to the sum of the abnormal values as the abnormal percentage of each position coordinate; The average value of the abnormal percentage is taken as the average percentage of the position coordinates If the ratio of the abnormal percentage to the average percentage is greater than a preset threshold, the position coordinate corresponding to the ratio is used as the abnormal substrate position.
4. The method according to claim 1, characterized in that: For each of the failure modes, generating an abnormal position heat map according to the abnormal substrate position corresponding to the failure mode includes: Obtaining a position coordinate template diagram of the substrate; The abnormal substrate positions under different failure modes are mapped to the position coordinate template map to generate the abnormal position heat map of each failure mode.
5. The method according to claim 1, characterized in that The test result information includes: the packaging batch number of the test chip, the positioning information on the substrate and the number of the chip failure mode.
6. The method according to claim 1, characterized in that The substrate position coordinates include: a tracking serial number of the substrate, a position code on the substrate, a row number on the substrate, and a column number on the substrate.
7. A device for generating a heat map of abnormal positions of chip packaging, characterized in that: include: An information acquisition module, used to acquire test result information and substrate position coordinates of test chips of each packaging batch; wherein each packaging batch uses multiple substrates of the same specification; An information extraction module, used to extract failure information corresponding to each failure mode in the test result information; an abnormal substrate position determination module, configured to determine the abnormal substrate position of each failure mode from the substrate position coordinates according to the failure information; The heat map generation module is used to generate an abnormal position heat map according to the abnormal substrate position corresponding to each failure mode.
8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the method for generating an abnormal position heat map of a chip package according to any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method for generating an abnormal position heat map of a chip package according to any one of claims 1 to 6 when executed.
10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method for generating an abnormal position heat map of a chip package according to any one of claims 1 to 6 is implemented.