Shifting register and driving method thereof, gate driving circuit and display device

Abstract

The invention provides a shift register and a driving method thereof, a gate driving circuit and a display device, relates to the technical field of display, and is used for reducing power consumption generated by a gate driving circuit part in a display product. In the shift register, a first holding sub-circuit is respectively coupled with a control signal input end and a first node and is used for keeping the voltage of the first node basically unchanged in a first working mode; the second holding sub-circuit is respectively coupled with the control signal input end and a second node, and is used for keeping the voltage of the second node basically unchanged in the first working mode.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] With the continuous development of display technology, the application fields of display products are becoming more and more extensive, and corresponding users have put forward higher and higher requirements for display products. In order to meet the user's demand for narrow borders of display products, display products can be set to use GOA (English: Gate On Array) technology, that is, the gate drive circuit is made on the array substrate of the display product.

[0003] The power consumption of display products is mainly generated by two parts, one is the pixel driving circuit part, and the other is the gate driving circuit part. The relevant technology has greatly reduced the power consumption generated by the pixel driving circuit part through corresponding technical means. Therefore, how to reduce the power consumption generated by the gate driving circuit part has become a key issue in reducing the overall power consumption of the display substrate. Summary of the invention

[0004] The object of the present invention is to provide a shift register and a driving method thereof, a gate driving circuit, and a display device, so as to reduce the power consumption generated by the gate driving circuit part in a display product.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A first aspect of the present invention provides a shift register, comprising: a first node, a second node, a first output subcircuit, and a second output subcircuit; the shift register further comprises a first holding subcircuit and / or a second holding subcircuit;

[0007] The first output subcircuit is coupled to the first level signal input terminal, the gate drive signal output terminal and the first node respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the gate drive signal output terminal under the control of the first node;

[0008] The second output subcircuit is coupled to the first clock signal input terminal, the gate drive signal output terminal and the second node respectively, and is used to control the conduction or disconnection of the electrical connection between the first clock signal input terminal and the gate drive signal output terminal under the control of the second node;

[0009] The first holding subcircuit is coupled to the control signal input terminal and the first node respectively, and is used to keep the voltage of the first node substantially unchanged in the first working mode;

[0010] The second holding subcircuit is coupled to the control signal input terminal and the second node respectively, and is used to keep the voltage of the second node substantially unchanged in the first working mode.

[0011] Optionally, the shift register further includes a third node, a fourth node, a third node control subcircuit and a fourth node control subcircuit, the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node;

[0012] The first holding subcircuit includes a tenth transistor, a gate of the tenth transistor is coupled to the control signal input terminal, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the third node;

[0013] The second holding subcircuit includes a ninth transistor, a gate of the ninth transistor is coupled to the control signal input terminal, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the fourth node.

[0014] Optionally, the ninth transistor and the tenth transistor include oxide transistors.

[0015] Optionally, the shift register further includes a fourth node and a fourth node control subcircuit, and the fourth node control subcircuit is used to control the potential of the fourth node;

[0016] The shift register also includes: a third holding sub-circuit, which is coupled to the second level signal input terminal, the fourth node and the second holding sub-circuit respectively, and is used to control the conduction or disconnection of the electrical connection between the fourth node and the second holding sub-circuit under the control of the second level signal input terminal.

[0017] Optionally, the third holding sub-circuit includes an eighth transistor, a gate of the eighth transistor is coupled to the second level signal input terminal, a first electrode of the eighth transistor is coupled to the second holding sub-circuit, and a second electrode of the eighth transistor is coupled to the fourth node.

[0018] Optionally, the shift register further includes a third node, a fourth node, a third node control subcircuit and a fourth node control subcircuit, the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node;

[0019] The third node control subcircuit is coupled to the second clock signal input terminal, the second level signal input terminal, the third node and the fourth node respectively, and is used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node under the control of the second clock signal input terminal; and is also used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node under the control of the fourth node.

[0020] Optionally, the third node control subcircuit includes a second transistor and a third transistor;

[0021] The gate of the second transistor is coupled to the fourth node, the first electrode of the second transistor is coupled to the second clock signal input terminal, and the second electrode of the second transistor is coupled to the third node;

[0022] A gate of the third transistor is coupled to the second clock signal input terminal, a first electrode of the third transistor is coupled to the second level signal input terminal, and a second electrode of the third transistor is coupled to the third node.

[0023] Optionally, the shift register further includes a third node, a fourth node, a third node control subcircuit and a fourth node control subcircuit, the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node;

[0024] The fourth node control subcircuit is coupled to the input signal terminal, the first clock signal input terminal, the second clock signal input terminal, the first level signal input terminal, the third node and the fourth node respectively; and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the fourth node under the control of the second clock signal input terminal; and is also used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the fourth node under the joint control of the third node and the first clock signal input terminal.

[0025] Optionally, the fourth node control subcircuit includes a first transistor, a sixth transistor and a seventh transistor;

[0026] The gate of the first transistor is coupled to the second clock signal input terminal, the first electrode of the first transistor is coupled to the input signal terminal, and the second electrode of the first transistor is coupled to the fourth node;

[0027] The gate of the sixth transistor is coupled to the third node, the first electrode of the sixth transistor is coupled to the first level signal input terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor;

[0028] A gate of the seventh transistor is coupled to the first clock signal input terminal, and a second electrode of the seventh transistor is coupled to the fourth node.

[0029] Optionally, the first output subcircuit includes a fourth transistor and a first capacitor, the gate of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the first level signal input terminal, and the second electrode of the fourth transistor is coupled to the gate drive signal output terminal; the first terminal of the first capacitor is coupled to the first level signal input terminal, and the second terminal of the first capacitor is coupled to the first node;

[0030] The second output subcircuit includes a fifth transistor and a second capacitor, the gate of the fifth transistor is coupled to the second node, the first electrode of the fifth transistor is coupled to the first clock signal input terminal, the second electrode of the fifth transistor is coupled to the gate drive signal input terminal, the first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the gate drive signal output terminal.

[0031] Based on the technical solution of the shift register, a second aspect of the present invention provides a gate drive circuit, comprising a plurality of cascaded shift registers.

[0032] Based on the technical solution of the gate driving circuit, a third aspect of the present invention provides a display device, comprising the above-mentioned gate driving circuit.

[0033] Based on the technical solution of the shift register, a fourth aspect of the present invention provides a shift register driving method for driving the shift register, wherein the driving method comprises a plurality of driving cycles, and in one driving cycle:

[0034] In the holding phase, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a first voltage signal;

[0035] The first output subcircuit, under the control of the first node, controls the electrical connection between the first level signal input terminal and the gate drive signal output terminal; the second output subcircuit, under the control of the second node, controls the electrical connection between the first clock signal input terminal and the gate drive signal output terminal to be disconnected; during at least part of the holding phase, the first holding subcircuit, under the control of the control signal input terminal, is in the first operating mode, keeping the voltage of the first node basically unchanged; the second holding subcircuit, under the control of the control signal input terminal, is in the first operating mode, keeping the voltage of the second node basically unchanged.

[0036] Optionally, the first holding subcircuit includes a tenth transistor, the second holding subcircuit includes a ninth transistor, and the ninth transistor and the tenth transistor include oxide transistors;

[0037] During at least a portion of the holding phase, under the control of the control signal input terminal, the ninth transistor and the tenth transistor are turned off.

[0038] Optionally, during a drive cycle:

[0039] In the refresh phase, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a clock signal; under the control of the control signal input terminal, the ninth transistor and the tenth transistor are turned on.

[0040] In the technical solution provided by the present invention, the first holding subcircuit is coupled to the control signal input terminal and the first node respectively, and is used to keep the voltage of the first node substantially unchanged in the first working mode; the second holding subcircuit is coupled to the control signal input terminal and the second node respectively, and is used to keep the voltage of the second node substantially unchanged in the first working mode. Therefore, in the shift register provided by the present invention, in the holding stage, the clock signal input terminal coupled to the shift register is controlled to input a first voltage signal maintaining a fixed potential, and the first holding subcircuit and the second holding subcircuit are controlled to be in the first working mode, so as to lock the voltages of the first node and the second node, and ensure the stability of the signal output by the gate drive signal output terminal.

[0041] Therefore, in the technical solution provided by the present invention, the driving function of the shift register is guaranteed in the refresh phase. In the holding phase, the signal inputted by the clock signal input terminal is switched from the high-frequency jump state to the fixed voltage holding state by controlling the clock signal input terminal, thereby effectively reducing the power consumption of the shift register. At the same time, in the holding phase, the voltages of the first node and the second node are locked by the first holding subcircuit and the second holding subcircuit, thereby preventing the voltages of the first node and the second node from shifting at the holding node, thereby ensuring the stability of the signal outputted by the gate drive signal output terminal. Therefore, when the technical solution provided by the present invention is applied to the gate drive circuit, the power consumption generated by the gate drive circuit part is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0043] Figure 1 A schematic diagram of a first sub-circuit of a shift register provided in an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of a second sub-circuit of a shift register provided in an embodiment of the present invention;

[0045] Figure 3 A first structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0046] Figure 4 A second structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0047] Figure 5 A schematic diagram of the timing of various signals connected to the shift register provided in an embodiment of the present invention;

[0048] Figure 6 for Figure 5 A1 is an enlarged schematic diagram;

[0049] Figure 7 A third structural diagram of a shift register provided by an embodiment of the present invention;

[0050] Figure 8 A fourth structural diagram of a shift register provided by an embodiment of the present invention;

[0051] Fig. 9 A schematic diagram of the timing of various signals connected to the shift register provided in an embodiment of the present invention;

[0052] Fig.10 for Fig. 9 A2 is an enlarged schematic diagram. DETAILED DESCRIPTION

[0053] In order to further illustrate the shift register and its driving method, gate driving circuit, and display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0054] See also Figure 1 , Figures 7 to 10 , an embodiment of the present invention provides a shift register, comprising: a first node PU, a second node PD, a first output sub-circuit 10, and a second output sub-circuit 20; the shift register further comprises a first holding sub-circuit 50 and / or a second holding sub-circuit 60;

[0055] The first output sub-circuit 10 is coupled to the first level signal input terminal VGH, the gate drive signal output terminal (such as GOUT_n and GOUT_n+1) and the first node PU respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGH and the gate drive signal output terminal under the control of the first node PU;

[0056] The second output sub-circuit 20 is respectively coupled to the first clock signal input terminal (the written signal is GCK or GCB), the gate drive signal output terminal and the second node PD, and is used to control the conduction or disconnection of the electrical connection between the first clock signal input terminal and the gate drive signal output terminal under the control of the second node PD;

[0057] The first holding subcircuit 50 is coupled to the control signal input terminal Vcon and the first node PU respectively, and is used to keep the voltage of the first node substantially unchanged in the first working mode;

[0058] The second holding sub-circuit 60 is coupled to the control signal input terminal Vcon and the second node PD respectively, and is used to keep the voltage of the second node substantially unchanged in the first working mode.

[0059] Exemplarily, the first node PU includes a pull-up node, and the second node PD includes the following nodes, but is not limited thereto.

[0060] Exemplarily, the first level signal input terminal VGH inputs a high level signal, but is not limited thereto.

[0061] Exemplarily, the shift register further includes a third node N3, a fourth node N4, a third node control module 30 and a fourth node control module 40; the third node control module 30 is coupled to the third node N3 for the potential of the third node N3; the fourth node control module 40 is coupled to the fourth node N4 for the potential of the fourth node N4;

[0062] The first holding subcircuit 50 is coupled to the control signal input terminal Vcon, the first node PU and the third node N3 respectively, and is used to control the conduction or disconnection of the electrical connection between the first node PU and the third node N3 under the control of the control signal input terminal Vcon.

[0063] The second holding subcircuit 60 is coupled to the control signal input terminal Vcon, the second node PD and the fourth node N4, respectively, and is used to control the conduction or disconnection of the electrical connection between the second node PD and the fourth node N4 under the control of the control signal input terminal Vcon.

[0064] Exemplarily, the first holding sub-circuit 50 includes a tenth transistor T10, a gate of the tenth transistor T10 is coupled to the control signal input terminal Vcon, a first electrode of the tenth transistor T10 is coupled to the first node PU, and a second electrode of the tenth transistor T10 is coupled to the third node N3. The second holding sub-circuit 60 includes a ninth transistor T9, a gate of the ninth transistor T9 is coupled to the control signal input terminal Vcon, a first electrode of the ninth transistor T9 is coupled to the second node PD, and a second electrode of the ninth transistor T9 is coupled to the fourth node N4.

[0065] Exemplarily, the ninth transistor T9 and the tenth transistor T10 include oxide transistors.

[0066] Exemplarily, the shift register may be applicable to low-frequency driving, but is not limited thereto.

[0067] For example, when driving at a low frequency, Fig.10 As shown, in the holding stage P2, the signal input to the first clock signal input terminal and / or the second clock signal input terminal (such as: GCK / GCB) is set to a high potential for a long time, that is, a first voltage signal is input to replace the original clock signal of the high-frequency jump mode, and the control signal input to the control signal input terminal Vcon is adjusted to a low voltage hold, and the ninth transistor T9 and the tenth transistor T10 are controlled to be turned off, so that the first holding sub-circuit 50 and the second holding sub-circuit 60 are both in the first working mode, and the low leakage characteristics of the oxide transistor are used to keep the voltage of the first node PU and the second node PD unchanged, thereby controlling the output signal of the gate drive signal output terminal to maintain a stable voltage. Fig. 9 As shown, by comparison, when the control signal is adjusted to a high voltage at 50ms, it can be found that the voltages of the first node PU and the second node PD gradually shift, which is not conducive to maintaining the output voltage of the gate drive signal output terminal.

[0068] It should be noted that the signal inputted by the first clock signal input terminal and / or the second clock signal input terminal (such as GCK / GCB) is set to a high potential for a long time and enters the holding stage P2. In the holding stage P2, when the control signal inputted by the signal input terminal Vcon is adjusted to a low voltage holding, the first holding sub-circuit 50 and the second holding sub-circuit 60 enter the first working mode.

[0069] Exemplarily, the shift register may be used to output a light emitting control signal or a gate scanning signal, but is not limited thereto.

[0070] Based on the problems existing in the background technology, it is found through research that Figure 3 , Figure 4 and Figure 6 As shown, when driving at a low frequency (for example, 10 Hz), the gate drive signal output terminal needs to maintain a high voltage output. At this time, the first node PU maintains a low voltage, and the second node PD maintains a high voltage. The first clock signal input to the first clock signal input terminal and the second clock signal input to the second clock signal input terminal always maintain a high-frequency toggle state during the high voltage output stage of the gate drive signal output terminal, which will generate a lot of power consumption. If the clock signals input to the first clock signal input terminal and the second clock signal input terminal are adjusted to the first voltage signal in the high voltage holding state during the high voltage output stage of the gate drive signal output terminal, the power consumption of the gate drive circuit can be greatly reduced. Figure 5 As shown, the gate drive signal output terminal of this timing setting can output normally in the initial stage, but as time goes on, the high voltage output by the gate drive signal output terminal begins to be unstable. The reason is that after the clock signal is adjusted to the first voltage signal, the voltage of the first node PU and the second node PD cannot be refreshed by the signal, and becomes a floating state, and gradually begins to drift, thereby making the high voltage output by the gate drive signal output terminal unstable.

[0071] According to the specific structure of the above shift register, in the shift register provided by the embodiment of the present invention, the first holding subcircuit 50 is coupled to the control signal input terminal and the first node PU respectively, and is used to keep the voltage of the first node PU basically unchanged in the first working mode; the second holding subcircuit 60 is coupled to the control signal input terminal and the second node PD respectively, and is used to keep the voltage of the second node PD basically unchanged in the first working mode. Therefore, in the shift register provided by the embodiment of the present invention, in the holding stage P2, the clock signal input terminal coupled to the shift register is controlled to input a first voltage signal with a fixed potential, and the first holding subcircuit 50 and the second holding subcircuit 60 are controlled to be in the first working mode, so as to lock the voltages of the first node PU and the second node PD, and ensure the stability of the signal output by the gate drive signal output terminal.

[0072] According to the specific structure of the above-mentioned shift register, in the shift register provided by the embodiment of the present invention, the first holding sub-circuit 50 is set to be able to control the conduction or disconnection of the electrical connection between the first node PU and the third node N3 under the control of the control signal input terminal Vcon; the second holding sub-circuit 60 is able to control the conduction or disconnection of the electrical connection between the second node PD and the fourth node N4 under the control of the control signal input terminal Vcon.

[0073] This arrangement makes it possible for the shift register to work, in the refresh phase P1, to control the clock signal input terminal coupled to the shift register to input a jumping clock signal, control the first holding subcircuit 50 to conduct the electrical connection between the first node PU and the third node N3, and control the second holding subcircuit 60 to conduct the electrical connection between the second node PD and the fourth node N4, thereby realizing the driving function of the shift register. In the holding phase P2, the clock signal input terminal coupled to the shift register is controlled to input a first voltage signal maintaining a fixed potential, control the first holding subcircuit 50 to disconnect the electrical connection between the first node PU and the third node N3, and control the second holding subcircuit 60 to disconnect the electrical connection between the second node PD and the fourth node N4, so as to lock the voltages of the first node PU and the second node PD, thereby ensuring the stability of the signal output from the gate drive signal output terminal.

[0074] Therefore, in the shift register provided by the embodiment of the present invention, the driving function of the shift register is guaranteed in the refresh phase P1. In the holding phase P2, the signal inputted into the clock signal input terminal is switched from the high-frequency jump state to the fixed voltage holding state by controlling the signal inputted into the clock signal input terminal, thereby effectively reducing the power consumption of the shift register. At the same time, in the holding phase P2, the voltages of the first node PU and the second node PD are locked by the first holding subcircuit 50 and the second holding subcircuit 60, thereby preventing the voltages of the first node PU and the second node PD from shifting at the holding nodes, thereby ensuring the stability of the signal outputted from the gate drive signal output terminal. Therefore, when the shift register provided by the embodiment of the present invention is applied to the gate drive circuit, the power consumption generated by the gate drive circuit part is effectively reduced.

[0075] like Figure 2 , Figure 7 and Figure 8 As shown, in some embodiments, the shift register also includes: a third holding sub-circuit 70, which is respectively coupled to the second level signal input terminal VGL, the fourth node N4 and the second holding sub-circuit 60, and is used to control the conduction or disconnection of the electrical connection between the fourth node N4 and the second holding sub-circuit 60 under the control of the second level signal input terminal VGL.

[0076] Exemplarily, the third holding subcircuit 70 includes an eighth transistor T8, a gate of the eighth transistor T8 is coupled to the second level signal input terminal VGL, a first electrode of the eighth transistor T8 is coupled to the second holding subcircuit 60, and a second electrode of the eighth transistor T8 is coupled to the fourth node N4. The second level signal input terminal VGL controls the conduction and cutoff of the eighth transistor T8.

[0077] Exemplarily, the second level signal input terminal VGL inputs a low level signal, but is not limited thereto.

[0078] Exemplarily, the eighth transistor T8 includes a low temperature polysilicon transistor, but is not limited thereto.

[0079] The third holding sub-circuit 70 can ensure that the drain-source voltage Vds of the first transistor T1 is not particularly large in any phase.

[0080] like Figure 2 , Figure 7 and Figure 8 As shown, in some embodiments, the third node control subcircuit 30 is respectively coupled to the second clock signal input terminal, the second level signal input terminal VGL, the third node N3 and the fourth node N4, and is used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node N3 under the control of the second clock signal input terminal; and is also used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node N3 under the control of the fourth node N4.

[0081] Exemplarily, the third node control subcircuit 30 includes a second transistor T2 and a third transistor T3;

[0082] The gate of the second transistor T2 is coupled to the fourth node N4, the first electrode of the second transistor T2 is coupled to the second clock signal input terminal, and the second electrode of the second transistor T2 is coupled to the third node N3; the fourth node N4 controls whether the second transistor T2 is turned on.

[0083] The gate of the third transistor T3 is coupled to the second clock signal input terminal, the first electrode of the third transistor T3 is coupled to the second level signal input terminal VGL, and the second electrode of the third transistor T3 is coupled to the third node N3. The second clock signal input terminal controls whether the third transistor T3 is turned on.

[0084] like Figure 2 , Figure 7 and Figure 8As shown, in some embodiments, the fourth node control subcircuit 40 is respectively coupled to the input signal terminal (such as: GOUT_n and GOUT_n-1), the first clock signal input terminal, the second clock signal input terminal, the first level signal input terminal VGH, the third node N3 and the fourth node N4; it is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the fourth node N4 under the control of the second clock signal input terminal; it is also used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGH and the fourth node N4 under the common control of the third node N3 and the first clock signal input terminal.

[0085] Exemplarily, the fourth node control subcircuit 40 includes a first transistor T1, a sixth transistor T6 and a seventh transistor T7;

[0086] The gate of the first transistor T1 is coupled to the second clock signal input terminal, the first electrode of the first transistor T1 is coupled to the input signal terminal, and the second electrode of the first transistor T1 is coupled to the fourth node N4; the second clock signal input terminal is used to control whether the first transistor T1 is turned on.

[0087] The gate of the sixth transistor T6 is coupled to the third node N3, the first electrode of the sixth transistor T6 is coupled to the first level signal input terminal VGH, the second electrode of the sixth transistor T6 is coupled to the first electrode of the seventh transistor T7; the third node N3 controls whether the sixth transistor T6 is turned on.

[0088] The gate of the seventh transistor T7 is coupled to the first clock signal input terminal, and the second electrode of the seventh transistor T7 is coupled to the fourth node N4. The first clock signal input terminal controls whether the seventh transistor T7 is turned on.

[0089] like Figure 2 , Figure 7 and Figure 8 As shown, in some embodiments, the first output sub-circuit 10 includes a fourth transistor T4 and a first capacitor C1, the gate of the fourth transistor T4 is coupled to the first node PU, the first electrode of the fourth transistor T4 is coupled to the first level signal input terminal VGH, and the second electrode of the fourth transistor T4 is coupled to the gate drive signal output terminal; the first end of the first capacitor C1 is coupled to the first level signal input terminal VGH, and the second end of the first capacitor C1 is coupled to the first node PU; the first node PU controls whether the fourth transistor T4 is turned on.

[0090] The second output subcircuit 20 includes a fifth transistor T5 and a second capacitor C2, the gate of the fifth transistor T5 is coupled to the second node PD, the first electrode of the fifth transistor T5 is coupled to the first clock signal input terminal, the second electrode of the fifth transistor T5 is coupled to the gate drive signal input terminal, the first terminal of the second capacitor C2 is coupled to the second node PD, and the second terminal of the second capacitor C2 is coupled to the gate drive signal output terminal. The second node PD controls whether the fifth transistor T5 is turned on.

[0091] Exemplarily, in the shift register, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 all include low-temperature polysilicon transistors, and the ninth transistor T9 and the tenth transistor T10 include oxide transistors, but are not limited to this.

[0092] An embodiment of the present invention further provides a gate driving circuit, comprising a plurality of cascaded shift registers provided by the above embodiments.

[0093] like Figure 7 and Figure 8 As shown, exemplarily, in two adjacent stages of shift registers, the gate drive signal output terminal GOUT_n of the upper stage shift register is coupled to the input signal terminal of the lower stage shift register.

[0094] Exemplarily, in two adjacent shift registers, the signal input to the first clock signal input terminal coupled to the previous shift register (e.g., GCB) is the same as the signal input to the second clock signal input terminal coupled to the next shift register (e.g., GCB), and the signal input to the second clock signal input terminal coupled to the previous shift register (e.g., GCK) is the same as the signal input to the first clock signal input terminal coupled to the next shift register (e.g., GCK), but is not limited to this.

[0095] Need to explain, Fig. 9 The frame start signal GSTV is also shown.

[0096] When the shift register provided by the above embodiment works, in the refresh phase P1, the clock signal input terminal coupled to the shift register is controlled to input a jumping clock signal, the first holding subcircuit 50 is controlled to conduct the electrical connection between the first node PU and the third node N3, and the second holding subcircuit 60 is controlled to conduct the electrical connection between the second node PD and the fourth node N4, so as to realize the driving function of the shift register. In the holding phase P2, the clock signal input terminal coupled to the shift register is controlled to input a first voltage signal maintaining a fixed potential, the first holding subcircuit 50 is controlled to disconnect the electrical connection between the first node PU and the third node N3, and the second holding subcircuit 60 is controlled to disconnect the electrical connection between the second node PD and the fourth node N4, so as to lock the voltage of the first node PU and the second node PD, and ensure the stability of the signal output by the gate drive signal output terminal. In the shift register provided by the above embodiment, the driving function of the shift register is guaranteed in the refresh phase P1. In the holding phase P2, the signal input at the clock signal input terminal is switched from a high-frequency jumping state to a fixed voltage holding state by controlling the signal input at the clock signal input terminal, thereby effectively reducing the power consumption of the shift register. At the same time, in the holding stage P2, the voltages of the first node PU and the second node PD are locked by the first holding sub-circuit 50 and the second holding sub-circuit 60, so as to prevent the voltages of the first node PU and the second node PD from shifting at the holding nodes, thereby ensuring the stability of the signal outputted by the gate drive signal output terminal. Therefore, when the gate drive circuit provided by the embodiment of the present invention includes the above-mentioned shift register, it can effectively reduce the power consumption generated by the gate drive circuit and ensure the stability of the output signal of the gate drive circuit.

[0097] An embodiment of the present invention further provides a display device, comprising the gate driving circuit provided by the above embodiment.

[0098] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0099] The gate driving circuit provided in the above embodiment can effectively reduce the power consumption generated by the gate driving circuit and ensure the stability of the output signal of the gate driving circuit. Therefore, the display device provided in the embodiment of the present invention also has the above beneficial effects when including the above gate driving circuit, which will not be repeated here.

[0100] The embodiment of the present invention further provides a shift register driving method, which is used to drive the shift register provided by the above embodiment. The driving method includes multiple driving cycles. In one driving cycle:

[0101] like Fig. 9 and Fig.10 As shown, in the holding phase P2, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a first voltage signal;

[0102] The first output sub-circuit 10, under the control of the first node PU, controls the electrical connection between the first level signal input terminal VGH and the gate drive signal output terminal; the second output sub-circuit 20, under the control of the second node PD, controls the electrical connection between the first clock signal input terminal and the gate drive signal output terminal to be disconnected; in at least part of the time period of the holding stage P2, the first holding sub-circuit 50, under the control of the control signal input terminal Vcon, is in the first working mode, keeping the voltage of the first node PU basically unchanged; the second holding sub-circuit 60, under the control of the control signal input terminal Vcon, is in the first working mode, keeping the voltage of the second node PD basically unchanged.

[0103] Illustratively, during at least part of the time period in the holding phase P2, the first holding sub-circuit 50, under the control of the control signal input terminal Vcon, controls the disconnection of the electrical connection between the first node PU and the third node N3; during at least part of the time period in the holding phase P2, the second holding sub-circuit 60, under the control of the control signal input terminal Vcon, controls the disconnection of the electrical connection between the second node PD and the fourth node N4.

[0104] Exemplarily, the first holding sub-circuit 50 includes a tenth transistor T10, the second holding sub-circuit 60 includes a ninth transistor T9, and the ninth transistor T9 and the tenth transistor T10 include oxide transistors; during at least part of the period in the holding phase P2, under the control of the control signal input terminal Vcon, the ninth transistor T9 and the tenth transistor T10 are turned off.

[0105] Exemplarily, a driving cycle includes a refresh phase P1 and a hold phase P2. In the refresh phase P1, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register input a clock signal, which is a high-frequency jump signal; under the control of the control signal input terminal Vcon, the ninth transistor T9 and the tenth transistor T10 are turned on. In the hold phase P2, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register input a first voltage signal; under the control of the control signal input terminal Vcon, the ninth transistor T9 and the tenth transistor T10 are turned off.

[0106] In the shift register provided in the above embodiment, the first holding sub-circuit 50 is set to be able to control the conduction or disconnection of the electrical connection between the first node PU and the third node N3 under the control of the control signal input terminal Vcon; the second holding sub-circuit 60 is able to control the conduction or disconnection of the electrical connection between the second node PD and the fourth node N4 under the control of the control signal input terminal Vcon.

[0107] When the driving method provided by the embodiment of the present invention is used to drive the shift register provided by the above embodiment, in the refresh phase P1, the clock signal input terminal coupled to the shift register is controlled to input a jumping clock signal, the first holding sub-circuit 50 is controlled to conduct the electrical connection between the first node PU and the third node N3, and the second holding sub-circuit 60 is controlled to conduct the electrical connection between the second node PD and the fourth node N4, so as to realize the driving function of the shift register. In the holding phase P2, the clock signal input terminal coupled to the shift register is controlled to input a first voltage signal maintaining a fixed potential, the first holding sub-circuit 50 is controlled to disconnect the electrical connection between the first node PU and the third node N3, and the second holding sub-circuit 60 is controlled to disconnect the electrical connection between the second node PD and the fourth node N4, so as to lock the voltages of the first node PU and the second node PD, and ensure the stability of the signal output by the gate drive signal output terminal.

[0108] Therefore, the driving method provided in the embodiment of the present invention is used to drive the shift register provided in the above embodiment, and the driving function of the shift register is guaranteed in the refresh phase P1. In the holding phase P2, the signal inputted into the clock signal input terminal is switched from the high-frequency jump state to the fixed voltage holding state by controlling the signal inputted into the clock signal input terminal, thereby effectively reducing the power consumption of the shift register. At the same time, in the holding phase P2, the voltages of the first node PU and the second node PD are locked by the first holding subcircuit 50 and the second holding subcircuit 60, thereby preventing the voltages of the first node PU and the second node PD from shifting at the holding nodes, thereby ensuring the stability of the signal outputted from the gate drive signal output terminal. Therefore, when the shift register provided in the embodiment of the present invention is applied to the gate drive circuit, the power consumption generated by the gate drive circuit part is effectively reduced.

[0109] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0110] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0111] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0112] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0113] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0114] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A shift register, characterized in that: include: A first node, a second node, a first output subcircuit, and a second output subcircuit; the shift register further includes a first holding subcircuit and / or a second holding subcircuit; The first output subcircuit is coupled to the first level signal input terminal, the gate drive signal output terminal and the first node respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the gate drive signal output terminal under the control of the first node; The second output subcircuit is coupled to the first clock signal input terminal, the gate drive signal output terminal and the second node respectively, and is used to control the conduction or disconnection of the electrical connection between the first clock signal input terminal and the gate drive signal output terminal under the control of the second node; The first holding subcircuit is coupled to the control signal input terminal and the first node respectively, and is used to keep the voltage of the first node substantially unchanged in the first working mode; The second holding subcircuit is coupled to the control signal input terminal and the second node respectively, and is used to keep the voltage of the second node substantially unchanged in the first working mode.

2. The shift register according to claim 1, characterized in that: The shift register further comprises a third node, a fourth node, a third node control subcircuit and a fourth node control subcircuit, wherein the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node; The first holding subcircuit includes a tenth transistor, a gate of the tenth transistor is coupled to the control signal input terminal, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the third node; The second holding subcircuit includes a ninth transistor, a gate of the ninth transistor is coupled to the control signal input terminal, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the fourth node.

3. The shift register according to claim 2, characterized in that: The ninth transistor and the tenth transistor include oxide transistors.

4. The shift register according to claim 1, wherein: The shift register further includes a fourth node and a fourth node control subcircuit, wherein the fourth node control subcircuit is used to control the potential of the fourth node; The shift register also includes: a third holding sub-circuit, which is coupled to the second level signal input terminal, the fourth node and the second holding sub-circuit respectively, and is used to control the conduction or disconnection of the electrical connection between the fourth node and the second holding sub-circuit under the control of the second level signal input terminal.

5. The shift register according to claim 4, characterized in that: The third holding subcircuit includes an eighth transistor, a gate of the eighth transistor is coupled to the second level signal input terminal, a first electrode of the eighth transistor is coupled to the second holding subcircuit, and a second electrode of the eighth transistor is coupled to the fourth node.

6. The shift register according to claim 1, characterized in that: The shift register further comprises a third node, a fourth node, a third node control subcircuit and a fourth node control subcircuit, wherein the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node; The third node control subcircuit is coupled to the second clock signal input terminal, the second level signal input terminal, the third node and the fourth node respectively, and is used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node under the control of the second clock signal input terminal; It is also used to control the conduction or disconnection of the electrical connection between the second clock signal input terminal and the third node under the control of the fourth node.

7. The shift register according to claim 6, characterized in that: The third node control subcircuit includes a second transistor and a third transistor; The gate of the second transistor is coupled to the fourth node, the first electrode of the second transistor is coupled to the second clock signal input terminal, and the second electrode of the second transistor is coupled to the third node; A gate of the third transistor is coupled to the second clock signal input terminal, a first electrode of the third transistor is coupled to the second level signal input terminal, and a second electrode of the third transistor is coupled to the third node.

8. The shift register according to claim 1, characterized in that: The shift register further comprises a third node, a fourth node, a third node control subcircuit and a fourth node control subcircuit, wherein the third node control subcircuit is used to control the potential of the third node, and the fourth node control subcircuit is used to control the potential of the fourth node; The fourth node control subcircuit is coupled to the input signal terminal, the first clock signal input terminal, the second clock signal input terminal, the first level signal input terminal, the third node and the fourth node respectively; and is used to control the conduction or disconnection of the electrical connection between the input signal terminal and the fourth node under the control of the second clock signal input terminal; It is also used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the fourth node under the common control of the third node and the first clock signal input terminal.

9. The shift register according to claim 8, characterized in that: The fourth node control subcircuit includes a first transistor, a sixth transistor and a seventh transistor; The gate of the first transistor is coupled to the second clock signal input terminal, the first electrode of the first transistor is coupled to the input signal terminal, and the second electrode of the first transistor is coupled to the fourth node; The gate of the sixth transistor is coupled to the third node, the first electrode of the sixth transistor is coupled to the first level signal input terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor; A gate of the seventh transistor is coupled to the first clock signal input terminal, and a second electrode of the seventh transistor is coupled to the fourth node.

10. The shift register according to claim 1, characterized in that: The first output subcircuit includes a fourth transistor and a first capacitor, the gate of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the first level signal input terminal, and the second electrode of the fourth transistor is coupled to the gate drive signal output terminal; the first terminal of the first capacitor is coupled to the first level signal input terminal, and the second terminal of the first capacitor is coupled to the first node; The second output subcircuit includes a fifth transistor and a second capacitor, the gate of the fifth transistor is coupled to the second node, the first electrode of the fifth transistor is coupled to the first clock signal input terminal, the second electrode of the fifth transistor is coupled to the gate drive signal input terminal, the first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the gate drive signal output terminal.

11. A gate drive circuit, characterized in that: The invention comprises a plurality of shift registers according to any one of claims 1 to 10 connected in cascade.

12. A display device, characterized in that: Comprising the gate driving circuit as claimed in claim 11.

13. A shift register driving method, characterized in that: Used to drive the shift register according to any one of claims 1 to 10, the driving method comprises a plurality of driving cycles, in one driving cycle: In the holding phase, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a first voltage signal; The first output sub-circuit, under the control of the first node, controls to conduct the electrical connection between the first level signal input terminal and the gate drive signal output terminal; The second output subcircuit, under the control of the second node, controls the disconnection of the electrical connection between the first clock signal input terminal and the gate drive signal output terminal; during at least part of the holding phase, the first holding subcircuit, under the control of the control signal input terminal, is in the first operating mode, keeping the voltage of the first node basically unchanged; the second holding subcircuit, under the control of the control signal input terminal, is in the first operating mode, keeping the voltage of the second node basically unchanged.

14. The driving method of the shift register according to claim 13, characterized in that: The first holding subcircuit includes a tenth transistor, the second holding subcircuit includes a ninth transistor, the ninth transistor and the tenth transistor include oxide transistors; During at least a portion of the holding phase, under the control of the control signal input terminal, the ninth transistor and the tenth transistor are turned off.

15. The shift register driving method according to claim 13, characterized in that: In a drive cycle: In the refresh phase, the first clock signal input terminal and / or the second clock signal input terminal coupled to the shift register inputs a clock signal; under the control of the control signal input terminal, the ninth transistor and the tenth transistor are turned on.

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