Display panel and display device

Abstract

The invention discloses a display panel and a display device, the display panel comprises a driving circuit, the driving circuit comprises N levels of shift registers which are cascaded with each other, and N is greater than or equal to 2; the shift register comprises a first control part and a second control part; the first control part controls a first output signal, and the first output signal of the ith-stage shift register is a first input signal of the jth-stage shift register; the first control part comprises a first node, and the potential of the first node is synchronous with the first output signal; the second control part at least receives a potential signal and a frequency control signal of the first node and controls a second output signal; the process that the first output signal jumps from the ineffective level to the effective level is a first voltage edge; when the first voltage edge of the first output signal is overlapped with the effective pulse of the frequency control signal, the second output signal is the effective pulse. According to the display panel, the refresh rates of different areas of the display panel are adjusted, so that the display panel applies different refresh rates in different areas, and the power consumption is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work.

[0003] The main component of an electronic device to realize the display function is the display panel. The current display panel has the function of zoned frequency modulation, that is, different areas of the display area can have different refresh frequencies, so as to reduce the panel power consumption by reducing the refresh frequency of some areas. However, the shift register circuit in the display panel with the zoned frequency modulation adjustment function will use both N-type transistors and P-type transistors. On the one hand, the separate preparation of N-type transistors and P-type transistors will increase the difficulty and process of preparation, and the corresponding occupied frame area is also larger, which is not conducive to the narrow frame design of the display panel. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device to achieve partition refresh at any position of the display panel, save display power consumption, ensure normal display of the picture, and further compress the frame space.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0006] A driving circuit, the driving circuit comprising N stages of shift registers cascaded to each other, N≥2;

[0007] The shift register comprises:

[0008] a first control unit and a second control unit, wherein the first control unit is electrically connected to the second control unit;

[0009] The first control unit is used to control a first output signal, the first output signal of the i-th stage shift register is the first input signal of the j-th stage shift register, 1≤i≤N, 2≤j≤N; the first control unit includes a first node, the potential of the first node is synchronized with the first output signal;

[0010] The second control unit receives at least a frequency control signal and a potential signal of the first node to control a second output signal;

[0011] The process in which the first output signal jumps from an invalid level to a valid level is a first voltage edge;

[0012] When the first voltage edge of the first output signal overlaps with a valid pulse of the frequency control signal, the second output signal is a valid pulse.

[0013] In a second aspect, an embodiment of the present invention further provides a display device, comprising a display panel as described in any one of the first aspects.

[0014] An embodiment of the present invention provides a display panel and a display device. The display panel can realize the cascade of at least two levels of first control units by setting a first control unit and a second control unit in a shift register, using the first control unit to control the first output signal, and making the first output signal of the i-th level shift register the first input signal of the j-th level shift register; at the same time, the second control unit is used to receive at least a frequency control signal and a potential signal of a first node, and control the second output signal to output a valid pulse when the first voltage edge of the first output signal overlaps with the valid pulse of the frequency control signal. In this way, the frequency control signal can be used to realize the conversion of the valid pulse and the invalid pulse of the second output signal, thereby controlling the pixel circuit and realizing the adjustment of the refresh frequency of different areas of the display panel, so that the display panel applies different refresh rates in different areas, and the high refresh rate signal cannot be normally output in the low refresh rate area, thereby realizing local frequency reduction and saving power consumption, and the position of the display panel that needs to be refreshed can be freely defined, and can be displayed at multiple different frequencies at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of a shift register in the related art;

[0016] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 3 yes Figure 2 A schematic diagram of the structure of a driving circuit in the display panel shown;

[0018] Figure 4 yes Figure 3 A schematic diagram of the structure of a shift register in the driving circuit shown;

[0019] Figure 5 yes Figure 3 A driving timing diagram of each level of shift register in the driving circuit shown;

[0020] Figure 6 yes Figure 3 Another driving timing diagram of each level of shift register in the driving circuit shown;

[0021] Figure 7-Figure 12 is a schematic structural diagram of six pixel circuits provided by an embodiment of the present invention;

[0022] Fig.13 and Fig.14 is a driving timing diagram of two display panels provided by an embodiment of the present invention;

[0023] Fig.15 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0024] Fig.16 is a schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0025] Fig.17 and Fig.18 yes Fig.16 The driving timing diagram of the two shift registers shown;

[0026] Fig.19 1 is a schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention;

[0027] Fig. 20 yes Fig.19 A driving timing diagram of the second control unit in the shift register shown;

[0028] Fig.21 yes Fig.19 Another driving timing diagram of the second control unit in the shift register shown;

[0029] Fig. 22 is a schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0030] Fig.23 yes Fig. 22 A driving timing diagram of the second control unit in the shift register shown;

[0031] Fig.24 yes Fig. 22 Another driving timing diagram of the second control unit in the shift register shown;

[0032] Fig.25 It is a circuit structure diagram of another shift register provided by an embodiment of the present invention;

[0033] Fig.26 yes Fig.25 A driving timing diagram of the second control unit in the shift register shown;

[0034] Fig. 27 is a driving timing diagram of a first control unit in a shift register provided by an embodiment of the present invention;

[0035] Fig.28 It is a circuit structure diagram of another shift register provided by an embodiment of the present invention;

[0036] Fig.29 yes Figure 3 Another driving timing diagram of each level of shift register in the driving circuit shown;

[0037] Fig.30 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0039] In the related art, the display panel includes a display area and a non-display area, wherein the non-display area is provided with a driving circuit, and the display area includes a plurality of pixel circuits arranged in an array and light-emitting elements electrically connected to the pixel circuits one by one. The driving circuit sequentially provides a driving signal to each row of pixel circuits through a scanning signal line, and the pixel circuit controls the corresponding electrically connected light-emitting elements to light up according to the driving signal. In a display frame, the light-emitting elements in the display area are sequentially controlled to light up, and by matching the colors of adjacent light-emitting elements of different colors, a specific pixel can be realized, and then the entire picture can be displayed macroscopically.

[0040] Figure 1 It is a structural diagram of a shift register in the related art, such as Figure 1 As shown, the driving circuit in the non-display area is provided with a cascaded multi-stage shift register circuit 10', and a gating circuit 20' is also provided for each stage of the shift register circuit 10'. The output end of each stage of the gating circuit 20' is connected to at least one row of pixel circuits through at least one scanning signal line. Figure 1 It can be understood as a circuit structure diagram of any level of shift register circuit 10' and the corresponding gating circuit 20'. The shift register circuit 10' is responsible for outputting the scan pulse signal SN_NEXT of each level, and the gating circuit 20' is correspondingly connected to the output end of the shift register circuit 10', for receiving the scan pulse signal SN_NEXT, and selectively outputting the scan pulse signal SN_NEXT through the control of the frequency control signal SN_CTRL. Therefore, the output frequency control of the scan pulse signal SN_NEXT can be achieved through the frequency control signal SN_CTRL to change the refresh frequency of the corresponding connected pixel row, thereby controlling different partitions of the display panel to have different refresh frequencies, realizing the partition frequency division function of the display panel, and adapting to the display power consumption requirements of different display scenarios.

[0041] However, continue to refer to Figure 1 , Figure 1 It is only a structural schematic diagram of the shift register circuit 10' and the corresponding gating circuit 20'. It can be clearly seen that there are both N-type transistors and P-type transistors in the circuit structure schematic diagram of the gating circuit 20'. On the one hand, when preparing the gating circuit 20' in the display panel, it is necessary to prepare the IGZO (Indium Gallium Zinc Oxide) semiconductor layer corresponding to the N-type transistor and the LTPS (Low-Temperature Polycrystalline Silicon) semiconductor layer corresponding to the P-type transistor, which will greatly increase the difficulty and process of the film preparation process. On the other hand, the circuit structure of the gating circuit 20' is located in the non-display area, the mobility of the IGZO semiconductor layer is low, and the size of the N-type transistor needs to be relatively larger. For example, the size of the N-type transistor (for example, the third transistor M3) near the output terminal SN_OUT of the gating circuit 20' needs to be relatively large, which requires a high frame space and is not conducive to the narrow frame design of the display panel. On the other hand, the stability of the IGZO semiconductor layer is not good, and the attenuation of the N-type transistor will cause the output capacity to become weak, and even cause the entire circuit to fail.

[0042] Based on the above technical problem, an embodiment of the present invention provides a display panel. The display panel includes:

[0043] A driving circuit, the driving circuit includes N stages of shift registers cascaded to each other, N≥2;

[0044] The shift register consists of:

[0045] A first control unit and a second control unit, the first control unit is electrically connected to the second control unit;

[0046] The first control unit is used to control the first output signal, the first output signal of the i-th stage shift register is the first input signal of the j-th stage shift register, 1≤i≤N, 2≤j≤N; the first control unit includes a first node, the potential of the first node is synchronized with the first output signal;

[0047] The second control unit receives at least the frequency control signal and the potential signal of the first node, and controls the second output signal;

[0048] The process of the first output signal jumping from the invalid level to the valid level is the first voltage edge;

[0049] When the first voltage edge of the first output signal overlaps with the effective pulse of the frequency control signal, the second output signal is a effective pulse.

[0050] According to the technical solution in the embodiment of the present invention, the display panel can realize the cascade of at least two levels of first control units by setting a first control unit and a second control unit in a shift register, using the first control unit to control the first output signal, and making the first output signal of the i-th level shift register the first input signal of the j-th level shift register; at the same time, the second control unit is used to receive at least the frequency control signal and the potential signal of the first node, and control the second output signal to output a valid pulse when the first voltage edge of the first output signal overlaps with the valid pulse of the frequency control signal. In this way, the frequency control signal can be used to realize the conversion of the valid pulse and the invalid pulse of the second output signal, thereby controlling the pixel circuit and realizing the adjustment of the refresh frequency of different areas of the display panel, so that the display panel applies different refresh rates in different areas, and the high refresh rate signal cannot be normally output in the low refresh rate area, thereby realizing local frequency reduction and saving power consumption, and the position of the display panel that needs to be refreshed can be freely defined, and can be displayed at multiple different frequencies at the same time.

[0051] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 3 yes Figure 2 The schematic diagram of the structure of the driving circuit in the display panel is shown in FIG. Figure 4 yes Figure 3 The schematic diagram of the structure of the shift register in the driving circuit shown in FIG. Figure 5 yes Figure 3 A driving timing diagram of each level of shift register in the driving circuit shown in FIG. Figure 2-Figure 5As shown, the display panel includes a driving circuit 100, the driving circuit 100 includes N-stage shift registers 110 cascaded with each other, N≥2; the shift register 110 includes: a first control unit 10 and a second control unit 20, the first control unit 10 is electrically connected to the second control unit 20; the first control unit 10 is used to control a first output signal SN_NEXT1, the first output signal SN_NEXT1 of the i-th stage shift register 110 is the first input signal SN_IN1 of the j-th stage shift register 110, 1≤i≤N, 2≤j≤N; the first control unit 10 is used to control a first output signal SN_NEXT1, the first output signal SN_NEXT1 of the i-th stage shift register 110 is the first input signal SN_IN1 of the j-th stage shift register 110, 1≤i≤N, 2≤j≤N; The part 10 includes a first node N1, and the potential of the first node N1 is synchronized with the first output signal SN_NEXT1; the second control part 20 receives at least the frequency control signal SN_CTRL and the potential signal of the first node N1, and controls the second output signal SN_OUT; the process of the first output signal SN_NEXT1 jumping from an invalid level to a valid level is a first voltage edge; when the first voltage edge of the first output signal SN_NEXT1 overlaps with the valid pulse of the frequency control signal SN_CTRL, the second output signal SN_OUT is a valid pulse.

[0053] Specifically, by Figure 2 and Figure 3 It can be seen that at least two stages of shift registers 110 are provided in the driving circuit 100 of the display panel. The at least two stages of shift registers 110 form a cascade connection, that is, the output signal of a certain stage of shift register 110 is the input signal of a certain stage of shift register 110 below. For example, Figure 3 The output signal of the adjacent upper-stage shift register 110 in the example is the input signal of the next-stage shift register 110. In the embodiment of the present invention, the shift register 110 is provided with a first control unit 10 and a second control unit 20 electrically connected, wherein the first control unit 10 in each stage of the shift register 110 actually forms the above-mentioned cascade relationship, that is, the first output signal SN_NEXT1 output by the first control unit 10 in a certain stage of the shift register 110 is the input signal of the first control unit 10 in the next stage of the shift register 110.

[0054] The first control unit 10 includes a first node N1, and the potential of the first node N1 is synchronized with the first output signal SN_NEXT1. In this way, the potential change of the first output signal SN_NEXT1 can be replaced by the potential change of the first node N1. The output end of the first output signal SN_NEXT1 output by the first control unit 10 can be electrically connected to the second control unit 20, or the first node N1 in the first control unit 10 can also be electrically connected to the second control unit 20. It should be noted that in this embodiment, the node in the first control unit 10 is essentially led out as the first node N1. Its specific position and connection relationship in the first control unit 10 will be described in detail later, and will not be explained here. For the second control unit 20 in each stage of the shift register 110, that is, on the basis of the first output signal SN_NEXT1 provided by the first control unit 10 as the control signal of the second control unit 20, the additional input frequency control signal SN_CTRL is used to control the gating, so as to control whether the first output signal SN_NEXT1 provided by the first control unit 10 is output to form the second output signal SN_OUT.

[0055] First of all, it should be noted that the effective pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned on, connected, and working, and the invalid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be disconnected, cut off, and not working, such as Figure 5The valid pulses of the first output signal SN_NEXT1, the second output signal SN_OUT and the frequency control signal SN_CTRL shown are all exemplified as high levels, and the invalid pulses are all exemplified as low levels, and the first voltage edge of the first output signal SN_NEXT1 is the rising edge here. Specifically, taking the first output signal SN_NEXT1_j of the j-th stage shift register 110 as an example, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting a valid pulse when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the valid pulse (high level) of the frequency control signal SN_CTRL, thereby forming the second output signal SN_OUT (high level). In a more convenient way to understand, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for controlling the first output signal SN_NEXT1 The time period corresponding to the first voltage edge (rising edge) is completely within the effective pulse (high level) time period of the frequency control signal SN_CTRL. Output, forming the second output signal SN_OUT (high level). More specifically, it can be understood that when the first voltage edge (rising edge) of the first output signal SN_NEXT1 is completely covered by the effective pulse (high level) of the frequency control signal SN_CTRL, the second control unit 20 will output the effective pulse (high level) of the first output signal SN_NEXT1. Therefore, the embodiment of the present invention can at least ensure that when the time period corresponding to the first voltage edge of the first output signal SN_NEXT1 is within the effective pulse time period of the frequency control signal SN_CTRL, the second output signal SN_OUT outputs a complete effective pulse, so that the pixel circuit 200 can always receive a normal driving signal, ensuring the normal operation of the pixel circuit 200 and displaying a normal picture.

[0056] And, taking the first output signal SN_NEXT1_h of the h-th stage shift register 110 as an example, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting a valid pulse by the second control unit 20 to form a second output signal SN_OUT (high level) when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the valid pulse (high level) of the frequency control signal SN_CTRL. It should also be noted that after the first voltage edge (rising edge) of the first output signal SN_NEXT1, that is, the first output signal SN_NEXT1 is a valid pulse (high level) and will overlap with the transition voltage edge of the frequency control signal SN_CTRL from a valid pulse (high level) to an invalid pulse (low level), at which time the second output signal SN_OUT still maintains a valid pulse (high level) output, and the transition voltage edge of the frequency control signal SN_CTRL will not cut off the second output signal SN_OUT.

[0057] Optionally, continue to refer to Figure 5 When the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, the second output signal SN_OUT is an invalid pulse.

[0058] Specifically, taking the first output signal SN_NEXT1_i of the i-th stage shift register 110 as an example, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse by the second control unit 20 to form a second output signal SN_OUT (low level) when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the invalid pulse (low level) of the frequency control signal SN_CTRL. It should also be noted that after the first voltage edge (rising edge) of the first output signal SN_NEXT1, that is, the first output signal SN_NEXT1 is a valid pulse (high level) and will overlap with the transition voltage edge of the frequency control signal SN_CTRL from the invalid pulse (low level) to the valid pulse (high level), at which time the second output signal SN_OUT still maintains the invalid pulse (low level) output, and the transition voltage edge of the frequency control signal SN_CTRL will not cut off the second output signal SN_OUT. In a more convenient way to understand, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for controlling the first output signal SN_NEXT1 to output an invalid pulse completely in the invalid pulse (low level) time period of the frequency control signal SN_CTRL, thereby forming the second output signal SN_OUT (low level). More specifically, it can be understood that when the first voltage edge (rising edge) of the first output signal SN_NEXT1 is not completely covered by the valid pulse (high level) of the frequency control signal SN_CTRL, the second control unit 20 will not output the valid pulse (high level) of the first output signal SN_NEXT1. Therefore, in the embodiment of the present invention, the second control unit 20 and the frequency control signal SN_CTRL can at least ensure that when the time period corresponding to the first voltage edge of the first output signal SN_NEXT1 is in the invalid pulse time period of the frequency control signal SN_CTRL, the second output signal SN_OUT outputs an invalid pulse, so that the corresponding pixel circuit 200 cannot receive a normal driving signal, and different refresh frequencies can be achieved in different areas, that is, the display panel can perform zoned frequency display.

[0059] Optionally, continue to refer to Figure 5 , when the first output signal SN_NEXT1 is an invalid pulse, the second output signal SN_OUT is an invalid pulse.

[0060] Specifically, taking the first output signal SN_NEXT1_k of the k-th stage shift register 110 as an example, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse to form the second output signal SN_OUT (low level) when the first output signal SN_NEXT1 is an invalid pulse (low level). In other words, when the first output signal SN_NEXT1 has no first voltage edge, the second control unit 20 outputs an invalid pulse to form the second output signal SN_OUT (low level). In a more understandable way, when the first output signal SN_NEXT1 is an invalid pulse, there is no need to determine whether it overlaps with the valid pulse or invalid pulse of the frequency control signal SN_CTRL, and the second output signal SN_OUT is quickly determined to be an invalid pulse.

[0061] It should be noted that, in this embodiment, no special requirements or specific limitations are made on the valid pulses and invalid pulses of the first output signal SN_NEXT1, the second output signal SN_OUT, and the frequency control signal SN_CTRL. In addition, illustratively, Figure 6 yes Figure 3 Another driving timing diagram of each level of shift register in the driving circuit shown in the figure, the effective pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned on, connected, and working, and the invalid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned off, cut off, and not working, such as Figure 6 The valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT are shown as high levels, and the invalid pulses are shown as low levels, while the valid pulses of the frequency control signal SN_CTRL are shown as low levels, and the invalid pulses are shown as high levels. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. Specifically, taking the first output signal SN_NEXT1_o of the o-th stage shift register 110 as an example, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting a valid pulse by the second control unit 20 to form the second output signal SN_OUT (high level) when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the valid pulse (low level) of the frequency control signal SN_CTRL. It should also be noted that after the first voltage edge (rising edge) of the first output signal SN_NEXT1, that is, when the first output signal SN_NEXT1 is a valid pulse (high level), it will overlap with the voltage edge of the frequency control signal SN_CTRL jumping from a valid pulse (low level) to an invalid pulse (high level). At this time, the second output signal SN_OUT still maintains a valid pulse (high level) output, and the voltage edge of the frequency control signal SN_CTRL jumping will not cut off the second output signal SN_OUT.

[0062] Taking the first output signal SN_NEXT1_p of the p-th stage shift register 110 as an example, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse to form a second output signal SN_OUT (low level) when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the invalid pulse (high level) of the frequency control signal SN_CTRL. Taking the first output signal SN_NEXT1_q of the q-th stage shift register 110 as an example, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse to form a second output signal SN_OUT (low level) when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the invalid pulse (high level) of the frequency control signal SN_CTRL. It should also be noted that after the first voltage edge (rising edge) of the first output signal SN_NEXT1, that is, when the first output signal SN_NEXT1 is a valid pulse (high level), it will overlap with the voltage edge of the frequency control signal SN_CTRL jumping from an invalid pulse (high level) to a valid pulse (low level). At this time, the second output signal SN_OUT still maintains an invalid pulse (low level) output, and the voltage edge of the frequency control signal SN_CTRL jumping will not cut off the second output signal SN_OUT.

[0063] Taking the first output signal SN_NEXT1_r of the r-th stage shift register 110 as an example, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse to form a second output signal SN_OUT (low level) when the first output signal SN_NEXT1 is an invalid pulse (low level). In other words, when the first output signal SN_NEXT1 does not have a first voltage edge, the second control unit 20 outputs an invalid pulse. To summarize, the first output signal SN_NEXT1 of the shift register 110 can always maintain a high refresh rate. When the first voltage edge of the first output signal SN_NEXT1 overlaps with the valid pulse of the frequency control signal SN_CTRL, the second output signal SN_OUT is the same as the first output signal SN_NEXT1, and the second output signal SN_OUT is output to the corresponding pixel circuit 200. When the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, or when the first output signal SN_NEXT1 is an invalid pulse, the second output signal SN_OUT is an invalid pulse, thereby achieving a local low refresh rate and realizing the partition refresh design of the display panel.

[0064] Optionally, continue to refer to Figure 5 and Figure 6, the pulse change frequency of the first output signal SN_NEXT1 is F1, and the pulse change frequency of the second output signal SN_OUT is F2; ​​wherein, F1≥F2.

[0065] Specifically, the second control unit 20 and the frequency control signal SN_CTRL are responsible for limiting the output of some valid pulses based on the first output signal SN_NEXT1 output by the first control unit 10. It can be seen that within the same time period, the number of valid pulses of the second output signal SN_OUT output by the second control unit 20 will definitely not exceed the number of valid pulses in the first output signal SN_NEXT1, that is, within the time period, the pulse change frequency F2 of the second output signal SN_OUT will definitely not exceed the pulse change frequency F1 of the first output signal SN_NEXT1, that is, F2≤F1.

[0066] Further, continue to refer to Figure 5 When the first voltage edge of the first output signal SN_NEXT1 overlaps with the valid pulse of the frequency control signal SN_CTRL, or when the first output signal SN_NEXT1 is an invalid pulse, F1=F2; when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, F1>F2.

[0067] Specifically, for the first output signal SN_NEXT1_j of the j-th shift register 110 or the first output signal SN_NEXT1_h of the h-th shift register 110, when the time period corresponding to the first voltage edge is within the valid pulse time period of the frequency control signal SN_CTRL, at this time, the second control unit 20 outputs a valid pulse, and the number of valid pulses is the same as the number of valid pulses of the first output signal SN_NEXT1, so the pulse change frequency is consistent, F2 = F1. Alternatively, for the first output signal SN_NEXT1_k of the k-th shift register 110, when the first output signal SN_NEXT1 is an invalid pulse, regardless of whether it is within the valid pulse time period of the frequency control signal SN_CTRL, at this time, the second control unit 20 outputs an invalid pulse, and the number of valid pulses is the same as the number of valid pulses of the first output signal SN_NEXT1, so the pulse change frequency is consistent, F2 = F1. For the first output signal SN_NEXT1_i of the i-th stage shift register 110, when the first voltage along the corresponding time period is located in the invalid pulse time period of the frequency control signal SN_CTRL, at this time, the second control unit 20 outputs an invalid pulse, and the number of valid pulses is less than the number of valid pulses of the first output signal SN_NEXT1, so its pulse change frequency is reduced, F2<F1.

[0068] Continue to refer Figure 5 and Figure 6In one embodiment, during at least a portion of the time period when the display panel is operating, when the first output signal SN_NEXT1 is a valid pulse, the second output signal SN_OUT is a valid pulse. In addition, in another embodiment, during at least a portion of the time period when the display panel is operating, when the first output signal SN_NEXT1 is a valid pulse, the second output signal SN_OUT is an invalid pulse.

[0069] Among them, during at least part of the time period when the display panel is working, there are both valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT, which means that during this time period, the first voltage of the first output signal SN_NEXT1 is located in the time period of the valid pulse of the frequency control signal SN_CTRL along the corresponding time period, so that the second output signal SN_OUT can provide a valid pulse to the display panel, thereby driving the corresponding pixel circuit 200 in the display panel to work normally. In other words, during at least part of the time period when the display panel is working, there are the first output signal SN_NEXT1 as a valid pulse and the second output signal SN_OUT as an invalid pulse, which means that during this time period, the first voltage of the first output signal SN_NEXT1 is located in the time period of the invalid pulse of the frequency control signal SN_CTRL along the corresponding time period, at this time, the second output signal SN_OUT provides an invalid pulse to the display panel, thereby driving the corresponding pixel circuit 200 in the display panel to stop working. Also, during at least part of the time period when the display panel is working, the first output signal SN_NEXT1 is an invalid pulse, and the corresponding second output signal SN_OUT is always an invalid pulse, which means that during this time period, regardless of the relationship between the effective pulse time periods of the first output signal SN_NEXT1 and the frequency control signal SN_CTRL, at this time, the second output signal SN_OUT provides an invalid pulse to the display panel, thereby driving the corresponding pixel circuit 200 in the display panel to stop working. In this way, the display panel driving frequency can be controlled, the partition refresh effect can be achieved, and the display effect or driving power consumption can be improved. Or when the first output signal SN_NEXT1 is an invalid pulse,

[0070] Optionally, Figure 7-Figure 12 is a schematic diagram of the structure of six pixel circuits provided by an embodiment of the present invention, referring to Figure 2 , Figure 7-Figure 12 The display panel also includes a pixel circuit 200, and the second output signal SN_OUT of the driving circuit 100 is a control signal of a preset module of the pixel circuit 200; when the second output signal SN_OUT is a valid pulse, the preset module is turned on; when the second output signal SN_OUT is an invalid pulse, the preset module is turned off.

[0071] Specifically, refer to Figure 7-Figure 12The pixel circuit 200 shown in the figure introduces the process of the driving circuit 100 driving the preset module therein. Firstly, those skilled in the art will know that Figure 7-Figure 12 The pixel circuit 200 shown may include a data writing module 210, a driving module 220, and a compensation module 230; the driving module 220 includes a driving transistor T2, and the driving transistor T2 is used to provide a driving current for the light-emitting element 300 of the display panel 100; the data writing module 210 is connected to the first electrode (i.e., the N02 node) of the driving transistor T2, and is used to provide a data signal to the driving transistor T2; the compensation module 230 is connected between the gate (i.e., the N01 node) and the second electrode (i.e., the N03 node) of the driving transistor T2, and is used to compensate for the threshold voltage of the driving transistor T2.

[0072] In addition, the pixel circuit 200 may also include a reset module 250 for providing a reset signal Vref for the gate of the driving transistor T2; an initialization module 260 for providing an initialization signal Vini for the light-emitting element 300; and a light-emitting control module 270 for selectively allowing the light-emitting element 300 to enter a light-emitting stage. Optionally, the light-emitting control module 270 includes a first light-emitting control module 271 and a second light-emitting control module 272. The first light-emitting control module 271 is connected between the first power supply signal terminal and one pole of the driving transistor T2, and the second light-emitting control module 272 is connected between the other pole of the driving transistor T2 and the light-emitting element 300.

[0073] The control end of the data writing module 210 receives a first scanning signal S1, which controls the opening and closing of the data writing module 210; the control end of the compensation module 230 receives a second scanning signal S2, which controls the opening and closing of the compensation module 230; the control end of the reset module 250 receives a third scanning signal S3, which controls the opening and closing of the reset module 250; the control end of the initialization module 260 receives a fourth scanning signal S4, which controls the opening and closing of the initialization module 260; the control end of the light-emitting control module 270 receives a light-emitting control signal EM, which controls the opening and closing of the light-emitting control module 270.

[0074] The data writing module 210 includes a data writing transistor T1, and the first scanning signal S1 controls the turning on and off of the data writing transistor T1; the compensation module 230 includes a compensation transistor T3, and the second scanning signal S2 controls the turning on and off of the compensation transistor T3; the reset module 250 includes a reset transistor T5, and the third scanning signal S3 controls the turning on and off of the reset transistor T5; the initialization module 260 includes an initialization transistor T6, and the fourth scanning signal S4 controls the turning on and off of the initialization transistor T6; the first light-emitting control module 271 includes a first light-emitting control transistor T7, and the second light-emitting control module 272 includes a second light-emitting control transistor T8, and the light-emitting control signal EM controls the turning on and off of the first light-emitting control transistor T7 and the second light-emitting control transistor T8.

[0075] It should be noted that if Figure 9-12 As shown, the pixel circuit 200 may further include a bias adjustment module 240 for providing a bias adjustment signal for the driving transistor T2. Fig. 9 and Fig.11 As shown, the bias adjustment module 240 is connected to the first electrode (ie, node N02) of the driving transistor T2; Fig.10 and Fig.12 As shown, the bias adjustment module 240 is connected to the second electrode (i.e., node N03) of the driving transistor T2. Optionally, the control end of the bias adjustment module 240 receives a bias adjustment control signal SV, and the bias adjustment control signal SV controls the on and off of the bias adjustment module 240; the bias adjustment module 240 includes a bias adjustment transistor T4, and the bias adjustment control signal SV controls the on and off of the bias adjustment transistor T4.

[0076] In addition, it should be noted that if Figure 7 , Fig. 9 , Fig.11 In the pixel circuit 200 shown, the driving transistor T2 is a PMOS transistor. The pixel circuit 200 further includes a storage capacitor C1, a first electrode of the storage capacitor C1 is connected to the first power signal terminal, and a second electrode of the storage capacitor C1 is connected to the gate of the driving transistor T2, for storing the signal transmitted to the gate of the driving transistor T2. Figure 8 , Fig.10 , Fig.12 In the pixel circuit 200 shown, the driving transistor T2 is an NMOS transistor. The pixel circuit 200 further includes a storage capacitor C1, a first electrode of the storage capacitor C1 is connected to the light emitting element 300, and a second electrode is connected to the gate of the driving transistor T2, for storing a signal transmitted to the gate of the driving transistor T2.

[0077] In this embodiment, the pixel unit receives power signals PVDD and PVEE, and controls the driving current through the potential difference between the power signals PVDD and PVEE, and the data signal Vdata written into the gate of the driving transistor T2, thereby driving the light-emitting element 300 to emit light. The PVDD signal can be a positive power signal, and the PVEE signal can be a negative power signal.

[0078] also, Figure 7-Figure 12 The structures of several pixel circuits 200 are provided for illustrative purposes only, but not all of them are included. Other pixel circuits 200 whose power supply signals PVDD and PVEE meet the requirements of this application are within the scope of protection of the embodiments of this application and will not be described in detail in this embodiment.

[0079] Based on the above-mentioned various types of pixel circuits 200, the driving circuit 100 in the embodiment of the present invention can provide control signals to the data writing module 210, the driving module 220, the compensation module 230, the reset module 250, the initialization module 260, the bias adjustment module 240 or the light emitting control module 270, that is, the preset module of the above pixel circuit 200 can be any one of the data writing module 210, the driving module 220, the compensation module 230, the reset module 250, the initialization module 260, the bias adjustment module 240 or the light emitting control module 270, and the second output signal SN_OUT of the driving circuit 100 can be a control signal of at least one of the above modules. Taking the second output signal SN_OUT of the driving circuit 100 as the control signal of the data writing module 210 as an example, the driving principle of the pixel circuit 200 is introduced below.

[0080] Continue to refer Figure 5Generally, the shift registers 110 of different levels will provide driving signals to the pixel circuits 200 of different rows, that is, provide data writing control signals to the data writing modules 210 in the pixel circuits 200 of different rows. Taking the i-th level shift register 110 as an example, when the first voltage of the first output signal SN_NEXT1_i is located in the valid pulse time period of the frequency control signal SN_CTRL along the corresponding time period, the second output signal SN_OUT outputs a valid pulse. At this time, the data writing module 210 is turned on, the pixel circuit 200 starts to write the data signal, and the storage capacitor C1 starts to charge. In addition, since the valid pulse output by the second output signal SN_OUT is a complete valid pulse, the storage capacitor C1 can be fully charged, so that the light-emitting element 300 can emit light normally as required during the light-emitting stage. For the j-th shift register 110, when the time period corresponding to the first voltage edge of its first output signal SN_NEXT1_j is within the invalid pulse time period of the frequency control signal SN_CTRL, and when the k-th shift register 110 has no corresponding first voltage edge, the second output signal SN_OUT outputs an invalid pulse, and the data writing module 210 cannot be turned on, and the charging process cannot be realized, that is, the corresponding light-emitting element 300 cannot emit light. It can be seen that the shift register 110 can realize the control of whether the light-emitting elements 300 in different rows emit light.

[0081] Those skilled in the art will know that for other modules in the pixel circuit 200, their opening process in each data refresh cycle directly affects whether the pixel circuit 200 can drive the corresponding light-emitting element 300 to emit light. In other words, for other modules except the data writing module 210, when the second output signal SN_OUT is used as the control signal, the shift register 110 can control whether the corresponding light-emitting element 300 can emit light normally. Those skilled in the art can deduce it according to the implementation method of the specific functions of each module, which will not be repeated here. It should be supplemented that the preset module in the pixel circuit 200 here refers more to a signal whose control signal is directly input from the outside, such as the data writing module 210, the compensation module 230, the reset module 250, the initialization module 260, the bias adjustment module 240 or the light control module 270. For the driving module 220 that is turned on or off by the input data signal, it is not directly controlled by an external signal. Therefore, the second output signal SN_OUT of the driving circuit 100 in the present invention cannot be used as a control signal of the preset module of the pixel circuit 200.

[0082] Generally, the second output signal SN_OUT refers to a scanning signal in which a high-level signal is a valid pulse and controls the NMOS transistor to turn on. In the embodiment of the present invention, the second output signal SN_OUT can also be inverted to make it a scanning signal in which a low-level signal is a valid pulse and controls the PMOS transistor to turn on. Figure 7-Figure 12 , taking the preset module as the data writing module 210 as an example, the preset module in the above pixel circuit 200 may include a PMOS transistor, and the second output signal SN_OUT is a control signal of the PMOS transistor, wherein when the second output signal SN_OUT is a low level signal, the second output signal SN_OUT is a valid pulse, controlling the PMOS transistor to turn on. It can be understood that Figure 7-Figure 12 The data writing module 210 shown can also be configured to include an NMOS transistor. At this time, if the second output signal SN_OUT is a control signal of the NMOS transistor, when the second output signal SN_OUT is a high level signal, the second output signal SN_OUT is a valid pulse to control the NMOS transistor to turn on.

[0083] Of course, the preset module may also be other modules in the pixel circuit 200, such as the compensation module 230, the reset module 250, the initialization module 260, the bias adjustment module 240 or the light emitting control module 270, see Figure 7-Figure 12 , for the reset module 250, which includes a PMOS transistor, the second output signal SN_OUT is a control signal of the PMOS transistor. When the second output signal SN_OUT is a low level signal, the second output signal SN_OUT is a valid pulse to control the PMOS transistor to turn on. Those skilled in the art will know that the valid pulses of the NMOS transistor and the PMOS transistor are at different potential levels, so the timing of the second output signal SN_OUT of the PMOS transistor is not shown in the figure here.

[0084] As mentioned above, since each shift register 110 can control the light-emitting frequency of the corresponding light-emitting element 300 through the second control unit 20 and the frequency control signal SN_CTRL, the working mode of the display panel can be changed as far as the display panel is concerned. Fig.13 and Fig.14 is a driving timing diagram of two display panels provided by an embodiment of the present invention, such as Fig.13 and Fig.14 As shown, the working process of the display panel includes a first mode MODEL1 and a second mode MODEL2. To put it simply, a pulse of the frequency control signal SN_CTRL can be understood as a refresh frame or a display frame. Fig.13 and Fig.14The corresponding working process of the display panel can be understood as the refresh conditions of the display panel under multiple refresh frames or display frames. The refresh conditions of the display panel under the first mode MODEL1 and the second mode MODEL2 are different.

[0085] In a specific embodiment, Fig.13 As shown, in the first mode MODEL1, the pulse change frequency of the frequency control signal SN_CTRL is Fc1, and in the second mode MODEL2, the pulse change frequency of the frequency control signal SN_CTRL is Fc2, wherein Fc1≠Fc2. And / or, in another specific embodiment, as Fig.14 As shown, in the first mode MODEL1, the time length of the effective pulse of the frequency control signal SN_CTRL is Wc1, and in the second mode MODEL2, the time length of the effective pulse of the frequency control signal SN_CTRL is Wc2, wherein Wc1≠Wc2.

[0086] First of all, it should be noted that a valid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned on, connected, and working, and an invalid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned off, cut off, and not working. Fig.13 and Fig.14 The valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT shown are both illustrated as high levels, and the invalid pulses are both illustrated as low levels, while the valid pulses of the frequency control signal SN_CTRL are illustrated as low levels, and the invalid pulses are illustrated as high levels. The first voltage edge of the first output signal SN_NEXT1 is the rising edge here.

[0087] Specifically, refer to Figure 5 and Figure 6It can be seen that since the second output signal SN_OUT of the shift register 110 is mainly generated by the second control unit 20 according to the first output signal SN_NEXT1 output by the first control unit 10 through the control of the frequency control signal SN_CTRL. Whether the second output signal SN_OUT outputs a valid pulse depends on the valid pulse of the frequency control signal SN_CTRL. Therefore, the frequency Fc and time length Wc of the valid pulse of the frequency control signal SN_CTRL can change the number and frequency of the valid pulses of the second output signal SN_OUT. Simply understand that one valid pulse of the second output signal SN_OUT corresponds to one light emission of the light-emitting element 300. The pulse change frequency Fc or the time length Wc of the valid pulse of the frequency control signal SN_CTRL directly determines the number or frequency of light emission of the light-emitting element 300. Therefore, by controlling all the light-emitting elements 300, the number or frequency of screen refresh of the display panel can be controlled macroscopically, and the adjustment and switching of the working mode can be realized. Therefore, this embodiment substantially controls the driving process of the pixel circuit 200 in the display panel by controlling the pulse change frequency of the frequency control signal SN_CTRL or the time length of the effective pulse, so as to adjust the light-emitting state of the light-emitting element 300, thereby realizing different working modes of the display panel on a macro level.

[0088] Based on the above embodiment, in the first mode MODEL1, the pulse change frequency of the second output signal SN_OUT is Fs1, and in the second mode MODEL2, the pulse change frequency of the second output signal SN_OUT is Fs2; wherein Fs1≠Fs2.

[0089] Specifically, continue to refer to Fig.13 and Fig.14 , the frequency control signal SN_CTRL directly determines the output of the effective pulse of the second output signal SN_OUT. Therefore, in different working modes of the display panel, when the frequency Fc of the frequency control signal SN_CTRL or the time length Wc of the effective pulse is different, the corresponding frequency of the second output signal SN_OUT is also different, that is, in the two different working modes of the first mode MODEL1 and the second mode MODEL2, the pulse frequency Fs1 of the second output signal SN_OUT must be different from the pulse frequency Fs2 of the second output signal SN_OUT. Exemplarily, Fig.13 The display panel in the first mode MODEL1 shown has two refresh frames or display frames, while the display panel in the second mode MODEL2 has one refresh frame or display frame. Fig.14 The display panel in the first mode MODEL1 shown has one refresh frame or display frame, and the display panel in the second mode MODEL2 has one refresh frame or display frame.

[0090] Furthermore, (Fc1-Fc2)×(Fs1-Fs2)>0; and / or, (Wc1-Wc2)×(Fs1-Fs2)>0.

[0091] It can be understood that since the effective pulse of the frequency control signal SN_CTRL directly determines the output of the effective pulse of the second output signal SN_OUT, the number of effective pulses of the frequency control signal SN_CTRL and the time length determine the number of effective pulses of the second output signal SN_OUT. When the number of effective pulses of the frequency control signal SN_CTRL increases or the time length increases, the number of effective pulses of the second output signal SN_OUT will also increase, that is, in the same time period, the number of effective pulses and the time length of the second output signal SN_OUT are positively correlated with the number of effective pulses of the frequency control signal SN_CTRL, respectively. Therefore, the pulse change frequency Fs and the time length Wc of the second output signal SN_OUT are positively correlated with the pulse change frequency Fc of the frequency control signal SN_CTRL, respectively. The larger the pulse change frequency Fc of the frequency control signal SN_CTRL and the larger the time length Wc, the larger the pulse change frequency Fs of the second output signal SN_OUT. Based on this, in the two working modes of the first mode MODEL1 and the second mode MODEL2, when Fc1-Fc2>0, Fs1-Fs2>0; when Fc1-Fc2<0, Fs1-Fs2<0; therefore, in the first mode MODEL1 and the second mode MODEL2, the pulse change frequency Fc of the frequency control signal SN_CTRL and the pulse change frequency Fs of the second output signal SN_OUT satisfy (Fc1-Fc2)×(Fs1-Fs2)>0. Similarly, in the first mode MODEL1 and the second mode MODEL2, when Wc1-Wc2>0, Fs1-Fs2>0; when Wc1-Wc2<0, Fs1-Fs2<0; therefore, in the first mode MODEL1 and the second mode MODEL2, the time length Wc of the frequency control signal SN_CTRL and the pulse change frequency Fs of the second output signal SN_OUT satisfy (Wc1-Wc2)×(Fs1-Fs2)>0.

[0092] Fig.15 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention, referring to Figure 7-Figure 12 as well as Fig.15 Optionally, in an embodiment of the present invention, the working process of the pixel circuit 200 includes a data writing frame Tdata and a holding frame Thold; wherein, in the data writing frame Tdata, the preset module is turned on; and in the holding frame Thold, the preset module is turned off.

[0093] First of all, it should be noted that Fig.15The valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT shown are both illustrated as high levels, and the invalid pulses are both illustrated as low levels, while the valid pulses of the frequency control signal SN_CTRL are illustrated as low levels, and the invalid pulses are illustrated as high levels. The first voltage edge of the first output signal SN_NEXT1 is the rising edge here.

[0094] Here, the data writing frame Tdata and holding frame Thold of the pixel circuit 200 can be understood as the picture display cycle of the display panel in two working modes. When the data writing frame Tdata of the pixel circuit 200 is in the pixel circuit 200, the pixel circuit 200 writes data and drives the light emission with the written data in the light emission stage. The second output signal SN_OUT of the driving circuit 100 is used as the control signal of the preset module of the pixel circuit 200. By reasonably setting the frequency control signal SN_CTRL (including a valid pulse and the first voltage edge corresponding to the first output signal SN_NEXT1 completely overlaps with it), the second output signal SN_OUT outputs a valid pulse in the data writing frame Tdata, thereby turning on the preset module, realizing the data writing process of the pixel circuit 200, and also realizing the data writing frame Tdata. Similarly, when the pixel circuit 200 holds the frame Thold, the pixel circuit 200 does not write data, but uses the data stored in the storage capacitor C1 when the previous data writing frame Tdata is used for light emission driving. The second output signal SN_OUT of the driving circuit 100 is used as the control signal of the preset module of the pixel circuit 200. By reasonably setting the frequency control signal SN_CTRL (not including a valid pulse, or the valid pulse does not overlap with the first voltage edge corresponding to the first output signal SN_NEXT1), the second output signal SN_OUT outputs an invalid pulse in the data writing frame Tdata, so that the preset module is turned off, and the pixel circuit 200 keeps the stored data without rewriting the data, thereby realizing the holding frame Thold. It should be added that this embodiment essentially uses the frequency control signal SN_CTRL to control the preset module in the pixel circuit 200, thereby realizing the control of whether data is written or not, and realizing different data refresh methods.

[0095] Further, in the first mode MODEL1, the data refresh frequency of the pixel circuit 200 is Fp1, and in the second mode MODEL2, the data refresh frequency of the pixel circuit 200 is Fp2; wherein, Fp1≠Fp2.

[0096] As mentioned above, the display panel in the embodiment of the present invention can control the pixel circuit 200 to switch between the data writing frame Tdata and the holding frame Thold by using the control preset module of the frequency control signal SN_CTRL, that is, the number of data writing frames Tdata can be controlled, thereby changing the data refresh frequency of the pixel circuit 200. Based on this, for the display panel, two working modes can be realized by using the frequency control signal SN_CTRL, and different data refresh frequencies are provided in the two working modes, that is, the data refresh frequency Fp1 under the first mode MODEL1 is not equal to the data refresh frequency Fp2 under the second mode MODEL2. Thus, different data refresh frequencies can be used for display in different application scenarios of the display panel. For example, when the display panel is playing a movie or playing a game, the data refresh frequency can be correspondingly increased to make the picture display smoother and meet the user's requirements for the smoothness of the picture display; when the display panel is in a static picture display, the data refresh frequency can be correspondingly reduced to reduce the driving power consumption and save energy.

[0097] Similarly, for the data refresh frequency of the pixel circuit 200, since the second output signal SN_OUT is responsible for controlling the on or off of the preset module in the pixel circuit 200, the data refresh frequency can be further adjusted. Therefore, the pulse change frequency Fs of the second output signal SN_OUT directly determines the data refresh frequency Fp of the pixel circuit 200, which is positively correlated. Therefore, the greater the pulse change frequency Fs of the second output signal SN_OUT, the greater the data refresh frequency Fp of the pixel circuit 200. In the first mode MODEL1 and the second mode MODEL2, when Fs1-Fs2>0, then Fp1-Fp2>0; when Fs1-Fs2<0, then Fp1-Fp2<0; therefore, in the first mode MODEL1 and the second mode MODEL2, the pulse change frequency Fs of the second output signal SN_OUT and the data refresh frequency Fp of the pixel circuit 200 satisfy (Fp1-Fp2)×(Fs1-Fs2)>0.

[0098] Fig.16 is a partial structural diagram of a display panel provided by an embodiment of the present invention, Fig.17 and Fig.18 yes Fig.16 The driving timing diagram of the two shift registers shown in the figure first refers to Fig.16Optionally, the display panel includes a first pixel circuit 201 and a second pixel circuit 202, and the driving circuit 100 includes a first shift register 111 and a second shift register 112; the second output signal SN_OUT of the first shift register 111 is a control signal of a first preset module of the first pixel circuit 201, and the second output signal SN_OUT of the second shift register 112 is a control signal of a second preset module of the second pixel circuit 202.

[0099] refer to Fig.17 and Fig.18 , wherein, in a specific embodiment, as Fig.17 As shown, the pulse change frequency of the frequency control signal SN_CTRL received by the first shift register 111 is Fc11, and the pulse change frequency of the frequency control signal SN_CTRL received by the second shift register 112 is Fc22, Fc11≠Fc22; and / or, in another specific embodiment, as Fig.18 As shown, the time length of the effective pulse of the frequency control signal SN_CTRL received by the first shift register 111 is Wc11, and the time length of the effective pulse of the frequency control signal SN_CTRL received by the second shift register 112 is Wc22, Wc11≠Wc22.

[0100] First, the first preset module in the first pixel circuit 201 and the second preset module in the second pixel circuit 202 are the same preset modules, for example, the aforementioned modules may be data writing modules, reset modules, initialization modules, threshold compensation modules, etc., which are not limited here. The only difference is that they belong to different pixel circuits 200 and receive control of different shift registers 110. Figure 16-Figure 18 For shift registers 110 of different levels, such as the first shift register 111 and the second shift register 112, their second output signals SN_OUT are control signals of the first preset modules in the first pixel circuit 201 and the second pixel circuit 202, respectively, which means that the two shift registers 110 drive the first pixel circuit 201 and the second pixel circuit 202 respectively. It can be seen that the frequency control signal SN_CTRL received by the two shift registers 110 can actually drive the two pixel circuits 200 respectively, and different frequency control signals SN_CTRL can be provided to the two shift registers 110, that is, the pulse change frequency Fc of the frequency control signal SN_CTRL of the two shift registers 110 is different and / or the time length Wc of the effective pulse is different, so as to adjust the driving state of the two pixel circuits 200 respectively and realize different data refresh frequencies, etc.

[0101] Based on the different pulse change frequencies Fc and / or effective pulse time lengths Wc of the frequency control signal SN_CTRL received by the two shift registers 110, the pulse change frequencies of the second output signal SN_OUT output by the two shift registers 110 will also be different, that is, the pulse change frequencies of the second output signal SN_OUT received by the preset modules of the two pixel circuits 200 will also be different. The pulse change frequency of the second output signal SN_OUT received by the first preset module is Fs11, and the pulse change frequency of the second output signal SN_OUT received by the second preset module is Fs22; wherein, Fs11≠Fs22.

[0102] Further, for the two shift registers 110, namely the first shift register 111 and the second shift register 112, the pulse change frequency Fs of the second output signal SN_OUT outputted therefrom is related to the pulse change frequency Fc of the received frequency control signal SN_CTRL and the time length Wc of the effective pulse, and is positively correlated. Therefore, when the pulse change frequency Fc of the frequency control signal SN_CTRL of the two shift registers 110 satisfies Fc11-Fc22>0, the pulse change frequency Fs of the second output signal SN_OUT outputted therefrom satisfies Fs11-Fs22>0; conversely, when the pulse change frequency Fc of the frequency control signal SN_CTRL of the two shift registers 110 satisfies Fc11-Fc22<0, the pulse change frequency Fs of the second output signal SN_OUT outputted therefrom satisfies Fs11-Fs22<0. Therefore, it can be obtained that (Fc11-Fc22)×(Fs11-Fs22)>0. Similarly, when the time length Wc of the effective pulse of the frequency control signal SN_CTRL of the two shift registers 110 satisfies Wc11-Wc22>0, the pulse change frequency Fs of the second output signal SN_OUT outputted therefrom satisfies Fs11-Fs22>0; conversely, when the time length Wc of the effective pulse of the frequency control signal SN_CTRL of the two shift registers 110 satisfies Wc11-Wc22<0, the pulse change frequency Fs of the second output signal SN_OUT outputted therefrom satisfies Fs11-Fs22<0. Therefore, it can be obtained that (Wc11-Wc22)×(Fs11-Fs22)>0.

[0103] Further, for the two pixel circuits 200, namely the first pixel circuit 201 and the second pixel circuit 202, different frequency control signals SN_CTRL may be provided to the two shift registers 110, so that they output second output signals SN_OUT with different pulse change frequencies, so as to adjust the driving states of the two pixel circuits 200 respectively and realize different data refresh frequencies. Therefore, in the embodiment of the present invention, the data refresh frequencies of the first pixel circuit 201 and the second pixel circuit 202 may be set to be different, and the data refresh frequency of the first pixel circuit 201 is Fp11, which is not equal to the data refresh frequency of the second pixel circuit 202 is Fp22; that is, Fp11≠Fp22.

[0104] Furthermore, for the two pixel circuits 200 , namely the first pixel circuit 201 and the second pixel circuit 202 , their data refresh frequency Fp is related to the pulse change frequency Fs of the second output signal SN_OUT received by the preset module therein, and they are positively correlated.

[0105] When the pulse change frequency Fs of the second output signal SN_OUT of the two shift registers 110 satisfies Fs11-Fs22>0, the corresponding data refresh frequency Fp of the two pixel circuits 200 satisfies Fp11-Fp22>0; conversely, when the pulse change frequency Fs of the second output signal SN_OUT of the two shift registers 110 satisfies Fs11-Fs22<0, the corresponding data refresh frequency Fp of the two pixel circuits 200 satisfies Fp11-Fp22<0. Therefore, (Fp11-Fp22)×(Fs11-Fs22)>0.

[0106] Continue to refer Fig.16 The display panel may include a first display area 1000 and a second display area 2000 , the first pixel circuit 201 is located in the first display area 1000 , and the second pixel circuit 202 is located in the second display area 2000 .

[0107] Therefore, the first pixel circuit 201 and the second pixel circuit 202 as described above are actually arranged in two display areas of the display panel, and the refresh frequencies of the two display areas can be driven differently by using two shift registers 100 and their corresponding frequency control signals SN_CTRL, so that the two display areas of the display panel have different picture refresh frequencies.

[0108] It should be noted that, in the embodiment of the present invention, the first display area 1000 and the second display area 2000 of the display panel can be the AA (Active Area, effective display) area and the CUP (Camera Under Panel, camera under the screen) area, respectively, or they can be two display areas in a period arranged periodically in the column direction. The embodiment of the present invention does not limit the specific method of partitioning, and those skilled in the art can set it according to actual needs. It can be seen from the above that through the control of the shift register and the frequency control signal SN_CTRL in the embodiment of the present invention, different display areas can have different screen refresh frequencies to adapt to the requirements of the area where they are located for screen smoothness or display power consumption.

[0109] As described above, the cascaded shift register 110 in the present invention is introduced in each embodiment. The frequency control signal SN_CTRL controls the output of the second output signal SN_OUT to realize the control of the preset module in the pixel circuit 200, and then the data refresh frequency of the pixel circuit 200 and the picture refresh frequency of the display panel are switched and adjusted. On the basis of the above-mentioned implementation purpose, the embodiment of the present invention provides a variety of specific structures of the shift register 110. The structure and working process of each type of shift register 110 are introduced below with reference to the accompanying drawings.

[0110] In a specific embodiment, the second control unit of the shift register 110 includes a first control unit, a second control unit, a third control unit and a second node; the first control unit also includes a third node, and the potential of the third node is inverted with the first output signal; the first control unit receives the potential signal and the first voltage signal of the first node, and is used to control the second output signal to be output as an invalid pulse; the second control unit receives the potential signal and the frequency control signal of the first node, and is used to control the potential of the second node; the third control unit receives the potential signal of the second node, the potential signal of the third node and the second voltage signal, and is used to control the second output signal to be output as a valid pulse; one of the first voltage signal and the second voltage signal is a high level signal, and the other is a low level signal. In another specific embodiment, the second control unit of the shift register 110 includes a first control unit, a second control unit, a third control unit and a second node; the first control unit also includes a third node, the potential of the third node is inverted with the first output signal; the first control unit receives the potential signal of the first node and the first voltage signal, and is used to control the second output signal to be output as an invalid pulse; the second control unit receives the potential signal of the first node and the frequency control signal, and is used to control the potential of the second node; the third control unit receives the potential signal of the second node and the potential signal of the third node, and is used to control the second output signal to be output as a valid pulse; the first voltage signal is a high level signal or a low level signal. Please refer to the accompanying drawings to specifically describe the structure and working process of various types of shift registers 110 as follows.

[0111] Optionally, Fig.19 is a schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention, such as Fig.19 As shown, the second control unit 20 of the shift register 110 includes a first control unit 21, a second control unit 22, a third control unit 23 and a second node N2; the first control unit 10 also includes a third node N3, and the potential of the third node N3 is inverted with the first output signal SN_NEXT1; the first control unit 21 receives the potential signal of the first node N1 and the first voltage signal V1, and is used to control the second output signal SN_OUT to output an invalid pulse; the second control unit 22 receives the potential signal of the first node N1 and the frequency control signal SN_CTRL, and is used to control the potential of the second node N2; the third control unit 23 receives the potential signal of the second node N2 and the potential signal of the third node N3, and is used to control the second output signal SN_OUT to output a valid pulse; the first voltage signal V1 is a high level signal VGH or a low level signal VGL.

[0112] Among them, the first control unit 21 receives the potential signal of the first node N1 and the first voltage signal V1, that is, under the control of the potential signal of the first node N1 and the first voltage signal V1, the second output signal SN_OUT can be output as an invalid pulse. And, the second node N2 can be understood as a node controlled by the second control unit 22, and is also a node that controls the output of the third control unit 23. Under the control of the potential signal of the first node N1 and the frequency control signal SN_CTRL, the potential of the second node N2 can change, and then the output potential of the third control unit 23 controlled by the potential signal of the second node N2 can change, generating the second output signal SN_OUT, so that the second output signal SN_OUT can be output as a valid pulse. It can be understood that the first voltage signal V1 participates in the control process of the second output signal SN_OUT outputting an invalid pulse. In this way, the first voltage signal V1 can be selected as a high-level signal VGH or a low-level signal VGL according to the need that the invalid pulse of the second output signal SN_OUT is high or low.

[0113] Specifically, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. When the first output signal SN_NEXT1 is a valid pulse, the first control unit 21 is turned on; when the first output signal SN_NEXT1 is an invalid pulse, the first control unit 21 is turned off. Fig.19The first control unit 21 shown includes a first transistor M1, which is a PMOS transistor. At this time, the valid pulse of the first output signal SN_NEXT1 is a low-level signal, and the invalid pulse is a high-level signal, that is, when the first output signal SN_NEXT1 is a low-level signal, the first transistor M1 in the first control unit 21 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the first transistor M1 in the first control unit 21 is turned off.

[0114] At this time, the first output signal SN_NEXT1 is substantially a control signal of the first control unit 21, connected to the control terminal of the first control unit 21, and the first output signal SN_NEXT1 is used to control the on or off of the first control unit 21. Optionally, when the first control unit 21 is turned on, the level signal corresponding to the first voltage signal V1 can be used to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT is output as an invalid pulse. Exemplarily, the invalid pulses of the first voltage signal V1 and the second output signal SN_OUT can both be low-level signals VGL.

[0115] Similarly, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. The second control unit 22 can be turned on when the first output signal SN_NEXT1 is a valid pulse, and turned off when the first output signal SN_NEXT1 is an invalid pulse. Fig.19 The second control unit 22 shown includes a second transistor M2 and a second capacitor C2, which are specifically PMOS transistors. At this time, the valid pulse of the first output signal SN_NEXT1 is a low-level signal, and the invalid pulse is a high-level signal, that is, when the first output signal SN_NEXT1 is a low-level signal, the second transistor M2 in the second control unit 22 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the second transistor M2 in the second control unit 22 is turned off.

[0116] At this time, the first output signal SN_NEXT1 is also substantially a control signal of the second control unit 22, connected to the control terminal of the second control unit 22, and the first output signal SN_NEXT1 controls the on or off of the second control unit 22. Optionally, when the second control unit 22 is turned on, the level signal corresponding to the frequency control signal SN_CTRL can be used to generate the potential signal of the second node N2, and at this time, the potential signal of the second node N2 can also be stored in the second capacitor C2.

[0117] It should be noted that, in the present embodiment, the node in the first control unit 10 is essentially led out as the third node N3, and its specific position and connection relationship in the first control unit 10 will be described in detail later, and will not be explained here for the time being. And the potential of the third node N3 is inverse to the first output signal SN_NEXT1, then when the first output signal SN_NEXT1 is a valid pulse, the potential signal of the third node N3 is an invalid pulse, and when the first output signal SN_NEXT1 is an invalid pulse, the potential signal of the third node N3 is a valid pulse. Exemplarily, the potential signal of the third node N3 can be a control signal of the third control unit 23, connected to the control end of the third control unit 23, and the conduction or shutoff of the third control unit 23 is controlled by the potential signal of the third node N3. Exemplarily, when the potential signal of the third node N3 is a valid pulse, the third control unit 23 can be turned on; when the potential signal of the third node N3 is an invalid pulse, the third control unit 23 is turned off. Fig.19 The third control unit 23 shown includes a third transistor M3, which is a PMOS transistor. At this time, the valid pulse of the potential signal of the third node N3 is a low-level signal, and the invalid pulse is a high-level signal, that is, when the potential signal of the third node N3 is a low-level signal, the third transistor M3 in the third control unit 23 is turned on; when the potential signal of the third node N3 is a high-level signal, the third transistor M3 in the third control unit 23 is turned off.

[0118] At this time, the potential signal of the second node N2 is substantially a conduction signal of the third control unit 23, connected to one end of the third control unit 23, and controls the generation of the potential signal of the other end of the third control unit 23 through the potential signal of the second node N2. Optionally, when the third control unit 23 is turned on, the level signal corresponding to the second node N2 can be used to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT is output as a valid pulse. Exemplarily, the valid pulses of the second output signal SN_OUT can all be high-level signals.

[0119] Optionally, continue to refer to Fig.19 The first control unit 21 includes a first transistor M1, a control end of the first transistor M1 is electrically connected to the first node N1, a first end of the first transistor M1 receives a first voltage signal V1, and a second end of the first transistor M1 outputs an invalid pulse of a second output signal SN_OUT.

[0120] Specifically, the first transistor M1 can be set as a PMOS transistor. At this time, the valid pulse of the potential signal of the first node N1 is a low-level signal, and the invalid pulse is a high-level signal. Exemplarily, the first voltage signal V1 can be VGL, and the invalid pulse of the second output signal SN_OUT corresponds to a low-level signal. That is, when the first transistor M1 is turned on and the first voltage signal V1 is VGL, the second output signal SN_OUT is output as an invalid pulse.

[0121] Further, continue to refer to Fig.19 The first control unit 21 further includes a first capacitor C1, a first plate of the first capacitor C1 is connected to the control end of the first transistor M1, and a second plate of the first capacitor C1 is connected to the second end of the first transistor M1.

[0122] Specifically, exemplarily, the control end of the first transistor M1 is the gate, and the second end of the first transistor M1 is the source. In this way, the two ends of the first capacitor C1 are connected between the gate and the source of the first transistor M1, so that a voltage difference is formed between the gate and the source of the first transistor M1, and the voltage difference is lower than the threshold voltage of the first transistor M1, thereby ensuring that the first transistor M1 is in an on state.

[0123] Optionally, continue to refer to Fig.19 The second control unit 22 includes a second transistor M2 and a second capacitor C2; the control end of the second transistor M2 is electrically connected to the first node N1, the first end of the second transistor M2 receives the frequency control signal SN_CTRL, the second end of the second transistor M2 is electrically connected to the first plate of the second capacitor C2 and the second node N2 respectively, and the second plate of the second capacitor C2 receives the fixed potential signal V'.

[0124] Specifically, the second transistor M2 can be set as a PMOS transistor, in which case the valid pulse of the potential signal of the first node N1 is a low level signal, and the invalid pulse is a high level signal. Exemplarily, the first end of the second transistor M2 receives the frequency control signal SN_CTRL, and the second end of the second transistor M2 is electrically connected to the second node N2, that is, when the second transistor M2 is turned on, the potential signal of the frequency control signal SN_CTRL can be generated at the second node N2, and at the same time, the second end of the second transistor M2 is electrically connected to the second capacitor C2, and the second capacitor C2 can also store the potential signal of the frequency control signal SN_CTRL. When the second transistor M2 is turned off, the potential signal of the frequency control signal SN_CTRL stored in the second capacitor C2 can be released to the second node N2, so that the second node N2 still floats as the potential signal of the frequency control signal SN_CTRL. In a more understandable way, when the second transistor M2 is turned off, no matter whether the frequency control signal SN_CTRL at the first end of the second transistor M2 is a valid pulse or an invalid pulse, the potential signal at the second end of the second transistor M2 remains as the potential signal of the frequency control signal SN_CTRL. In other words, the function of the second transistor M2 is to write the frequency control signal SN_CTRL to the second node N2 after a complete pulse signal of the first node N1 is output, so as to prevent the first node N1 from outputting a valid pulse when the frequency control signal SN_CTRL jumps, resulting in an incomplete second output signal SN_OUT. That is, the setting of the second transistor M2 and the second capacitor C2 is the basis for solving the problem that the potential signal at the second node N2 is cut off by the frequency control signal SN_CTRL, resulting in an incomplete pulse signal output, thereby solving the problem that the effective pulse of the second output signal SN_OUT is cut off by the frequency control signal SN_CTRL, resulting in an incomplete pulse signal output.

[0125] Further, continue to refer to Fig.19 The third control unit 23 includes a third transistor M3, a control end of the third transistor M3 is electrically connected to the third node N3, a first end of the third transistor M3 is electrically connected to the second node N2, and a second end of the third transistor M3 outputs a valid pulse of the second output signal SN_OUT.

[0126] Specifically, the third transistor M3 can be set as a PMOS transistor. At this time, the valid pulse of the potential signal of the third node N3 is a low-level signal, and the invalid pulse is a high-level signal. Exemplarily, the valid pulse of the potential signal of the third node N3 is a low-level signal, and the valid pulse of the second output signal SN_OUT is a high-level signal. That is, when the third transistor M3 is turned on, the second output signal SN_OUT is output as a valid pulse.

[0127] Fig. 20 yes Fig.19 A driving timing diagram of the second control unit in the shift register shown in FIG. Fig.19 and Fig. 20 , the working principle and process of the second control unit 20 in the shift register of the embodiment of the present invention are introduced:

[0128] First of all, it should be noted that a valid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned on, connected, and working, and an invalid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned off, cut off, and not working. Fig. 20 The valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT shown are both illustrated as high levels, and the invalid pulses are both illustrated as low levels, while the valid pulses of the frequency control signal SN_CTRL are illustrated as high levels, and the invalid pulses are illustrated as low levels. The first voltage edge of the first output signal SN_NEXT1 is the rising edge here, the first voltage signal V1 is the low level signal VGL, and the fixed voltage signal V' is the high level signal VGH or the low level signal VGL.

[0129] In the Ta phase, the first output signal SN_NEXT1 is at a low level, there is no rising edge in the first output signal SN_NEXT1, and the frequency control signal SN_CTRL is at a high level. At this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2; since the third node N3 is at a high level, the third transistor M3 is turned off, and the high level of the frequency control signal SN_CTRL can be stored in the second capacitor C2.

[0130] In the Tb stage, the first output signal SN_NEXT1 is at a high level, the first output signal SN_NEXT1 has a rising edge, and the frequency control signal SN_CTRL is converted from a high level to a low level. At this time, the first node N1 is at a high level, the first transistor M1 and the second transistor M2 are both turned off, and at the same time, the third node N3 is at a low level, and the third transistor M3 is turned on. The potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 is transmitted to the output end through the third transistor M3, so that the second output signal SN_OUT is a high level, that is, a valid pulse.

[0131] In the Tc phase, the first output signal SN_NEXT1 is at a low level, there is no rising edge in the first output signal SN_NEXT1, and the frequency control signal SN_CTRL is at a low level. At this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2; since the third node N3 is at a high level, the third transistor M3 is turned off, and the low level of the frequency control signal SN_CTRL can be stored in the second capacitor C2.

[0132] as well as, Fig.21 yes Fig.19 Another driving timing diagram of the second control unit in the shift register shown in FIG. Fig.19 and Fig.21 , the working principle and process of the second control unit 20 in the shift register of the embodiment of the present invention are introduced:

[0133] First of all, it should be noted that a valid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned on, connected, and working, and an invalid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned off, cut off, and not working. Fig.21 The valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT shown are both illustrated as high levels, and the invalid pulses are both illustrated as low levels, while the valid pulses of the frequency control signal SN_CTRL are illustrated as high levels, and the invalid pulses are illustrated as low levels. The first voltage edge of the first output signal SN_NEXT1 is the rising edge here, the first voltage signal V1 is the low level signal VGL, and the fixed voltage signal V' is the high level signal VGH or the low level signal VGL.

[0134] In the Td phase, the first output signal SN_NEXT1 is at a low level, there is no rising edge in the first output signal SN_NEXT1, and the frequency control signal SN_CTRL is at a high level. At this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2; since the third node N3 is at a high level, the third transistor M3 is turned off, and the high level of the frequency control signal SN_CTRL can be stored in the second capacitor C2.

[0135] In the Te phase, the first output signal SN_NEXT1 is at a low level, there is no rising edge in the first output signal SN_NEXT1, and the frequency control signal SN_CTRL is converted from a high level to a low level. At this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2; since the third node N3 is still at a high level, the third transistor M3 is still turned off.

[0136] In the Tf stage, the first output signal SN_NEXT1 is at a high level, the first output signal SN_NEXT1 has a rising edge, and the frequency control signal SN_CTRL is at a low level. At this time, the first node N1 is at a high level, the first transistor M1 and the second transistor M2 are both turned off, and at the same time, the third node N3 is at a low level, and the third transistor M3 is turned on. Then, the potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 is transmitted to the output end through the third transistor M3, so that the second output signal SN_OUT is at a low level.

[0137] In the Tg phase, the first output signal SN_NEXT1 is at a low level, there is no rising edge in the first output signal SN_NEXT1, and the frequency control signal SN_CTRL is at a low level. At this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2; since the third node N3 is at a high level, the third transistor M3 is turned off, and the low level of the frequency control signal SN_CTRL can be stored in the second capacitor C2.

[0138] Optionally, Fig. 22 is a schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention, such as Fig. 22As shown, the second control unit 20 of the shift register 110 includes a first control unit 21, a second control unit 22, a third control unit 23 and a second node N2; the first control unit 10 also includes a third node N3, and the potential of the third node N3 is inverted with the first output signal SN_NEXT1; the first control unit 21 receives the potential signal of the first node N1 and the first voltage signal V1, and is used to control the second output signal SN_OUT to output an invalid pulse; the second control unit 22 receives the potential signal of the first node N1 and the frequency control signal SN_CTRL, and is used to control the potential of the second node N2; the third control unit 23 receives the potential signal of the second node N2, the potential signal of the third node N3 and the second voltage signal V2, and is used to control the second output signal SN_OUT to output a valid pulse; one of the first voltage signal V1 and the second voltage signal V2 is a high level signal VGH, and the other is a low level signal VGL.

[0139] Among them, the first control unit 21 receives the potential signal of the first node N1 and the first voltage signal V1, that is, under the control of the potential signal of the first node N1 and the first voltage signal V1, the second output signal SN_OUT can be output as an invalid pulse. And, the second node N2 can be understood as a node controlled by the second control unit 22, and is also a node that controls the output of the third control unit 23. Under the control of the potential signal of the first node N1 and the frequency control signal SN_CTRL, the potential of the second node N2 can change, and then the output potential of the third control unit 23 controlled by the potential signal of the second node N2 and the second voltage signal V2 can change, generating the second output signal SN_OUT, so that the second output signal SN_OUT can be output as a valid pulse. It can be understood that the first voltage signal V1 participates in the control process of the second output signal SN_OUT outputting an invalid pulse, and the second voltage signal V2 participates in the control process of the second output signal SN_OUT outputting a valid pulse. Exemplarily, VGH is the voltage value of the high-level signal in the first voltage signal V1 and the second voltage signal V2, and VGL is the voltage value of the low-level signal in the first voltage signal V1 and the second voltage signal V2. Therefore, by controlling the output of the first voltage signal V1 or the second voltage signal V2, the switching of the high-level signal and the low-level signal of the second output signal SN_OUT, that is, the switching of the valid pulse and the invalid pulse, can be achieved.

[0140] Specifically, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. When the first output signal SN_NEXT1 is a valid pulse, the first control unit 21 is turned on; when the first output signal SN_NEXT1 is an invalid pulse, the first control unit 21 is turned off. Fig. 22The first control unit 21 shown includes a first transistor M1, which is a PMOS transistor. At this time, the valid pulse of the first output signal SN_NEXT1 is a low-level signal, and the invalid pulse is a high-level signal, that is, when the first output signal SN_NEXT1 is a low-level signal, the first transistor M1 in the first control unit 21 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the first transistor M1 in the first control unit 21 is turned off.

[0141] At this time, the first output signal SN_NEXT1 is also substantially a control signal of the first control unit 21, connected to the control terminal of the first control unit 21, and the first output signal SN_NEXT1 is used to control the on or off of the first control unit 21. Optionally, when the first control unit 21 is turned on, the level signal corresponding to the first voltage signal V1 can be used to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT is output as an invalid pulse. Exemplarily, the invalid pulses of the first voltage signal V1 and the second output signal SN_OUT can both be low-level signals VGL.

[0142] Similarly, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. The second control unit 22 can be turned on when the first output signal SN_NEXT1 is a valid pulse, and turned off when the first output signal SN_NEXT1 is an invalid pulse. Fig. 22 The second control unit 22 shown includes a second transistor M2 and a second capacitor C2, which are specifically PMOS transistors. At this time, the valid pulse of the first output signal SN_NEXT1 is a low-level signal, and the invalid pulse is a high-level signal, that is, when the first output signal SN_NEXT1 is a low-level signal, the second transistor M2 in the second control unit 22 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the second transistor M2 in the second control unit 22 is turned off.

[0143] At this time, the first output signal SN_NEXT1 is substantially a control signal of the second control unit 22, connected to the control end of the second control unit 22, and the conduction or shutoff of the second control unit 22 is controlled by the first output signal SN_NEXT1. Optionally, when the second control unit 22 is turned on, the level signal corresponding to the frequency control signal SN_CTRL can be applied to generate the potential signal of the second node N2, and the potential signal of the second node N2 can also be stored in the second capacitor C2. Furthermore, the potential signal of the second node N2 can also be substantially a conduction signal of the third control unit 23, connected to the control end of the third control unit 23, and the conduction or shutoff of the third control unit 23 is controlled by the potential signal of the second node N2. Afterwards, when the potential signal of the second node N2 is a valid pulse, the third control unit 23 is turned on; when the potential signal of the second node N2 is an invalid pulse, the third control unit 23 is turned off. Fig. 22 The third control unit 23 shown includes a third transistor M3, which is a PMOS transistor. At this time, the valid pulse of the potential signal of the second node N2 is a low-level signal, and the invalid pulse is a high-level signal, that is, when the potential signal of the second node N2 is a low-level signal, the third transistor M3 in the third control unit 23 is turned on; when the potential signal of the second node N2 is a high-level signal, the third transistor M3 in the third control unit 23 is turned off.

[0144] It should be noted that, in this embodiment, the node in the first control unit 10 is essentially led out as the third node N3, and its specific position and connection relationship in the first control unit 10 will be described in detail later, and will not be explained here. And the potential of the third node N3 is inverse to the first output signal SN_NEXT1, so when the first output signal SN_NEXT1 is a valid pulse, the potential signal of the third node N3 is an invalid pulse, and when the first output signal SN_NEXT1 is an invalid pulse, the potential signal of the third node N3 is a valid pulse. Exemplarily, the potential signal of the third node N3 can be a turn-on signal of the third control unit 23, connected to one end of the third control unit 23, and the generation of the potential signal of the other end of the third control unit 23 is controlled by the potential signal of the third node N3. Optionally, when the third control unit 23 is turned on, the potential signal corresponding to the third node N3 and the second voltage signal V2 can be used to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT is output as a valid pulse. Exemplarily, the valid pulses of the second output signal SN_OUT can all be high-level signals.

[0145] Optionally, continue to refer to Fig. 22The first control unit 21 includes a first transistor M1, a control end of the first transistor M1 is electrically connected to the first node N1, a first end of the first transistor M1 receives a first voltage signal V1, and a second end of the first transistor M1 outputs an invalid pulse of a second output signal SN_OUT.

[0146] Optionally, continue to refer to Fig. 22 The first control unit 21 further includes a first capacitor C1, a first plate of the first capacitor C1 is connected to the control end of the first transistor M1, and a second plate of the first capacitor C1 is connected to the second end of the first transistor M1.

[0147] Optionally, continue to refer to Fig. 22 The second control unit 22 includes a second transistor M2 and a second capacitor C2; the control end of the second transistor M2 is electrically connected to the first node N1, the first end of the second transistor M2 receives the frequency control signal SN_CTRL, the second end of the second transistor M2 is electrically connected to the first plate of the second capacitor C2 and the second node N2 respectively, and the second plate of the second capacitor C2 receives the fixed potential signal V'.

[0148] Optionally, continue to refer to Fig. 22 The third control unit 23 includes a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6; the control end of the fourth transistor M4 is electrically connected to the second node N2, the first end of the fourth transistor M4 is electrically connected to the third node N3, and the second end of the fourth transistor M4 is electrically connected to the first end of the fifth transistor M5 and the control end of the sixth transistor M6 respectively; the control end of the fifth transistor M5 is electrically connected to the first node N1, and the second end of the fifth transistor M5 receives the third voltage signal V3; the third voltage signal V3 is the same as the potential of the valid pulse of the first output signal SN_NEXT1; the first end of the sixth transistor M6 receives the second voltage signal V2, and the second end of the sixth transistor M6 outputs the valid pulse of the second output signal SN_OUT.

[0149] Specifically, any one of the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 can be set as a PMOS transistor, in which case the valid pulse of the potential signal corresponding to its control terminal is a low-level signal, and the invalid pulse is a high-level signal. Exemplarily, the control terminal of the fourth transistor M4 is electrically connected to the second node N2, the first terminal of the fourth transistor M4 is electrically connected to the third node N3, and the second terminal of the fourth transistor M4 is electrically connected to the first terminal of the fifth transistor M5 and the control terminal of the sixth transistor M6, respectively, that is, when the fourth transistor M4 is turned on, the potential signal at the third node N3 can be output to the first terminal of the fifth transistor M5, and at the same time, the potential signal at the third node N3 can also be output to the control terminal of the sixth transistor M6. And, the control end of the fifth transistor M5 is electrically connected to the first node N1. It should be noted that the potential of the third node N3 is in phase with the first output signal SN_NEXT1, the potential of the first node N1 is in phase with the first output signal SN_NEXT1, and the third voltage signal V3 is the same as the potential of the effective pulse of the first output signal SN_NEXT1. In this way, when the fifth transistor M5 is turned on, the potential signal at the third node N3 at the first end of the fifth transistor M5 and the third voltage signal V3 at the second end of the fifth transistor M5 can be exemplified as high-level signals VGH. And, the control end of the sixth transistor M6 is electrically connected to the third node N3, and the first end of the sixth transistor M6 receives the second voltage signal V2. That is, when the sixth transistor M6 is turned on, the level signal corresponding to the second voltage signal V2 can be used to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT is output as an effective pulse. For example, the second voltage signal V2 can be VGH, and the effective pulse of the second output signal SN_OUT can be a high-level signal VGH.

[0150] Further, continue to refer to Fig. 22 The third control unit 23 further includes a third capacitor C3, a first plate of the third capacitor C3 is electrically connected to the control end of the sixth transistor M6, and a second plate of the third capacitor C3 is electrically connected to the first end of the sixth transistor M6.

[0151] Specifically, exemplarily, the control end of the sixth transistor M6 is the gate, and the first end of the sixth transistor M6 is the source. In this way, the two ends of the third capacitor C3 are connected between the gate and the source of the sixth transistor M6, so that a voltage difference is formed between the gate and the source of the sixth transistor M6, and the voltage difference is lower than the threshold voltage of the sixth transistor M6, thereby ensuring that the sixth transistor M6 is in an on state.

[0152] Optionally, continue to refer to Fig. 22 , the second voltage signal V2 and the third voltage signal V3 are voltage signals of the same potential.

[0153] Specifically, when the fifth transistor M5 is turned on, the potential signal at the third node N3 at the first end of the fifth transistor M5 and the third voltage signal V3 at the second end of the fifth transistor M5 can be exemplified as high-level signals VGH. When the sixth transistor M6 is turned on, the level signal corresponding to the second voltage signal V2 can be applied to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT is output as a valid pulse. For example, the second voltage signal V2 can be VGH, and the valid pulse of the second output signal SN_OUT can be a high-level signal. That is, the second voltage signal V2 and the third voltage signal V3 can be exemplified as high-level signals VGH.

[0154] Fig.23 yes Fig. 22 A driving timing diagram of the second control unit in the shift register shown in FIG. Fig. 22 and Fig.23 , the working principle and process of the second control unit 20 in the shift register of the embodiment of the present invention are introduced:

[0155] First of all, it should be noted that a valid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned on, connected, and working, and an invalid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned off, cut off, and not working. Fig.23 The valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT shown are both illustrated as high levels, and the invalid pulses are both illustrated as low levels, while the valid pulses of the frequency control signal SN_CTRL are illustrated as low levels, and the invalid pulses are illustrated as high levels. The first voltage edge of the first output signal SN_NEXT1 is the rising edge here, the first voltage signal V1 is a low level signal VGL, the second voltage signal V2 is a high level signal VGH, the third voltage signal V3 is a high level signal VGH, and the fixed voltage signal V' is a high level signal VGH.

[0156] In the Th phase, the first output signal SN_NEXT1 is at a low level, the first output signal SN_NEXT1 does not have a rising edge, the frequency control signal SN_CTRL is at a low level, at this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 and the fifth transistor M5 are turned on, the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, and then the fourth transistor M4 is turned on, and the third voltage signal V3 is transmitted to the control end of the sixth transistor M6 through the fifth transistor M5 (or because the third node N3 is at a high level), the sixth transistor M6 is turned off, and the potential signal of the frequency control signal SN_CTRL can be stored at the second capacitor C2.

[0157] In the Ti stage, the first output signal SN_NEXT1 is at a high level, the first output signal SN_NEXT1 has a rising edge, and the frequency control signal SN_CTRL is converted from a low level to a high level. At this time, the first node N1 is at a high level, the first transistor M1, the second transistor M2 and the fifth transistor M5 are all turned off, and the potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 makes the fourth transistor M4 turned on. At the same time, the third node N3 is at a low level, then the third node N3 is transmitted to the control end of the sixth transistor M6 through the fourth transistor M4, the sixth transistor M6 is turned on, and the second voltage signal V2 is transmitted to the output end through the sixth transistor M6, so that the second output signal SN_OUT is at a high level.

[0158] In the Tj phase, the first output signal SN_NEXT1 is at a low level, there is no rising edge in the first output signal SN_NEXT1, and the frequency control signal SN_CTRL is at a low level. At this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 and the fifth transistor M5 are turned on, the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, and then the fourth transistor M4 is turned on, and the third voltage signal V3 is transmitted to the control end of the sixth transistor M6 through the fifth transistor M5 (or because the third node N3 is at a high level), the sixth transistor M6 is turned off, and the potential signal of the frequency control signal SN_CTRL is still stored at the second capacitor C2.

[0159] as well as, Fig.24 yes Fig. 22 Another driving timing diagram of the second control unit in the shift register shown in FIG. Fig. 22 and Fig.24 , the working principle and process of the second control unit 20 in the shift register of the embodiment of the present invention are introduced:

[0160] First of all, it should be noted that a valid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned on, connected, and working, and an invalid pulse can be understood as the realization of controlling the corresponding connected units, circuits, etc. to be turned off, cut off, and not working. Fig.24 The valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT shown are both illustrated as high levels, and the invalid pulses are both illustrated as low levels, while the valid pulses of the frequency control signal SN_CTRL are illustrated as low levels, and the invalid pulses are illustrated as high levels. The first voltage edge of the first output signal SN_NEXT1 is the rising edge here, the first voltage signal V1 is a low level signal VGL, the second voltage signal V2 is a high level signal VGH, the third voltage signal V3 is a high level signal VGH, and the fixed voltage signal V' is a high level signal VGH.

[0161] In the Tk phase, the first output signal SN_NEXT1 is at a low level, there is no rising edge in the first output signal SN_NEXT1, and the frequency control signal SN_CTRL is at a high level. At this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 and the fifth transistor M5 are turned on, the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, and then the fourth transistor M4 is turned off, and the third voltage signal V3 is transmitted to the control end of the sixth transistor M6 through the fifth transistor M5, and the sixth transistor M6 is turned off, then the potential signal of the frequency control signal SN_CTRL can be stored at the second capacitor C2.

[0162] In the Tl stage, the first output signal SN_NEXT1 is at a high level, the first output signal SN_NEXT1 has a rising edge, and the frequency control signal SN_CTRL is at a high level. At this time, the first node N1 is at a high level, the first transistor M1, the second transistor M2 and the fifth transistor M5 are all turned off, and the potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 still turns off the fourth transistor M4. At the same time, the third voltage signal V3 stored at the third capacitor C3 turns off the sixth transistor M6, and the level state of the second output signal SN_OUT floats to the low level of the Tk stage.

[0163] In the Tm phase, the first output signal SN_NEXT1 is at a low level, there is no rising edge in the first output signal SN_NEXT1, and the frequency control signal SN_CTRL is at a high level. At this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 and the fifth transistor M5 are turned on, the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, and then the fourth transistor M4 is turned on, and the third voltage signal V3 is transmitted to the control end of the sixth transistor M6 through the fifth transistor M5 (or because the third node N3 is at a high level), the sixth transistor M6 is turned off, and the potential signal of the frequency control signal SN_CTRL is still stored at the second capacitor C2.

[0164] Optionally, continue to refer to Figure 5 and Fig.19 , and references Figure 6 and Fig. 22 When the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, the first control unit 21 and the third control unit 23 do not output, and the second output signal SN_OUT maintains the level state of the second output signal SN_OUT when the first output signal SN_NEXT1 is the invalid pulse.

[0165] Specifically, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, the transistor inside the first control unit 21 is not turned on, the first control unit 21 does not output, and the first control unit 21 cannot control the second output signal SN_OUT to output as an invalid pulse. At the same time, the transistor inside the third control unit 23 is not turned on, the third control unit 23 does not output, and the third control unit 23 cannot control the second output signal SN_OUT to output as a valid pulse. In this way, the second output signal SN_OUT needs to maintain the level state of the second output signal SN_OUT when the first output signal SN_NEXT1 is an invalid pulse, that is, the second output signal SN_OUT maintains the output of the invalid pulse. In a more understandable way, when both the first control unit 21 and the third control unit 23 do not output, the output of the second output signal SN_OUT can float to the level state of the previous moment.

[0166] Optionally, in Fig. 22 On the basis of Fig.25 is a schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention, such as Fig.25As shown, the second control unit 20 also includes a fourth control unit 24, which receives at least the potential signal of the first node N1 and controls the second output signal SN_OUT to output an invalid pulse when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL.

[0167] Specifically, it can be understood that when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, the floating level state of the second output signal SN_OUT is unstable and susceptible to interference from other level signals. If the output of the second output signal SN_OUT is changed from an invalid pulse to a valid pulse at this time, it will affect the operation of the corresponding pixel circuit 200 and the accuracy of the partition refresh. In this way, the fourth control unit 24 is additionally provided in this embodiment, which is responsible for controlling the second output signal SN_OUT to output an invalid pulse when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL at least through the potential signal of the first node N1. It should be noted that at this time, the invalid pulse corresponding to the second output signal SN_OUT is output under the control of the fourth control unit 24, rather than the floating level state of the second output signal SN_OUT, which is not easily interfered by other level signals, and can make the second output signal SN_OUT more stable.

[0168] Further, continue to refer to Fig.25 The fourth control unit 24 is further used to control the second output signal SN_OUT, and output a valid pulse when the first voltage edge of the first output signal SN_NEXT1 overlaps with the valid pulse of the frequency control signal SN_CTRL and the first output signal SN_NEXT1 is a valid pulse.

[0169] Specifically, the fourth control unit 24 is additionally provided in this embodiment, and is responsible for controlling the second output signal SN_OUT to be output as a valid pulse when the first voltage edge of the first output signal SN_NEXT1 overlaps with the valid pulse of the frequency control signal SN_CTRL and the first output signal SN_NEXT1 is a valid pulse at least through the potential signal of the first node N1. It should be noted that at this time, the valid pulse corresponding to the second output signal SN_OUT is the result of the joint action of the fourth control unit 24 and / or the third control unit 23, which can further ensure the output of the valid pulse corresponding to the second output signal SN_OUT.

[0170] Optionally, continue to refer to Fig.25The fourth control unit 24 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and a fourth capacitor C4; the control end of the seventh transistor M7 is electrically connected to the first node N1, the first end of the seventh transistor M7 receives the fourth voltage signal V4, and the second end of the seventh transistor M7 is electrically connected to the first end of the eighth transistor M8 and the first end of the ninth transistor M9 respectively; the second end of the eighth transistor M8 receives the fifth voltage signal V5, and the conduction state of the eighth transistor M8 is synchronized with the conduction state of the third control unit 23; the control end of the ninth transistor M9 receives the sixth voltage signal V6, and the conduction state of the ninth transistor M9 is synchronized with the conduction state of the third control unit 23; The second end is respectively connected to the control end of the tenth transistor M10 and the first plate of the fourth capacitor C4; the first end of the tenth transistor M10 receives the seventh voltage signal V7, the second end of the tenth transistor M10 is electrically connected to the second plate of the fourth capacitor C4 and outputs the second output signal SN_OUT; the fourth voltage signal V4 has the same potential as the invalid pulse of the second output signal SN_OUT, the fifth voltage signal V5 has the same potential as the valid pulse of the second output signal SN_OUT, the sixth voltage signal V6 is configured to control the ninth transistor M9 to be normally open, and the seventh voltage signal V7 has the same potential as the invalid pulse of the second output signal SN_OUT.

[0171] Specifically, any one of the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 can be set as a PMOS transistor, in which case the valid pulse of the potential signal corresponding to its control end is a low level signal, and the invalid pulse is a high level signal. Exemplarily, the control end of the seventh transistor M7 is electrically connected to the first node N1, the first end of the seventh transistor M7 receives the fourth voltage signal V4, and the second end of the seventh transistor M7 is electrically connected to the first end of the eighth transistor M8 and the first end of the ninth transistor M9, respectively, that is, when the seventh transistor M7 is turned on, the fourth voltage signal V4 can be output to the first end of the eighth transistor M8, and at the same time, the fourth voltage signal V4 can be output to the first end of the ninth transistor M9. And, the conduction state of the eighth transistor M8 is synchronized with the conduction state of the third control unit 23, and exemplarily, the control end of the eighth transistor M8 and the control end of the transistor in the third control unit 23 are controlled by the same level signal, and the eighth transistor M8 and the transistor in the third control unit 23 are both exemplified as PMOS transistors, so as to ensure that the eighth transistor M8 and the third control unit 23 are synchronously turned on or off. The second end of the eighth transistor M8 receives the fifth voltage signal V5, that is, when the eighth transistor M8 is turned on, the fifth voltage signal V5 at the second end of the eighth transistor M8 is output to the first end of the eighth transistor M8. And, the control end of the ninth transistor M9 receives the sixth voltage signal V6, the second end of the ninth transistor M9 is respectively connected to the control end of the tenth transistor M10 and the first plate of the fourth capacitor C4, and the sixth voltage signal V6 is configured to control the ninth transistor M9 to be normally open, that is, when the ninth transistor M9 is turned on and the seventh transistor M7 is turned on, the fourth voltage signal V4 at the first end of the ninth transistor M9 can be output to the second end of the ninth transistor M9, that is, output to the control end of the tenth transistor M10, and at the same time, the fourth capacitor C4 can also store the level signal at the control end of the tenth transistor M10. Alternatively, the sixth voltage signal V6 is configured to control the ninth transistor M9 to be normally open. When the ninth transistor M9 is turned on and the eighth transistor M8 is turned on, the fifth voltage signal V5 at the first end of the ninth transistor M9 can be output to the second end of the ninth transistor M9, that is, to the control end of the tenth transistor M10. In this way, according to the conversion of the fourth voltage signal V4 and the fifth voltage signal V5, the tenth transistor M10 can be turned on or off accordingly. The fourth voltage signal V4 has the same potential as the invalid pulse of the second output signal SN_OUT. For example, the invalid pulse of the second output signal SN_OUT can be a low level signal VGL, and the fourth voltage signal V4 can be a low level signal VGL. The fifth voltage signal V5 has the same potential as the valid pulse of the second output signal SN_OUT. For example, the valid pulse of the second output signal SN_OUT can be a high level signal VGH, and the fifth voltage signal V5 can be a high level signal VGH.And, the first end of the tenth transistor M10 receives the seventh voltage signal V7, the second end of the tenth transistor M10 is electrically connected to the second plate of the fourth capacitor C4, and the second end of the tenth transistor M10 can also output the second output signal SN_OUT, that is, when the tenth transistor M10 is turned on, the seventh voltage signal V7 at the first end of the tenth transistor M10 can be output to the second end of the tenth transistor M10, thereby causing the second output signal SN_OUT to be output. When the tenth transistor M10 is turned off, the second end of the tenth transistor M10 is electrically connected to the second plate of the fourth capacitor C4, and the level signal at the control end of the tenth transistor M10 stored in the fourth capacitor C4 can also be released, so that the second output signal SN_OUT is output. The seventh voltage signal V7 has the same potential as the invalid pulse of the second output signal SN_OUT. Exemplarily, the invalid pulse of the second output signal SN_OUT can be a low level signal VGL, and the seventh voltage signal V7 can be a low level signal VGL.

[0172] In a specific embodiment, optionally, continue to refer to Fig.25 , the first voltage signal V1, the fourth voltage signal V4, the sixth voltage signal V6 and the seventh voltage signal V7 are signals of the same potential; the fifth voltage signal V5 and the second voltage signal V2 are signals of the same potential. In another specific embodiment, optionally, continue to refer to Fig.25 , at least two of the fourth voltage signal V4, the sixth voltage signal V6 and the seventh voltage signal V7 are voltage signals of the same potential.

[0173] Specifically, the embodiment is essentially to multiplex at least two high-level signals, or to multiplex at least two low-level signals, thereby saving the number of high-level signal lines or low-level signal lines, thereby facilitating the arrangement of the wiring, simplifying the circuit structure of the shift register 110, and reducing the complexity of the shift register 110. Exemplarily, the first voltage signal V1, the fourth voltage signal V4, the sixth voltage signal V6, and the seventh voltage signal V7 can be exemplified as low-level signals VGL, and the fifth voltage signal V5 and the second voltage signal V2 can be exemplified as high-level signals VGH.

[0174] Fig.26 yes Fig.25 A driving timing diagram of the second control unit in the shift register shown in FIG. Fig.25 and Fig.26 , the working principle and process of the second control unit 20 in the shift register of the embodiment of the present invention are introduced:

[0175] First of all, it should be noted that Fig.26The valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT shown are both illustrated as high levels, and the invalid pulses are both illustrated as low levels, while the valid pulses of the frequency control signal SN_CTRL are illustrated as low levels, and the invalid pulses are illustrated as high levels. The first voltage edge of the first output signal SN_NEXT1 is the rising edge here, the first voltage signal V1 is a low level signal VGL, the second voltage signal V2 is a high level signal VGH, the third voltage signal V3 is a high level signal VGH, the fixed voltage signal V' is a high level signal VGH, the fourth voltage signal V4 is a low level, the fifth voltage signal V5 is a high level, the sixth voltage signal V6 is a low level, and the seventh voltage signal V7 is a low level.

[0176] In the Tn phase, the first output signal SN_NEXT1 is at a low level, there is no rising edge in the first output signal SN_NEXT1, and the frequency control signal SN_CTRL is at a high level. At this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2, the fifth transistor M5 and the seventh transistor M7 are turned on, the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, and then the fourth transistor M4 is turned off, and the third voltage signal V3 is transmitted to the control end of the sixth transistor M6 and the control end of the eighth transistor M8 respectively through the fifth transistor M5, and the sixth transistor M6 and the eighth transistor M8 are turned off. And, the ninth transistor M9 is normally open (the sixth voltage signal V6 at the control end of the ninth transistor M9 is always the low level signal VGL), and the fourth voltage signal V4 is sequentially transmitted to the control end of the tenth transistor M10 through the seventh transistor M7 and the ninth transistor M9, so that the tenth transistor M10 is turned on, and further the second output signal SN_OUT is maintained at a low level. At this time, the low level signal VGL of the fourth voltage signal V4 can be stored at the fourth capacitor C4, and / or the low level signal VGL of the seventh voltage signal V7 can be stored at the fourth capacitor C4.

[0177] In the To stage, the first output signal SN_NEXT1 is at a high level, the first output signal SN_NEXT1 has a rising edge, the frequency control signal SN_CTRL is at a high level, at this time, the first node N1 is at a high level, the first transistor M1, the second transistor M2 and the fifth transistor M5 are all turned off, and the potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 still turns off the fourth transistor M4. At the same time, the third voltage signal V3 stored at the third capacitor C3 turns off the sixth transistor M6, and the level state of the second output signal SN_OUT floats to the low level of the Tk stage. And, the first node N1 is at a high level, the fifth transistor M5 and the seventh transistor M7 are turned off, the ninth transistor M9 is normally open, and the low level signal VGL stored at the fourth capacitor C4 can be released to the output end, so that the second output signal SN_OUT still remains at a low level. In this way, it is further ensured that the low level state of the second output signal SN_OUT will not drift and cause the output of the abnormally high level second output signal SN_OUT.

[0178] In the Tp phase, the first output signal SN_NEXT1 is at a low level, the first output signal SN_NEXT1 does not have a rising edge, the frequency control signal SN_CTRL is at a high level, at this time, the first node N1 is at a low level, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output end through the first transistor M1, so that the second output signal SN_OUT is at a low level. At the same time, the first node N1 is at a low level, the second transistor M2 and the fifth transistor M5 are turned on, the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, and then the fourth transistor M4 is turned on, and the third voltage signal V3 is transmitted to the control end of the sixth transistor M6 through the fifth transistor M5 (or because the third node N3 is at a high level), and the sixth transistor M6 is turned off. And, the first node N1 is at a low level, the second transistor M2, the fifth transistor M5 and the seventh transistor M7 are turned on, the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, and then the fourth transistor M4 is turned off, and the third voltage signal V3 is transmitted to the control end of the sixth transistor M6 and the control end of the eighth transistor M8 respectively through the fifth transistor M5, and the sixth transistor M6 and the eighth transistor M8 are turned off. And, the ninth transistor M9 is normally open (the sixth voltage signal V6 at the control end of the ninth transistor M9 is always a low level signal VGL), and the fourth voltage signal V4 is transmitted to the control end of the tenth transistor M10 through the seventh transistor M7 and the ninth transistor M9 in turn, so that the tenth transistor M10 is turned on, and further the second output signal SN_OUT is kept at a low level. At this time, the low level signal VGL of the fourth voltage signal V4 can be stored at the fourth capacitor C4, and / or, the low level signal VGL of the seventh voltage signal V7 can be stored at the fourth capacitor C4.

[0179] As shown in the previous embodiment, the internal structure of the second control unit 20 in the shift register 110 and the working principle of outputting the second output signal SN_OUT according to the first output signal SN_NEXT1 of the first control unit 10 and the frequency control signal SN_CTRL, the internal structure of the first control unit 10 and the working principle of controlling the first output signal SN_NEXT1 are introduced below.

[0180] Optionally, continue to refer to Fig.19 , Fig. 22 and Fig.25 The first control unit 10 includes a fifth control unit 11, a sixth control unit 12 and a seventh control unit 13; the fifth control unit 11 is used to receive the first input signal SN_IN1, the eighth voltage signal V8, the ninth voltage signal V9 and the clock signal CK, and control the potential of the fourth node N4 and the potential of the fifth node N5; one end of the sixth control unit 12 receives the tenth voltage signal V10, and the other end of the sixth control unit 12 is used to output the first output signal SN_NEXT1, and the control end of the sixth control unit 12 is electrically connected to the fourth node N4; one end of the seventh control unit 13 receives the eleventh voltage signal V11, and the other end of the seventh control unit 13 is used to output the first output signal SN_NEXT1, and the control end of the seventh control unit 13 is electrically connected to the fifth node N5; one of the eighth voltage signal V8 and the ninth voltage signal V9 is a high level signal VGH, and the other is a low level signal VGL; one of the tenth voltage signal V10 and the eleventh voltage signal V11 is a high level signal VGH, and the other is a low level signal VGL.

[0181] Specifically, the fifth control unit 11 can receive the first input signal SN_IN1, the eighth voltage signal V8, the ninth voltage signal V9 and the clock signal CK, and control the potential of the fourth node N4 and the potential of the fifth node N5, so as to determine the conversion of the first output signal SN_NEXT1 output as a valid pulse or an invalid pulse according to the potential of the fourth node N4 and the potential of the fifth node N5. The control end of the sixth control unit 12 is electrically connected to the fourth node N4, one end of the sixth control unit 12 receives the tenth voltage signal V10, and the other end of the sixth control unit 12 is used to output the first output signal SN_NEXT1, that is, when the sixth control unit 12 is turned on, the tenth voltage signal V10 at one end of the sixth control unit 12 is output to the other end of the sixth control unit 12 to form the output of the first output signal SN_NEXT1, at this time, the potential signal output by the first output signal SN_NEXT1 is the same as the tenth voltage signal V10. The control end of the seventh control unit 13 is electrically connected to the fifth node N5, one end of the seventh control unit 13 receives the eleventh voltage signal V11, and the other end of the seventh control unit 13 is used to output the first output signal SN_NEXT1, that is, when the seventh control unit 13 is turned on, the eleventh voltage signal V11 at one end of the seventh control unit 13 is output to the other end of the seventh control unit 13 to form the output of the first output signal SN_NEXT1. At this time, the potential signal output by the first output signal SN_NEXT1 is the same as the eleventh voltage signal V11.

[0182] One of the eighth voltage signal V8 and the ninth voltage signal V9 is a high-level signal VGH, and the other is a low-level signal VGL. It can be understood that the eighth voltage signal V8 and the ninth voltage signal V9 respectively participate in the control process of the second output signal SN_OUT outputting a valid pulse or an invalid pulse. Exemplarily, VGH is the voltage value of the high-level signal in the eighth voltage signal V8 and the ninth voltage signal V9, and VGL is the voltage value of the low-level signal in the eighth voltage signal V8 and the ninth voltage signal V9. Therefore, by controlling the output of the eighth voltage signal V8 and the ninth voltage signal V9, the switching of the high-level signal and the low-level signal of the second output signal SN_OUT, that is, the switching of the valid pulse and the invalid pulse, can be achieved. Similarly, one of the tenth voltage signal V10 and the eleventh voltage signal V11 is a high-level signal VGH, and the other is a low-level signal VGL. It can be understood that the tenth voltage signal V10 and the eleventh voltage signal V11 respectively participate in the control process of the second output signal SN_OUT outputting a valid pulse or an invalid pulse. Exemplarily, VGH is the voltage value of the high-level signal in the tenth voltage signal V10 and the eleventh voltage signal V11, and VGL is the voltage value of the low-level signal in the tenth voltage signal V10 and the eleventh voltage signal V11. Therefore, by controlling the output of the tenth voltage signal V10 and the eleventh voltage signal V11, the switching of the high-level and low-level signals of the second output signal SN_OUT, that is, the switching of the valid pulse and the invalid pulse, can be achieved.

[0183] Optionally, continue to refer to Fig.19 , Fig. 22 and Fig.25 , the eighth voltage signal V8 and the tenth voltage signal V10 are voltage signals of the same potential; the ninth voltage signal V9 and the eleventh voltage signal V11 are voltage signals of the same potential.

[0184] Specifically, the embodiment is essentially to multiplex at least two high-level signals, or to multiplex at least two low-level signals, thereby saving the number of high-level signal lines or low-level signal lines, thereby facilitating the arrangement of the wiring, simplifying the circuit structure of the shift register 110, and reducing the complexity of the shift register 110. Exemplarily, the eighth voltage signal V8 and the tenth voltage signal V10 can be exemplified as both low-level signals VGH, and the ninth voltage signal V9 and the eleventh voltage signal V11 can be exemplified as both high-level signals VGL.

[0185] Optionally, continue to refer to Fig.19 , Fig. 22 and Fig.25The fifth control unit 11 includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15 and a fifth capacitor C5; a first end of the eleventh transistor M11 and a control end of the twelfth transistor M12 are electrically connected to receive a first input signal SN_IN1, a control end of the eleventh transistor M11, a first plate of the fifth capacitor C5 and a first end of the thirteenth transistor M13 are electrically connected to receive a clock signal CK, and a second end of the eleventh transistor M11 is electrically connected to a first plate of the fourteenth transistor M14 and a second plate of the fifth capacitor C5. One end is electrically connected to the control end of the fifteenth transistor M15; the first end of the twelfth transistor M12 is electrically connected to the second plate of the fifth capacitor C5 and the control end of the thirteenth transistor M13 respectively, the second end of the twelfth transistor M12 is electrically connected to the first end of the fifteenth transistor M15 and receives the eighth voltage signal V8; the second end of the thirteenth transistor M13 and the second end of the fifteenth transistor M15 are both electrically connected to the fourth node N4; the second end of the fourteenth transistor M14 is electrically connected to the fifth node N5, and the control end of the fourteenth transistor M14 receives the ninth voltage signal V9.

[0186] Specifically, any one of the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 can be set as a PMOS transistor, in which case the valid pulse of the potential signal corresponding to its control end is a low level signal, and the invalid pulse is a high level signal. Exemplarily, the control end of the eleventh transistor M11 receives the clock signal CK, the first end of the eleventh transistor M11 receives the first input signal SN_IN1, and the second end of the eleventh transistor M11 is electrically connected to the first end of the fourteenth transistor M14 and the control end of the fifteenth transistor M15, that is, when the eleventh transistor M11 is turned on, the first input signal SN_IN1 at the first end of the eleventh transistor M11 can be output to the first end of the fourteenth transistor M14, and at the same time, the first input signal SN_IN1 at the first end of the eleventh transistor M11 can be output to the control end of the fifteenth transistor M15. The control terminal of the twelfth transistor M12 receives the first input signal, the first terminal of the twelfth transistor M12 is electrically connected to the second plate of the fifth capacitor C5, and the second terminal of the twelfth transistor M12 receives the eighth voltage signal V8, that is, when the twelfth transistor M12 is turned on, the eighth voltage signal V8 at the second terminal of the twelfth transistor M12 can be output to the first terminal of the twelfth transistor M12, and at the same time, the fifth capacitor C5 can store the eighth voltage signal V8. The control terminal of the thirteenth transistor M13 is electrically connected to the first terminal of the twelfth transistor M12 and the second plate of the fifth capacitor C5, the first terminal of the thirteenth transistor M13 receives the clock signal CK, and the second terminal of the thirteenth transistor M13 is electrically connected to the fourth node N4, that is, when the thirteenth transistor M13 is turned on, the eighth voltage signal V8 stored in the fifth capacitor C5 can be output to the fourth node N4, so as to facilitate the subsequent output of the first output signal SN_NEXT1. The control end of the fourteenth transistor M14 receives the ninth voltage signal V9, the first end of the fourteenth transistor M14 is electrically connected to the second end of the eleventh transistor M11, and the second end of the fourteenth transistor M14 is electrically connected to the fifth node N5, that is, when the fourteenth transistor M14 is turned on, the potential signal at the second end of the eleventh transistor M11 can be output to the fifth node N5, so as to facilitate the subsequent output of the first output signal SN_NEXT1.

[0187] Optionally, continue to refer to Fig.19 , Fig. 22 and Fig.25The sixth control unit 12 includes a sixteenth transistor M16 and a sixth capacitor C6; the control end of the sixteenth transistor M16 and the first plate of the sixth capacitor C6 are both electrically connected to the fourth node N4, the first end of the sixteenth transistor M16 and the second plate of the sixth capacitor C6 are electrically connected and receive the tenth voltage signal V10, and the second end of the sixteenth transistor M16 outputs the first output signal SN_NEXT1.

[0188] Specifically, the sixteenth transistor M16 can be set as a PMOS transistor, in which case the valid pulse of the potential signal corresponding to its control terminal is a low level signal, and the invalid pulse is a high level signal. Exemplarily, the sixteenth transistor M16 can be a PMOS transistor, the gate of the sixteenth transistor M16 is electrically connected to the fourth node N4, the source of the sixteenth transistor M16 receives the tenth voltage signal V10, the drain of the sixteenth transistor M16 outputs the first output signal SN_NEXT1, and the two ends of the sixth capacitor C6 are connected between the gate and the source of the sixteenth transistor M16, so that a voltage difference is formed between the gate and the source of the sixteenth transistor M16, and the voltage difference is lower than the threshold voltage of the sixteenth transistor M16, thereby ensuring that the sixteenth transistor M16 is in a conducting state.

[0189] Optionally, continue to refer to Fig.19 , Fig. 22 and Fig.25 The seventh control unit 13 includes a seventeenth transistor M17 and a seventh capacitor C7; the control end of the seventeenth transistor M17 and the first plate of the seventh capacitor C7 are both electrically connected to the fifth node N5, the first end of the seventeenth transistor M17 receives the eleventh voltage signal V11, the second end of the seventeenth transistor M17 is electrically connected to the second plate of the seventh capacitor C7 and outputs the first output signal SN_NEXT1.

[0190] Specifically, the seventeenth transistor M17 can be set as a PMOS transistor, in which case the valid pulse of the potential signal corresponding to its control terminal is a low level signal, and the invalid pulse is a high level signal. Exemplarily, the seventeenth transistor M17 can be a PMOS transistor, the gate of the seventeenth transistor M17 is electrically connected to the fifth node N5, the source of the seventeenth transistor M17 receives the eleventh voltage signal V11, the drain of the seventeenth transistor M17 outputs the first output signal SN_NEXT1, and the two ends of the seventh capacitor C7 are connected between the gate and the source of the seventeenth transistor M17, so that a voltage difference is formed between the gate and the source of the seventeenth transistor M17, and the voltage difference is lower than the threshold voltage of the seventeenth transistor M17, thereby ensuring that the seventeenth transistor M17 is in a conducting state.

[0191] In addition, it should be noted that the first node N1 in the first control unit 10 can be Fig.19 , Fig. 22 and Fig.25 In the example, the node at which the sixteenth transistor M16 and the seventeenth transistor M17 are electrically connected, the first node N1 can also be the fourth node N4 (the first node N1 outputs the same potential signal as the fourth node N4), and the first node N1 can also be the fifth node N5 (the first node N1 outputs the same potential signal as the fifth node N5). In this embodiment, the first node N1 is used as the node at which the sixteenth transistor M16 and the seventeenth transistor M17 are electrically connected for drawing. In fact, other schematic diagrams of the electrical connection relationship of the first node N1 may also be included.

[0192] Fig. 27 is a driving timing diagram of the first control unit in a shift register provided by an embodiment of the present invention, and the following reference is made to Fig.19 , Fig. 22 , Fig.25 and Fig. 27 , the working principle and process of the first control unit 10 in the shift register of the embodiment of the present invention are introduced:

[0193] First of all, it should be noted that Fig. 27 The valid pulses of the first input signal SN_IN1, the clock signal CK and the first output signal SN_NEXT1 shown are all illustrated as high levels, the invalid pulses are all illustrated as low levels, and the eighth voltage signal V8 and the tenth voltage signal V8 are both illustrated as high-level signals VGH, and the ninth voltage signal V9 and the eleventh voltage signal V11 are both illustrated as low-level signals VGL.

[0194] In the Tq stage, the first input signal SN_IN1 is at a low level, and the clock signal CK is at a low level. At this time, the eleventh transistor M11 and the twelfth transistor M12 are turned on, and the fourteenth transistor M14 is normally open (the ninth voltage signal V9 at the control end of the fourteenth transistor M14 is always the low level signal VGL). The first input signal SN_IN1 is transmitted to the fifth node N5 through the eleventh transistor M11 and the fourteenth transistor M14 in sequence. When the fifth node N5 is at a low level, the seventeenth transistor M17 is turned on, and the eleventh voltage signal V11 is transmitted to the first output signal SN_NEXT1 through the seventeenth transistor M17, so that the first output signal SN_NEXT1 is at a low level, that is, the first node N1 is at a low level. At the same time, the eighth voltage signal V8 is transmitted to the thirteenth transistor M13 through the twelfth transistor M12, so that the thirteenth transistor M13 is turned off, the first input signal SN_IN1 is transmitted to the fifteenth transistor M15 through the eleventh transistor M11, so that the fifteenth transistor M15 is turned on, and the eighth voltage signal V8 is also transmitted to the third node N3 through the fifteenth transistor M15, so that the third node N3 is at a high level, and then the sixteenth transistor M16 is turned off.

[0195] In the Tr stage, the first input signal SN_IN1 is at a low level, and the clock signal CK is at a high level. At this time, the twelfth transistor M12 is turned on, the fourteenth transistor M14 is normally open, and the potential signal of the fourth node N4 floats to a low level in the Tq stage, then the fifteenth transistor M15 and the seventeenth transistor M17 are turned on, and the eleventh voltage signal V11 is transmitted to the first output signal SN_NEXT1 through the seventeenth transistor M17, so that the first output signal SN_NEXT1 is at a low level, that is, the first node N1 is at a low level. And, the eighth voltage signal V8 is also transmitted to the third node N3 through the fifteenth transistor M15, so that the third node N3 is at a high level, and then the sixteenth transistor M16 is turned off.

[0196] In the Ts stage, the first input signal SN_IN1 is at a high level, and the clock signal CK is at a high level. At this time, the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 are turned off, the fourteenth transistor M14 is normally turned on, and the potential signal of the fourth node N4 floats to the low level of the Tr stage, then the fifteenth transistor M15 and the seventeenth transistor M17 are turned on, and the eleventh voltage signal V11 is transmitted to the first output signal SN_NEXT1 through the seventeenth transistor M17, so that the first output signal SN_NEXT1 is at a low level, that is, the first node N1 is at a low level. And, the eighth voltage signal V8 is also transmitted to the third node N3 through the fifteenth transistor M15, so that the third node N3 is at a high level, and then the sixteenth transistor M16 is turned off.

[0197] In the Tt phase, the first input signal SN_IN1 is at a high level, and the clock signal CK is at a low level. At this time, the twelfth transistor M12 is turned off, the eleventh transistor M11 and the thirteenth transistor M13 are turned on, and the fourteenth transistor M14 is normally open. The first input signal SN_IN1 is transmitted to the fifteenth transistor M15 through the eleventh transistor M11, so that the fifteenth transistor M15 is turned off. At the same time, the first input signal SN_IN1 is transmitted to the seventeenth transistor M17 through the eleventh transistor M11 and the fourteenth transistor M14 in sequence, so that the seventeenth transistor M17 is turned off. In addition, the clock signal CK is transmitted to the third node N3 through the fifteenth transistor M15, so that the third node N3 is at a low level, and then the sixteenth transistor M16 is turned on, and the tenth voltage signal V10 is transmitted to the first output signal SN_NEXT1 through the sixteenth transistor M16, so that the first output signal SN_NEXT1 is at a high level, that is, the first node N1 is at a high level.

[0198] In the Tu phase, the first input signal SN_IN1 is at a high level, and the clock signal CK is at a high level. At this time, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are turned off, the fourteenth transistor M14 is normally on, and the potential signal of the fourth node N4 floats to a high level in the Tt phase, then the fifteenth transistor M15 and the seventeenth transistor M17 are turned off. Also, the potential signal of the third node N3 floats to a low level in the Tt phase, then the sixteenth transistor M16 is turned on, and the tenth voltage signal V10 is transmitted to the first output signal SN_NEXT1 through the sixteenth transistor M16, so that the first output signal SN_NEXT1 is at a high level, that is, the first node N1 is at a high level.

[0199] In the Tv phase, the first input signal SN_IN1 is at a low level, and the clock signal CK is at a high level. At this time, the twelfth transistor M12 is turned on, the eleventh transistor M11 and the thirteenth transistor M13 are turned off, the fourteenth transistor M14 is normally on, and the potential signal of the fourth node N4 floats to a high level in the Tu phase, then the fifteenth transistor M15 and the seventeenth transistor M17 are turned off. Also, the potential signal of the third node N3 floats to a low level in the Tu phase, then the sixteenth transistor M16 is turned on, and the tenth voltage signal V10 is transmitted to the first output signal SN_NEXT1 through the sixteenth transistor M16, so that the first output signal SN_NEXT1 is at a high level, that is, the first node N1 is at a high level.

[0200] In addition, continue to refer to Fig. 27 It can be clearly found that the potential signal of the fourth node N4 and the potential signal of the fifth node N5 are respectively the same as the potential signal of the first output signal SN_NEXT1 in real time, so the fourth node N4 can be reused as the first node N1 defined in this application, and the fifth node N5 can also be reused as the first node N1 defined in this application, which is consistent with the meaning that the potential of the first node N1 is synchronized with the first output signal SN_NEXT1 defined in this application. And, the potential signal of the third node N3 is opposite to the potential signal of the first output signal SN_NEXT1 in real time, which is consistent with the meaning that the potential of the third node N3 is inverted with the first output signal SN_NEXT1 defined in this application.

[0201] Optionally, Fig.28 is a schematic diagram of a circuit structure of another shift register provided by an embodiment of the present invention, Fig.29 yes Figure 3 Another driving timing diagram of each level of shift register in the driving circuit shown in FIG. Fig.28 and Fig.29As shown, the first control unit 10 is also used to control the third output signal SN_NEXT2, and the third output signal SN_NEXT2 of the i-th stage shift register 110 is the second input signal SN_IN2 of the j-th stage shift register 110; within the preset time length range, the first output signal SN_NEXT1 includes a first valid pulse, a first invalid pulse and a second valid pulse that are adjacent in sequence. During the time period of the first valid pulse, the first invalid pulse and the second valid pulse, the third output signal SN_NEXT2 is a valid pulse, and the voltage edge of the third output signal SN_NEXT2 that jumps from an invalid level to a valid level is synchronized with the voltage edge of the first valid pulse that jumps from an invalid level to a valid level; the voltage edge of the third output signal SN_NEXT2 that jumps from a valid level to an invalid level is synchronized with the voltage edge of the second valid pulse that jumps from a valid level to an invalid level; the second control unit 20 receives the potential signal of the first node N1, the frequency control signal SN_CTRL and the third output signal SN_NEXT2, and controls the second output signal SN_OUT.

[0202] Specifically, in a specific embodiment, the first output signal SN_NEXT1 can be exemplified as a DVH signal of a bias adjustment module, and the bias adjustment of the driving transistor needs to be performed before and after the data writing stage. In this way, before and after the data writing stage, the first output signal SN_NEXT1 needs to output two adjacent valid pulse signals to ensure the implementation of the bias adjustment of the driving transistor. That is, the first output signal SN_NEXT1 includes a first valid pulse, a first invalid pulse, and a second valid pulse that are adjacent in sequence. It should be noted that in order to avoid the voltage edge of the second valid pulse jumping from an invalid level to a valid level, when the corresponding frequency control signal SN_CTRL is an invalid pulse, the second valid pulse cannot be output to form the corresponding second output signal SN_OUT. Therefore, it is necessary to additionally set up the third output signal SN_NEXT2, and limit the voltage edge of the third output signal SN_NEXT2 jumping from the invalid level to the valid level to be synchronized with the voltage edge of the first valid pulse jumping from the invalid level to the valid level; the voltage edge of the third output signal SN_NEXT2 jumping from the valid level to the invalid level is synchronized with the voltage edge of the second valid pulse jumping from the valid level to the invalid level.

[0203] Optionally, continue to refer to Fig.28 The first control unit 10 includes an eighth control unit 14, which is used to receive the second input signal SN_IN2, the twelfth voltage signal V12 and the clock signal CK, and control the third output signal SN_NEXT2; wherein the twelfth voltage signal V12 has the same potential as the invalid pulse of the third output signal SN_NEXT2.

[0204] Specifically, the eighth control unit 14 can receive the second input signal SN_IN2, the twelfth voltage signal V12 and the clock signal CK to control the output of the third output signal SN_NEXT2. For example, the inactive pulses of the twelfth voltage signal V12 and the third output signal SN_NEXT2 can both be low level signals VGL.

[0205] Optionally, continue to refer to Fig.28 The eighth control unit 14 includes an eighteenth transistor M18 and an eighth capacitor C8; the first end of the eighteenth transistor M18 receives the second input signal SN_IN2, the second end of the eighteenth transistor M18 is electrically connected to the first plate of the eighth capacitor C8 and outputs a third output signal SN_NEXT2; the second plate of the eighth capacitor C8 receives the twelfth voltage signal V12.

[0206] Specifically, the eighteenth transistor M18 can be set as a PMOS transistor, in which case the valid pulse of the potential signal corresponding to its control terminal is a low level signal, and the invalid pulse is a high level signal. Exemplarily, the eighteenth transistor M18 can be a PMOS transistor, the gate of the eighteenth transistor M18 is electrically connected to the clock signal CK, the source of the eighteenth transistor M18 receives the second input signal SN_IN2, the drain of the eighteenth transistor M18 outputs the third output signal SN_NEXT2, and the two ends of the eighth capacitor C8 are connected between the third output signal SN_NEXT2 and the twelfth voltage signal V12, so that the third output signal SN_NEXT2 is more stable.

[0207] Optionally, continue to refer to Fig.28 and Fig.29, the first control unit 10 also includes a sixth node N6, the potential signal output of the sixth node N6 is the third output signal SN_NEXT2, the third output signal SN_NEXT2 of the i-th stage shift register 110 is the second input signal SN_IN2 of the j-th stage shift register 110; within the preset time range, the first output signal SN_NEXT1 includes a first valid pulse, a first invalid pulse and a second valid pulse that are adjacent in sequence, and in the time period of the first valid pulse, the first invalid pulse and the second valid pulse, the third output signal SN_NEXT2 is a valid pulse, and the voltage edge of the third output signal SN_NEXT2 jumping from the invalid level to the valid level is synchronized with the voltage edge of the first valid pulse jumping from the invalid level to the valid level; the third output signal SN_NEXT2 jumps from the valid level to the invalid level The voltage edge of the jump is synchronized with the voltage edge of the second valid pulse jumping from the valid level to the invalid level; the second control unit 20 includes a first control unit 21, a second control unit 22, a third control unit 23 and a second node N2; the first control unit 21 receives the potential signal of the first node N1 and the first voltage signal V1, and is used to control the second output signal SN_OUT to be output as an invalid pulse; the second control unit 22 receives the potential signal of the sixth node N6 and the frequency control signal SN_CTRL, and is used to control the potential of the second node N2; the third control unit 23 receives at least the potential signal of the second node N2 and the second voltage signal V2, and is used to control the second output signal SN_OUT to be output as a valid pulse; one of the first voltage signal V1 and the second voltage signal V2 is a high level signal VGH, and the other is a low level signal VGL.

[0208] Specifically, in a specific embodiment, the first output signal SN_NEXT1 can be exemplified as a DVH signal of a bias adjustment module, and the bias adjustment of the driving transistor needs to be performed before and after the data writing stage. In this way, before and after the data writing stage, the first output signal SN_NEXT1 needs to output two adjacent valid pulse signals to ensure the implementation of the bias adjustment of the driving transistor. That is, the first output signal SN_NEXT1 includes a first valid pulse, a first invalid pulse, and a second valid pulse that are adjacent in sequence. It should be noted that in order to avoid the voltage edge of the second valid pulse jumping from an invalid level to a valid level, when the corresponding frequency control signal SN_CTRL is an invalid pulse, the second valid pulse cannot be output to form the corresponding second output signal SN_OUT. Therefore, it is necessary to additionally set up the third output signal SN_NEXT2, and limit the voltage edge of the third output signal SN_NEXT2 jumping from the invalid level to the valid level to be synchronized with the voltage edge of the first valid pulse jumping from the invalid level to the valid level; the voltage edge of the third output signal SN_NEXT2 jumping from the valid level to the invalid level is synchronized with the voltage edge of the second valid pulse jumping from the valid level to the invalid level.

[0209] The sixth node N6 can be understood as a connection point for realizing an electrical connection relationship between the first control unit 10 and the second control unit 20. At the same time, the second control unit 20 includes a first control unit 21, a second control unit 22, and a third control unit 23. Among them, the first control unit 21 receives the potential signal of the first node N1 and the first voltage signal V1, that is, under the control of the potential signal of the first node N1 and the first voltage signal V1, the second output signal SN_OUT can be output as an invalid pulse. And, the second node N2 can be understood as a node controlled by the second control unit 22, and is also a node that controls the output of the third control unit 23. Under the control of the potential signal of the sixth node N6 and the frequency control signal SN_CTRL, the potential of the second node N2 can change, and then the output potential of the third control unit 23 controlled by the potential signal of the second node N2 and the second voltage signal V2 can change, generating a second output signal SN_OUT, so that the second output signal SN_OUT can be output as a valid pulse. It can be understood that the first voltage signal V1 participates in the control process of the second output signal SN_OUT outputting an invalid pulse, and the second voltage signal V2 participates in the control process of the second output signal SN_OUT outputting a valid pulse. Exemplarily, VGH is the voltage value of the high-level signal in the first voltage signal V1 and the second voltage signal V2, and VGL is the voltage value of the low-level signal in the first voltage signal V1 and the second voltage signal V2. Therefore, by controlling the output of the first voltage signal V1 or the second voltage signal V2, the switching of the high-level signal and the low-level signal of the second output signal SN_OUT, that is, the switching of the valid pulse and the invalid pulse, can be achieved.

[0210] Specifically, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. When the first output signal SN_NEXT1 is a valid pulse, the first control unit 21 is turned on; when the first output signal SN_NEXT1 is an invalid pulse, the first control unit 21 is turned off. Fig.28 The first control unit 21 shown includes a first transistor M1, which is a PMOS transistor. At this time, the valid pulse of the first output signal SN_NEXT1 is a low-level signal, and the invalid pulse is a high-level signal, that is, when the first output signal SN_NEXT1 is a low-level signal, the first transistor M1 in the first control unit 21 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the first transistor M1 in the first control unit 21 is turned off.

[0211] At this time, the first output signal SN_NEXT1 is substantially a control signal of the first control unit 21, connected to the control terminal of the first control unit 21, and the first output signal SN_NEXT1 is used to control the on or off of the first control unit 21. Optionally, when the first control unit 21 is turned on, the level signal corresponding to the first voltage signal V1 can be used to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT is output as an invalid pulse. Exemplarily, the invalid pulses of the first voltage signal V1 and the second output signal SN_OUT can both be low-level signals VGL.

[0212] Similarly, when the potential signal of the sixth node N6 is a valid pulse, the second control unit 22 is turned on; when the potential signal of the sixth node N6 is an invalid pulse, the second control unit 22 is turned off. At this time, the third output signal SN_NEXT2 is substantially a control signal of the second control unit 22, connected to the control end of the second control unit 22, and the second control unit 22 is controlled to be turned on or off by the third output signal SN_NEXT2. Optionally, when the second control unit 22 is turned on, the level signal corresponding to the frequency control signal SN_CTRL can be used to generate the potential signal of the second node N2.

[0213] Afterwards, the third control unit 23 can be set to turn on when the potential signal of the second node N2 is a valid pulse; the third control unit 23 can be turned off when the potential signal of the second node N2 is an invalid pulse. At this time, the potential signal of the second node N2 is essentially a control signal of the third control unit 23, which is connected to the control end of the third control unit 23, and the conduction or shutdown of the third control unit 23 is controlled by the potential signal of the second node N2. Optionally, when the third control unit 23 is turned on, the level signal corresponding to the second voltage signal V2 can be used to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT is output as a valid pulse. Exemplarily, the valid pulses of the second voltage signal V2 and the second output signal SN_OUT can both be high-level signals VGH.

[0214] Optionally, continue to refer to Fig.28 and Fig.29 The second control unit 22 includes a second transistor M2 and a second capacitor C2; the control end of the second transistor M2 is electrically connected to the sixth node N6, the first end of the second transistor M2 receives the frequency control signal SN_CTRL, the second end of the second transistor M2 is electrically connected to the first plate of the second capacitor C2 and the second node N2 respectively, and the second plate of the second capacitor C2 receives the fixed potential signal V'.

[0215] Specifically, the second transistor M2 can be set as a PMOS transistor, at which time, the valid pulse of the potential signal of the sixth node N6 is a low level signal, and the invalid pulse is a high level signal. Exemplarily, the first end of the second transistor M2 receives the frequency control signal SN_CTRL, and the second end of the second transistor M2 is electrically connected to the second node N2, that is, when the second transistor M2 is turned on, the potential signal of the frequency control signal SN_CTRL can be generated at the second node N2, and at the same time, the second end of the second transistor M2 is electrically connected to the second capacitor C2, and the second capacitor C2 can also store the potential signal of the frequency control signal SN_CTRL. When the second transistor M2 is turned off, the potential signal of the frequency control signal SN_CTRL stored in the second capacitor C2 can be released to the second node N2, so that the second node N2 still floats as the potential signal of the frequency control signal SN_CTRL. In a more understandable way, when the second transistor M2 is turned off, no matter whether the frequency control signal SN_CTRL at the first end of the second transistor M2 is a valid pulse or an invalid pulse, the potential signal at the second end of the second transistor M2 remains as the potential signal of the frequency control signal SN_CTRL. In other words, the function of the second transistor M2 is to write the frequency control signal SN_CTRL to the second node N2 after a complete pulse signal of the sixth node N6 is output, so as to prevent the sixth node N6 from outputting a valid pulse when the frequency control signal SN_CTRL jumps, resulting in an incomplete second output signal SN_OUT. That is, the setting of the second transistor M2 and the second capacitor C2 is the basis for solving the problem that the potential signal at the second node N2 is cut off by the frequency control signal SN_CTRL, resulting in an incomplete pulse signal output, thereby solving the problem that the effective pulse of the second output signal SN_OUT is cut off by the frequency control signal SN_CTRL, resulting in an incomplete pulse signal output.

[0216] First of all, it should be noted that Fig.29The valid pulses of the first output signal SN_NEXT1_m, the third output signal SN_NEXT2_m and the second output signal SN_OUT are all shown as high levels, and the invalid pulses are all shown as low levels, while the valid pulses of the frequency control signal SN_CTRL are shown as low levels, and the invalid pulses are all shown as high levels. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. Specifically, taking the first output signal SN_NEXT1_m and the third output signal SN_NEXT2_m of the m-th stage shift register 110 as examples, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for overlapping the first voltage edge (rising edge) of the first valid pulse of the first output signal SN_NEXT1 with the valid pulse (low level) of the frequency control signal SN_CTRL, and when the first voltage edge (rising edge) of the third output signal SN_NEXT2 is synchronized with the rising edge of the first valid pulse of the first output signal SN_NEXT1, the second control unit 20 outputs the first valid pulse to form the second output signal SN_OUT (high level). Afterwards, after the first valid pulse of the first output signal SN_NEXT1 is output, during the output of the first invalid pulse and the second valid pulse, when the falling edge of the third output signal SN_NEXT2 is synchronized with the falling edge of the second valid pulse of the first output signal SN_NEXT1, the second control unit 20 outputs the second valid pulse to form the second output signal SN_OUT (high level). In a more understandable way, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for controlling the time period corresponding to the first voltage edge (rising edge) of the first valid pulse of the first output signal SN_NEXT1 to be completely within the valid pulse (low level) time period of the frequency control signal SN_CTRL, and the time period corresponding to the first voltage edge (rising edge) of the first valid pulse of the first output signal SN_NEXT1 and the time period corresponding to the falling edge of the second valid pulse are completely within the valid pulse (high level) time period of the third output signal SN_NEXT2, corresponding to the formation of two consecutive valid pulses (high level) output of the second output signal SN_OUT.

[0217] Taking the first output signal SN_NEXT1_n and the third output signal SN_NEXT2_n of the n-th stage shift register 110 as an example, in the embodiment of the present invention, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse to form a second output signal SN_OUT (low level) through the frequency control signal SN_CTRL when the first voltage edge (rising edge) of the first valid pulse of the first output signal SN_NEXT1 overlaps with the invalid pulse (high level) of the frequency control signal SN_CTRL, regardless of whether the first voltage edge (rising edge) of the third output signal SN_NEXT2 is synchronized with the rising edge of the first valid pulse of the first output signal SN_NEXT1. Furthermore, taking the first output signal SN_NEXT1_y and the third output signal SN_NEXT2_y of the y-th stage shift register 110 as examples, in the embodiment of the present invention, through the frequency control signal SN_CTRL and the second control unit 20, it is responsible for when the first output signal SN_NEXT1 is an invalid pulse (low level), in other words, when the first output signal SN_NEXT1 has no first voltage edge, the second control unit 20 outputs an invalid pulse to form the second output signal SN_OUT (low level).

[0218] Optionally, continue to refer to Fig.19 , Fig. 22 , Fig.25 and Fig.28 The first control unit 10 and / or the second control unit 20 includes a plurality of transistors, and the channel types of the transistors are all P-type.

[0219] Specifically, the manufacturing method of PMOS transistors is simple and occupies less frame space, which is conducive to saving frame space and avoiding risks such as low mobility, weakened output capacity, and circuit structure failure.

[0220] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Fig.30 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.30 As shown, the display device includes the display panel 1 provided by any embodiment of the present invention. Therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, which will not be repeated here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, which is not limited by the embodiment of the present invention.

[0221] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: A driving circuit, the driving circuit comprising N stages of shift registers cascaded to each other, N≥2; The shift register comprises: a first control unit and a second control unit, wherein the first control unit is electrically connected to the second control unit; The first control unit is used to control a first output signal, the first output signal of the i-th stage shift register is the first input signal of the j-th stage shift register, 1≤i≤N, 2≤j≤N; the first control unit includes a first node, the potential of the first node is synchronized with the first output signal; The second control unit receives at least a frequency control signal and a potential signal of the first node to control a second output signal; The process in which the first output signal jumps from an invalid level to a valid level is a first voltage edge; When the first voltage edge of the first output signal overlaps with a valid pulse of the frequency control signal, the second output signal is a valid pulse.

2. The display panel according to claim 1, characterized in that: When the first voltage edge of the first output signal overlaps with an invalid pulse of the frequency control signal, the second output signal is an invalid pulse.

3. The display panel according to claim 1, characterized in that: When the first output signal is an invalid pulse, the second output signal is an invalid pulse.

4. The display panel according to claim 1, characterized in that: The pulse change frequency of the first output signal is F1, and the pulse change frequency of the second output signal is F2; ​​wherein F1≥F2.

5. The display panel according to claim 4, characterized in that: When the first voltage edge of the first output signal overlaps with a valid pulse of the frequency control signal, or when the first output signal is an invalid pulse, F1=F2; When the first voltage edge of the first output signal overlaps with the invalid pulse of the frequency control signal, F1>F2.

6. The display panel according to claim 1, characterized in that: The display panel comprises a pixel circuit, and the second output signal of the driving circuit is a control signal of a preset module of the pixel circuit; When the second output signal is a valid pulse, the preset module is turned on; When the second output signal is an invalid pulse, the preset module is turned off.

7. The display panel according to claim 6, characterized in that: The working process of the display panel includes a first mode and a second mode; In the first mode, the pulse change frequency of the frequency control signal is Fc1, and in the second mode, the pulse change frequency of the frequency control signal is Fc2, wherein Fc1≠Fc2; and / or, In the first mode, the time length of the effective pulse of the frequency control signal is Wc1, and in the second mode, the time length of the effective pulse of the frequency control signal is Wc2, wherein Wc1≠Wc2.

8. The display panel according to claim 7, characterized in that: In the first mode, the pulse change frequency of the second output signal is Fs1, and in the second mode, the pulse change frequency of the second output signal is Fs2; wherein Fs1≠Fs2.

9. The display panel according to claim 1, characterized in that: The second control unit includes a first control unit, a second control unit, a third control unit and a second node; The first control unit further includes a third node, the potential of the third node is inverse to the first output signal; The first control unit receives the potential signal of the first node and the first voltage signal, and is used to control the second output signal to be output as an invalid pulse; The second control unit receives the potential signal of the first node and the frequency control signal, and is used to control the potential of the second node; The third control unit receives the potential signal of the second node, the potential signal of the third node and the second voltage signal, and is used to control the second output signal to be output as a valid pulse; or, The second control unit receives the potential signal of the first node and the frequency control signal, and is used to control the potential of the second node; The third control unit receives the potential signal of the second node and the potential signal of the third node, and is used to control the second output signal to be output as a valid pulse; One of the first voltage signal and the second voltage signal is a high level signal, and the other is a low level signal.

10. The display panel according to claim 9, characterized in that: The first control unit includes a first transistor, a control terminal of the first transistor is electrically connected to the first node, a first terminal of the first transistor receives the first voltage signal, and a second terminal of the first transistor outputs an invalid pulse of the second output signal.

11. The display panel according to claim 10, characterized in that: The first control unit further includes a first capacitor, a first plate of the first capacitor is connected to the control end of the first transistor, and a second plate of the first capacitor is connected to the second end of the first transistor.

12. The display panel according to claim 9, characterized in that: The second control unit includes a second transistor and a second capacitor; The control end of the second transistor is electrically connected to the first node, the first end of the second transistor receives the frequency control signal, the second end of the second transistor is electrically connected to the first plate of the second capacitor and the second node respectively, and the second plate of the second capacitor receives a fixed potential signal.

13. The display panel according to claim 9, characterized in that: The third control unit includes a third transistor, a control terminal of the third transistor is electrically connected to the third node, a first terminal of the third transistor is electrically connected to the second node, and a second terminal of the third transistor outputs a valid pulse of the second output signal.

14. The display panel according to claim 9, characterized in that: The third control unit includes a fourth transistor, a fifth transistor and a sixth transistor; The control terminal of the fourth transistor is electrically connected to the second node, the first terminal of the fourth transistor is electrically connected to the third node, and the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor and the control terminal of the sixth transistor respectively; The control terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor receives a third voltage signal; the third voltage signal has the same potential as the effective pulse of the first output signal; The first terminal of the sixth transistor receives the second voltage signal, and the second terminal of the sixth transistor outputs a valid pulse of the second output signal.

15. The display panel according to claim 14, characterized in that: The third control unit further includes a third capacitor, a first plate of the third capacitor is electrically connected to the control end of the sixth transistor, and a second plate of the third capacitor is electrically connected to the first end of the sixth transistor.

16. The display panel according to claim 14, characterized in that: The second voltage signal and the third voltage signal are voltage signals with the same potential.

17. The display panel according to claim 9, characterized in that: When the first voltage edge of the first output signal overlaps with the invalid pulse of the frequency control signal, neither the first control unit nor the third control unit outputs anything, and the second output signal maintains the level state of the second output signal when the first output signal is an invalid pulse.

18. The display panel according to claim 9, characterized in that: The second control unit also includes a fourth control unit, which receives at least the potential signal of the first node and controls the second output signal to output an invalid pulse when the first voltage edge of the first output signal overlaps with the invalid pulse of the frequency control signal.

19. The display panel according to claim 18, characterized in that: The fourth control unit is further used to control the second output signal to output a valid pulse when the first voltage edge of the first output signal overlaps with the valid pulse of the frequency control signal and the first output signal is a valid pulse.

20. The display panel according to claim 18, characterized in that: The fourth control unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a fourth capacitor; The control terminal of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor receives a fourth voltage signal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor and the first terminal of the ninth transistor respectively; The second end of the eighth transistor receives a fifth voltage signal, and the conduction state of the eighth transistor is synchronized with the conduction state of the third control unit; The control terminal of the ninth transistor receives a sixth voltage signal, and the second terminal of the ninth transistor is respectively connected to the control terminal of the tenth transistor and the first plate of the fourth capacitor; The first end of the tenth transistor receives the seventh voltage signal, and the second end of the tenth transistor is electrically connected to the second plate of the fourth capacitor and outputs the second output signal; The fourth voltage signal has the same potential as the invalid pulse of the second output signal, the fifth voltage signal has the same potential as the valid pulse of the second output signal, the sixth voltage signal is configured to control the ninth transistor to be normally open, and the seventh voltage signal has the same potential as the invalid pulse of the second output signal.

21. The display panel according to claim 20, characterized in that: The first voltage signal, the fourth voltage signal, the sixth voltage signal and the seventh voltage signal are signals of the same potential; The fifth voltage signal and the second voltage signal are signals of the same potential.

22. The display panel according to claim 20, characterized in that: At least two of the fourth voltage signal, the sixth voltage signal, and the seventh voltage signal are voltage signals of the same potential.

23. The display panel according to claim 1, characterized in that: The first control unit includes a fifth control unit, a sixth control unit and a seventh control unit; The fifth control unit is used to receive the first input signal, the eighth voltage signal, the ninth voltage signal and the clock signal, and control the potential of the fourth node and the potential of the fifth node; One end of the sixth control unit receives the tenth voltage signal, the other end of the sixth control unit is used to output the first output signal, and the control end of the sixth control unit is electrically connected to the fourth node; One end of the seventh control unit receives the eleventh voltage signal, the other end of the seventh control unit is used to output the first output signal, and the control end of the seventh control unit is electrically connected to the fifth node; One of the eighth voltage signal and the ninth voltage signal is a high level signal, and the other is a low level signal; One of the tenth voltage signal and the eleventh voltage signal is a high level signal, and the other is a low level signal.

24. The display panel according to claim 23, characterized in that: The eighth voltage signal and the tenth voltage signal are voltage signals of the same potential; the ninth voltage signal and the eleventh voltage signal are voltage signals of the same potential.

25. The display panel according to claim 23, characterized in that: The fifth control unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a fifth capacitor; The first end of the eleventh transistor and the control end of the twelfth transistor are electrically connected to receive the first input signal, the control end of the eleventh transistor, the first plate of the fifth capacitor and the first end of the thirteenth transistor are electrically connected to receive the clock signal, and the second end of the eleventh transistor is electrically connected to the first end of the fourteenth transistor and the control end of the fifteenth transistor respectively; The first end of the twelfth transistor is electrically connected to the second plate of the fifth capacitor and the control end of the thirteenth transistor respectively, and the second end of the twelfth transistor is electrically connected to the first end of the fifteenth transistor and receives the eighth voltage signal; The second end of the thirteenth transistor and the second end of the fifteenth transistor are both electrically connected to the fourth node; The second terminal of the fourteenth transistor is electrically connected to the fifth node, and the control terminal of the fourteenth transistor receives the ninth voltage signal.

26. The display panel according to claim 23, characterized in that: The sixth control unit includes a sixteenth transistor and a sixth capacitor; The control end of the sixteenth transistor and the first plate of the sixth capacitor are both electrically connected to the fourth node, the first end of the sixteenth transistor and the second plate of the sixth capacitor are electrically connected and receive the tenth voltage signal, and the second end of the sixteenth transistor outputs the first output signal.

27. The display panel according to claim 23, characterized in that: The seventh control unit includes a seventeenth transistor and a seventh capacitor; The control end of the seventeenth transistor and the first plate of the seventh capacitor are both electrically connected to the fifth node, the first end of the seventeenth transistor receives the eleventh voltage signal, and the second end of the seventeenth transistor is electrically connected to the second plate of the seventh capacitor and outputs the first output signal.

28. The display panel according to claim 9, characterized in that: The first control unit is further used to control a third output signal, wherein the third output signal of the i-th stage shift register is the second input signal of the j-th stage shift register; Within a preset time range, the first output signal includes a first valid pulse, a first invalid pulse, and a second valid pulse that are adjacent to each other in sequence; during a time period of the first valid pulse, the first invalid pulse, and the second valid pulse, the third output signal is a valid pulse, and a voltage edge of the third output signal that transitions from an invalid level to a valid level is synchronized with a voltage edge of the first valid pulse that transitions from an invalid level to a valid level; The voltage edge at which the third output signal changes from a valid level to an invalid level is synchronized with the voltage edge at which the second valid pulse changes from a valid level to an invalid level; The second control unit receives the potential signal of the first node, the frequency control signal, and the third output signal, and controls the second output signal.

29. The display panel according to claim 28, characterized in that: The first control unit includes an eighth control unit, the eighth control unit is used to receive the second input signal, the twelfth voltage signal and the clock signal, and control the third output signal; The twelfth voltage signal has the same potential as the invalid pulse of the third output signal.

30. The display panel according to claim 29, characterized in that: The eighth control unit includes an eighteenth transistor and an eighth capacitor; The first end of the eighteenth transistor receives the second input signal, the second end of the eighteenth transistor is electrically connected to the first plate of the eighth capacitor and outputs the third output signal; the second plate of the eighth capacitor receives the twelfth voltage signal.

31. The display panel according to claim 1, characterized in that: The first control unit and / or the second control unit includes a plurality of transistors, and the channel types of the transistors are all P-type.

32. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-31.

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