Display substrate and display device

Abstract

A display substrate comprises a substrate (10) and a gate drive circuit arranged on the substrate (10), the gate drive circuit comprises: a plurality of cascaded shift register circuits (GOA), each shift register circuit (GOA) comprises: a plurality of NOT gate circuits, each NOT gate circuit comprises: a first control transistor and a second control transistor, the first control transistor and the second control transistor have different transistor types. The arrangement modes of transistors of at least two NOT gate circuits in a plurality of NOT gate circuits of the shift register circuit (GOA) are different.

Description

[0001] This application is a divisional application of an application with an application date of September 19, 2023, application number 202380010761.2, and invention name “Display substrate and display device”. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] On the one hand, this embodiment provides a display substrate, comprising: a substrate and a gate driving circuit arranged on the substrate, the gate driving circuit comprising a multi-stage shift register circuit, the shift register circuit comprising an oxide output transistor and a plurality of oxide switching transistors; the oxide output transistor comprising a first bottom gate layer, a first top gate layer, and an active layer at least partially located between the first bottom gate layer and the first top gate layer; the oxide switching transistor comprising a second bottom gate layer, a second top gate layer, and an active layer at least partially located between the second bottom gate layer and the second top gate layer; the first bottom gate layer and the second bottom gate layer are independent of each other; the first bottom gate layer and the first top gate layer are coupled; the second bottom gate layers of at least some of the oxide switching transistors among the plurality of oxide switching transistors are coupled.

[0007] In some exemplary embodiments, all second bottom gate layers included in the plurality of oxide switching transistors are coupled.

[0008] In some exemplary embodiments, the multiple oxide switching transistors are divided into at least two transistor groups, each transistor group includes at least one oxide switching transistor; the second bottom gate layers of the multiple oxide switching transistors belonging to the same transistor group are coupled; and the second bottom gate layers of the oxide switching transistors belonging to different transistor groups are independent of each other.

[0009] In some exemplary embodiments, the shift register circuit includes a plurality of functional modules, and oxide switch transistors belonging to the same functional module are divided into the same transistor group.

[0010] In some exemplary embodiments, the second bottom gate layer included in the oxide switch transistor of the at least some oxide switch transistors extends along a first direction or a second direction, and the first direction intersects the second direction. The display substrate further includes: at least one bottom gate connection portion, the bottom gate connection portion being coupled to the second bottom gate layer included in the corresponding oxide switch transistor.

[0011] In some exemplary embodiments, the at least some oxide switch transistors are divided into a first transistor group and a second transistor group. The display substrate includes: a first bottom gate connection portion and a second bottom gate connection portion, the first bottom gate connection portion is coupled to the second bottom gate layer included in the oxide switch transistors in the first transistor group, and the second bottom gate connection portion is coupled to the second bottom gate layer included in the oxide switch transistors in the second transistor group. The first bottom gate connection portion and the second bottom gate connection portion are coupled through a first conductive connection portion; or, the first bottom gate connection portion and the second bottom gate connection portion are independent of each other.

[0012] In some exemplary embodiments, the first bottom gate connection portion and the second bottom gate layer coupled thereto are an integrated structure connected to each other, and the second bottom gate connection portion and the second bottom gate layer coupled thereto are an integrated structure connected to each other. The first bottom gate connection portion and the second bottom gate connection portion are provided in the same layer and the same material, and the first bottom gate connection portion and the first conductive connection portion are provided in different layers.

[0013] In some exemplary embodiments, the display substrate further includes: a second gate metal layer and a first source-drain metal layer; the first bottom gate connection portion is located in the second gate metal layer, and the first conductive connection portion is located in the first source-drain metal layer.

[0014] In some exemplary embodiments, when the first bottom gate connection portion and the second bottom gate connection portion are independent of each other, the display substrate further includes: a first signal line and a second signal line, the first signal line is coupled to the first bottom gate connection portion, and the second signal line is coupled to the second bottom gate connection portion.

[0015] In some exemplary embodiments, in two adjacent shift register circuits, the second bottom gate layer of at least a portion of the oxide switching transistors in the previous shift register circuit is coupled to the second bottom gate layer of at least a portion of the oxide switching transistors in the next shift register circuit; or, the second bottom gate layer of the oxide switching transistor in the previous shift register circuit is independent of the second bottom gate layer of the oxide switching transistor in the next shift register circuit.

[0016] In some exemplary embodiments, the second bottom gate layer of at least part of the oxide switch transistor in the previous shift register circuit and the second bottom gate layer of at least part of the oxide switch transistor in the next shift register circuit are interconnected as an integrated structure.

[0017] In some exemplary embodiments, the second bottom gate layer of at least a portion of the oxide switching transistors in the previous stage shift register circuit is coupled to the second bottom gate layer of at least a portion of the oxide switching transistors in the next stage shift register circuit through a second conductive connection portion, and the second conductive connection portion is arranged in a different layer from the second bottom gate layer.

[0018] In some exemplary embodiments, the shift register circuit further includes: a light-shielding layer and a plurality of low-temperature polysilicon transistors, wherein an orthographic projection of the light-shielding layer on the substrate at least partially overlaps with an orthographic projection of an active layer of the low-temperature polysilicon transistor on the substrate; and at least a portion of the light-shielding layer of the shift register circuit is coupled.

[0019] In some exemplary embodiments, the light shielding layer included in at least a portion of the shift register circuit is coupled via a third conductive connection portion, and the third conductive connection portion is disposed in a different layer from the light shielding layer.

[0020] In some exemplary embodiments, the display substrate further includes: a nineteenth conductive connection portion, the nineteenth conductive connection portion being coupled to the first bottom gate layer and the first top gate layer, respectively.

[0021] On the other hand, this embodiment provides a display device, including the display substrate as described above.

[0022] On the other hand, the present embodiment provides a driving method for a display substrate, which is used to drive the display substrate as described above, and the driving method includes: providing the same signal to the first bottom gate layer and the first top gate layer to control the oxide output transistor to be turned on or off; independently providing signals to the second bottom gate layer and the second top gate layer of the oxide switching transistor, wherein the second bottom gate layers of at least some of the multiple oxide switching transistors are coupled to receive the same signal.

[0023] On the other hand, the present embodiment provides a display substrate, comprising: a substrate and a gate driving circuit arranged on the substrate, the gate driving circuit comprising: a plurality of cascaded shift register circuits, the shift register circuit comprising: a plurality of NOT gate circuits, the NOT gate circuit comprising: a first control transistor and a second control transistor, the transistor types of the first control transistor and the second control transistor being different; the gate of the first control transistor is connected to the gate of the second control transistor, as the first input end of the NOT gate circuit; the second electrode of the first control transistor is connected to the second electrode of the second control transistor, as the output end of the NOT gate circuit; the first electrode of the first control transistor is used as the second input end of the NOT gate circuit; the first electrode of the second control transistor is used as the third input end of the NOT gate circuit, and the second input end and the third input end of the NOT gate circuit are configured to access different voltage signals. The transistor arrangement of at least two NOT gate circuits among the plurality of NOT gate circuits of the shift register circuit is different.

[0024] In some exemplary embodiments, at least one of the multiple NOT gate circuits satisfies one of the following: the active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit have the same extension direction, and the arrangement direction of the first control transistor and the second control transistor is the same as the extension direction of the active layer; the active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit have the same extension direction, and the arrangement direction of the first control transistor and the second control transistor crosses the extension direction of the active layer; the extension directions of the active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit cross, and the arrangement direction of the first control transistor and the second control transistor is the same as the extension direction of the active layer of the first control transistor or the second control transistor.

[0025] In some exemplary embodiments, the plurality of NOT gate circuits include at least: a first NOT gate circuit and a second NOT gate circuit; the output end of the first NOT gate circuit is connected to the output end of the second NOT gate circuit; the first NOT gate circuit and the second NOT gate circuit are adjacent in the second direction; the transistor arrangement of the first NOT gate circuit is the same as the transistor arrangement of the second NOT gate circuit; the active layer of the first control transistor of the first NOT gate circuit and the active layer of the first control transistor of the second NOT gate circuit are an integrated structure connected to each other.

[0026] In some exemplary embodiments, the second input terminal of the first NOT gate circuit is connected to the first voltage line through a first transmission transistor, the second input terminal of the second NOT gate circuit is connected to the first voltage line through a second transmission transistor, and the first transmission transistor, the second transmission transistor and the first control transistor are of the same transistor type. The active layers of the first control transistor of the first NOT gate circuit, the first control transistor of the second NOT gate circuit, the first transmission transistor and the second transmission transistor are interconnected as an integrated structure, and the orthographic projection shape of the integrated structure on the substrate is C-shaped or ring-shaped.

[0027] In some exemplary embodiments, the third input terminal of the first NOT gate circuit is connected to the second voltage line through a third transfer transistor, the third input terminal of the second NOT gate circuit is connected to the second voltage line through a fourth transfer transistor, and the third transfer transistor, the fourth transfer transistor and the second control transistor are of the same transistor type. The gate of the third transfer transistor is connected to the gate of the second transfer transistor, and the gate of the fourth transfer transistor is connected to the gate of the first transfer transistor. The active layer of the second control transistor of the first NOT gate circuit and the active layer of the third transfer transistor are an integrated structure connected to each other; the active layer of the second control transistor of the second NOT gate circuit and the active layer of the fourth transfer transistor are an integrated structure connected to each other.

[0028] In some exemplary embodiments, the plurality of NOT gate circuits further include: a third NOT gate circuit, a first input terminal of the third NOT gate circuit being connected to output terminals of the first NOT gate circuit and the second NOT gate circuit, and an output terminal of the third NOT gate circuit being connected to a first input terminal of the second NOT gate circuit. The third NOT gate circuit is adjacent to the second NOT gate circuit in the second direction; and a transistor arrangement mode of the third NOT gate circuit is the same as a transistor arrangement mode of the second NOT gate circuit.

[0029] In some exemplary embodiments, the first input terminal of the third NOT gate circuit is connected to an integrated structure of active layers of the first control transistor of the first NOT gate circuit and the first control transistor of the second NOT gate circuit.

[0030] In some exemplary embodiments, the second electrode of the first control transistor of the third NOT gate circuit and the second electrode of the second control transistor are connected to the gate of the first control transistor of the second NOT gate circuit through different conductive connecting parts, and the gate of the second control transistor of the second NOT gate circuit and the second electrode of the second control transistor of the third NOT gate circuit are connected to the gate of the first control transistor of the second NOT gate circuit through the same conductive connecting part.

[0031] In some exemplary embodiments, the plurality of NOT gate circuits further include: a fourth NOT gate circuit; a first input terminal of the fourth NOT gate circuit is connected to the gate of the second transmission transistor, and an output terminal of the fourth NOT gate circuit is connected to the gate of the first transmission transistor; a transistor arrangement of the fourth NOT gate circuit is different from a transistor arrangement of the first NOT gate circuit and the second NOT gate circuit. The fourth NOT gate circuit is located on the same side of the first NOT gate circuit and the second NOT gate circuit in a first direction; the first direction intersects the second direction.

[0032] In some exemplary embodiments, the first input terminal of the fourth NOT gate circuit of the 2i-1th stage shift register circuit of the gate drive circuit is connected to the first clock signal line, and the first input terminal of the fourth NOT gate circuit of the 2ith stage shift register circuit of the gate drive circuit is connected to the second clock signal line, and i is an integer greater than 0.

[0033] In some exemplary embodiments, the shift register circuit further includes: a NAND gate circuit; the NAND gate circuit is connected to at least one NAND gate circuit. The NAND gate circuit includes: a third control transistor, a fourth control transistor, a fifth control transistor and a sixth control transistor; the third control transistor and the fourth control transistor are of the same transistor type, and the fifth control transistor and the sixth control transistor are of the same transistor type. The gates of the third control transistor and the fifth control transistor are connected as the first input terminal of the NAND gate circuit; the gates of the fourth control transistor and the sixth control transistor are connected as the second input terminal of the NAND gate circuit; the first electrode of the third control transistor is connected to the first electrode of the fourth control transistor as the third input terminal of the NAND gate circuit; the second electrode of the third control transistor, the second electrode of the fourth control transistor and the second electrode of the fifth control transistor are connected as the output terminal of the NAND gate circuit; the first electrode of the fifth control transistor is connected to the second electrode of the sixth control transistor; the first electrode of the sixth control transistor is used as the fourth input terminal of the NAND gate circuit; the third input terminal and the fourth input terminal of the NAND gate circuit are configured to access different voltage signals. The third control transistor and the fourth control transistor are located between the fifth control transistor and the sixth control transistor.

[0034] In some exemplary embodiments, the sixth control transistor, the fourth control transistor, the third control transistor and the fifth control transistor are arranged sequentially along the second direction; the gate of the sixth control transistor, the gate of the fourth control transistor, the gate of the third control transistor and the gate of the fifth control transistor are arranged alternately in the second direction.

[0035] In some exemplary embodiments, the active layer of the third control transistor and the active layer of the fourth control transistor are interconnected as an integral structure, and an orthographic projection shape of the integral structure on the substrate is C-shaped or ring-shaped.

[0036] In some exemplary embodiments, the plurality of NOT gate circuits include: a fifth NOT gate circuit and a sixth NOT gate circuit. The input terminal of the sixth NOT gate circuit is connected to the output terminal of the fifth NOT gate circuit, and the output terminal of the sixth NOT gate circuit is connected to the second input terminal of the NAND gate circuit. The fifth NOT gate circuit is adjacent to the sixth NOT gate circuit in the first direction; the fifth NOT gate circuit and the sixth NOT gate circuit are located on the same side of the NAND gate circuit in the second direction; the first direction intersects the second direction. The transistor arrangement of the fifth NOT gate circuit is the same as the transistor arrangement of the sixth NOT gate circuit.

[0037] In some exemplary embodiments, the first control transistor of the fifth NOT gate circuit and the first control transistor of the sixth NOT gate circuit are aligned in the first direction, and the second control transistor of the fifth NOT gate circuit and the second control transistor of the sixth NOT gate circuit are aligned in the first direction.

[0038] In some exemplary embodiments, the plurality of NOT gate circuits further include: a seventh NOT gate circuit. The input end of the seventh NOT gate circuit is connected to the output end of the NAND gate circuit, and the output end of the seventh NOT gate circuit serves as the driving output end of the shift register circuit. The first control transistor and the second control transistor of the seventh NOT gate circuit are arranged along the second direction, the first control transistor is adjacent to the NAND gate circuit in the first direction, and the first direction intersects with the second direction.

[0039] In some exemplary embodiments, the shift register circuit at least includes: a cascade signal generating circuit, a gating circuit, a voltage maintaining circuit, an output control circuit and an output circuit; the cascade signal generating circuit includes at least one NOT gate circuit, the output circuit includes at least one NOT gate circuit, the voltage maintaining circuit includes at least one NOT gate circuit, and the output control circuit includes a NAND gate circuit. The cascade signal generating circuit is connected to the cascade input terminal and the cascade output terminal, and is configured to perform a shift operation on the cascade signal provided by the previous stage shift register circuit received by the cascade input terminal, and provide the cascade signal of the current stage shift register circuit to the cascade output terminal. The gating circuit is connected to the gating input terminal, the cascade input terminal, the cascade output terminal and the third node, and is configured to write the gating input signal provided by the gating input terminal to the third node under the control of the cascade output terminal and the cascade input terminal. The voltage maintaining circuit is connected to the third node, the cascade input terminal, the clock signal terminal and the fifth node, and is configured to control the potential of the fifth node under the control of the third node, the cascade input terminal and the clock signal terminal. The output control circuit is connected to the cascade output terminal, the fifth node and the sixth node, and is configured to perform a negative AND operation on the potential of the cascade output terminal and the fifth node to control the potential of the sixth node. The output circuit is connected to the sixth node and the drive output terminal, and is configured to perform an inverting operation on the potential of the sixth node to output a drive signal. The output control circuit is located between the cascade signal generating circuit and the output circuit in the first direction, the gating circuit is adjacent to the cascade signal generating circuit in the second direction, the voltage maintaining circuit is located between the gating circuit and the output circuit in the first direction, and is adjacent to the output control circuit in the second direction; the first direction intersects with the second direction.

[0040] In some exemplary embodiments, the shift register circuit further includes: an initialization circuit, the initialization circuit being connected to the initial control terminal, the third node, and the cascade output terminal, and configured to initialize the third node and the cascade output terminal under the control of the initial control terminal. The initialization circuit is located on a side of the gating circuit away from the voltage maintaining circuit in the first direction, and is adjacent to the cascade signal generating circuit in the second direction.

[0041] In some exemplary embodiments, the gating circuit includes: a seventeenth transistor and an eighteenth transistor; the seventeenth transistor and the eighteenth transistor are of different transistor types. The gate of the seventeenth transistor is connected to the cascade output terminal, the first electrode of the seventeenth transistor is connected to the gating input terminal, and the second electrode of the seventeenth transistor is connected to the first electrode of the eighteenth transistor; the gate of the eighteenth transistor is connected to the cascade input terminal, and the second electrode of the eighteenth transistor is connected to the third node. The seventeenth transistor and the eighteenth transistor are arranged in sequence along the second direction, and the eighteenth transistor is adjacent to the cascade signal generating circuit in the second direction.

[0042] In some exemplary embodiments, the first control transistor is a low temperature polysilicon transistor, and the second control transistor is an oxide transistor.

[0043] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the base. The first semiconductor layer includes at least: an active layer of the first control transistor. The first conductive layer includes at least: a gate of the first control transistor. The second conductive layer includes at least: a bottom gate of the second control transistor. The second semiconductor layer includes at least: an active layer of the second control transistor. The third conductive layer includes at least: a top gate of the second control transistor. The fourth conductive layer includes at least: a plurality of conductive connection portions connected to the first control transistor and the second control transistor. The fifth conductive layer includes at least: a signal line connected to the shift register circuit.

[0044] In some exemplary embodiments, the shift register circuit includes a plurality of oxide transistors, the plurality of oxide transistors including: an oxide output transistor and a plurality of oxide switch transistors; the oxide output transistor is connected to a driving output terminal. The bottom gate of the oxide output transistor is independently arranged from the bottom gates of the plurality of oxide switch transistors, and the bottom gate of the oxide output transistor is connected to a top gate. The bottom gates of at least some of the oxide switch transistors in the plurality of oxide switch transistors are interconnected as an integrated structure.

[0045] On the other hand, this embodiment provides a display device, including the display substrate as described above.

[0046] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to provide further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0048] Figure 1 is a schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0049] Figure 2 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0050] Figure 3 is a partial cross-sectional schematic diagram of a display area of ​​a display substrate of at least one embodiment of the present disclosure;

[0051] Figure 4 is a partial top view schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0052] Figure 5 for Figure 4 A schematic diagram of a display substrate after forming a first semiconductor layer;

[0053] Fig. 6A for Figure 4 A schematic diagram of a display substrate after forming a first conductive layer;

[0054] Figure 6B for Fig. 6A A schematic diagram of a first conductive layer in FIG.

[0055] Fig. 7A for Figure 4 A schematic diagram of a display substrate after a second conductive layer is formed in FIG.

[0056] Figure 7B for Fig. 7A A schematic diagram of a second conductive layer in FIG.

[0057] Fig. 8A for Figure 4 A schematic diagram of a display substrate after forming a second semiconductor layer;

[0058] Figure 8B for Fig. 8A A schematic diagram of a second semiconductor layer in FIG.

[0059] Fig. 9A for Figure 4 A schematic diagram of a display substrate after a third conductive layer is formed;

[0060] Fig. 9B for Fig. 9A A schematic diagram of a third conductive layer in FIG.

[0061] Fig. 10A and Fig. 10Bfor Figure 4 A schematic diagram of a display substrate after a fifth insulating layer is formed;

[0062] Fig.11 for Figure 4 A schematic diagram of a fourth conductive layer in FIG.

[0063] Fig.12 A schematic diagram of a display substrate after a seventh insulating layer is formed according to at least one embodiment of the present disclosure;

[0064] Fig.13A A schematic diagram of a display substrate after a fifth conductive layer is formed according to at least one embodiment of the present disclosure;

[0065] Fig. 13B for Fig.13A A schematic diagram of a fifth conductive layer in FIG.

[0066] Fig.14 A schematic diagram of the connection of the bottom gate connection portion of at least one embodiment of the present disclosure;

[0067] Fig.15 is another partial top view schematic diagram of a display substrate of at least one embodiment of the present disclosure;

[0068] Fig.16A for Fig.15 A schematic diagram of a display substrate after forming a first semiconductor layer;

[0069] Fig. 16B for Fig.15 A schematic diagram of a display substrate after forming a first conductive layer;

[0070] Fig. 16C for Fig.15 A schematic diagram of a fourth conductive layer in FIG.

[0071] Fig.17 is another partial top view schematic diagram of a display substrate of at least one embodiment of the present disclosure;

[0072] Fig.18A for Fig.17 A schematic diagram of a display substrate after a fourth conductive layer is formed;

[0073] Fig.18B for Fig.17 A schematic diagram of connection between the shift register circuit and the first clock signal line and the second clock signal line;

[0074] Fig.19 A schematic diagram of connecting bottom gate connecting parts of adjacent shift register circuits according to at least one embodiment of the present disclosure;

[0075] Fig. 20is another connection schematic diagram of bottom gate connection parts of adjacent shift register circuits according to at least one embodiment of the present disclosure;

[0076] Fig.21 Another connection diagram of the bottom gate connection portion of the shift register circuit according to at least one embodiment of the present disclosure;

[0077] Fig.22A for Fig.21 Schematic diagram of the bottom gate structure in FIG.

[0078] Fig. 22B and Fig. 22C for Fig.21 A schematic diagram of the connection relationship of the bottom gate connection part in FIG.

[0079] Fig.23 is a schematic diagram of a light shielding layer according to at least one embodiment of the present disclosure;

[0080] Fig.24 is another schematic diagram of a light shielding layer according to at least one embodiment of the present disclosure;

[0081] Fig.25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0083] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0084] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0085] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0086] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0087] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0088] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0089] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged. In addition, the gate electrode may also be called a control electrode.

[0090] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0091] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0092] In this disclosure, "about" and "substantially" mean that the limits are not strictly defined and the process and measurement errors are allowed. In this disclosure, "same" includes completely the same and substantially the same, and "substantially the same" means that the numerical values ​​differ by less than 10%.

[0093] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the present disclosure, "A extends along direction B" means "the main part of A extends along direction B".

[0094] With the rapid development of OLED display technology, multiple requirements have been put forward for display products, such as high resolution, narrow borders, and low power consumption. Partial refresh technology (for example, a part of the screen displays high-frequency refreshes, and another part displays low-frequency refreshes) has considerable benefits in reducing power consumption, so it has attracted much attention. In display products using partial refresh technology, the structure of the gate drive circuit is relatively complex. How to achieve better drive stability and how to reasonably plan the setting space of the gate drive circuit to take into account the narrowing of the border are problems that need to be solved.

[0095] The present embodiment provides a display substrate and a display device, which can effectively improve the driving stability of a gate driving circuit while reducing power consumption, and can reasonably plan the installation space of the gate driving circuit to save space while taking into account the narrowing of the frame.

[0096] The present embodiment provides a display substrate, comprising: a substrate and a gate drive circuit arranged on the substrate. The gate drive circuit comprises: a plurality of cascaded shift register circuits (also referred to as shift register units). The shift register circuit comprises: a plurality of NOT gate circuits. The NOT gate circuit comprises: a first control transistor and a second control transistor, and the transistor types of the first control transistor and the second control transistor are different. The gate of the first control transistor is connected to the gate of the second control transistor as the first input terminal of the NOT gate circuit; the second electrode of the first control transistor is connected to the second electrode of the second control transistor as the output terminal of the NOT gate circuit; the first electrode of the first control transistor is used as the second input terminal of the NOT gate circuit; the first electrode of the second control transistor is used as the third input terminal of the NOT gate circuit. The second input terminal and the third input terminal of the NOT gate circuit are configured to access different voltage signals. The transistor arrangement of at least two NOT gate circuits among the plurality of NOT gate circuits of the shift register circuit is different.

[0097] In this example, the transistor arrangement of the NOT gate circuit may include at least one of the following: the positional relationship between the first control transistor and the second control transistor of the NOT gate circuit, and the relationship between the extension directions of the active layers of the first control transistor and the second control transistor of the NOT gate circuit. The different transistor arrangement modes of at least two NOT gate circuits may include: the positional relationship of the transistors of at least two NOT gate circuits is different, such as the two transistors of one NOT gate circuit are arranged along the first direction, and the two transistors of another NOT gate circuit are arranged along the second direction; or, the relationship between the extension directions of the active layers of the transistors of at least two NOT gate circuits is different, such as the extension directions of the two transistors of one NOT gate circuit are the same, and the extension directions of the two transistors of another NOT gate circuit are crossed; or, the positional relationship and the extension directions of the active layers of at least two NOT gate circuits are different, such as the two transistors of one NOT gate circuit are arranged along the first direction, and the extension directions of the active layers of the two transistors are the same, and the two transistors of another NOT gate circuit are arranged along the second direction, and the extension directions of the active layers of the two transistors are crossed. This embodiment is not limited to this.

[0098] In some examples, the first control transistor may be a low temperature polysilicon transistor, and the second control transistor may be an oxide transistor. For example, the first control transistor may be a P-type transistor, and the second control transistor may be an N-type transistor. However, this embodiment is not limited to this. In other examples, the second control transistor may be a low temperature polysilicon transistor, and the first control transistor may be an oxide transistor.

[0099] In some examples, the NOT gate circuit may include: a first input terminal, a second input terminal, a third input terminal, and an output terminal. For example, the second input terminal may be connected to a first voltage signal, the third input terminal may be connected to a second voltage signal, and the first voltage signal may be greater than the second voltage signal. This embodiment is not limited to this.

[0100] The display substrate provided in this embodiment can realize a local refresh function by setting a shift register circuit including multiple NOT gate circuits to effectively reduce the power consumption of the display substrate; by adopting different arrangements of transistors of at least two NOT gate circuits of the shift register circuit, it is possible to save space, which is conducive to reasonable planning of the setting space of the shift register circuit to take into account the narrowing of the frame.

[0101] In some exemplary embodiments, at least one of the multiple NOT gate circuits of the shift register circuit may satisfy one of the following conditions: the active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit have the same extension direction, and the arrangement direction of the first control transistor and the second control transistor is the same as the extension direction of the active layer; the active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit have the same extension direction, and the arrangement direction of the first control transistor and the second control transistor intersects with the extension direction of the active layer; the active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit intersect, and the arrangement direction of the first control transistor and the second control transistor is the same as the extension direction of the active layer of the first control transistor or the second control transistor. This example can save space through the design of multiple NOT gate structures, which is conducive to the reasonable planning of the setting space of the shift register circuit to take into account the narrowing of the frame.

[0102] The solution of this embodiment is described below by means of some examples.

[0103] In some examples, the display substrate may include: a display area and a non-display area. For example, the non-display area may be a peripheral area located outside the display area. However, this embodiment is not limited to this. For example, the non-display area may be located between adjacent display areas.

[0104] In some examples, the display area may include multiple sub-pixels. A pixel unit in the display area may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.

[0105] In some examples, a sub-pixel may include: a pixel circuit (also referred to as a sub-pixel driving circuit) and a light-emitting element connected to the pixel circuit. The shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a herringbone manner; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a square manner. However, this embodiment is not limited to this.

[0106] In some examples, the display area may include at least: a plurality of pixel circuits arranged in an array (i.e., including a plurality of rows of pixel circuits and a plurality of columns of pixel circuits), a plurality of gate lines extending along a first direction (e.g., including: a scan line, a reset signal line, a light emitting control line), and a plurality of data lines and power lines extending along a second direction. The plurality of rows of pixel circuits may be arranged along the second direction, and each row of pixel circuits may include a plurality of pixel circuits arranged along the first direction. The first direction and the second direction may be located in the same plane, and the first direction intersects with the second direction, for example, the first direction may be perpendicular to the second direction. For example, the first direction may include a horizontal direction, and the second direction may include a vertical direction.

[0107] In some examples, the pixel circuit can be configured to drive the connected light-emitting element. For example, the pixel circuit can be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0108] In some examples, the pixel circuit may include a first type transistor and a second type transistor. The transistor types of the first type transistor and the second type transistor are different. For example, the first type transistor may be a P-type transistor, and the second type transistor may be an N-type transistor. The second type transistor may be, for example, an oxide thin film transistor, and the first type transistor may be, for example, a low temperature polycrystalline silicon thin film transistor. The active layer of the low temperature polycrystalline silicon thin film transistor adopts low temperature polycrystalline silicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). Low temperature polycrystalline silicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Low temperature polycrystalline silicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form a low temperature polycrystalline oxide (LTPO+Oxide) display substrate, which can take advantage of the advantages of both, can achieve low frequency driving, can reduce power consumption, and can improve display quality.

[0109] In some examples, the non-display area may be provided with a timing controller, a data driving circuit, and a gate driving circuit. Among them, the gate driving circuit may be respectively arranged on opposite sides of the display area, for example, the left and right sides of the display area (such as the left frame area and the right frame area included in the peripheral area); the timing controller and the data driving circuit may be arranged on one side of the display area, such as the lower side of the display area (such as the lower frame area included in the peripheral area). However, this embodiment is not limited to this. In some examples, the gate driving circuit may be located in the display area.

[0110] In some examples, the data driving circuit can provide a data signal to the sub-pixel of the display area through the data line. The timing controller can provide a driving signal to the data driving circuit and the gate driving circuit. Among them, the actions of the gate driving circuit and the data driving circuit can be controlled by the timing controller. The timing controller can provide the data driving circuit with grayscale data specifying the grayscale to be displayed in the sub-pixel. The data driving circuit can provide a data signal with a potential corresponding to the grayscale data of the sub-pixel to the sub-pixel of the row selected by the gate driving circuit via the data line.

[0111] In some examples, the display substrate may include multiple gate drive circuits, such as a gate drive circuit for outputting a scan signal, a gate drive circuit for outputting a light-emitting control signal, and the like. For example, the gate drive circuit for outputting a scan signal may provide a scan signal to a sub-pixel through a scan line, and provide a reset signal to the sub-pixel through a reset signal line; the gate drive circuit for outputting a light-emitting control signal may provide a light-emitting control signal to the sub-pixel through a light-emitting control line. Each gate drive circuit may include multiple cascaded shift register circuits. The output end of each stage of the shift register circuit may be respectively connected to a plurality of pixel circuits in a corresponding row of pixel circuits, and configured to provide a drive signal (e.g., a scan signal) to the pixel circuit in that row.

[0112] Figure 1 FIG. 4 is a schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure. Figure 1 The equivalent circuit diagram of the n-th stage shift register circuit is shown in FIG. , where n can be a positive integer greater than 1. In some examples, such as Figure 1 As shown, the shift register circuit provided in this embodiment may include: a cascade signal generating circuit 101 , a gating circuit 102 , an output control circuit 103 , an output circuit 104 , a voltage maintaining circuit 105 and an initialization circuit 106 .

[0113] In some examples, the cascade signal generating circuit 101 can be electrically connected to the cascade input terminal (also referred to as the first scan signal input terminal) NS(n-1), the clock signal terminal (also referred to as the first clock signal input terminal) CK, the first voltage input terminal (also referred to as the first level signal input terminal) VGH, the second voltage input terminal (also referred to as the second voltage signal input terminal) VGL and the cascade output terminal (also referred to as the second scan signal input terminal) NS(n), and is configured to perform a shift operation on the cascade signal provided by the n-1th stage shift register circuit received by the cascade input terminal NS(n-1), and output the cascade signal of the nth stage shift register circuit to the cascade output terminal NS(n). The cascade input terminal of the current stage shift register circuit (e.g., the nth stage shift register circuit) is connected to the cascade output terminal of the previous stage shift register circuit (e.g., the n-1th stage shift register circuit). The cascade signal generating circuit 101 of the shift register circuit at this stage (for example, the nth stage shift register circuit) can utilize the cascade signal output by the shift register circuit at the previous stage (for example, the n-1th stage shift register circuit) to generate the cascade signal of the shift register circuit at this stage, and provide it to the cascade input terminal of the shift register circuit at the next stage (for example, the n+1th stage shift register circuit).

[0114] In some examples, the gating circuit 102 can be connected to the gating input terminal (also referred to as the shielding signal input terminal) VCT, the cascade input terminal NS(n-1), the cascade output terminal NS(n) and the third node N3, and is configured to write the gating input signal provided by the gating input terminal VCT to the third node N3 under the control of the cascade input terminal NS(n-1) and the cascade output terminal NS(n).

[0115] In some examples, the voltage maintenance circuit 105 can be connected to the first voltage input terminal VGH, the second voltage input terminal VGL, the clock signal terminal CK, the cascade input terminal NS(n-1), the third node N3 and the fifth node N5, and is configured to control the potential of the fifth node N5 under the control of the third node N3, the cascade input terminal NS(n-1) and the clock signal terminal CK. The voltage maintenance circuit 105 can be configured to stabilize the selection input signal provided by the selection input terminal VCT and compensate for the transmission loss of the selection input signal.

[0116] In some examples, the output control circuit 103 can be connected to the cascade output terminal NS(n), the fifth node N5, the sixth node N6, the first voltage input terminal VGH, and the second voltage input terminal VGL, and is configured to perform a NAND operation on the potentials of the cascade output terminal NS(n) and the fifth node N5 to control the potential of the sixth node N6.

[0117] In some examples, the output circuit 104 can be connected to the sixth node N6, the drive output terminal (also referred to as the gate drive signal output terminal) NO(n), the first voltage input terminal VGH and the second voltage input terminal VGL, and is configured to invert the potential of the sixth node N6 and output a drive signal.

[0118] In some examples, the initialization circuit 106 can be connected to the initial control terminal (also referred to as the second clock signal input terminal) NCX, the cascade output terminal NS(n), the first voltage input terminal VGH and the third node N3, and is configured to initialize the cascade output terminal NS(n) and the third node N3 under the control of the initial control terminal NCX.

[0119] In some examples, the first voltage input terminal VGH can continuously provide a high-level first voltage signal, and the second voltage input terminal VGL can continuously provide a low-level second voltage signal. The first voltage signal can be greater than the second voltage signal. The first voltage input terminal VGH can be connected to a first voltage line that transmits a first voltage signal, and the second voltage input terminal VGL can be connected to a second voltage line that transmits a second voltage signal. However, this embodiment is not limited to this.

[0120] The “high level” and “low level” mentioned in this article are relative, and the voltage value of the “high level” and the voltage value of the “low level” are not limited.

[0121] In some examples, the cascade signal generating circuit 101 may include: a first control circuit, a second control circuit, a third control circuit, and a fourth control circuit. The first control circuit and the second control circuit may be inverting circuits including a transmission gate, and the third control circuit and the fourth control circuit may be inverting circuits. The first control circuit, the second control circuit, and the third control circuit are all connected to the second node N2, and the first control circuit, the second control circuit, and the fourth control circuit are all connected to the first node N1.

[0122] In some examples, the first control circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first transistor T1 and the second transistor T2 are of the same transistor type, the third transistor T3 and the fourth transistor T4 are of the same transistor type, and the transistor type of the second transistor T2 is different from the transistor type of the third transistor T3. The first transistor T1 and the second transistor T2 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0123] In some examples, the gate of the first transistor T1 is connected to the first node N1, the first electrode of the first transistor T1 is connected to the first voltage input terminal VGH, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2. The gate of the second transistor T2 is connected to the cascade input terminal NS(n-1), and the second electrode of the second transistor T2 is connected to the second node N2. The gate of the third transistor T3 is connected to the cascade input terminal NS(n-1), the second electrode of the third transistor T3 is connected to the second node N2, and the first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4. The gate of the fourth transistor T4 is connected to the clock signal terminal CK, and the first electrode of the fourth transistor T4 is connected to the second voltage input terminal VGL.

[0124] In some examples, the second control circuit may include: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The fifth transistor T5 and the sixth transistor T6 are of the same transistor type, the seventh transistor T7 and the eighth transistor T8 are of the same transistor type, and the sixth transistor T6 and the seventh transistor T7 are of different transistor types. The fifth transistor T5 and the sixth transistor T6 may be P-type transistors, and the seventh transistor T7 and the eighth transistor T8 may be N-type transistors.

[0125] In some examples, the gate of the fifth transistor T5 is connected to the clock signal terminal CK, the first electrode of the fifth transistor T5 is connected to the first voltage input terminal VGH, and the second electrode of the fifth transistor T5 is connected to the first electrode of the sixth transistor T6. The gate of the sixth transistor T6 is connected to the cascade output terminal NS(n), and the second electrode of the sixth transistor T6 is connected to the second node N2. The gate of the seventh transistor T7 is connected to the cascade output terminal NS(n), the second electrode of the seventh transistor T7 is connected to the second node N2, and the first electrode of the seventh transistor T7 is connected to the second electrode of the eighth transistor T8. The gate of the eighth transistor T8 is connected to the first node N1, and the first electrode of the eighth transistor T8 is connected to the second voltage input terminal VGL.

[0126] In some examples, the third control circuit may include: a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 and the tenth transistor T10 are of different transistor types. The ninth transistor T9 may be a P-type transistor, and the tenth transistor T10 may be an N-type transistor. The gate of the ninth transistor T9 is connected to the second node N2, the first electrode of the ninth transistor T9 is connected to the first voltage input terminal VGH, and the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 are both connected to the cascade output terminal NS(n). The gate of the tenth transistor T10 is connected to the second node N2, and the first electrode of the tenth transistor T10 is connected to the second voltage input terminal VGL.

[0127] In some examples, the fourth control circuit may include: a twenty-seventh transistor T27 and a twenty-eighth transistor T28. The transistor types of the twenty-seventh transistor T27 and the twenty-eighth transistor T28 are different. The twenty-seventh transistor T27 may be a P-type transistor, and the twenty-eighth transistor T28 may be an N-type transistor. The gate of the twenty-seventh transistor T27 is connected to the clock signal terminal CK, the first electrode of the twenty-seventh transistor T27 is connected to the first voltage input terminal VGH, and the second electrode of the twenty-seventh transistor T27 and the second electrode of the twenty-eighth transistor T28 are both connected to the first node N1. The gate of the twenty-eighth transistor T28 is connected to the clock signal terminal CK, and the first electrode of the twenty-eighth transistor T28 is connected to the second voltage input terminal VGL.

[0128] In some examples, the gating circuit 102 may include: a seventeenth transistor T17 and an eighteenth transistor T18. The transistor types of the seventeenth transistor T17 and the eighteenth transistor T18 may be different. The seventeenth transistor T17 may be a P-type transistor, and the eighteenth transistor T18 may be an N-type transistor. The gate of the seventeenth transistor T17 is connected to the cascade output terminal NS(n), the first electrode of the seventeenth transistor T17 is connected to the gating input terminal VCT, and the second electrode of the seventeenth transistor T17 is connected to the first electrode of the eighteenth transistor T18. The gate of the eighteenth transistor T18 is connected to the cascade input terminal NS(n-1), and the second electrode of the eighteenth transistor T18 is connected to the third node N3.

[0129] In some examples, a low level signal is provided at the cascade output terminal NS(n), the seventeenth transistor T17 is turned on, a high level signal is provided at the cascade input terminal NS(n-1), the eighteenth transistor T18 is turned on, and the gating input signal provided by the gating input terminal VCT can be written into the third node N3. A high level signal is provided at the cascade output terminal NS(n), the seventeenth transistor T17 is turned off, or a low level signal is provided at the cascade input terminal NS(n-1), the eighteenth transistor T18 is turned off, and the gating input signal provided by the gating input terminal VCT cannot be written into the third node N3. The gating circuit of this example realizes the transmission of the gating input signal by turning on two signals (the cascade signals of the previous stage and the current stage shift register circuit) at the same time, and the gating input signal state within a high-low frequency switching cycle can be obtained.

[0130] In some examples, the output control circuit 103 may include: a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, and a twenty-fourth transistor T24. The twenty-first transistor T21 and the twenty-second transistor T22 are of the same transistor type, and the twenty-third transistor T23 and the twenty-fourth transistor T24 are of the same transistor type. The twenty-first transistor T21 and the twenty-second transistor T22 may be P-type transistors, and the twenty-third transistor T23 and the twenty-fourth transistor T24 may be N-type transistors. The gate of the twenty-first transistor T21 is connected to the cascade output terminal NS(n), the first electrode of the twenty-first transistor T21 is connected to the first voltage input terminal VGH, and the second electrode of the twenty-first transistor T21 is connected to the sixth node N6. The gate of the twenty-second transistor T22 is connected to the fifth node N5, the first electrode of the twenty-second transistor T22 is connected to the first voltage input terminal VGH, and the second electrode of the twenty-second transistor T22 is connected to the sixth node N6. The gate of the twenty-third transistor T23 is connected to the cascade output terminal NS(n), the second electrode of the twenty-third transistor T23 is connected to the sixth node N6, the first electrode of the twenty-third transistor T23 is connected to the second electrode of the twenty-fourth transistor T24. The gate of the twenty-fourth transistor T24 is connected to the fifth node N5, and the first electrode of the twenty-fourth transistor T24 is connected to the second voltage input terminal VGL.

[0131] In some examples, the output circuit 104 may include: a nineteenth transistor T19 and a twentieth transistor T20. The nineteenth transistor T19 and the twentieth transistor T20 are of different transistor types. The nineteenth transistor T19 may be a P-type transistor, and the twentieth transistor T20 may be an N-type transistor. The gate of the nineteenth transistor T19 is connected to the sixth node N6, the first electrode of the nineteenth transistor T19 is connected to the first voltage input terminal VGH, and the second electrode of the nineteenth transistor T19 and the second electrode of the twentieth transistor T20 are both connected to the drive output terminal NO(n). The gate of the twentieth transistor T20 is connected to the sixth node N6, and the first electrode of the twentieth transistor T20 is connected to the second voltage input terminal VGL.

[0132] In some examples, the voltage maintaining circuit 105 may include: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a twenty-fifth transistor T25, and a twenty-sixth transistor T26. The twelfth transistor T12, the fourteenth transistor T14, and the twenty-fifth transistor T25 are of the same transistor type, for example, they may be P-type transistors; the thirteenth transistor T13, the fifteenth transistor T15, and the twenty-sixth transistor T26 are of the same transistor type, for example, they may be N-type transistors.

[0133] In some examples, the gate of the twelfth transistor T12 is connected to the third node N3, the first electrode of the twelfth transistor T12 is connected to the first voltage input terminal VGH, and the second electrode of the twelfth transistor T12 is connected to the fourth node N4. The gate of the thirteenth transistor T13 is connected to the third node N3, the second electrode of the thirteenth transistor T13 is connected to the fourth node N4, and the first electrode of the thirteenth transistor T13 is connected to the second voltage input terminal VGL. The gate of the fourteenth transistor T14 is connected to the fourth node N4, the first electrode of the fourteenth transistor T14 is connected to the first voltage input terminal VGH, and the second electrode of the fourteenth transistor T14 is connected to the fifth node N5. The gate of the fifteenth transistor T15 is connected to the fourth node N4, the second electrode of the fifteenth transistor T15 is connected to the fifth node N5, and the first electrode of the fifteenth transistor T15 is connected to the second voltage input terminal VGL. The gate of the twenty-fifth transistor T25 is connected to the cascade input terminal NS(n-1), the first electrode of the twenty-fifth transistor T25 is connected to the third node N3, and the second electrode of the twenty-fifth transistor T25 is connected to the fifth node N5. A gate of the twenty-sixth transistor T26 is connected to the clock signal terminal CK, a first electrode of the twenty-sixth transistor T26 is connected to the third node N3, and a second electrode of the twenty-sixth transistor T26 is connected to the fifth node N5.

[0134] In some examples, since the P-type transistor has a threshold voltage loss when transmitting a low voltage, and the N-type transistor has a threshold voltage loss when transmitting a high voltage, the absolute value of the potential of the third node N3 will decrease, and the absolute value of the potential of the third node N3 can be controlled to increase through the twelfth transistor T12 to the fifteenth transistor T15, so as to better control the turning on or off of the corresponding transistors in the output circuit 104. The twenty-fifth transistor T25 and the twenty-sixth transistor T26 can control the disconnection between the third node N3 and the fifth node N5 when the seventeenth transistor T17 and the eighteenth transistor T18 of the gating circuit 102 are both turned on, so as to avoid affecting the potential writing of the third node N3.

[0135] In some examples, the initialization circuit 106 may include: an eleventh transistor T11 and a sixteenth transistor T16. The eleventh transistor T11 and the sixteenth transistor T16 are of the same transistor type, for example, both are P-type transistors. The gate of the eleventh transistor T11 is connected to the initial control terminal NCX, the first electrode of the eleventh transistor T11 is connected to the first voltage input terminal VGH, and the second electrode of the eleventh transistor T11 is connected to the cascade output terminal NS(n). The gate of the sixteenth transistor T16 is connected to the initial control terminal NCX, the first electrode of the sixteenth transistor T16 is connected to the first voltage input terminal VGH, and the second electrode of the sixteenth transistor T16 is connected to the third node N3.

[0136] In some examples, when the cascade input terminal NS(n-1) provides a high voltage signal, the cascade output terminal NS(n) outputs a low voltage signal. If the enable input terminal VCT outputs a low voltage signal, when the cascade output terminal NS(n) outputs a high voltage signal, the driver output terminal NO(n) outputs a low voltage signal; when the cascade input terminal NS(n-1) provides a high voltage signal, the cascade output terminal NS(n) outputs a low voltage signal. If the enable input terminal VCT outputs a high voltage signal, when the cascade output terminal NS(n) outputs a high voltage signal, the driver output terminal NO(n) outputs a high voltage signal.

[0137] In some examples, the first node N1 may be a connection point of the first transistor T1, the eighth transistor T8, the twenty-seventh transistor T27, and the twenty-eighth transistor T28. The second node N2 may be a connection point of the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10. The third node N3 may be a connection point of the eighteenth transistor T18, the sixteenth transistor T16, the twelfth transistor T12, the thirteenth transistor T13, the twenty-fifth transistor T25, and the twenty-sixth transistor T26. The fourth node N4 may be a connection point of the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15. The fifth node N5 may be a connection point of the fourteenth transistor T14, the fifteenth transistor T15, the twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-second transistor T22, and the twenty-fourth transistor T24. The sixth node N6 may be a connection point of the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the nineteenth transistor T19, and the twentieth transistor T20. In this example, the first node N1, the second node N2, the third node N3, the fourth node N4, the fifth node N5, and the sixth node N6 do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram being equivalent.

[0138] In some examples, the driving signal provided by the driving output terminal NO(n) of the shift register circuit of this example can be configured to be transmitted to the gate of the N-type transistor in the pixel circuit in the display area as a control signal for controlling whether the N-type transistor in the pixel circuit is turned on. For example, by controlling the conduction or disconnection of the N-type transistor in the pixel circuit, the pixel brightness can be refreshed. Therefore, when it is desired to achieve non-refresh of some pixels, it is sufficient to ensure that the N-type transistor in the pixel circuit is disconnected.

[0139] In some examples, the shift register circuit of this example may include twenty-eight transistors, including fifteen P-type transistors and thirteen N-type transistors. The P-type transistors may be low temperature polysilicon transistors, including a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, a ninth transistor T9, an eleventh transistor T11, a twelfth transistor T12, a fourteenth transistor T14, a sixteenth transistor T16, a seventeenth transistor T17, a nineteenth transistor T19, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-fifth transistor T25, and a twenty-seventh transistor T27. The N-type transistors may be oxide transistors, including a third transistor T3, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8, a tenth transistor T10, a thirteenth transistor T13, a fifteenth transistor T15, an eighteenth transistor T18, a twentieth transistor T20, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-sixth transistor T26, and a twenty-eighth transistor T28. The multiple oxide transistors of the shift register circuit of this example may include: an oxide output transistor and multiple oxide switch transistors. The oxide output transistor may include a twentieth transistor T20, and the multiple oxide switch transistors may include a third transistor T3, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8, a tenth transistor T10, a thirteenth transistor T13, a fifteenth transistor T15, an eighteenth transistor T18, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-sixth transistor T26, and a twenty-eighth transistor T28.

[0140] In some examples, the shift register circuit may include multiple NOT gate circuits (also referred to as inverting circuits or inverters). The multiple NOT gate circuits of the shift register circuit may include, for example: a first NOT gate circuit to a seventh NOT gate circuit. Each NOT gate circuit may include: a first control transistor and a second control transistor, the first control transistor and the second control transistor having different transistor types, such as the first control transistor may be a P-type transistor, the second control transistor may be an N-type transistor, and the P-type transistor and the N-type transistor work in a complementary manner. For example, the NOT gate circuit may be a complementary metal oxide semiconductor (CMOS) tube formed by a P-type transistor and an N-type transistor that appear in pairs and work in a complementary manner.

[0141] In some examples, the gate of the first control transistor in the NOT gate circuit is connected to the gate of the second control transistor as the first input terminal of the NOT gate circuit; the second electrode of the first control transistor is connected to the second electrode of the second control transistor as the output terminal of the NOT gate circuit; the first electrode of the first control transistor is used as the second input terminal of the NOT gate circuit; the first electrode of the second control transistor is used as the third input terminal of the NOT gate circuit. The second input terminal and the third input terminal of the NOT gate circuit can be configured to receive different voltage signals.

[0142] In some examples, such as Figure 1 As shown, the first control transistor of the first NOT gate circuit may be the second transistor T2, and the second control transistor may be the third transistor T3. The first control transistor of the second NOT gate circuit may be the sixth transistor T6, and the second control transistor may be the seventh transistor T7. The first control transistor of the third NOT gate circuit may be the ninth transistor T9, and the second control transistor may be the tenth transistor T10. The first control transistor of the fourth NOT gate circuit may be the twenty-seventh transistor T27, and the second control transistor may be the twenty-eighth transistor T28. The first control transistor of the fifth NOT gate circuit may be the twelfth transistor T12, and the second control transistor may be the thirteenth transistor T13. The first control transistor of the sixth NOT gate circuit may be the fourteenth transistor T14, and the second control transistor may be the fifth transistor T15. The first control transistor of the seventh NOT gate circuit may be the nineteenth transistor T19, and the second control transistor may be the twentieth transistor T20. The cascade signal generating circuit 101 may include four NOT gate circuits (i.e., the first NOT gate circuit to the fourth NOT gate circuit). The voltage maintaining circuit 105 may include two NOT gate circuits (i.e., the fifth NOT gate circuit and the sixth NOT gate circuit). The output circuit 104 may include a NOT gate circuit (i.e., the seventh NOT gate circuit).

[0143] In some examples, the shift register circuit may include a NAND gate circuit. The NAND gate circuit may include: a third control transistor, a fourth control transistor, a fifth control transistor, and a sixth control transistor. The transistor type of the third control transistor and the fourth control transistor may be the same, for example, they may be P-type transistors; the transistor type of the fifth control transistor and the sixth control transistor may be the same, for example, they may be N-type transistors. Among them, the gates of the third control transistor and the fifth control transistor are connected as the first input terminal of the NAND gate circuit; the gates of the fourth control transistor and the sixth control transistor are connected as the second input terminal of the NAND gate circuit; the first electrode of the third control transistor and the first electrode of the fourth control transistor are connected as the third input terminal of the NAND gate circuit; the second electrode of the third control transistor, the second electrode of the fourth control transistor and the second electrode of the fifth control transistor are connected as the output terminal of the NAND gate circuit; the first electrode of the fifth control transistor is connected to the second electrode of the sixth control transistor; the first electrode of the sixth control transistor serves as the fourth input terminal of the NAND gate circuit. The third input terminal and the fourth input terminal of the NAND gate circuit may be configured to access different voltage signals.

[0144] In some examples, such as Figure 1 As shown, the third control transistor of the NAND gate circuit may be a twenty-first transistor T21, the fourth control transistor may be a twenty-second transistor T22, the fifth control transistor may be a twenty-third transistor T23, and the sixth control transistor may be a twenty-fourth transistor T24.

[0145] In some examples, the third input terminal can be connected to a high-level first voltage signal, and the fourth input terminal can be connected to a low-level second voltage signal. The first input terminal of the NAND gate circuit receives a high-level signal, and the second input terminal receives a high-level signal, and the output terminal of the NAND gate circuit can output a low-level signal; the first input terminal of the NAND gate circuit receives a high-level signal, and the second input terminal receives a low-level signal, and the output terminal of the NAND gate circuit can output a high-level signal; the first input terminal of the NAND gate circuit receives a low-level signal, and the second input terminal receives a high-level signal, and the output terminal of the NAND gate circuit can output a high-level signal; the first input terminal of the NAND gate circuit receives a low-level signal, and the second input terminal receives a low-level signal, and the output terminal of the NAND gate circuit can output a high-level signal. The output control circuit 103 of this example may include a NAND gate circuit.

[0146] The shift register circuit of this embodiment includes 28 transistors and no capacitor is provided, so that partial refresh of the display area can be realized. This example can realize the update of the partial picture of the display screen by controlling the selection input signal provided by the selection input terminal VCT, thereby reducing power consumption, or realize ultra-low power consumption of OLED display products such as wearable products, mobile terminals, and notebook computers (NB) by partial update of the display picture.

[0147] Figure 2 Schematic diagram of a gate drive circuit of at least one embodiment of the present disclosure. Figure 2 As shown, the gate drive circuit may include a plurality of cascaded shift register circuits (such as GOA (1) to GOA (4)). The cascade output terminal of the n-1th shift register circuit GOA (n-1) is connected to the cascade input terminal of the nth shift register circuit GOA (n). Except for the last shift register circuit, the cascade signal provided by the cascade output terminal of each shift register circuit can be used as an input signal of the cascade input terminal of the next shift register circuit. Wherein, n can be an integer greater than 1. The cascade input terminal of the first shift register circuit can be connected to the start signal line STV.

[0148] In some examples, the clock signal terminal of the 2i-1th shift register circuit can be connected to the first clock signal line CKL, and the clock signal terminal of the 2ith shift register circuit can be connected to the second clock signal line CBL. Wherein, i can be an integer greater than 0. The first voltage input terminal VGH of each shift register circuit can be connected to the first voltage line VH, the second voltage input terminal VGL of each shift register circuit can be connected to the second voltage line VL, the selection input terminal VCT of each shift register circuit can be connected to the selection input signal line VT, and the initial control terminal NCX of each shift register circuit can be connected to the initial control signal line NX. The selection input signal line VT can provide a selection input signal, and the selection input signal can be a pulse signal.

[0149] Figure 3 The present invention is a partial cross-sectional schematic diagram of a display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 3 The stacking sequence of the film layers of the display substrate is shown in FIG. Figure 3 As shown, in a direction perpendicular to the display substrate, the display substrate may include: a base (also referred to as a substrate) 10, and a circuit structure layer 20, a light emitting structure layer 30 and a packaging structure layer 40 sequentially arranged on the base 10.

[0150] In some examples, the circuit structure layer 20 may include: a buffer layer BF, a first semiconductor layer (also referred to as a polysilicon active layer) PY1, a first insulating layer (also referred to as a first gate insulating layer) GI1, a first conductive layer (also referred to as a first gate metal layer) GT1, a second insulating layer (also referred to as a second gate insulating layer) GI2, a second conductive layer (also referred to as a second gate metal layer) GT2, a third insulating layer (also referred to as a third gate insulating layer) GI3, a second semiconductor layer (also referred to as an oxide active layer) PY2, a fourth insulating layer (also referred to as a fourth gate insulating layer) GI4, a third conductive layer (also referred to as a third gate metal layer) GT3, a fifth insulating layer (also referred to as an interlayer insulating layer) ILD, a fourth conductive layer (also referred to as a first source-drain metal layer) SD1, a sixth insulating layer (also referred to as a passivation layer) PVX, a seventh insulating layer (also referred to as a first planar layer) PLN1, a fifth conductive layer (also referred to as a second source-drain metal layer) SD2, and an eighth insulating layer (also referred to as a second planar layer) PLN2, which are sequentially disposed on the substrate 10. However, this embodiment is not limited to this. In other examples, the sixth insulating layer PVX may be omitted, or the sixth insulating layer PVX may be located between the seventh insulating layer and the fifth conductive layer.

[0151] In some examples, the light emitting structure layer 30 may include: an anode layer ANO, a pixel definition layer (also referred to as a pixel defining layer) PDL, a light emitting functional layer EL, and a cathode layer CATH. The anode layer ANO may include an anode of a light emitting element, the pixel definition layer PDL may be formed with a plurality of pixel openings exposing the anode layer ANO, the light emitting functional layer EL may be disposed in the pixel openings and connected to the anode in the anode layer ANO. The cathode layer CATH may be connected to the light emitting functional layer EL.

[0152] In some examples, the encapsulation structure layer 40 may include: a first encapsulation layer CVD1, a second encapsulation layer IJP, and a third encapsulation layer CVD2. The first encapsulation layer CVD1 and the third encapsulation layer CVD2 may be made of inorganic materials, the second encapsulation layer IJP may be made of organic materials, and the second encapsulation layer IJP may be arranged between the first encapsulation layer CVD1 and the third encapsulation layer CVD2 to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 30. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0153] Figure 4 It is a partial top view schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 4 FIG. 1 shows a top view of a shift register circuit of a display substrate. The equivalent circuit of the shift register circuit of this example can be shown as follows: Figure 1 shown.

[0154] In some examples, such as Figure 4 As shown, in a plane parallel to the display substrate, the outer contour of a single shift register circuit can be roughly rectangular. The cascade signal generating circuit 101, the output control circuit 103 and the output circuit 104 can be arranged in sequence along the first direction X, and the initialization circuit 106, the gating circuit 102, and the voltage maintaining circuit 105 can be arranged in sequence along the first direction X. The initialization circuit 106 is adjacent to the cascade signal generating circuit 101 in the second direction Y, the gating circuit 102 is adjacent to the cascade signal generating circuit 101 in the second direction Y, a part of the voltage maintaining circuit 105 is adjacent to the cascade signal generating circuit 101 in the second direction Y, and another part is adjacent to the output control circuit 103 in the second direction Y. The initialization circuit 106, the gating circuit 102, and the voltage maintaining circuit 105 are located on the same side of the cascade signal generating circuit 101 in the second direction Y. A part of the output circuit 104 is adjacent to the output control circuit 103 in the first direction X, and another part is adjacent to the voltage maintaining circuit 105 in the first direction X. The first direction X and the second direction Y intersect, for example, the first direction X may be perpendicular to the second direction Y. The arrangement of the shift register circuit in this example can save space and is conducive to achieving a narrow frame.

[0155] In some examples, such as Figure 4 As shown, in a plane parallel to the display substrate, the output end of the first NOT gate circuit (including the second transistor T2 and the third transistor T3) is connected to the output end of the second NOT gate circuit (including the sixth transistor T6 and the seventh transistor T7), and the first NOT gate circuit and the second NOT gate circuit are adjacent in the second direction Y. The first NOT gate circuit can be located on one side of the second NOT gate circuit in the second direction Y. The transistor arrangement mode of the first NOT gate circuit can be the same as the transistor arrangement mode of the second NOT gate circuit. Among them, the third transistor T3 and the second transistor T2 in the first NOT gate circuit can be arranged in sequence along the first direction X, and the seventh transistor T7 and the sixth transistor T6 in the second NOT gate circuit can be arranged in sequence along the first direction X. The third transistor T3 and the seventh transistor T7 can be arranged roughly aligned in the second direction Y, and the second transistor T2 and the sixth transistor T6 can be arranged roughly aligned in the second direction Y.

[0156] In some examples, the second input terminal of the first NOT gate circuit is connected to the first transistor T1 (as the first transmission transistor), and the third input terminal of the first NOT gate circuit is connected to the fourth transistor T4 (as the third transmission transistor); the second input terminal of the second NOT gate circuit is connected to the fifth transistor T5 (as the second transmission transistor), and the third input terminal of the second NOT gate circuit is connected to the eighth transistor T8 (as the fourth transmission transistor). The first transistor T1 can be located on one side of the second transistor T2 in the first direction X, and the fourth transistor T4 can be located on one side of the third transistor T3 in the opposite direction of the first direction X. The fifth transistor T5 can be located on one side of the sixth transistor T6 in the first direction X, and the eighth transistor T8 can be located on one side of the seventh transistor T7 in the opposite direction of the first direction X. The first transistor T1 and the fifth transistor T5 can be arranged roughly aligned in the second direction Y, and the fourth transistor T4 and the eighth transistor T8 can be arranged roughly aligned in the second direction Y.

[0157] In some examples, the third NOT gate circuit (including the ninth transistor T9 and the tenth transistor T10) is adjacent to the second NOT gate circuit in the second direction Y. The third NOT gate circuit may be located on the side of the second NOT gate circuit in the opposite direction of the second direction Y. The transistor arrangement of the third NOT gate circuit may be the same as the transistor arrangement of the second NOT gate circuit. Among them, the tenth transistor T10 and the ninth transistor T9 may be arranged in sequence along the first direction X. The ninth transistor T9 and the sixth transistor T6 may be arranged roughly aligned in the second direction Y, and the tenth transistor T10 and the seventh transistor T7 may be arranged roughly aligned in the second direction Y.

[0158] In some examples, the fourth NOT gate circuit (including the twenty-seventh transistor T27 and the twenty-eighth transistor T28) can be located on one side of the first NOT gate circuit and the second NOT gate circuit in the opposite direction of the first direction X. The transistor arrangement of the fourth NOT gate circuit can be different from the transistor arrangement of the first NOT gate circuit, the second NOT gate circuit, and the third NOT gate circuit. Among them, the twenty-seventh transistor T27 and the twenty-eighth transistor T28 can be arranged in sequence along the second direction Y.

[0159] In some examples, the NAND gate circuit (including the 21st transistor T21 to the 24th transistor T24) can be located on one side of the first NOT gate circuit and the second NOT gate circuit in the first direction X, and located on one side of the seventh NOT gate circuit (including the 19th transistor T19 and the 20th transistor T20) in the opposite direction of the first direction X. The NAND gate circuit is adjacent to the fifth NOT gate circuit (including the 12th transistor T12 and the 13th transistor T13) and the sixth NOT gate circuit (including the 14th transistor T14 and the 15th transistor T15) in the second direction Y. The four transistors in the NAND gate circuit can be arranged in sequence along the second direction Y.

[0160] In some examples, the fifth NOT gate circuit and the sixth NOT gate circuit may be adjacent in the first direction X. The sixth NOT gate circuit may be located on one side of the fifth NOT gate circuit in the first direction X. The transistor arrangement of the fifth NOT gate circuit may be the same as the transistor arrangement of the sixth NOT gate circuit. Among them, the twelfth transistor T12 and the thirteenth transistor T13 may be arranged in sequence along the second direction Y, and the fourteenth transistor T14 and the fifteenth transistor T15 may be arranged in sequence along the second direction Y. In addition, the twelfth transistor T12 and the fourteenth transistor T14 may be adjacent and aligned in the first direction X; the thirteenth transistor T13 and the fifteenth transistor T15 may be adjacent and aligned in the first direction X.

[0161] In some examples, the nineteenth transistor T19 and the twentieth transistor T20 of the seventh NOT gate circuit may be arranged sequentially along the second direction Y. The nineteenth transistor T19 may be located on one side of the twentieth transistor T20 along the second direction Y. The nineteenth transistor T19 may be adjacent to the NAND gate circuit in the first direction X, and the twentieth transistor T20 may be adjacent to the sixth NOT gate circuit in the first direction.

[0162] In some examples, the seventeenth transistor T17 and the eighteenth transistor T18 included in the gating circuit 102 may be arranged in sequence along the second direction Y. The eighteenth transistor T18 may be located on one side of the seventeenth transistor T17 in the second direction Y. The sixteenth transistor T16 included in the initialization circuit 106 may be located on one side of the eighteenth transistor T18 in the opposite direction of the first direction X. The eleventh transistor T11 included in the initialization circuit 106 may be approximately located on one side of the sixteenth transistor T16 in the opposite direction of the second direction Y. The twenty-fifth transistor T25 and the twenty-sixth transistor T26 included in the voltage maintaining circuit 105 may be arranged in sequence along the first direction X. The twenty-fifth transistor T25 may be located on one side of the gating circuit 102 along the first direction X, the twenty-sixth transistor T26 may be located on one side of the twenty-fifth transistor T25 along the first direction X, and the fifth NOT gate circuit may be located on one side of the twenty-sixth transistor T26 along the first direction X. The twenty-sixth transistor T26 may be arranged approximately aligned with the thirteenth transistor T13 of the fifth NOT gate circuit in the first direction.

[0163] The preparation process of the display substrate is exemplified below. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0164] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the projection of A includes the projection of B" means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B. In this example, the shape of A refers to the shape of the positive projection of A on the substrate.

[0165] The manufacturing process of the display substrate of this exemplary embodiment may include the following steps: The manufacturing process of the circuit structure layer is taken as an example for description.

[0166] (1) Provide a substrate. In some examples, the substrate may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be, but is not limited to, one or more of glass and quartz; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the water and oxygen resistance of the substrate.

[0167] (2) Forming a first semiconductor layer. In some examples, a buffer film and a first semiconductor film are sequentially deposited on a substrate, and the first semiconductor film is patterned by a patterning process to form a buffer layer and a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0168] Figure 5 for Figure 4 Schematic diagram of a display substrate after forming a first semiconductor layer in FIG. Figure 5 As shown, the first semiconductor layer of the display substrate may include at least: active layers of multiple P-type transistors of the shift register circuit, for example, including an active layer 31 of a first transistor T1, an active layer 32 of a second transistor T2, an active layer 35 of a fifth transistor T5, an active layer 36 of a sixth transistor T6, an active layer 39 of a ninth transistor T9, an active layer 311 of an eleventh transistor T11, an active layer 312 of a twelfth transistor T12, an active layer 314 of a fourteenth transistor T14, an active layer 316 of a sixteenth transistor T16, an active layer 317 of a seventeenth transistor T17, an active layer 319 of a nineteenth transistor T19, an active layer 321 of a twenty-first transistor T21, an active layer 322 of a twenty-second transistor T22, an active layer 325 of a twenty-fifth transistor T25, and an active layer 327 of a twenty-seventh transistor T27.

[0169] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region of the first type transistor may not be doped with impurities and may have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region and may be doped with impurities and may therefore be conductive. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. For example, the first region of the active layer may be interpreted as a first pole of the transistor, and the second region of the active layer may be interpreted as a second pole of the transistor. Portions of the active layer between transistors may be interpreted as wiring doped with impurities, which may be used to electrically connect transistors. This embodiment is not limited to this.

[0170] In some examples, the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 36 of the sixth transistor T6, and the active layer 35 of the fifth transistor T5 may be sequentially connected to form an integrated structure. The shape of the integrated structure may be substantially C-shaped. Among them, the second area of ​​the active layer 31 of the first transistor T1 may also serve as the first area of ​​the active layer 32 of the second transistor T2, the second area of ​​the active layer 32 of the second transistor T2 may also serve as the second area of ​​the active layer 36 of the sixth transistor T6, and the first area of ​​the active layer 36 of the sixth transistor T6 may also serve as the second area of ​​the active layer 35 of the fifth transistor T5.

[0171] In some examples, the shape of the active layer 311 of the eleventh transistor T11 may be substantially a strip extending along the first direction X, and the shape of the active layer 316 of the sixteenth transistor T16 may be substantially a strip extending along the second direction Y. The active layer 311 of the eleventh transistor T11 and the active layer 316 of the sixteenth transistor T16 may be an integrated structure connected to each other, and the shape of the integrated structure may be substantially L-shaped. The first region of the active layer 311 of the eleventh transistor T11 may also serve as the first region of the active layer 316 of the sixteenth transistor T16.

[0172] In some examples, the active layer 321 of the twenty-first transistor T21 and the active layer 322 of the twenty-second transistor T22 may extend at least along the first direction X. The active layer 321 of the twenty-first transistor T21 and the active layer 322 of the second transistor T22 may be an integrated structure connected to each other, and the shape of the integrated structure may be approximately C-shaped. Among them, the second region of the active layer 321 of the twenty-first transistor T21 may also serve as the second region of the active layer 322 of the twenty-second transistor T22. The opening of the integrated structure of the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 36 of the sixth transistor T6, and the active layer 35 of the fifth transistor T5 may face the opening of the integrated structure of the active layer 321 of the twenty-first transistor T21 and the active layer 322 of the second transistor T22.

[0173] In some examples, the active layer 39 of the ninth transistor T9 can be shaped roughly like a strip extending along the second direction Y, and is located on the side of the integrated structure of the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 36 of the sixth transistor T6 and the active layer 35 of the fifth transistor T5 in the opposite direction of the second direction Y.

[0174] In some examples, the shape of the active layer 312 of the twelfth transistor T12 may be substantially a strip extending along the first direction X. The shape of the active layer 314 of the fourteenth transistor T14 may be substantially a strip extending along the first direction X. The active layer 312 of the twelfth transistor T12 and the active layer 314 of the fourteenth transistor T14 may be adjacent to each other in the first direction X, and may be aligned in the first direction X. The active layer 312 of the twelfth transistor T12 may be located on one side of the twenty-fifth transistor T25 in the first direction X, and the active layer 314 of the fourteenth transistor T14 may be located on one side of the active layer 312 of the twelfth transistor T12 in the first direction X.

[0175] In some examples, the active layer 317 of the seventeenth transistor T17 may be shaped substantially like a strip extending along the first direction X. The active layer 317 of the seventeenth transistor T17 may be located in the first direction X between the active layer 311 of the eleventh transistor T11 and the active layer 325 of the twenty-fifth transistor T25 .

[0176] In some examples, the active layer 319 of the nineteenth transistor T19 may be substantially rectangular in shape. The active layer 319 of the nineteenth transistor T19 may be located on one side of the first direction X of the integrated structure of the active layer 321 of the twenty-first transistor T21 and the active layer 322 of the twenty-second transistor T22.

[0177] In some examples, the active layer 325 of the twenty-fifth transistor T25 may be shaped substantially like a strip extending along the second direction Y. The active layer 325 of the twenty-fifth transistor T25 may be located at one side of the active layer 317 of the seventeenth transistor T17 in the first direction X.

[0178] In some examples, the shape of the active layer 327 of the twenty-seventh transistor T27 may be substantially a strip extending along the second direction Y. The active layer 327 of the twenty-seventh transistor T27 may be located on one side of the integrated structure of the active layer 311 of the eleventh transistor T11 and the active layer 316 of the sixteenth transistor T16 in the second direction Y, and may be located on one side of the integrated structure of the active layers 31, 32, 36, and 35 in the opposite direction of the first direction X.

[0179] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer.

[0180] Fig. 6A for Figure 4 Schematic diagram of a display substrate after forming a first conductive layer. Figure 6B for Fig. 6A Schematic diagram of the first conductive layer in FIG. Fig. 6A and Figure 6B As shown, the first conductive layer of the display substrate may include at least: gates of multiple P-type transistors of the shift register circuit (for example, including: the gate 21 of the first transistor T1, the gate 22 of the second transistor T2, the gate 25 of the fifth transistor T5, the gate 26 of the sixth transistor T6, the gate 29 of the ninth transistor T9, the gate 211 of the eleventh transistor T11, the gate 212 of the twelfth transistor T12, the gate 214 of the fourteenth transistor T14, the gate 216 of the sixteenth transistor T16, the gate 217 of the seventeenth transistor T17, the gate 219 of the nineteenth transistor T19, the gate 221 of the twenty-first transistor T21, the gate 222 of the twenty-second transistor T22, the gate 225 of the twenty-fifth transistor T25, and the gate 227 of the twenty-seventh transistor T27), and multiple connecting electrodes (for example, including the first connecting electrode 401 and the second connecting electrode 402).

[0181] In some examples, the shape of the gate 21 of the first transistor T1 may be approximately n-shaped. The shape of the gate 22 of the second transistor T2 may be approximately strip-shaped extending along the second direction Y. The shape of the gate 25 of the fifth transistor T5 may be approximately strip-shaped extending along the second direction Y. The shape of the gate 26 of the sixth transistor T6 may be approximately J-shaped. The shape of the gate 29 of the ninth transistor T9 may be approximately strip-shaped extending along the first direction X. The shape of the gate 211 of the eleventh transistor T11 may be approximately strip-shaped extending along the second direction Y. The shape of the gate 212 of the twelfth transistor T12 and the gate 214 of the fourteenth transistor T14 may be approximately strip-shaped extending along the second direction Y. The shape of the gate 216 of the sixteenth transistor T16 may be approximately strip-shaped extending along the first direction X. The shape of the gate 217 of the seventeenth transistor T17 may be approximately J-shaped. The shape of the gate 219 of the nineteenth transistor T19 may be approximately comb-shaped. The shape of the gate 221 of the twenty-first transistor T21 may be a combination of an L-shape and an n-shape. The shape of the gate 222 of the twenty-second transistor T22 may be a zigzag shape extending along the second direction Y. The shape of the gate 225 of the twenty-fifth transistor T25 may be a combination of an n-shape and an L-shape. The shape of the gate 227 of the twenty-seventh transistor T27 may be a stripe shape extending along the first direction X.

[0182] In some examples, the gate 211 of the eleventh transistor T11 and the gate 216 of the sixteenth transistor T16 may be an integrated structure connected to each other. The nineteenth transistor T19 may be a tri-gate transistor to prevent and reduce the occurrence of leakage current. However, this embodiment is not limited to this.

[0183] In some examples, the shape of the first connection electrode 401 may be substantially a dumbbell extending along the second direction Y. The first connection electrode 401 may be located on one side of the gate 21 of the second transistor T2 and the gate 25 of the fifth transistor T5 in the first direction X, and on one side of the gate 211 of the twenty-first transistor T21 in the opposite direction of the first direction X.

[0184] In some examples, the second connection electrode 402 may be shaped substantially like a dumbbell extending along the second direction Y. The second connection electrode 402 may be located on one side of the gate 216 of the sixteenth transistor T16 in the second direction Y.

[0185] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer.

[0186] Fig. 7A for Figure 4 Schematic diagram of a display substrate after a second conductive layer is formed. Figure 7B for Fig. 7A Schematic diagram of the second conductive layer in FIG. Fig. 7A and 7B As shown, the second conductive layer of the display substrate may at least include: bottom gates of multiple N-type transistors of the shift register circuit (for example, including: a bottom gate 53 of a third transistor T3, a bottom gate 54 of a fourth transistor T4, a bottom gate 57 of a seventh transistor T7, a bottom gate 58 of an eighth transistor T8, a bottom gate 510 of a tenth transistor T10, a bottom gate 513 of a thirteenth transistor T13, a bottom gate 515 of a fifteenth transistor T15, a bottom gate 518 of an eighteenth transistor T18, a bottom gate 520 of a twentieth transistor T20, a bottom gate 523 of a twenty-third transistor T23, a bottom gate 524 of a twenty-fourth transistor T24, a bottom gate 526 of a twenty-sixth transistor T26, and a bottom gate 528 of a twenty-eighth transistor T28), a bottom gate connection portion 60 (for example, including a first bottom gate connection portion 601 and a second bottom gate connection portion 602), and an output electrode 61. In this example, the bottom gate of the transistor may also be referred to as a bottom gate layer, and the top gate of the transistor may also be referred to as a top gate layer.

[0187] In some examples, the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 57 of the seventh transistor T7, the bottom gate 58 of the eighth transistor T8, the bottom gate 523 of the twenty-third transistor T23, the bottom gate 524 of the twenty-fourth transistor T24, the bottom gate 513 of the thirteenth transistor T13, and the bottom gate 515 of the fifteenth transistor T15 may be substantially strip-shaped extending along the second direction Y; the bottom gate 510 of the tenth transistor T10, the bottom gate 518 of the eighteenth transistor T18, and the bottom gate 526 of the twenty-sixth transistor T26 may be substantially strip-shaped extending along the first direction X. The bottom gate 520 of the twentieth transistor T20 may be substantially comb-shaped.

[0188] In some examples, the bottom gate 53 of the third transistor T3 and the bottom gate 57 of the seventh transistor T7 may be an integrated structure connected to each other. The bottom gate 54 of the fourth transistor T4 and the bottom gate 58 of the eighth transistor T8 may be an integrated structure connected to each other. The bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, the bottom gate 57 of the seventh transistor T7, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 510 of the tenth transistor T10, and the bottom gate 523 of the twenty-third transistor T23 may be connected via the first bottom gate connection portion 601.

[0189] In some examples, the first bottom gate connection portion 601 may include: a first line segment extending along the first direction X, a second line segment extending along the third direction, a third line segment extending along the first direction X, a fourth line segment extending along the second direction Y, and a fifth line segment extending along the first direction X, a first extension segment, and a second extension segment, the first line segment, the second line segment, the third line segment, the fourth line segment, and the fifth line segment may be connected in sequence, and the fourth line segment and the fifth line segment may be located on one side of the third line segment in the second direction Y. The first line segment may be connected to the first extension segment and the second extension segment extending along the second direction Y, and the second extension segment may be located on one side of the first extension segment. The third direction may be parallel to the plane where the first direction X and the second direction Y are located, and intersects both the first direction X and the second direction Y.

[0190] In some examples, the bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, and the bottom gate 57 of the seventh transistor T7 can be located on one side of the first line segment in the second direction Y and directly connected to the first line segment; the bottom gate 518 of the eighteenth transistor T18 and the bottom gate 510 of the tenth transistor T10 can be located on one side of the first line segment in the opposite direction of the second direction Y, and the bottom gate 518 of the eighteenth transistor T18 can be connected to the first line segment through a first extension segment, and the bottom gate 510 of the tenth transistor T10 can be connected to the first line segment through a second extension segment; the bottom gate 523 of the twenty-third transistor T23 can be located on one side of the fifth line segment in the opposite direction of the second direction Y and directly connected to the fifth line segment.

[0191] In some examples, the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, the bottom gate 57 of the seventh transistor T7, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 510 of the tenth transistor T10, the bottom gate 523 of the twenty-third transistor T23, and the first bottom gate connection portion 601 may be an integrated structure connected to each other. This example does not limit the shape of the first bottom gate connection portion, for example, the first bottom gate connection portion may adopt other irregular structures.

[0192] In some examples, the second bottom gate connection portion 602 may include a sixth line segment extending along the second direction Y, a seventh line segment extending along the third direction, and an eighth line segment extending along the first direction X, the sixth line segment, the seventh line segment, and the eighth line segment being sequentially connected.

[0193] In some examples, the bottom gate 526 of the twenty-sixth transistor T26 may be located on a side of the sixth line segment in the opposite direction of the first direction X and connected to the sixth line segment. The bottom gate 524 of the twenty-fourth transistor T24 may be located on a side of the eighth line segment in the second direction Y and connected to the eighth line segment. The bottom gate 513 of the thirteenth transistor T13 and the bottom gate 515 of the fifteenth transistor T15 may be located on a side of the eighth line segment in the opposite direction of the second direction Y and connected to the eighth line segment.

[0194] In some examples, the bottom gate 526 of the 26th transistor T26, the bottom gate 513 of the 13th transistor T13, the bottom gate 515 of the 15th transistor T15, the bottom gate 524 of the 24th transistor T24, and the second bottom gate connection portion 602 may be an integrated structure connected to each other. This example does not limit the shape of the second bottom gate connection portion, for example, the second bottom gate connection portion may adopt other irregular structures.

[0195] This example can achieve bottom gate connection of a corresponding plurality of N-type transistors by providing a bottom gate connection portion, and is helpful in reducing the layout difficulty of the shift register circuit.

[0196] In some examples, the output electrode 61 may be in the shape of a strip extending at least along the first direction X. The output electrode 61 may be located on one side of the bottom gate 520 of the twentieth transistor T20 in the first direction X. The output electrode 61 may serve as a driving output terminal of the shift register circuit to transmit a driving signal to a pixel circuit in the display area.

[0197] In some examples, the orthographic projection of the second conductive layer on the substrate may not overlap with the orthographic projections of the first semiconductor layer and the first conductive layer on the substrate to reduce the impact on the P-type transistor.

[0198] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate on which the aforementioned pattern is formed, and the second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO).

[0199] Fig. 8A for Figure 4 Schematic diagram of a display substrate after forming a second semiconductor layer. Figure 8B for Fig. 8A Schematic diagram of the second semiconductor layer in FIG. Fig. 8A and Figure 8B As shown, the second semiconductor layer of the display substrate may include at least: active layers of multiple N-type transistors of the shift register circuit (for example, including: an active layer 33 of a third transistor T3, an active layer 34 of a fourth transistor T4, an active layer 37 of a seventh transistor T7, an active layer 38 of an eighth transistor T8, an active layer 310 of a tenth transistor T10, an active layer 313 of a thirteenth transistor T13, an active layer 315 of a fifteenth transistor T15, an active layer 318 of an eighteenth transistor T18, an active layer 320 of a twentieth transistor T20, an active layer 323 of a twenty-third transistor T23, an active layer 324 of a twenty-fourth transistor T24, an active layer 326 of a twenty-sixth transistor T26, and an active layer 328 of a twenty-eighth transistor T28).

[0200] In some examples, the active layer 33 of the third transistor T3 and the active layer 34 of the fourth transistor T4 may be an integrated structure connected to each other, and the integrated structure may be a strip extending along the first direction X, and the integrated structure may be located between the active layer 327 of the twenty-seventh transistor T27 and the active layer 32 of the second transistor T2 in the first direction X. The first region of the active layer 33 of the third transistor T3 may also serve as the second region of the active layer 34 of the fourth transistor T4.

[0201] In some examples, the active layer 37 of the seventh transistor T7, the active layer 38 of the eighth transistor T8, and the active layer 328 of the twenty-eighth transistor T28 may be an integral structure connected in sequence, and the integral structure may be a strip extending along the first direction X, and the integral structure may be located on one side of the active layer 36 of the sixth transistor T6 in the opposite direction of the first direction X, and aligned with the active layer 36 of the sixth transistor T6 in the first direction X. The first region of the active layer 37 of the seventh transistor T7 may also serve as the second region of the active layer 38 of the eighth transistor T8, and the first region of the active layer 38 of the eighth transistor T8 may also serve as the first region of the active layer 328 of the twenty-eighth transistor T28. The active layer 328 of the twenty-eighth transistor T28 may be located on one side of the active layer 327 of the twenty-seventh transistor T27 in the opposite direction of the second direction Y.

[0202] In some examples, the active layer 310 of the tenth transistor T10, the active layer 318 of the eighteenth transistor T18, and the active layer 326 of the twenty-sixth transistor T26 may be shaped substantially like a strip extending along the second direction Y. The active layer 310 of the seventh transistor T10 may be located on one side of the active layer 39 of the ninth transistor T9 in the opposite direction of the first direction X, and aligned with the active layer 39 in the first direction X. The active layer 318 of the eighteenth transistor T18 may be located on one side of the active layer 317 of the seventeenth transistor T17 in the second direction Y. The active layer 318 of the eighteenth transistor T18 and the active layer 310 of the tenth transistor T10 may be arranged in a staggered manner along the second direction Y. The active layer 326 of the twenty-sixth transistor T26 may be located on one side of the active layer 325 of the twenty-fifth transistor T25 along the first direction X.

[0203] In some examples, the active layer 313 of the thirteenth transistor T13, the active layer 315 of the fifteenth transistor T15, the active layer 324 of the twenty-fourth transistor T24, and the active layer 323 of the twenty-third transistor T23 may be substantially strip-shaped extending along the first direction X. The active layer 313 of the thirteenth transistor T13 may be located on one side of the active layer 312 of the twelfth transistor T12 in the second direction Y. The active layer 315 of the fifteenth transistor T15 may be located on one side of the active layer 314 of the fourteenth transistor T14 in the second direction Y. The active layer 313 of the thirteenth transistor T13 and the active layer 315 of the fifteenth transistor T15 are adjacent and aligned in the first direction X. The active layer 324 of the twenty-fourth transistor T24 may be located between the active layer 322 of the twenty-second transistor T22 and the active layer 315 of the fifteenth transistor T15 in the second direction Y. The active layer 323 of the twenty-third transistor T23 may be located at one side of the active layer 321 of the twenty-first transistor T21 in the second direction Y.

[0204] In some examples, the active layer 320 of the twentieth transistor T20 may be substantially rectangular in shape. The active layer 320 of the twentieth transistor T20 may be located on a side of the active layer 319 of the nineteenth transistor T19 in the opposite direction of the second direction Y and aligned with the active layer 319 in the second direction Y.

[0205] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed, and the third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer.

[0206] Fig. 9A for Figure 4 Schematic diagram of a display substrate after a third conductive layer is formed. Fig. 9B for Fig. 9A Schematic diagram of the third conductive layer in FIG. In some examples, such as Fig. 9A and Fig. 9B As shown, the third conductive layer of the display substrate may include at least: top gates of multiple N-type transistors of the shift register circuit (for example, including: a top gate 23 of a third transistor T3, a top gate 24 of a fourth transistor T4, a top gate 27 of a seventh transistor T7, a top gate 28 of an eighth transistor T8, a top gate 210 of a tenth transistor T10, a top gate 213 of a thirteenth transistor T13, a top gate 215 of a fifteenth transistor T15, a top gate 218 of an eighteenth transistor T18, a top gate 220 of a twentieth transistor T20, a top gate 223 of a twenty-third transistor T23, a top gate 224 of a twenty-fourth transistor T24, a top gate 226 of a twenty-sixth transistor T26, and a top gate 228 of a twenty-eighth transistor T28).

[0207] In some examples, the shape of the top gate 23 of the third transistor T3 may be roughly F-shaped. The shape of the top gate 24 of the fourth transistor T4 may be roughly L-shaped. The shape of the top gate 27 of the seventh transistor T7 and the top gate 28 of the eighth transistor T8 may be roughly L-shaped. The shape of the top gate 210 of the tenth transistor T10 may be a strip extending along the first direction X. The shape of the top gate 213 of the thirteenth transistor T13 and the top gate 215 of the fifteenth transistor T15 may be roughly L-shaped. The shape of the top gate 218 of the eighteenth transistor T18 may be roughly a strip extending along the first direction X. The shape of the top gate 223 of the twenty-third transistor T23 and the top gate 224 of the twenty-fourth transistor T24 may be roughly a strip extending along the second direction Y. The shape of the top gate 226 of the twenty-sixth transistor T26 may be roughly a broken line extending along the first direction X. The shape of the top gate 228 of the twenty-eighth transistor T28 may be roughly a strip extending along the second direction Y. The top gate 220 of the twentieth transistor T20 may be substantially in the shape of a comb.

[0208] In some examples, the orthographic projection of the overlapping region of the top gate of the N-type transistor and the active layer on the substrate may be located within the orthographic projection range of the overlapping region of the bottom gate of the N-type transistor and the active layer on the substrate. In this example, the characteristics of the N-type transistor can be adjusted by setting the bottom gate of the N-type transistor, thereby achieving better transistor performance.

[0209] (7) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating film can be patterned by two patterning processes, and a first group of vias can be formed in the fifth insulating layer by the first patterning process, and a second group of vias can be formed in the fifth insulating layer by the second patterning process. For example, the first group of vias can expose a portion of the surface of the first semiconductor layer, the first conductive layer, and the second conductive layer, and the second group of vias can expose a portion of the surface of the second semiconductor layer and the third conductive layer.

[0210] Fig. 10A and Fig. 10B for Figure 4 Schematic diagram of a display substrate after a fifth insulating layer is formed. Fig. 10A The first set of vias in the fifth insulating layer is shown in FIG. Fig. 10B A second set of vias in the fifth insulating layer is illustrated in FIG.

[0211] In some examples, such as Fig. 10AAs shown, the first group of via holes of the fifth insulating layer of the display substrate may include: the first via hole V1 to the twenty-sixth via hole V26, the twenty-eighth via hole V28 to the fiftieth via hole V50, and the fifty-first via hole V51 to the fifty-fifth via hole V55. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the first via hole V1 to the twenty-sixth via hole V26 may be removed to expose a portion of the surface of the first semiconductor layer; the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-eighth via hole V28 to the fiftieth via hole V50 may be removed to expose a portion of the surface of the first conductive layer; the fifth insulating layer, the fourth insulating layer and the third insulating layer in the fifty-first via hole V51 to the fifty-fifth via hole V55 may be removed to expose a portion of the surface of the second conductive layer.

[0212] In some examples, such as Fig. 10B As shown, the second group of via holes of the fifth insulating layer of the display substrate may include: the sixty-first via hole V61 to the eighty-fourth via hole V84, and the ninety-first via hole V91 to the one hundred and fourth via hole V104. The fifth insulating layer and the fourth insulating layer in the sixty-first via hole V61 to the eighty-fourth via hole V84 may be removed to expose a portion of the surface of the second semiconductor layer; the fifth insulating layer in the ninety-first via hole V91 to the one hundred and fourth via hole V104 may be removed to expose a portion of the surface of the third conductive layer.

[0213] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer.

[0214] Fig.11 for Figure 4 Schematic diagram of the fourth conductive layer in FIG. In some examples, such as Figure 4 and Fig.11 As shown, the fourth conductive layer of the display substrate may include at least: an input electrode 62, and a plurality of conductive connection parts (eg, including a first conductive connection part D1, a fourth conductive connection part D4 to a thirty-ninth conductive connection part D39).

[0215] In some examples, the shape of the input electrode 62 may be substantially rectangular. The input electrode 62 may be located on one side of the twenty-seventh transistor T27 in the second direction Y. The input electrode 62 may be connected to one end of the top gate 23 of the third transistor T3 through the ninety-first via hole V91. The input electrode 62 may serve as a cascade input terminal of the current stage shift register circuit, and may be connected to a cascade output terminal of the previous stage shift register circuit.

[0216] In some examples, the shape of the first conductive connection portion D1 may be substantially a dumbbell extending along the second direction Y. The first conductive connection portion D1 may be located between the cascade signal generating circuit 101 and the output control circuit 103. One end of the first conductive connection portion D1 may be connected to the first bottom gate connection portion 601 through a fifty-second via V52 (e.g., connected to the connection position of the third line segment and the fourth line segment of the first bottom gate connection portion 601), and the other end may be connected to the second bottom gate connection portion 602 through a fifty-third via V53 (e.g., connected to the connection position of the seventh line segment and the eighth line segment of the second bottom gate connection portion 602).

[0217] In some examples, the shape of the fourth conductive connection portion D4 can be roughly a combination of a T-shape and an L-shape. The fourth conductive connection portion D4 can be adjacent to the eleventh transistor T11 and the sixteenth transistor T16 in the first direction X. The fourth conductive connection portion D4 of the shift register circuit at this stage can serve as a cascade output terminal of the shift register circuit at this stage, and be connected to the input electrode 62 of the shift register circuit at the next stage. For example, the fourth conductive connection portion D4 of the shift register circuit at this stage and the input electrode 62 of the shift register circuit at the next stage can be an integrated structure connected to each other. The fourth conductive connection portion D4 can be connected to the second connection electrode 402 through the forty-fifth via V45, and can also be connected to the active layer 311 of the eleventh transistor T11 through the eleventh via V11, and can also be connected to the gate 217 of the seventeenth transistor T17 through the forty-second via V42.

[0218] In some examples, the shape of the fifth conductive connection portion D5 may be substantially a dumbbell extending along the third direction. One end of the fifth conductive connection portion D5 may be connected to the first region of the active layer 327 of the twenty-seventh transistor T27 through the fifth via V5. The other end of the fifth conductive connection portion D5 may be connected to a first transmission line 711 formed subsequently and located in the fifth conductive layer.

[0219] In some examples, the shape of the sixth conductive connection portion D6 may be substantially L-shaped. The sixth conductive connection portion D6 may be located on one side of the fifth conductive connection portion D5 in the first direction X. One end of the sixth conductive connection portion D6 may be connected to the top gate 24 of the fourth transistor T4 through the ninety-third via hole V93, may be connected to the top gate 228 of the twenty-eighth transistor T28 through the ninety-fourth via hole V94, and may be connected to the gate 227 of the twenty-seventh transistor T27 through the thirty-fifth via hole V35. The other end of the sixth conductive connection portion D6 may be connected to a second clock signal line CBL formed subsequently and located in the fifth conductive layer.

[0220] In some examples, the shape of the seventh conductive connection portion D7 may be substantially a dumbbell extending along the second direction Y. The seventh conductive connection portion D7 may be located on one side of the sixth conductive connection portion D6 in the opposite direction of the second direction Y. One end of the seventh conductive connection portion D7 may be connected to the first region of the active layer 34 of the fourth transistor T4 through the sixty-first via hole V61, and the other end may be connected to the first region of the active layer 38 of the eighth transistor T8 through the sixty-fourth via hole V64. The seventh conductive connection portion D7 may be connected to a fifth transmission line 715 located in the fifth conductive layer formed subsequently.

[0221] In some examples, the shape of the eighth conductive connection portion D8 may be substantially a zigzag extending along the first direction X. The eighth conductive connection portion D8 may be located on one side of the seventh conductive connection portion D7 in the first direction X. One end of the eighth conductive connection portion D8 may be connected to the gate 25 of the fifth transistor T5 through the thirty-second via V32. The other end of the eighth conductive connection portion D8 may be connected to a second clock signal line CBL formed subsequently and located in the fifth conductive layer.

[0222] In some examples, the ninth conductive connection portion D9 may be shaped substantially like a dumbbell extending along the first direction X. The ninth conductive connection portion D9 may be located on one side of the eighth conductive connection portion D8 in the second direction Y. The ninth conductive connection portion D9 may be connected to the second region of the active layer 32 of the second transistor T2 through the second via hole V2, and may also be connected to the second region of the active layer 33 of the third transistor T3 through the sixty-second via hole V62.

[0223] In some examples, the shape of the tenth conductive connection portion D10 may be substantially a strip extending along the first direction X. The tenth conductive connection portion D10 may be located on one side of the ninth conductive connection portion D9 in the second direction Y. One end of the tenth conductive connection portion D10 may be connected to the gate 22 of the second transistor T2 through the thirty-first via V31, and may also be connected to the top gate 23 of the third transistor T3 through the ninety-second via V92, and the other end may be connected to one end of the first connection electrode 401 through the thirty-sixth via V36. The other end of the first connection electrode 401 may be connected to one end of the eleventh conductive connection portion D11 through the thirty-seventh via V37.

[0224] In some examples, the eleventh conductive connection portion D11 may be shaped like a dumbbell extending along the second direction Y. The eleventh conductive connection portion D11 may be located on one side of the first conductive connection portion D1 in the opposite direction of the first direction X. The other end of the eleventh conductive connection portion D11 may be connected to the gate 225 of the twenty-fifth transistor T25 through the fortieth via hole V40.

[0225] In some examples, the shape of the twelfth conductive connection portion D12 may be substantially L-shaped. The twelfth conductive connection portion D12 may be located on one side of the first conductive connection portion D1 in the first direction X. One end of the twelfth conductive connection portion D12 may be connected to the first region of the active layer 323 of the twenty-third transistor T23 through the seventy-sixth via hole V76, and the other end may be connected to the second region of the active layer 324 of the twenty-fourth transistor T24 through the seventy-eighth via hole V78.

[0226] In some examples, the shape of the thirteenth conductive connection portion D13 may be substantially a strip extending along the first direction X. The thirteenth conductive connection portion D13 may be located on one side of the twelfth conductive connection portion D12 in the first direction X. One end of the thirteenth conductive connection portion D13 may be connected to the gate 221 of the twenty-first transistor T21 through the twenty-eighth via V28, and the other end may be connected to the top gate 223 of the twenty-third transistor T23 through the one-hundred-and-third via V103.

[0227] In some examples, the shape of the fourteenth conductive connection portion D14 may be substantially a strip extending along the first direction X. The fourteenth conductive connection portion D14 may be located on one side of the twelfth conductive connection portion D12 in the first direction X. The fourteenth conductive connection portion D14 may be connected to the first bottom gate connection portion 601 (e.g., the fifth line segment of the first bottom gate connection portion 601) through the fifty-first via V51. The fourteenth conductive connection portion D14 may be connected to the seventh transmission line 717 located in the fifth conductive layer formed subsequently.

[0228] In some examples, the shape of the fifteenth conductive connection portion D15 may be a special-shaped structure, for example, a T-shaped and L-shaped connection structure. The fifteenth conductive connection portion D15 may be located on the side of the fourteenth conductive connection portion D14 in the opposite direction of the second direction Y. One end of the fifteenth conductive connection portion D15 may be connected to the second region of the active layer 321 of the twenty-first transistor T21 through the twentieth via V20, and may also be connected to the second region of the active layer 322 of the twenty-second transistor T22 through the twenty-second via V22, and the other end may be connected to the second region of the active layer 323 of the twenty-third transistor T23 through the seventy-seventh via V77, and may also be connected to the gate 219 of the nineteenth transistor T19 through the forty-sixth via V46.

[0229] In some examples, the shape of the sixteenth conductive connection portion D16 may be substantially a strip extending along the first direction X. The sixteenth conductive connection portion D16 may be located on one side of the fourteenth conductive connection portion D14 in the first direction X. The sixteenth conductive connection portion D16 may be connected to the first region of the active layer 319 of the nineteenth transistor T19 through a plurality of (e.g., four) twenty-third via holes V23 arranged laterally.

[0230] In some examples, the shape of the seventeenth conductive connection portion D17 may be substantially stepped. The seventeenth conductive connection portion D17 may be located on one side of the fifteenth conductive connection portion D15 in the first direction X. One end of the seventeenth conductive connection portion D17 may be connected to the first region of the active layer 322 of the twenty-second transistor T22 through the twenty-first via hole V21, and the other end may be connected to another first region of the active layer 319 of the nineteenth transistor T19 through a plurality of (e.g., four) twenty-fifth via holes V25 arranged laterally.

[0231] In some examples, the shape of the eighteenth conductive connection portion D18 may be substantially a strip extending along the first direction X. The eighteenth conductive connection portion D18 may be located on one side of the fifteenth conductive connection portion D15 in the opposite direction of the second direction Y. One end of the eighteenth conductive connection portion D18 may be connected to the gate 222 of the twenty-second transistor T22 through the forty-eighth via V48, and the other end may be connected to the top gate 224 of the twenty-fourth transistor T24 through the one-hundred-and-second via V102.

[0232] In some examples, the shape of the nineteenth conductive connection portion D19 may be substantially L-shaped. The nineteenth conductive connection portion D19 may be located on one side of the eighteenth conductive connection portion D18 in the first direction X. The nineteenth conductive connection portion D19 may be connected to the bottom gate 520 of the twentieth transistor T20 through the fifty-fourth via hole V54, may be connected to the top gate 220 of the twentieth transistor T20 through the one hundred and fourth via hole V104, and may be connected to the gate 219 of the nineteenth transistor T19 through the forty-seventh via hole V47. The top gate 220 of the twentieth transistor T20 and the gate 219 of the nineteenth transistor T19 may be electrically connected via the nineteenth conductive connection portion D19, and the gate 219 of the nineteenth transistor T19, the second electrode of the twenty-first transistor T21, the second electrode of the twenty-second transistor T22, and the second electrode of the twenty-third transistor T23 may be electrically connected via the fifteenth conductive connection portion D15, and therefore, the fifteenth conductive connection portion D15, the gate 219 of the nineteenth transistor T19, and the nineteenth conductive connection portion D19 may be connected as a sixth node N6.

[0233] In some examples, the shape of the twentieth conductive connection portion D20 may be substantially a zigzag shape extending along the first direction X. The twentieth conductive connection portion D20 may be located on one side of the nineteenth conductive connection portion D19 in the opposite direction of the second direction Y. One end of the twentieth conductive connection portion D20 may be connected to the first region of the active layer 324 of the twenty-fourth transistor T24 through the seventy-ninth via hole V79, and the other end may be connected to the first first region of the active layer 320 of the twentieth transistor T20 through a plurality of (e.g., four) eighty-first via holes V81 arranged laterally. The twentieth conductive connection portion D20 may be connected to the eighth transmission line 718 located in the fifth conductive layer formed subsequently.

[0234] In some examples, the shape of the twenty-first conductive connection portion D21 may be substantially comb-shaped. The twenty-first conductive connection portion D21 may be located at one side of the twentieth conductive connection portion D20 in the first direction X. The twenty-first conductive connection portion D21 can be connected to the second area of ​​the active layer 319 of the nineteenth transistor T19 through a plurality of (for example, four) twenty-fourth vias V24 arranged laterally, can be connected to another second area of ​​the active layer 319 of the nineteenth transistor T19 through a plurality of (for example, four) twenty-sixth vias V26 arranged laterally, can be connected to the first second area of ​​the active layer 320 of the twentieth transistor T20 through a plurality of (for example, four) eightieth vias V80 arranged laterally, can be connected to the second second area of ​​the active layer 320 of the twentieth transistor T20 through a plurality of (for example, four) eighty-second vias V82 arranged laterally, can be connected to the third second area of ​​the active layer 320 of the twentieth transistor T20 through a plurality of (for example, four) eighty-fourth vias V84 arranged laterally, and can be connected to the output electrode 61 through two fifty-fifth vias V55 arranged laterally.

[0235] In some examples, the shape of the twenty-second conductive connection portion D22 may be substantially a strip extending along the first direction X. The twenty-second conductive connection portion D22 may be located on one side of the twenty-first conductive connection portion D21 in the opposite direction of the first direction X. The twenty-second conductive connection portion D22 may be connected to the second first region of the active layer 320 of the twentieth transistor T20 through four eighty-third vias V83 arranged laterally. The twenty-second conductive connection portion D22 may be connected to the eighth transmission 718 located in the fifth conductive layer formed subsequently.

[0236] In some examples, the shape of the twenty-third conductive connection portion D23 may be substantially T-shaped. The twenty-third conductive connection portion D23 may be located on one side of the twenty-second conductive connection portion D22 in the opposite direction of the first direction X. The twenty-third conductive connection portion D23 may be connected to the second region of the active layer 313 of the thirteenth transistor T13 through the seventy-third via hole V73, and may also be connected to the second region of the active layer 312 of the twelfth transistor T12 through the seventeenth via hole V17, and may also be connected to the gate 214 of the fourteenth transistor T14 through the thirtieth via hole V30, and may also be connected to the top gate 215 of the fifteenth transistor T15 through the one hundred and first via hole V101. The second electrode of the twelfth transistor T12, the second electrode of the thirteenth transistor T13, the gate of the fourteenth transistor T14, and the gate of the fifteenth transistor T15 may be electrically connected through the twenty-third conductive connection portion D23, and the twenty-third conductive connection portion D23 may serve as the fourth node N4.

[0237] In some examples, the shape of the twenty-fourth conductive connection portion D24 may be substantially n-shaped. The twenty-fourth conductive connection portion D24 may be located on one side of the first conductive connection portion D1 in the opposite direction of the second direction Y. The twenty-fourth conductive connection portion D24 may be connected to the first region of the active layer 313 of the thirteenth transistor T13 through the seventy-second via V72, and may also be connected to the first region of the active layer 315 of the fifteenth transistor T15 through the seventy-fourth via V74. The twenty-fourth conductive connection portion D24 may be connected to a sixth transmission line 716 located in the fifth conductive layer formed subsequently.

[0238] In some examples, the shape of the twenty-fifth conductive connection portion D25 may be substantially L-shaped. The twenty-fifth conductive connection portion D25 may be located on one side of the twenty-first conductive connection portion D21 in the opposite direction of the first direction X. The twenty-fifth conductive connection portion D25 may be connected to the gate 222 of the twenty-second transistor T22 through the forty-ninth via V49, may be connected to the second region of the active layer 314 of the fourteenth transistor T14 through the nineteenth via V19, may be connected to the second region of the active layer 325 of the twenty-fifth transistor T25 through the thirteenth via V13, may be connected to the second region of the active layer 315 of the fifteenth transistor T15 through the seventy-fifth via V75, and may be connected to the second region of the active layer 326 of the twenty-sixth transistor T26 through the seventy-first via V71. The gate of the twenty-second transistor T22, the second electrode of the fourteenth transistor T14, the second electrode of the fifteenth transistor T15, the second electrode of the twenty-fifth transistor T25 and the second electrode of the twenty-sixth transistor T25 can be connected through the twenty-fifth conductive connection part D25, and the gate of the twenty-fourth transistor T24 and the gate of the twenty-second transistor T22 can be connected through the eighteenth conductive connection part D18. Therefore, the eighteenth conductive connection part D18, the gate of the twenty-second transistor T22 and the twenty-fifth conductive connection part D25 can be connected in sequence as the fifth node N5.

[0239] In some examples, the shape of the twenty-sixth conductive connection portion D26 may be substantially stepped. The twenty-sixth conductive connection portion D26 may be located between the twenty-fifth conductive connection portion D25 and the twenty-third conductive connection portion D23 in the second direction Y. The twenty-sixth conductive connection portion D26 may be connected to the first region of the active layer 312 of the twelfth transistor T12 through the sixteenth via V16, and may also be connected to the first region of the active layer 314 of the fourteenth transistor T14 through the eighteenth via V18. The twenty-sixth conductive connection portion D26 may be connected to a second transmission line 712 located in the fifth conductive layer formed subsequently.

[0240] In some examples, the shape of the twenty-seventh conductive connection portion D27 may be substantially L-shaped. The twenty-seventh conductive connection portion D27 may be located between the eighth conductive connection portion D8 and the eleventh conductive connection portion D11 in the first direction X. The twenty-seventh conductive connection portion D27 may be connected to the first region of the active layer 31 of the first transistor T1 through the first via V1, may be connected to the first region of the active layer 35 of the fifth transistor T5 through the third via V3, and may be connected to the first region of the active layer 39 of the ninth transistor T9 through the eighth via V8. The twenty-seventh conductive connection portion D27 may be connected to a second transmission virtual line 712 located in the fifth conductive layer formed subsequently.

[0241] In some examples, the shape of the twenty-eighth conductive connection portion D28 may be substantially a zigzag shape extending along the first direction X. The twenty-eighth conductive connection portion D28 may be located on one side of the twenty-third conductive connection portion D23 in the opposite direction of the first direction X. The twenty-eighth conductive connection portion D28 may be connected to the gate 212 of the twelfth transistor T12 through the twenty-ninth via hole V29, may be connected to the top gate 213 of the thirteenth transistor T13 through the one hundredth via hole V100, may be connected to the first region of the active layer 326 of the twenty-sixth transistor T26 through the seventieth via hole V70, may be connected to the first region of the active layer 325 of the twenty-fifth transistor T25 through the twelfth via hole V12, may be connected to the second region of the active layer 316 of the sixteenth transistor T16 through the ninth via hole V9, and may be connected to the second region of the active layer 318 of the eighteenth transistor T18 through the sixty-eighth via hole V68. The gate of the twelfth transistor T12, the gate of the thirteenth transistor T13, the first electrode of the twenty-fifth transistor T25, the first electrode of the twenty-sixth transistor T26, the second electrode of the sixteenth transistor T16, and the second electrode of the eighteenth transistor T18 can be electrically connected through a twenty-eighth conductive connection portion D28, and the twenty-eighth conductive connection portion D28 can serve as a third node N3.

[0242] In some examples, the shape of the twenty-ninth conductive connection portion D29 may be substantially dumbbell-shaped. The twenty-ninth conductive connection portion D29 may be located on one side of the twenty-fifth conductive connection portion D25 in the opposite direction of the first direction X. The twenty-ninth conductive connection portion D29 may be connected to the first region of the seventeenth transistor T17 through the fifteenth via V15. The twenty-ninth conductive connection portion D29 may serve as a gate input terminal of the shift register circuit at this stage. The twenty-ninth conductive connection portion D29 may be connected to a gate input signal line VT formed subsequently and located at the fifth conductive layer.

[0243] In some examples, the shape of the 30th conductive connection portion D30 may be substantially rectangular. The 30th conductive connection portion D30 may be located on one side of the 28th conductive connection portion D28 in the opposite direction of the second direction Y. The 30th conductive connection portion D30 may be connected to the top gate 218 of the 18th transistor T18 through the 98th via V98, and may also be connected to the gate 225 of the 25th transistor T25 through the 41st via V41.

[0244] In some examples, the shape of the thirty-first conductive connection portion D31 may be substantially rectangular. The thirty-first conductive connection portion D31 may be located on one side of the twenty-ninth conductive connection portion D29 in the opposite direction of the second direction Y. The thirty-first conductive connection portion D31 may be connected to the gate 226 of the twenty-sixth transistor T26 through the ninety-ninth via V99. The thirty-first conductive connection portion D31 may be connected to a second clock signal line CBL formed later and located in the fifth conductive layer.

[0245] In some examples, the shape of the thirty-second conductive connection portion D32 may be substantially a dumbbell extending along the second direction Y. The thirty-second conductive connection portion D32 may be located on one side of the twenty-ninth conductive connection portion D29 in the opposite direction of the first direction X. The thirty-second conductive connection portion D32 may be connected to the first region of the active layer 318 of the eighteenth transistor T18 through the sixty-ninth via hole V69, and may also be connected to the second region of the active layer 317 of the seventeenth transistor T17 through the fourteenth via hole V14.

[0246] In some examples, the shape of the thirty-third conductive connection portion D33 may be substantially a zigzag extending along the first direction X. The thirty-third conductive connection portion D33 may be located on one side of the twenty-eighth conductive connection portion D28 along the second direction Y. The thirty-third conductive connection portion D33 may be connected to the first region of the active layer 310 of the tenth transistor T10 through the sixty-seventh via V67. The thirty-third conductive connection portion D33 may be connected to a fifth transmission line 715 located in the fifth conductive layer formed subsequently.

[0247] In some examples, the shape of the thirty-fourth conductive connection portion D34 may be substantially rectangular. The thirty-fourth conductive connection portion D34 may be located between the fourth conductive connection portion D4 and the thirty-second conductive connection portion D32 in the first direction X. The thirty-fourth conductive connection portion D34 may be connected to the first region of the active layer 316 of the sixteenth transistor T16 through the tenth via V10. The thirty-fourth conductive connection portion D34 may be connected to the first transmission line 711 located in the fifth conductive layer formed subsequently.

[0248] In some examples, the shape of the thirty-fifth conductive connection portion D35 may be substantially L-shaped. The thirty-fifth conductive connection portion D35 may be located on one side of the twenty-seventh conductive connection portion D27 in the opposite direction of the first direction X. The thirty-fifth conductive connection portion D35 may be connected to the gate 26 of the sixth transistor T6 through the thirty-third via V33, may be connected to the second region of the active layer 39 of the ninth transistor T9 through the seventh via V7, and may be connected to the gate 221 of the twenty-first transistor T21 through the thirty-ninth via V39.

[0249] In some examples, the shape of the thirty-sixth conductive connection portion D36 may be substantially rectangular. The thirty-sixth conductive connection portion D36 may be located on one side of the fourth conductive connection portion D4 in the opposite direction of the first direction X. The thirty-sixth conductive connection portion D36 may be connected to the gate 216 of the sixteenth transistor T16 through the forty-third via V43. The thirty-sixth conductive connection portion D36 may serve as an initial control terminal of the shift register circuit at this stage, and may be connected to an initial control signal line NX formed subsequently and located at the fifth conductive layer.

[0250] In some examples, the shape of the thirty-seventh conductive connection portion D37 may be substantially L-shaped. The thirty-seventh conductive connection portion D37 may be located on one side of the thirty-third conductive connection portion D33 in the second direction Y. The thirty-seventh conductive connection portion D37 may be connected to the second connection electrode 402 through the forty-fourth via hole V44, may be connected to the second region of the active layer 310 of the tenth transistor T10 through the sixty-sixth via hole V66, may be connected to the gate 27 of the seventh transistor T7 through the ninety-sixth via hole V96, and may be connected to the gate 26 of the sixth transistor T6 through the thirty-fourth via hole V34. The gate of the sixth transistor T6, the gate of the seventh transistor T7, and the second electrode of the tenth transistor T10 are connected through the thirty-seventh conductive connection part D37, the gate of the sixth transistor T6, the second electrode of the ninth transistor T9, and the gate of the twenty-first transistor T21 can be connected through the thirty-fifth conductive connection part D35, the gate of the twenty-first transistor T21 and the gate of the twenty-third transistor T23 can be connected through the thirteenth conductive connection part D13, the thirty-seventh conductive connection part D37 can be connected to the fourth conductive connection part D4 through the second connection electrode 402, and the fourth conductive connection part D4 is connected to the second electrode of the eleventh transistor T11, so that the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twenty-first transistor T21 and the twenty-third transistor T23 are all connected to the cascade output end.

[0251] In some examples, the shape of the thirty-eighth conductive connection portion D38 may be substantially U-shaped. The thirty-eighth conductive connection portion D38 may be located on one side of the seventh conductive connection portion D7 in the opposite direction of the first direction X. The thirty-eighth conductive connection portion D38 may be connected to the gate 21 of the first transistor T1 through the fiftieth via V50, and may also be connected to the second region of the active layer 27 of the twenty-seventh transistor T27 through the sixth via V6, and may also be connected to the gate 28 of the eighth transistor T8 through the ninety-fifth via V95, and may also be connected to the second region of the active layer 328 of the twenty-eighth transistor T28 through the sixty-fifth via V65. The gate of the first transistor T1, the gate of the eighth transistor T8, the second electrode of the twenty-seventh transistor T27, and the second electrode of the twenty-eighth transistor T28 may be connected through the thirty-eighth conductive connection portion D38, and the thirty-eighth conductive connection portion D38 may serve as the first node N1.

[0252] In some examples, the shape of the thirty-ninth conductive connection portion D39 may be substantially 1-shaped. The thirty-ninth conductive connection portion D39 may be located between the thirty-seventh conductive connection portion D37 and the thirty-fifth conductive connection portion D35. The thirty-ninth conductive connection portion D39 may be connected to the top gate 210 of the tenth transistor T10 through the ninety-seventh via V97, may be connected to the gate 29 of the ninth transistor T9 through the thirty-eighth via V38, may be connected to the second region of the active layer 36 of the sixth transistor T6 through the fourth via V4, and may be connected to the second region of the active layer 37 of the seventh transistor T7 through the sixty-third via V63. The second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, the gate of the ninth transistor T9 and the gate of the tenth transistor T10 can be connected through the thirty-ninth conductive connection portion D39, the second electrode of the second transistor T2 and the second electrode of the third transistor T3 can be connected through the ninth conductive connection portion D9, the second electrode of the second transistor T2 and the second electrode of the sixth transistor T6 can be connected through the active layer 22 of the second transistor T2 and the active layer 26 of the sixth transistor T6 as an integrated structure to achieve connection, and the integrated structure of the active layer 22 of the second transistor T2 and the active layer 26 of the sixth transistor T6, the ninth conductive connection portion D9 and the thirty-ninth conductive connection portion D39 can be connected as the second node N2.

[0253] (9) Forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer, and then a seventh insulating film is coated, and the seventh insulating film is patterned by a patterning process to form a seventh insulating layer.

[0254] Fig.12 FIG. 1 is a schematic diagram of a display substrate after forming a seventh insulating layer according to at least one embodiment of the present disclosure. Fig.12 As shown, the seventh insulating layer of the display substrate is provided with a plurality of via holes, for example, including: the 111th via hole V111 to the 127th via hole V127. The seventh insulating layer and the sixth insulating layer in the 111th via hole V111 to the 127th via hole V127 can be removed to expose part of the surface of the fourth conductive layer.

[0255] (10) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer.

[0256] Fig.13A It is a schematic diagram of a display substrate after a fifth conductive layer is formed according to at least one embodiment of the present disclosure. Fig. 13B for Fig.13A Schematic diagram of the fifth conductive layer in .

[0257] In some examples, such as Fig.13A and Fig. 13B As shown, the fifth conductive layer of the display substrate may include at least: a plurality of signal lines, such as: a first clock signal line CKL, a second clock signal line CBL, a selection input signal line VT, an initial control signal line NX, and a plurality of transmission lines (for example, a first transmission line 711, a second transmission line 712, a third transmission line 713, a fourth transmission line 714, a fifth transmission line 715, a sixth transmission line 716, a seventh transmission line 717 and an eighth transmission line 718).

[0258] In some examples, the first clock signal line CKL, the second clock signal line CBL, the gate input signal line VT, the initial control signal line NX, and the plurality of transmission lines may all be in the shape of strips extending along the second direction Y. In the first direction X, the initial signal control line NX, the first transmission line 711, the fifth transmission line 715, the second clock small signal line CBL, the gate input signal line VT, the first clock signal line CKL, the second transmission line 712, the sixth transmission line 716, the seventh transmission line 717, the third transmission line 713, the fourth transmission line 714, and the eighth transmission line 718 may be arranged in sequence.

[0259] In some examples, the initial control signal line NX may be connected to the thirty-sixth conductive connection portion D36 through the one-hundred-and-seventeenth via hole V117 to provide an initial control signal to the initial control terminal of the shift register circuit.

[0260] In some examples, the gate input signal line VT may be located between the second clock signal line CBL and the second clock signal line CKL in the first direction X. The gate input signal line VT may be connected to the twenty-ninth conductive connection portion D29 through the one hundred and nineteenth via hole V119 to provide a gate input signal to the gate input terminal of the shift register circuit.

[0261] In some examples, the line width of the second clock signal line CBL and the first clock signal line CKL can be substantially the same, and the line width can be greater than the line width of the remaining routing lines, which can reduce the transmission resistance of the clock signal. The clock signal end of the n-th level (for example, n can be equal to 2i) shift register circuit of this example can be connected to the second clock signal line CBL. Among them, the second clock signal line CBL can be connected to the sixth conductive connection part D6 through the 112th via V112 to provide a clock signal to the fourth transistor T4, the 27th transistor T27 and the 28th transistor T28; it can also be connected to the eighth conductive connection part D8 through the 114th via V114 to provide a clock signal to the fifth transistor T5; it can also be connected to the thirty-first conductive connection part D31 through the 118th via V118 to provide a clock signal to the 26th transistor T26. The first clock signal line CKL can be connected to the clock signal end of the n-1th level shift register circuit.

[0262] In some examples, the voltage signal transmitted by the first transmission line 711, the second transmission line 712, the third transmission line 713 and the fourth transmission line 714 may be greater than the voltage signal transmitted by the fifth transmission line 715, the sixth transmission line 716, the seventh transmission line 717 and the eighth transmission line 718. For example, the first transmission line 711, the second transmission line 712, the third transmission line 713 and the fourth transmission line 714 may all be used as the first voltage line to transmit the first voltage signal; the fifth transmission line 715, the sixth transmission line 716, the seventh transmission line 717 and the eighth transmission line 718 may all be used as the second voltage line to transmit the second voltage signal. However, this embodiment is not limited to this. In other examples, the fifth transmission line 715, the sixth transmission line 716 and the eighth transmission line 718 may transmit the same voltage signal, and the seventh transmission line 717 may transmit a different voltage signal from the fifth transmission line 715.

[0263] In some examples, the first transmission line 711 can be connected to the fifth conductive connection portion D5 through the 111th via V111 to achieve electrical connection with the 27th transistor T27; it can also be connected to the 34th via V34 through the 127th via V127 to achieve connection with the 11th transistor T11 and the 16th transistor T16.

[0264] In some examples, the second transmission line 712 can be connected to the twenty-seventh conductive connection portion D27 through the one-hundred-thirteenth via V113 to achieve connection with the first transistor T1 and the fifth transistor T5; it can also be connected to the twenty-sixth conductive connection portion D26 through the one-hundred-twenty via V120 to achieve connection with the twelfth transistor T12 and the fourteenth transistor T14.

[0265] In some examples, the third transmission line 713 can be connected to the sixteenth conductive connection portion D16 through the one hundred and twenty-third via V123, and can also be connected to the seventeenth conductive connection portion D17 through the one hundred and twenty-fourth via V124, to achieve connection with the nineteenth transistor T19, the twenty-first transistor T21 and the twenty-second transistor T22.

[0266] In some examples, the fourth transmission line 714 may be adjacent to the third transmission line 713 in the first direction X, for example, located on one side of the third transmission line 713 in the first direction X. The fourth transmission line 714 may not be connected to the n-th stage (n may be equal to 2i) shift register circuit, and may be connected to the n-1-th stage shift register circuit.

[0267] In some examples, the fifth transmission line 715 may be adjacent to the first transmission line 711 in the first direction X, for example, located on one side of the first transmission line 711 in the first direction X. The fifth transmission line 715 may be connected to the seventh conductive connection portion D7 through the 115th via hole V115 to achieve connection with the fourth transistor T4, the eighth transistor T8 and the twenty-eighth transistor T28; and may also be connected to the thirty-third conductive connection portion D33 through the 116th via hole V116 to achieve connection with the tenth transistor T10.

[0268] In some examples, the sixth transmission line 716 may be adjacent to the second transmission line 712 in the first direction X, for example, located on one side of the second transmission line 712 in the first direction X. The sixth transmission line 716 may be connected to the twenty-fourth conductive connection portion D24 through the one hundred and twenty-first via hole V121 to achieve connection with the thirteenth transistor T13 and the fifteenth transistor T15.

[0269] In some examples, the seventh transmission line 717 may be adjacent to the third transmission line 713 and the sixth transmission line 716 in the first direction X, for example, may be located on one side of the third transmission line 713 in the opposite direction of the first direction X, and located on one side of the sixth transmission line 716 in the first direction X. The spacing between the seventh transmission line 717 and the sixth transmission line 716 may be greater than the spacing between the seventh transmission line 717 and the third transmission line 713. The seventh transmission line 717 may be connected to the fourteenth conductive connection portion D14 through the one hundred and twenty-second via hole V122, thereby being connected to the first bottom gate connection portion 601.

[0270] In some examples, the eighth transmission line 718 may be located on one side of the fourth transmission line 714 in the first direction X. The eighth transmission line 718 may be connected to the twentieth conductive connection portion D20 through the one hundred and twenty-fifth via hole V125 to achieve connection with the twentieth transistor T20 and the twenty-fourth transistor T24; and may also be connected to the twenty-second conductive connection portion D22 through the one hundred and twenty-sixth via hole V126 to achieve connection with the twentieth transistor T20.

[0271] In some examples, a pixel circuit can be formed in a display area while a shift register circuit is formed on a display substrate. For example, the first semiconductor layer of the display area may include: an active layer of a first type transistor (e.g., a P-type transistor) of the pixel circuit, the first conductive layer of the display area may include: a gate of the first type transistor of the pixel circuit and a first plate of a storage capacitor, the second conductive layer of the display area may include: a second plate of the storage capacitor of the pixel circuit and a bottom gate of the second type transistor, the second semiconductor layer of the display area may include: an active layer of a second type transistor (e.g., an N-type transistor) of the pixel circuit, the third conductive layer of the display area may include: a top gate of the second type transistor of the pixel circuit, the fourth conductive layer of the display area may include at least: connection electrodes of multiple transistors of the pixel circuit, and the fifth conductive layer of the display area may include at least: a data line and a power line connected to the pixel circuit. This embodiment is not limited to this.

[0272] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The sixth insulating layer and the seventh insulating layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. However, this embodiment is not limited to this.

[0273] The structure and preparation process shown in this exemplary embodiment are only an exemplary description. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment, can be well compatible with existing preparation processes, and has simple process implementation, easy implementation, high production efficiency, low production cost, and high yield rate.

[0274] In this example, the gate of the second transistor T2 of the first NOT gate circuit and the gate of the third transistor T3 are connected to receive the same signal, the second electrode of the second transistor T2 and the second electrode of the third transistor T3 are connected via a ninth conductive connection portion D9 located on the fourth conductive layer, the first electrode of the second transistor T2 can be connected to the first transistor T1 via an active layer integrated structure located on the first semiconductor layer, and the first electrode of the third transistor T3 can be connected to the fourth transistor T4 via an active layer integrated structure located on the second semiconductor layer. By designing the active layers of the second transistor T2 and the first transistor T1 to be an interconnected integrated structure, and the active layers of the third transistor T3 and the fourth transistor T4 to be an interconnected integrated structure, circuit space can be saved.

[0275] In this example, the gate of the sixth transistor T6 of the second NOT gate circuit and the gate of the seventh transistor T7 are connected to receive the same signal, the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are connected through the thirty-ninth conductive connection portion D39 located on the fourth conductive layer, the first electrode of the sixth transistor T6 can be connected to the fifth transistor T5 through the active layer integrated structure located on the first semiconductor layer, and the first electrode of the seventh transistor T7 can be connected to the eighth transistor T8 through the active layer integrated structure located on the second semiconductor layer. By designing the active layers of the sixth transistor T6 and the fifth transistor T5 to be an integrated structure connected to each other, and the active layers of the seventh transistor T7 and the eighth transistor T8 to be an integrated structure connected to each other, the circuit space occupied can be saved. The thirty-ninth conductive connection portion D39 and the ninth conductive connection portion D9 can be connected through the integrated structure of the active layer of the second transistor T2 and the sixth transistor T6 located on the first semiconductor layer, which can be conducive to the reasonable arrangement of the conductive connection portion of the fourth conductive layer.

[0276] In this example, the gate of the ninth transistor T9 and the gate of the tenth transistor T10 of the third NOT gate circuit can both be connected to the thirty-ninth conductive connection portion D39 to achieve connection with the output ends of the first NOT gate circuit and the second NOT gate circuit. The third NOT gate circuit can be connected in series with the first NOT gate circuit and the second NOT gate circuit. The second electrode of the ninth transistor T9 can be connected to the thirty-fifth conductive connection portion D35 located on the fourth conductive layer, the second electrode of the tenth transistor T10 can be connected to the thirty-seventh conductive connection portion D37 located on the fourth conductive layer, the thirty-seventh conductive connection portion D37 and the thirty-fifth conductive connection portion D35 can be connected through the gate 26 of the sixth transistor T6 located on the first conductive layer, the thirty-seventh conductive connection portion D37 can be connected to the second connection electrode 402 located on the first conductive layer, the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 can be connected through the thirty-fifth conductive connection portion D35 located on the fourth conductive layer, the gate 26 of the sixth transistor T6 located on the first conductive layer, the thirty-seventh conductive connection portion D37 located on the fourth conductive layer, and the second connection electrode 402 located on the first conductive layer, and then connected to other transistors. The first electrode of the ninth transistor T9 can be connected to the second transmission line 712 located in the fifth conductive layer through the twenty-seventh conductive connection portion D27 located in the fourth conductive layer to receive the first voltage signal. The first electrode of the tenth transistor T10 can be connected to the fifth transmission line 715 located in the fifth conductive layer through the thirty-third conductive connection portion D33 located in the fourth conductive layer to receive the second voltage signal. The transistor arrangement and connection method of the NOT gate circuit in this example can save space.

[0277] In this example, the second electrode of the twelfth transistor T12 and the second electrode of the thirteenth transistor T13 of the fifth NOT gate circuit, the gate of the fourteenth transistor T14 and the gate of the fifteenth transistor T15 of the sixth NOT gate circuit can be connected through the twenty-third conductive connection portion D23 located on the fourth conductive layer. The fifth NOT gate circuit can be connected in series with the sixth NOT gate circuit.

[0278] In this example, the active layer 32 of the second transistor T2 of the first NOT gate circuit and the active layer 33 of the third transistor T3 extend in the same direction, for example, both extend along the first direction X; the active layer 32 of the second transistor T2 and the active layer 33 of the third transistor T3 are arranged in sequence along the first direction X, and can be arranged in a substantially straight line. The arrangement direction of the second transistor T2 and the third transistor T3 of the first NOT gate circuit can be the same as the extension direction of the active layer, that is, they are arranged in sequence along the first direction X.

[0279] In this example, the active layer 36 of the sixth transistor T6 of the second NOT gate circuit and the active layer 37 of the seventh transistor T7 extend in the same direction, for example, both extend along the first direction X; the active layer 36 of the sixth transistor T6 and the active layer 37 of the seventh transistor T7 are arranged in sequence along the first direction X, and can be arranged in a substantially straight line. The arrangement direction of the sixth transistor T6 and the seventh transistor T7 of the second NOT gate circuit can be the same as the extension direction of the active layer, that is, they are arranged in sequence along the first direction X.

[0280] In this example, the active layer 39 of the ninth transistor T9 of the third NOT gate circuit and the active layer 310 of the tenth transistor T10 may extend in the same direction, for example, both extend along the first direction X; the active layer 39 of the ninth transistor T9 and the active layer 310 of the tenth transistor T10 are arranged in sequence along the first direction X, and may be arranged in a substantially straight line. The arrangement direction of the ninth transistor T9 and the tenth transistor T10 of the third NOT gate circuit may be the same as the extension direction of the active layer, that is, they are arranged in sequence along the first direction X.

[0281] In this example, the active layer 327 of the 27th transistor T27 of the fourth NOT gate circuit extends along the second direction Y, and the active layer 328 of the 28th transistor T28 extends along the first direction X, and the extension directions of the two intersect; the active layer 327 of the 27th transistor T27 and the active layer 328 of the 28th transistor T28 can be arranged in a substantially L-shaped manner. The 27th transistor T27 and the 28th transistor T28 of the fourth NOT gate circuit can be arranged in the second direction Y, which can be substantially the same as the extension direction of the active layer 327 of the 27th transistor T27.

[0282] In this example, the active layer 312 of the twelfth transistor T12 and the active layer 313 of the thirteenth transistor T13 of the fifth NOT gate circuit extend in the same direction, for example, both extend in the first direction X; the active layer 312 of the twelfth transistor T12 and the active layer 313 of the thirteenth transistor T13 are sequentially arranged along the second direction Y. The active layer 312 of the twelfth transistor T12 and the active layer 313 of the thirteenth transistor T13 can be arranged in parallel. The arrangement direction of the twelfth transistor T12 and the thirteenth transistor T13 of the fifth NOT gate circuit can intersect with the extension direction of the active layer, for example, they are sequentially arranged along the second direction Y.

[0283] In this example, the active layer 314 of the fourteenth transistor T14 and the active layer 315 of the fifteenth transistor T15 of the sixth NOT gate circuit extend in the same direction, for example, both extend in the first direction X; the active layer 314 of the fourteenth transistor T14 and the active layer 315 of the fifteenth transistor T15 are sequentially arranged along the second direction Y. The active layer 314 of the fourteenth transistor T14 and the active layer 315 of the fifteenth transistor T15 can be arranged in parallel. The arrangement direction of the fourteenth transistor T14 and the fifteenth transistor T15 of the sixth NOT gate circuit can intersect with the extension direction of the active layer, for example, they are sequentially arranged along the second direction Y.

[0284] This example provides a variety of arrangements of transistors of a NOT gate circuit. The combination of the various arrangements can help save space and facilitate the narrowing of the frame.

[0285] In this example, the twenty-first transistor T21 and the twenty-second transistor T22 of the NAND gate circuit can be located in the middle of the twenty-third transistor T23 and the twenty-fourth transistor T24. The top gate 223 of the twenty-third transistor T23, the gate 221 of the twenty-first transistor T21, the gate 222 of the twenty-second transistor T22, and the top gate 224 of the twenty-fourth transistor T24 can be arranged along the second direction Y and staggered to save space. The arrangement of the NAND gate circuit in this example can save the setting space of the NAND gate circuit.

[0286] The display substrate provided by this exemplary embodiment can save the space occupied by the shift register circuit by designing the layout of the shift register circuit on the basis of realizing partial refresh, which is conducive to realizing a display substrate with a narrow frame.

[0287] Fig.14 Schematic diagram of the connection of the bottom gate connection portion of at least one embodiment of the present disclosure. Fig.14 FIG. 2 shows a second conductive layer and a portion of the structure connected to the bottom gate connection portion. In some examples, such as Fig.14 As shown, the first bottom gate connection portion 601 can be connected to the second bottom gate connection portion 602 through the first conductive connection portion D1 located in the fourth conductive layer. The first bottom gate connection portion 601 can also be connected to the seventh transmission line 717 through the fourteenth conductive connection portion D14 located in the fourth conductive layer, for example, to receive the second voltage signal. The top gate 320 of the twentieth transistor T20 can be connected to the bottom gate 320 through the nineteenth conductive connection portion D19 located in the fourth conductive layer.

[0288] In this example, the bottom gate 520 and the top gate 320 of the twentieth transistor T20 are connected, so that the top gate 320 and the bottom gate 520 of the twentieth transistor T20 can be written with the same control signal, and the conduction or cutoff of the twentieth transistor T20 can be controlled simultaneously. Moreover, the bottom gates of the remaining N-type transistors are independently controlled from the bottom gate of the twentieth transistor T20 as the output transistor, which can ensure that the remaining N-type transistors and the twentieth transistor T20 as the output transistor do not interfere with each other, thereby improving the stability of the drive signal output by the shift register circuit.

[0289] Fig.15 FIG. 4 is another partial top view of a display substrate according to at least one embodiment of the present disclosure. Fig.16A for Fig.15 Schematic diagram of a display substrate after forming a first semiconductor layer. Fig. 16B for Fig.15 Schematic diagram of a display substrate after forming a first conductive layer. Fig. 16C for Fig.15 Schematic diagram of the fourth conductive layer in .

[0290] In some examples, such as Figures 15 to 16C As shown, the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 36 of the sixth transistor T6, and the active layer 35 of the fifth transistor T5 may be an integrated structure connected to each other, and the shape of the integrated structure may be a ring, such as a rectangular ring. Among them, the second area of ​​the active layer 31 of the first transistor T1 may also serve as the first area of ​​the active layer 32 of the second transistor T2, the second area of ​​the active layer 32 of the second transistor T2 may also serve as the second area of ​​the active layer 36 of the sixth transistor T6, the first area of ​​the active layer 36 of the sixth transistor T6 may also serve as the second area of ​​the active layer 35 of the fifth transistor T5, and the first area of ​​the active layer 31 of the first transistor T1 may also serve as the first area of ​​the active layer 35 of the fifth transistor T5.

[0291] In some examples, the active layer 321 of the twenty-first transistor T21 and the active layer 322 of the twenty-second transistor T22 may be an integrated structure connected to each other, and the shape of the integrated structure may be approximately annular, such as a rectangular ring. The second region of the active layer 321 of the twenty-first transistor T21 may also serve as the second region of the active layer 322 of the twenty-second transistor T22, and the first region of the active layer 321 of the twenty-first transistor T21 may also serve as the first region of the active layer of the twenty-second transistor T22.

[0292] In some examples, the twenty-seventh conductive connection portion D27 located in the fourth conductive layer can be connected to the first region of the active layer 31 of the first transistor T1 and the first region of the active layer 35 of the fifth transistor T5 through a single via hole to achieve access to the same signal. The fifteenth conductive connection portion D15 located in the fourth conductive layer can be connected to the first region of the active layer 321 of the twenty-first transistor T21 and the first region of the active layer 322 of the twenty-second transistor T22 through a single via hole to achieve access to the same signal.

[0293] In this example, for a plurality of transistors whose first electrodes are connected to each other and whose second electrodes are also connected to each other, a ring channel structure design can be adopted, which can reduce the number of holes.

[0294] Fig.17 FIG. 4 is another partial top view of a display substrate according to at least one embodiment of the present disclosure. Fig.18A for Fig.17 Schematic diagram of a display substrate after a fourth conductive layer is formed. Fig.18B for Fig.17 A schematic diagram of connection between the shift register circuit and the first clock signal line and the second clock signal line. Fig.17 Schematically shows two cascaded shift register circuits GOA(n-1) and GOA(n), where n can be 2i and i can be an integer greater than 0.

[0295] In some examples, such as Fig.17 , Fig.18A and Fig.18BAs shown, the shift register circuit GOA(n-1) can be connected to the first clock signal line CKL, and the shift register circuit GOA(n) can be connected to the second clock signal line CBL. The shape of the eighth conductive connection part D8 of the shift register circuit GOA(n-1) located in the fourth conductive layer can be roughly rectangular, the eighth conductive connection part D8 can be connected to the first clock signal line CKL, and the eighth conductive connection part D8 can be connected to the gate of the fifth transistor T5. The sixth conductive connection part D6 of the shift register circuit GOA(n-1) located in the fourth conductive layer can extend to one side of the tenth conductive connection part D10 in the second direction Y and be connected to the first clock signal line CKL, and the sixth conductive connection part D6 can be connected to the gate of the twenty-seventh transistor T27, the gate of the twenty-eighth transistor T28, and the gate of the first transistor T1. The top gate 226 of the twenty-sixth transistor T26 of the shift register circuit GOA(n-1) may be in the shape of a strip extending along the first direction X, and the top gate 226 of the twenty-sixth transistor T26 may be connected to the thirty-first conductive connection portion D31 located in the fourth conductive layer; the thirty-first conductive connection portion D31 may be in the shape of a strip extending along the second direction Y, and is located between the twenty-eighth conductive connection portion D28 and a portion of the twenty-fifth conductive connection portion D25 in the second direction Y. The thirty-first conductive connection portion D31 of the shift register circuit GOA(n-1) may be connected to the first clock signal line CKL. The description of the connection method between the shift register circuit GOA(n) and the second clock signal line CBL may refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0296] In this example, the first clock signal line CKL is set to provide a clock signal to the odd-numbered shift register circuit, and the second clock signal line CBL is set to provide a clock signal to the even-numbered shift register circuit, and in a single shift register circuit, the received clock signal is inverted by the fourth NOT gate circuit (including the twenty-seventh transistor T27 and the twenty-eighth transistor T28) to obtain a clock inversion signal. The setting method of this example can reduce the coupling between the clock signals provided by the first clock signal line CKL and the second clock signal line CBL, which is conducive to ensuring the stability of the drive signal output by the shift register circuit.

[0297] In some examples, the shift register circuit GOA(n-1) can be connected to the fourth transmission line 714, and the shift register circuit GOA(n) can be connected to the third transmission line 713. The third transmission line 713 and the fourth transmission line 714 can be configured to transmit the same first voltage signal. The sixteenth conductive connection portion D16 and the seventeenth conductive connection portion D17 of the shift register circuit GOA(n-1) located on the fourth conductive layer can be connected to the fourth transmission line 714 located on the fifth conductive layer.

[0298] The layout design of the shift register circuit of this example is conducive to saving space and facilitating wiring layout. The structure of the shift register circuit GOA(n) of this example and the rest of the structure of the shift register circuit GOA(n-1) can refer to the description of the previous embodiment, so it will not be repeated here.

[0299] Fig.19 Schematic diagram of the connection of the bottom gate connection parts of adjacent shift register circuits according to at least one embodiment of the present disclosure. Fig.19 As shown, the first bottom gate connection portion 601 of the shift register circuit GOA(n-1) can be connected to the second bottom gate connection portion 602 through the first conductive connection portion D1 located in the fourth conductive layer, and can also be connected to the seventh transmission line 717 located in the fifth conductive layer through the fourteenth conductive connection portion D14. The seventh transmission line 717 can be connected to the first bottom gate connection portion of the shift register circuit GOA(n). The bottom gate connection portions of adjacent shift register circuits can be connected through the seventh transmission line 717 located in the fifth conductive layer. In this example, adjacent shift register circuits can be connected to the same signal line (i.e., the seventh transmission line 717) to access the same signal. The remaining structures of this example can refer to the description of the aforementioned embodiment, so they are not repeated here.

[0300] Fig. 20 1 is another connection diagram of the bottom gate connection portion of the adjacent shift register circuit according to at least one embodiment of the present disclosure. Fig. 20 As shown, the first bottom gate connection portion 601 of each stage of the shift register circuit can be connected to the second bottom gate connection portion 602 through the first conductive connection portion D1 located in the fourth conductive layer. The bottom gate 515 of the fifteenth transistor T15 of the shift register circuit GOA (n-1) can be connected to the first bottom gate connection portion 601 of the shift register circuit GOA (n) through the fifth connection electrode 405. The bottom gate 515 of the fifteenth transistor T15 of the shift register circuit GOA (n-1), the bottom gate of the thirteenth transistor T13, the bottom gate 524 of the twenty-fourth transistor T24, the bottom gate 526 of the twenty-sixth transistor T26, the second bottom gate connection portion 602, the fifth connection electrode 405 and the first bottom gate connection portion 601 of the shift register circuit GOA (n) can be an integrated structure connected to each other. The arrangement of the bottom gates and bottom gate connection portions of adjacent shift register circuits in this example does not require additional drilling, which can simplify the process flow. The remaining structures of this example can refer to the description of the aforementioned embodiment, so they are not repeated here.

[0301] Fig.21 Another connection diagram of the bottom gate connection portion of the shift register circuit according to at least one embodiment of the present disclosure is shown. Fig.21 FIG. 4 illustrates a partial structure of two adjacent shift register circuits. Fig.22Afor Fig.21 Schematic diagram of the bottom gate structure. Fig. 22B and Fig. 22C for Fig.21 Schematic diagram of the connection relationship of the bottom gate connection part.

[0302] In some examples, such as Figures 21 to 22C As shown, the second conductive layer of the display substrate may include at least: a bottom gate 53 of the third transistor T3 of the shift register circuit, a bottom gate 54 of the fourth transistor T4, a bottom gate 57 of the seventh transistor T7, a bottom gate 58 of the eighth transistor T8, a bottom gate 510 of the tenth transistor T10, a bottom gate 513 of the thirteenth transistor T13, a bottom gate 515 of the fifteenth transistor T15, a bottom gate 518 of the eighteenth transistor T18, a bottom gate 520 of the twentieth transistor T20, a bottom gate 523 of the twenty-third transistor T23, a bottom gate 524 of the twenty-fourth transistor T24, a bottom gate 525 of the twenty-fifth transistor T25, a bottom gate 526 of the twenty-sixth transistor T26 and a bottom gate 528 of the twenty-eighth transistor T28.

[0303] In some examples, the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 57 of the seventh transistor T7, the bottom gate 58 of the eighth transistor T8, the bottom gate 510 of the tenth transistor T10, the bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 525 of the twenty-fifth transistor T25, the bottom gate 526 of the twenty-sixth transistor T26, and the bottom gate 528 of the twenty-eighth transistor T28 may be connected via the first bottom gate connection portion 601.

[0304] In some examples, the first bottom gate connection portion 601 may include: a first line segment extending along the first direction X, a second line segment extending along the third direction, a third line segment extending along the first direction X, a fourth line segment extending along the second direction Y, and a fifth line segment extending along the first direction X, and a first extension segment and a second extension segment extending along the second direction Y. The first line segment, the second line segment, the third line segment, the fourth line segment, and the fifth line segment may be connected in sequence, and the fourth line segment and the fifth line segment may be located on one side of the third line segment in the opposite direction of the second direction Y. The first line segment may be connected to the first extension segment and the second extension segment extending along the second direction Y, and the second extension segment may be located on one side of the first extension segment.

[0305] In some examples, the bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, and the bottom gate 57 of the seventh transistor T7 may be located on one side of the first line segment in the second direction Y and directly connected to the first line segment; the bottom gate 54 of the fourth transistor T4 may be connected to the first line segment through the bottom gate 58 of the eighth transistor T8, and the bottom gate 53 of the third transistor T3 may be connected to the first line segment through the bottom gate 57 of the seventh transistor T7. The bottom gate 518 of the eighteenth transistor T18 and the bottom gate 510 of the tenth transistor T10 may be located on one side of the first line segment in the opposite direction of the second direction Y, and the bottom gate 518 of the eighteenth transistor T18 may be connected to the first line segment through the first extension segment, and the bottom gate 510 of the tenth transistor T10 may be connected to the first line segment through the second extension segment. The bottom gate 526 of the twenty-sixth transistor T26 may be located on one side of the fourth line segment in the opposite direction of the first direction X and directly connected to the fourth line segment. The bottom gate 513 of the thirteenth transistor T13 and the bottom gate 515 of the fifteenth transistor T15 may be located at one side of the fifth line segment in the second direction Y and directly connected to the fifth line segment.

[0306] In some examples, the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, the bottom gate 57 of the seventh transistor T7, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 510 of the tenth transistor T10, the bottom gate 526 of the twenty-sixth transistor T26, the bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, and the first bottom gate connection portion 601 can be an integrated structure connected to each other.

[0307] In some examples, the bottom gate 523 of the twenty-third transistor T23 and the bottom gate 524 of the twenty-fourth transistor T24 may be connected via a second bottom gate connection portion 602. The second bottom gate connection portion 602 may be substantially in the shape of a strip extending along the third direction. For example, the bottom gate 523 of the twenty-third transistor T23, the bottom gate 524 of the twenty-fourth transistor T24, and the second bottom gate connection portion 602 may be an integrated structure connected to each other.

[0308] In some examples, such as Fig. 22BAs shown, the fourth conductive layer of the display substrate may include at least: a third connection electrode 403 and a fourth connection electrode 404. The shape of the third connection electrode 403 may be substantially a strip extending along the first direction X. The third connection electrode 403 may be connected to the extension portion of the bottom gate 523 of the twenty-third transistor T23. The fourth connection electrode 404 may be located on the side of the bottom gate 513 of the thirteenth transistor T13 in the opposite direction of the second direction, and may be aligned with the bottom gate 513 in the second direction Y. The shape of the fourth connection electrode 404 may be substantially a strip extending along the second direction Y. The fourth connection electrode 404 may be connected to the first bottom gate connection portion 601.

[0309] In some examples, such as Fig. 22C As shown, the fifth conductive layer of the display substrate may include at least: a seventh transmission line 717 and a ninth transmission line 719. The seventh transmission line 717 may be located on one side of the ninth transmission line 719 in the first direction X. For example, the ninth transmission line 719 may be located between the aforementioned sixth transmission line and the seventh transmission line 717, or the ninth transmission line 719 and the aforementioned sixth transmission line may be an integral structure. The seventh transmission line 717 may be connected to the third connection electrode 403 to provide a voltage signal to the bottom gate 523 of the twenty-third transistor T23, the bottom gate 524 of the twenty-fourth transistor T24, and the second bottom gate connection 602. The ninth transmission line 719 may be connected to the fourth connection electrode 404 to provide a voltage signal to the first bottom gate connection portion 601 and the bottom gate connected thereto.

[0310] In some examples, the seventh transmission line 717 and the ninth transmission line 719 can be configured to transmit the same voltage signal, such as the second voltage signal. However, this embodiment is not limited to this. In other examples, the seventh transmission line 717 and the ninth transmission line 719 can transmit different voltage signals.

[0311] This example divides the N-type transistors except the second transistor T20 as the output transistor into two groups, and the bottom gates of the two groups of N-type transistors are independently set, so as to reduce the electrostatic discharge (ESD) risk that may be caused by the full-surface connection of the N-type transistors of multiple shift register circuits.

[0312] Fig.23Schematic diagram of a light shielding layer of at least one embodiment of the present disclosure. In some examples, the display substrate may further include: a light shielding layer BSM located on a side of the first semiconductor layer close to the substrate. The orthographic projection of the light shielding layer BSM on the substrate may at least partially overlap with the orthographic projection of the first semiconductor layer on the substrate. The light shielding layer BSM may at least partially overlap with the orthographic projection of the active layer of the low-temperature polysilicon transistor of the shift register circuit on the substrate. For example, the light shielding layer BSM may cover the orthographic projection of the active layer of multiple low-temperature polysilicon transistors of the shift register circuit on the substrate.

[0313] In some examples, the display substrate may include multiple gate drive circuits, for example, a gate drive circuit for providing a light emitting control signal, a gate drive circuit for providing a control signal to an N-type transistor of a pixel circuit, and a gate drive circuit for providing a control signal to a P-type transistor of a pixel circuit. Each gate drive circuit may include multiple shift register circuits in cascade.

[0314] In some examples, the plurality of gate driving circuits may be divided into a plurality of circuit regions, and the plurality of circuit regions may be arranged sequentially along the second direction Y. Fig.23 Two circuit areas 81a and 81b are illustrated in FIG. Each circuit area (e.g., circuit area 81a) may include: a first area 801, a second area 802, and a third area 803 arranged in sequence along a first direction X. The shift register circuit provided in the first area 801 may be a shift register circuit included in a gate drive circuit for providing a light emitting control signal. The shift register circuit provided in the second area 802 may be a shift register circuit included in a gate drive circuit for providing a control signal to an N-type transistor of a pixel circuit. The shift register circuit provided in the third area 803 may be a gate drive circuit for providing a control signal to a P-type transistor of a pixel circuit. The shift register circuit provided in the aforementioned embodiment may be provided in the second area 802.

[0315] In some examples, such as Fig.23 As shown, the shading layers BSM corresponding to the first area 801, the second area 802, and the third area 803 can be interconnected as an integrated structure, and the shading layers BSM in adjacent circuit areas can be interconnected as an integrated structure, thereby forming a mesh-like integrated structure of the shading layer BSM in the entire display substrate.

[0316] Fig.24 is another schematic diagram of a light shielding layer according to at least one embodiment of the present disclosure. Fig.24As shown, the shading layers in adjacent circuit areas 81a and 81b can be connected through a third conductive connection portion D3. The third conductive connection portion D3 can be roughly a trace extending along the second direction Y. The third conductive connection portion D3 can be connected to the shading layer BSM in the first area of ​​the circuit area to achieve signal transmission of the shading layer BSM in the second direction Y. The shading layers in the first area, the second area and the third area of ​​each circuit area can be an integrated structure connected to each other. For example, the third conductive connection portion D3 can be located in the fifth conductive layer. The shading layer arrangement of this example can reduce the ESD risk that may be generated by the whole-surface connection of the shading layer BSM in multiple shift register circuits. The relevant description of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0317] This embodiment provides a display substrate, including: a substrate and a gate drive circuit disposed on the substrate. The gate drive circuit includes a multi-stage shift register circuit, and the shift register circuit includes an oxide output transistor (e.g. Figure 1 The twentieth transistor T20 in the embodiment of the present invention) and a plurality of oxide switch transistors (for example, including Figure 1 The third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the thirteenth transistor T13, the fifteenth transistor T15, the eighteenth transistor T18, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-sixth transistor T26 and the twenty-eighth transistor T28 in the oxide output transistor. The oxide output transistor includes a first bottom gate layer (for example, the bottom gate 520 of the twentieth transistor T20), a first top gate layer (for example, the top gate 220 of the twentieth transistor T20), and an active layer at least partially located between the first bottom gate layer and the first top gate layer (for example, the active layer 320 of the twentieth transistor T20). The oxide switching transistor includes a second bottom gate layer, a second top gate layer, and an active layer at least partially located between the second bottom gate layer and the second top gate layer. The first bottom gate layer and the second bottom gate layer are independent of each other; the first bottom gate layer and the first top gate layer are coupled; the second bottom gate layers of at least some of the oxide switching transistors in the plurality of oxide switching transistors are coupled.

[0318] In some examples, the first bottom gate layer and the second bottom gate layer are independent of each other, and the first bottom gate layer and the second bottom gate layer can be connected to the same or different signals. The first bottom gate layer is coupled to the first top gate layer, and the first bottom gate layer and the first top gate layer are connected to the same signal. The second bottom gate layers of at least some of the oxide switch transistors in the plurality of oxide switch transistors are coupled, and the coupled second bottom gate layers are connected to the same signal.

[0319] In some examples, the first bottom gate layer in the oxide output transistor and the second bottom gate layer in the oxide switch transistor are both arranged in the same layer and the same material as the second gate metal layer (i.e., the aforementioned second conductive layer). The first top gate layer in the oxide output transistor and the second top gate layer in the oxide switch transistor are both arranged in the same layer and the same material as the third gate metal layer (i.e., the aforementioned third conductive layer). The active layer in the oxide output transistor and the active layer in the oxide switch transistor are both arranged in the same layer and the same material as the oxide active layer (i.e., the aforementioned second semiconductor layer).

[0320] In the display substrate provided in this embodiment, a shift register circuit is provided, including an oxide output transistor and a plurality of oxide switching transistors. The oxide transistor has the property of low power consumption, and the shift register circuit can realize local refresh, that is, a part of the screen area (for example: the animation area) displays high-frequency refresh, and another part of the screen area (for example: the text area) displays low-frequency refresh, thereby effectively reducing the power consumption of the display substrate.

[0321] In the display substrate provided in the present embodiment, the first bottom gate layer of the oxide output transistor is coupled to the first top gate layer, so that the first bottom gate layer and the first top gate layer of the oxide output transistor can write the same control signal (for example, the signal conducted by other transistors), and simultaneously control the on or off state of the oxide output transistor; moreover, the first bottom gate layer of the oxide output transistor and the second bottom gate layer of the oxide switching transistor are set to be independent of each other, so that the oxide switching transistor and the oxide output transistor can be separately and independently controlled, which can ensure that the oxide switching transistor and the oxide output transistor do not interfere with each other, thereby improving the stability of the driving signal output by the shift register circuit in the display substrate.

[0322] In the display substrate provided in this embodiment, by setting the second bottom gate layers of at least some of the oxide switch transistors in the multiple oxide switch transistors to be coupled and connected to the same signal, the characteristics of at least some of the oxide switch transistors can be adjusted at the same time to achieve better transistor performance. Moreover, the above-mentioned setting method can only set one signal line, that is, it can provide signals to all the second bottom gate layers included in at least some of the oxide switch transistors, which is conducive to reducing the complexity of the shift register circuit, and thus reducing the layout difficulty of the display substrate. Moreover, the second top gate layers of the multiple oxide switch transistors are set to be independent of each other, and the conduction or cutoff of the oxide switch transistor can be controlled by the second top gate layer of the oxide switch transistor, which can ensure the normal working performance of the shift register circuit.

[0323] In some exemplary embodiments, all second bottom gate layers included in multiple oxide switch transistors may be coupled. The configuration of this example may adjust the characteristics of all oxide switch transistors at the same time to achieve better transistor performance. Moreover, the configuration of this example may only set one signal line, that is, it may provide signals to all second bottom gate layers included in all oxide switch transistors, which is beneficial to reduce the complexity of the shift register circuit, thereby reducing the layout difficulty of the display substrate. Moreover, the second top gate layers of multiple oxide switch transistors are set to be independent of each other, and the conduction or cutoff of the oxide switch transistor may be controlled by the second top gate layer of the oxide switch transistor, which may ensure the normal working performance of the shift register circuit.

[0324] In some exemplary embodiments, the plurality of oxide switch transistors may be divided into at least two transistor groups. Each transistor group may include at least one oxide switch transistor. The second bottom gate layers of the plurality of oxide switch transistors belonging to the same transistor group may be coupled. The second bottom gate layers of the oxide switch transistors belonging to different transistor groups may be independent of each other.

[0325] In some examples, the shift register circuit may include multiple functional modules, and the oxide switch transistors in the same functional module may be divided into the same transistor group. The functional module may include a NOT gate series structure, a parallel structure, or a series-parallel structure. This embodiment is not limited to this.

[0326] In some examples, the second bottom gate layers in the same transistor group are connected to the same signal, and the second bottom gate layers in different transistor groups are connected to different signals. Figure 1As shown, the output ends of the first NOT gate circuit and the second NOT gate circuit are connected, and the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 can be divided into a transistor group. The third NOT gate circuit forms a NOT gate series structure with the first NOT gate circuit, and the third NOT gate circuit forms a NOT gate series structure with the second NOT gate circuit, so that the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9 and the tenth transistor T10 can be divided into a transistor group. The fifth NOT gate circuit forms a NOT gate series structure with the sixth NOT gate circuit, and the twelfth transistor T12 and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 can be divided into a transistor group. The twenty-seventh transistor T27 and the twenty-eighth transistor T28 of the fourth NOT gate circuit can be divided into a transistor group. The seventeenth transistor T17 and the eighteenth transistor T18 can form a gating circuit and can be divided into a transistor group. The twenty-fifth transistor T25 and the twenty-sixth transistor T26 can form a transmission gate structure and can be divided into a transistor group. The twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23 and the twenty-fourth transistor T24 form a NAND gate circuit and can be divided into a transistor group. The first transistor T1, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the eleventh transistor T11 and the sixteenth transistor T16 are all independent transistors that act as switches. In this example, by coupling the second bottom gate layers of the oxide switch transistors belonging to the same functional module and connecting the same signal, characteristic adjustment can be achieved at the same time to achieve better transistor performance; moreover, the above-mentioned setting method can make the characteristics of the oxide switch transistors belonging to different functional modules independently adjustable.

[0327] In some exemplary embodiments, the second bottom gate layer included in the oxide switch transistor in at least some of the oxide switch transistors may extend along the first direction or the second direction, and the first direction intersects the second direction, for example, the first direction is perpendicular to the second direction. The display substrate may also include: at least one bottom gate connection portion, the bottom gate connection portion is coupled to the second bottom gate layer included in the corresponding oxide switch transistor. For example, the display substrate may include a first bottom gate connection portion 601 and a second bottom gate connection portion 602. The arrangement of this example can ensure that the bottom gate connection portion couples the second bottom gate layers included in the corresponding multiple oxide switch transistors, and is also conducive to reducing the layout difficulty of the shift register circuit.

[0328] In some exemplary embodiments, at least some of the oxide switch transistors may be divided into a first transistor group and a second transistor group. The display substrate includes a first bottom gate connection portion 601 and a second bottom gate connection portion 602, and the first bottom gate connection portion 600 may be connected to a second bottom gate layer (e.g., Fig.14 The bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 57 of the seventh transistor T7, the bottom gate 58 of the eighth transistor T8, the bottom gate 510 of the tenth transistor T10, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 523 of the twenty-third transistor T23, and the bottom gate 528 of the twenty-eighth transistor T28 are coupled, and the second bottom gate connection portion 602 can be coupled to the second bottom gate layer (e.g., Fig.14 The bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, the bottom gate 524 of the twenty-fourth transistor T24, and the bottom gate 526 of the twenty-sixth transistor T26 are coupled. The first bottom gate connection portion 601 and the second bottom gate connection portion 602 can be connected through the first conductive connection portion D1 (such as Fig.14 shown) coupling.

[0329] In some examples, the first bottom gate connection portion 601 and the second bottom gate layer coupled thereto may be an integral structure connected to each other, and the second bottom gate connection portion 602 and the second bottom gate layer coupled thereto may be an integral structure connected to each other. The first bottom gate connection portion 601 and the second bottom gate connection portion 602 may be provided in the same layer and the same material, and the first bottom gate connection portion 601 and the first conductive connection portion D1 may be provided in different layers. For example, the first bottom gate connection portion 601 may be located in the second gate metal layer (i.e., the aforementioned second conductive layer), and the first conductive connection portion D1 may be located in the first source-drain metal layer (i.e., the aforementioned fourth conductive layer). In some examples, the orthographic projection of the second bottom gate layer on the substrate may not overlap with the orthographic projection of the first gate metal layer (i.e., the aforementioned first conductive layer) on the substrate, and the orthographic projection of the first conductive connection portion D1 on the substrate may overlap with the orthographic projection of the first gate metal layer on the substrate.

[0330] In some exemplary embodiments, at least some of the oxide switch transistors may be divided into a first transistor group and a second transistor group. The display substrate may include a first bottom gate connection portion 601 and a second bottom gate connection portion 602. The first bottom gate connection portion 601 is connected to a second bottom gate layer (e.g., Fig.22AThe bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 57 of the seventh transistor T7, the bottom gate 58 of the eighth transistor T8, the bottom gate 510 of the tenth transistor T10, the bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 526 of the twenty-sixth transistor T26, and the bottom gate 528 of the twenty-eighth transistor T28 are coupled to the second bottom gate connection portion 602 and the second bottom gate layer (e.g., the oxide switch transistors in the second transistor group) included in the second transistor group. Fig.22A The bottom gate 523 of the twenty-third transistor T23 is coupled to the bottom gate 524 of the twenty-fourth transistor T24. The first bottom gate connection portion 601 and the second bottom gate connection portion 602 may be independent of each other.

[0331] In some examples, when the first bottom gate connection portion 601 and the second bottom gate connection portion 602 are independent of each other, the display substrate may further include a first signal line (ie, Fig.21 and Fig. 22C The ninth transmission line 719 shown) and the second signal line (ie Fig.21 and Fig. 22C The seventh transmission line 717 is shown. The first signal line is coupled to the first bottom gate connection portion 601 and is configured to provide a first signal to the first bottom gate connection portion 601; the second signal line is coupled to the second bottom gate connection portion 602 and is configured to provide a second signal to the second bottom gate connection portion 602. The method of this example can achieve independent adjustment of the characteristics of the oxide switch transistors in different transistor groups.

[0332] In some exemplary embodiments, in two adjacent shift register circuits, the second bottom gate layer of the oxide switch transistor in the previous shift register circuit and the second bottom gate layer of the oxide switch transistor in the next shift register circuit can be independent of each other. The configuration of this example can realize independent control of the second bottom gate layers in the two adjacent shift register circuits.

[0333] In some exemplary embodiments, in two adjacent shift register circuits, the second bottom gate layer of at least part of the oxide switch transistors in the previous shift register circuit can be coupled to the second bottom gate layer of at least part of the oxide switch transistors in the next shift register circuit. In the configuration of this example, the voltage signal of the second bottom gate layer can be connected to the lower frame area of ​​the display substrate. For example, Fig. 20 As shown, the second bottom gate layer of at least part of the oxide switch transistor in the previous stage shift register circuit and the second bottom gate layer of at least part of the oxide switch transistor in the next stage shift register circuit can form an integrated structure. Fig. 20As shown, the second bottom gate layer of at least part of the oxide switch transistors in the previous stage shift register circuit and the second bottom gate layer of at least part of the oxide switch transistors in the next stage shift register circuit are both arranged in the same layer and the same material as the second gate metal layer in the display substrate. The arrangement of this example does not require additional drilling, which can simplify the manufacturing process.

[0334] In some exemplary embodiments, the second bottom gate layer of at least part of the oxide switch transistor in the previous stage shift register circuit and the second bottom gate layer of at least part of the oxide switch transistor in the next stage shift register circuit can be connected through the second conductive connection portion (i.e. Fig.19 The second conductive connection portion is coupled to the seventh transmission line 717 shown in the figure, and the second conductive connection portion is arranged in a different layer from the second bottom gate layer. In some examples, in the previous stage shift register circuit, the positive projection of the second conductive connection portion on the substrate is aligned with the first transfer pattern (i.e. Fig.19 The orthographic projection of the fourteenth conductive connection portion D14 shown on the substrate has an overlapping area, in which the second conductive connection portion is coupled to the first transfer pattern through a via; the orthographic projection of the first transfer pattern on the substrate has an overlapping area with the orthographic projection of the bottom gate connection portion in the previous stage shift register circuit on the substrate, in which the first transfer pattern is coupled to the bottom gate connection portion in the previous stage shift register circuit through a via. In some examples, the second conductive connection portion may be located in the second source-drain metal layer (i.e., the aforementioned fifth conductive layer). This example can reduce the risk of electrostatic discharge (ESD, Electro-Static Discharge) that may be generated by the full-surface connection of the second bottom gate layer in multiple shift register circuits by setting the second bottom gate layer of at least part of the oxide switching transistor in the previous stage shift register circuit to be coupled to the second bottom gate layer of at least part of the oxide switching transistor in the next stage shift register circuit through the second conductive connection portion.

[0335] In some exemplary embodiments, the shift register circuit may further include: a light shielding layer BSM (eg Fig.23 and Fig.24 as shown), and a plurality of low temperature polysilicon transistors (eg including Figure 1 The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the fourteenth transistor T14, the sixteenth transistor T16, the seventeenth transistor T17, the nineteenth transistor T19, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-fifth transistor T25 and the twenty-seventh transistor T27 are shown). The orthographic projection of the light shielding layer BSM on the substrate may at least partially overlap with the orthographic projection of the active layer of the low-temperature polysilicon transistor on the substrate. At least part of the shift register circuit (e.g. Fig.23The light shielding layer BSM of the shift register circuit provided in the middle circuit regions 81a and 81b is coupled.

[0336] In some examples, at least a portion of the light shielding layer BSM of the shift register circuit can be connected to the light shielding layer BSM through the third conductive connection portion D3 (eg, Fig.24 ) is coupled, and the third conductive connection portion D3 can be arranged in a different layer from the light shielding layer BSM. For example, the thirteenth conductive connection portion D3 can be located in the fifth conductive layer. In some examples, the shift register circuit may further include a second transfer pattern, in the previous stage shift register circuit, the orthographic projection of the third conductive connection portion D3 on the substrate has an overlapping area with the orthographic projection of the second transfer pattern on the substrate, and in this overlapping area, the third conductive connection portion D3 and the second transfer pattern are coupled through a via; the orthographic projection of the second transfer pattern on the substrate has an overlapping area with the orthographic projection of the light shielding layer BSM in the previous stage shift register circuit on the substrate, and in this overlapping area, the second transfer pattern is coupled to the light shielding layer BSM in the previous stage shift register circuit through a via. In this example, by setting the light shielding layer BSM of at least part of the shift register circuit to be coupled through the third conductive connection portion, and the third conductive connection portion D3 and the light shielding layer BSM are arranged in different layers, the ESD risk that may be generated by the full-surface connection of the light shielding layer BSM in multiple shift register circuits can be reduced.

[0337] The relevant descriptions about the display substrate of this embodiment can refer to the descriptions of the aforementioned embodiments, and thus will not be repeated here.

[0338] The present embodiment also provides a driving method for a display substrate, which is used to drive the display substrate as described above, and the driving method includes: providing the same signal to the first bottom gate layer and the first top gate layer to control the oxide output transistor to be turned on or off; independently providing signals to the second bottom gate layer and the second top gate layer of the oxide switching transistor, wherein the second bottom gate layers of at least some of the oxide switching transistors among the multiple oxide switching transistors are coupled to receive the same signal.

[0339] By using the driving method provided in this embodiment to drive the display substrate, the same control signal can be written into the first bottom gate layer and the first top gate layer of the oxide output transistor, and the on or off of the oxide output transistor can be controlled at the same time; moreover, the first bottom gate layer and the second bottom gate layer are set to be independent of each other, so that the oxide switching transistor and the oxide output transistor can be controlled separately and independently, thereby ensuring that the oxide switching transistor and the oxide output transistor do not interfere with each other, and improving the stability of the driving signal output by the shift register circuit in the display substrate. Moreover, by using the driving method provided in this embodiment to drive the display substrate, the characteristics of at least part of the oxide switching transistor can be adjusted at the same time to achieve better transistor performance. The rest of the description of this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0340] Fig.25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.25 As shown, this embodiment provides a display device 91, including a display substrate 910. The display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be: an OLED display device, a watch, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. However, this embodiment is not limited to this.

[0341] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures can refer to the usual design. In the absence of conflict, the embodiments of the present disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the forms and details of implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A substrate and a gate driving circuit arranged on the substrate, wherein the gate driving circuit comprises: a plurality of cascaded shift register circuits, the shift register circuit comprises: a plurality of NOT gate circuits, the NOT gate circuit comprises: a first control transistor and a second control transistor, the first control transistor and the second control transistor are of different transistor types; the gate of the first control transistor is connected to the gate of the second control transistor, serving as the first input terminal of the NOT gate circuit; the second electrode of the first control transistor is connected to the second electrode of the second control transistor, serving as the output terminal of the NOT gate circuit; the first electrode of the first control transistor serves as the second input terminal of the NOT gate circuit; the first electrode of the second control transistor serves as the third input terminal of the NOT gate circuit, the second input terminal and the third input terminal of the NOT gate circuit are configured to access different voltage signals; and the transistor arrangement modes of at least two NOT gate circuits among the plurality of NOT gate circuits of the shift register circuit are different.

2. The display substrate according to claim 1, characterized in that: At least one NOT gate circuit among the plurality of NOT gate circuits satisfies one of the following: The active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit extend in the same direction, and the arrangement direction of the first control transistor and the second control transistor is the same as the extending direction of the active layer; The active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit have the same extension direction, and the arrangement direction of the first control transistor and the second control transistor intersects with the extension direction of the active layer; The extension directions of the active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit intersect, and the arrangement direction of the first control transistor and the second control transistor is the same as the extension direction of the active layer of the first control transistor or the second control transistor.

3. The display substrate according to claim 1, characterized in that: The multiple NOT gate circuits at least include: a first NOT gate circuit and a second NOT gate circuit; the output end of the first NOT gate circuit is connected to the output end of the second NOT gate circuit; the first NOT gate circuit and the second NOT gate circuit are adjacent in the second direction; the transistor arrangement method of the first NOT gate circuit is the same as the transistor arrangement method of the second NOT gate circuit; the active layer of the first control transistor of the first NOT gate circuit and the active layer of the first control transistor of the second NOT gate circuit are an integrated structure connected to each other.

4. The display substrate according to claim 3, characterized in that: The second input terminal of the first NOT gate circuit is connected to the first voltage line through a first transmission transistor, the second input terminal of the second NOT gate circuit is connected to the first voltage line through a second transmission transistor, and the first transmission transistor, the second transmission transistor and the first control transistor are of the same transistor type; The first control transistor of the first NOT gate circuit, the first control transistor of the second NOT gate circuit, the first transfer transistor and the active layers of the second transfer transistor are interconnected as an integrated structure, and the orthographic projection shape of the integrated structure on the substrate is C-shaped or ring-shaped.

5. The display substrate according to claim 4, characterized in that: The third input terminal of the first NOT gate circuit is connected to the second voltage line through a third transmission transistor, the third input terminal of the second NOT gate circuit is connected to the second voltage line through a fourth transmission transistor, and the third transmission transistor, the fourth transmission transistor and the second control transistor are of the same transistor type; A gate of the third transfer transistor is connected to a gate of the second transfer transistor, and a gate of the fourth transfer transistor is connected to a gate of the first transfer transistor; The active layer of the second control transistor of the first NOT gate circuit and the active layer of the third transfer transistor are interconnected as an integrated structure; the active layer of the second control transistor of the second NOT gate circuit and the active layer of the fourth transfer transistor are interconnected as an integrated structure.

6. The display substrate according to any one of claims 3 to 5, characterized in that: The plurality of NOT gate circuits further include: a third NOT gate circuit, a first input terminal of the third NOT gate circuit being connected to output terminals of the first NOT gate circuit and the second NOT gate circuit, and an output terminal of the third NOT gate circuit being connected to a first input terminal of the second NOT gate circuit; The third NOT gate circuit is adjacent to the second NOT gate circuit in the second direction; and a transistor arrangement mode of the third NOT gate circuit is the same as a transistor arrangement mode of the second NOT gate circuit.

7. The display substrate according to claim 6, characterized in that: The first input terminal of the third NOT gate circuit is connected to an integrated structure of an active layer of a first control transistor of the first NOT gate circuit and a first control transistor of the second NOT gate circuit.

8. The display substrate according to claim 6, characterized in that: The second electrode of the first control transistor and the second electrode of the second control transistor of the third NOT gate circuit are connected to the gate of the first control transistor of the second NOT gate circuit through different conductive connecting parts, and the gate of the second control transistor of the second NOT gate circuit and the second electrode of the second control transistor of the third NOT gate circuit are connected to the gate of the first control transistor of the second NOT gate circuit through the same conductive connecting part.

9. The display substrate according to claim 4, characterized in that: The plurality of NOT gate circuits further include: a fourth NOT gate circuit; a first input terminal of the fourth NOT gate circuit is connected to the gate of the second transmission transistor, and an output terminal of the fourth NOT gate circuit is connected to the gate of the first transmission transistor; a transistor arrangement mode of the fourth NOT gate circuit is different from a transistor arrangement mode of the first NOT gate circuit and a transistor arrangement mode of the second NOT gate circuit; The fourth NOT gate circuit is located on the same side of the first NOT gate circuit and the second NOT gate circuit in a first direction; the first direction intersects the second direction.

10. The display substrate according to claim 9, characterized in that: The first input end of the fourth NOT gate circuit of the 2i-1th level shift register circuit of the gate drive circuit is connected to the first clock signal line, and the first input end of the fourth NOT gate circuit of the 2ith level shift register circuit of the gate drive circuit is connected to the second clock signal line, where i is an integer greater than 0.

11. The display substrate according to claim 1, characterized in that: The shift register circuit further includes: a NAND gate circuit; the NAND gate circuit is connected to at least one NOT gate circuit; The NAND gate circuit includes: a third control transistor, a fourth control transistor, a fifth control transistor and a sixth control transistor; the third control transistor and the fourth control transistor are of the same transistor type, and the fifth control transistor and the sixth control transistor are of the same transistor type; The gates of the third control transistor and the fifth control transistor are connected as the first input terminal of the NAND gate circuit; the gates of the fourth control transistor and the sixth control transistor are connected as the second input terminal of the NAND gate circuit; the first electrode of the third control transistor and the first electrode of the fourth control transistor are connected as the third input terminal of the NAND gate circuit; the second electrode of the third control transistor, the second electrode of the fourth control transistor and the second electrode of the fifth control transistor are connected as the output terminal of the NAND gate circuit; the first electrode of the fifth control transistor is connected to the second electrode of the sixth control transistor; the first electrode of the sixth control transistor serves as the fourth input terminal of the NAND gate circuit; the third input terminal and the fourth input terminal of the NAND gate circuit are configured to access different voltage signals; The third control transistor and the fourth control transistor are located between the fifth control transistor and the sixth control transistor.

12. The display substrate according to claim 11, characterized in that: The sixth control transistor, the fourth control transistor, the third control transistor and the fifth control transistor are arranged in sequence along the second direction; the gate of the sixth control transistor, the gate of the fourth control transistor, the gate of the third control transistor and the gate of the fifth control transistor are arranged alternately in the second direction.

13. The display substrate according to claim 11, characterized in that: The active layer of the third control transistor and the active layer of the fourth control transistor are an integrated structure connected to each other, and the orthographic projection shape of the integrated structure on the substrate is C-shaped or ring-shaped.

14. The display substrate according to claim 11, characterized in that: The plurality of NOT gate circuits include: a fifth NOT gate circuit and a sixth NOT gate circuit; The input end of the sixth NOT gate circuit is connected to the output end of the fifth NOT gate circuit, and the output end of the sixth NOT gate circuit is connected to the second input end of the NAND gate circuit; The fifth NOT gate circuit is adjacent to the sixth NOT gate circuit in the first direction; the fifth NOT gate circuit and the sixth NOT gate circuit are located on the same side of the NAND gate circuit in the second direction; the first direction intersects the second direction; The transistor arrangement of the fifth NOT gate circuit is the same as the transistor arrangement of the sixth NOT gate circuit.

15. The display substrate according to claim 14, characterized in that: The first control transistor of the fifth NOT gate circuit and the first control transistor of the sixth NOT gate circuit are aligned in the first direction, and the second control transistor of the fifth NOT gate circuit and the second control transistor of the sixth NOT gate circuit are aligned in the first direction.

16. The display substrate according to claim 11, characterized in that: The plurality of NOT gate circuits further include: a seventh NOT gate circuit; The input end of the seventh NOT gate circuit is connected to the output end of the NAND gate circuit, and the output end of the seventh NOT gate circuit serves as the driving output end of the shift register circuit; The first control transistor and the second control transistor of the seventh NOT gate circuit are arranged along a second direction, the first control transistor is adjacent to the NAND gate circuit in the first direction, and the first direction intersects the second direction.

17. The display substrate according to claim 1, characterized in that: The shift register circuit at least comprises: a cascade signal generating circuit, a gating circuit, a voltage maintaining circuit, an output control circuit and an output circuit; the cascade signal generating circuit comprises at least one NOT gate circuit, the output circuit comprises at least one NOT gate circuit, the voltage maintaining circuit comprises at least one NOT gate circuit, and the output control circuit comprises a NAND gate circuit; The cascade signal generating circuit is connected to the cascade input terminal and the cascade output terminal, and is configured to perform a shift operation on the cascade signal provided by the previous stage shift register circuit received by the cascade input terminal, and provide the cascade signal of the current stage shift register circuit to the cascade output terminal; The gating circuit is connected to the gating input terminal, the cascade input terminal, the cascade output terminal and the third node, and is configured to write the gating input signal provided by the gating input terminal into the third node under the control of the cascade output terminal and the cascade input terminal; The voltage maintaining circuit is connected to the third node, the cascade input terminal, the clock signal terminal and the fifth node, and is configured to control the potential of the fifth node under the control of the third node, the cascade input terminal and the clock signal terminal; The output control circuit is connected to the cascade output terminal, the fifth node and the sixth node, and is configured to perform a NAND operation on the potentials of the cascade output terminal and the fifth node to control the potential of the sixth node; The output circuit is connected to the sixth node and the driving output terminal, and is configured to perform an inverting operation on the potential of the sixth node and output a driving signal; The output control circuit is located between the cascade signal generating circuit and the output circuit in the first direction, the selection circuit is adjacent to the cascade signal generating circuit in the second direction, the voltage maintaining circuit is located between the selection circuit and the output circuit in the first direction and adjacent to the output control circuit in the second direction; the first direction intersects with the second direction.

18. The display substrate according to claim 17, characterized in that: The shift register circuit further includes: an initialization circuit, the initialization circuit being connected to the initial control terminal, the third node and the cascade output terminal, and configured to initialize the third node and the cascade output terminal under the control of the initial control terminal; The initialization circuit is located at a side of the gating circuit away from the voltage maintaining circuit in the first direction, and is adjacent to the cascade signal generating circuit in the second direction.

19. The display substrate according to claim 17, characterized in that: The gating circuit comprises: a seventeenth transistor and an eighteenth transistor; the seventeenth transistor and the eighteenth transistor are of different transistor types; The gate of the seventeenth transistor is connected to the cascade output terminal, the first electrode of the seventeenth transistor is connected to the selection input terminal, and the second electrode of the seventeenth transistor is connected to the first electrode of the eighteenth transistor; the gate of the eighteenth transistor is connected to the cascade input terminal, and the second electrode of the eighteenth transistor is connected to the third node; The seventeenth transistor and the eighteenth transistor are arranged in sequence along the second direction, and the eighteenth transistor is adjacent to the cascade signal generating circuit in the second direction.

20. The display substrate according to claim 1, characterized in that: The first control transistor is a low temperature polysilicon transistor, and the second control transistor is an oxide transistor.

21. The display substrate according to claim 20, characterized in that: In a direction perpendicular to the display substrate, the display substrate comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged on the base; The first semiconductor layer at least includes: an active layer of the first control transistor; The first conductive layer at least includes: a gate of the first control transistor; The second conductive layer at least includes: a bottom gate of the second control transistor; The second semiconductor layer at least includes: an active layer of the second control transistor; The third conductive layer at least includes: a top gate of the second control transistor; The fourth conductive layer at least includes: a plurality of conductive connection parts connected to the first control transistor and the second control transistor; The fifth conductive layer at least includes: a signal line connected to the shift register circuit.

22. The display substrate according to claim 20, characterized in that: The shift register circuit includes a plurality of oxide transistors, and the plurality of oxide transistors include: an oxide output transistor and a plurality of oxide switch transistors; the oxide output transistor is connected to a driving output terminal; The bottom gate of the oxide output transistor is independently arranged from the bottom gates of the plurality of oxide switch transistors, and the bottom gate of the oxide output transistor is connected to the top gate; The bottom gates of at least some of the oxide switching transistors are interconnected as an integrated structure.

23. A display device, characterized in that: Comprising the display substrate as claimed in any one of claims 1 to 22.

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