Open circuit detection method and system based on MBI5034 chip, medium, program and electronic terminal

Abstract

The invention provides an open circuit detection method and system based on an MBI5034 chip, a medium, a program and an electronic terminal, and the method comprises the steps: building a mapping relation between each brightness level and display lightening duration in a frame of image through employing a binary rule, and enabling each brightness level to have display turn-off time in a refresh cycle; setting the display turn-off time corresponding to all the brightness levels at the tail end of the refresh cycle; the image data updating operation is executed at the tail end of the last refresh cycle, the open circuit detection triggering action is executed at the starting end of the current refresh cycle, and the image display operation is executed after the open circuit detection is triggered, so that the image data updated in the last refresh cycle is displayed, and the black screen phenomenon caused by open circuit detection is eliminated.

Description

Technical Field

[0001] The present application relates to the field of display control, and in particular to an open circuit detection method, medium, program, electronic terminal and system based on an MBI5034 chip. Background Art

[0002] MBI5034 is a multi-channel constant current LED driver chip with advanced error detection and current gain functions. It can provide uniform and stable current to drive LEDs, ensuring the uniformity and stability of the display effect. It is widely used in the field of display screens, especially display screen products in the field of outdoor transportation. In addition, the chip has the function of forced open circuit detection, which can perform open circuit detection without the need for other components. In electronic circuit systems, open circuits are a common type of fault. In circuit systems using MBI5034 chips, open circuits may occur due to various reasons, such as disconnected wires, loose solder joints, and poor contact of component pins. The open circuit detection function can quickly and accurately determine whether there is such a problem in the circuit, so that repairs can be made in a timely manner. For example, in the driver circuit of an LED display, if an open circuit occurs in the connection of a certain LED, the open circuit detection of MBI5034 can quickly detect the fault. Open circuit detection to check the fault of LED display screen is very important to improve the stability and reliability of the system, especially for highway information board products. Due to the distribution characteristics of highways, it is impossible for managers to frequently monitor the information board displays on various highways. Therefore, the display screen needs to be able to detect bad pixels on the screen and report them, so that the staff can obtain the damage status of the display screens on each section in the control center. When the damage is serious, it is necessary to report for inspection and maintenance.

[0003] The working principle of MBI5034 chip for open circuit detection is as follows Figure 1As shown, CLK is the abbreviation of Clock, that is, the clock signal pin, which is used to provide data synchronization clock for the chip. During data transmission, the reading, writing and execution of various operations of data need to be synchronized with the rising or falling edge of the clock signal to ensure the accuracy and stability of the data. LE is the abbreviation of Latch Enable, that is, the latch enable pin, which is used to control the latching operation of data. When the LE pin receives a specific level signal (usually a high or low level pulse signal), the chip will latch the data previously input through other pins into the internal register or buffer for subsequent processing and output. OE is the abbreviation of Output Enable, that is, the output enable pin, which is used to control the opening and closing of the chip data output channel. When the OE pin is high, the output of the chip is disabled and the current will not be conducted from the output pin of the chip; when the OE pin is low, the output of the chip is enabled, and the output pin can conduct current to drive external loads (such as LEDs, etc.). The open circuit detection of MBI5034 chip is completed by the cooperation of three signals, OE, CLK and LE. Specifically, the process of open circuit detection can be divided into two stages, one is the trigger detection stage, and the other is the stage of reading back the detection data. The defect of open circuit detection exists in the trigger detection stage. Since the trigger detection operation is incompatible with the image data update timing (the read-back detection data operation is compatible with the image data update timing), during the trigger detection process, the OE signal always maintains a high level. In this high level state, the chip's drive channel is closed, and the current used to drive the load LED is cut off. After the LE falling edge, although OE is at a high level at this time, the chip allows a weak current to flow through the drive port to drive the external LED for open circuit detection, and this weak current can generate a voltage at the drive port for the chip to detect whether the external load exists, but it is not enough to light up the LED. Therefore, during the high level period of OE after the LE falling edge, the display screen will suddenly go black and flash. This screen flickering phenomenon is a defect of the open circuit detection of the MBI5034 chip. Although the screen flickering time of the MBI5034 is very short when performing open circuit detection, in certain specific situations, such as video content with high contrast or pure color background, fast dynamic scenes or long static images, this short black screen time will also have a great impact on the display effect. Many display screen users do not want this black screen situation to occur.

[0004] In the prior art, one frame of image is usually displayed in one scanning cycle, and the brightness is controlled by controlling the display duty cycle in one scanning cycle, that is, the longer the OE high level time in the same cycle, the lower the visual brightness; the longer the OE low level time, the higher the visual brightness. The display controller controls the data update of all driver chips in one scanning cycle. Therefore, the following two solutions are usually used to minimize the impact of the above black screen condition:

[0005] Solution 1: In each scanning cycle, set the OE to be turned off for about 1us. This solution will cause the overall brightness of the display to be lower due to the visual persistence phenomenon of the human eye. In addition, the shorter the scanning cycle, the lower the brightness because the percentage of 1us time in the entire scanning time (display duty cycle) increases. Brightness is a key indicator of the display, and this solution sacrifices a lot of the brightness of the display.

[0006] Solution 2: Perform open circuit detection when the screen brightness is low, so that most of the time in the scanning cycle is in the OE high level state, and open circuit detection in the OE high level state does not need to sacrifice the original brightness. However, this solution must perform open circuit detection when the brightness is low, which will delay the detection and repair of faults in many scenarios and may bring potential risks in emergency situations.

[0007] In summary, the problem existing in the prior art is that the open circuit detection solution provided cannot eliminate the screen flickering phenomenon caused by the open circuit detection of the MBI5034 chip while ensuring normal display brightness or preventing fault detection from being delayed. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, the purpose of this application is to provide an open circuit detection method, medium, program, electronic terminal and system based on the MBI5034 chip to solve the above-mentioned problems in the prior art.

[0009] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides an open circuit detection method based on the MBI5034 chip, which performs grayscale scanning on the display screen, including: setting the number of grayscale levels to n, then each pixel has a total of 2 n brightness levels, each brightness level corresponds to a different display lighting duration in a refresh cycle; a mapping relationship between each brightness level and the display lighting duration is established using a binary rule, and each brightness level has a display off time in the refresh cycle; the display off times corresponding to all brightness levels are set at the end of the refresh cycle; an image data update operation is performed at the end of the previous refresh cycle, and an open circuit detection trigger action is performed at the beginning of the current refresh cycle, and an image display operation is performed after the open circuit detection is triggered to display the image data updated in the previous refresh cycle.

[0010] In an embodiment of the first aspect of the present application, a mapping relationship between each brightness level and the display lighting duration is established using a binary rule, and a step of making each brightness level have a display off time within a refresh cycle includes: using an n-bit binary number to represent the display lighting duration corresponding to each brightness level, and the binary numbers from small to large correspond to the brightness levels from dark to bright; wherein each refresh cycle is evenly divided into x scanning cycles (x≥n), a corresponding number of scanning cycles are allocated to each bit of the binary number, and a corresponding display duty cycle is set for the scanning cycle allocated to each bit; and the display duty cycle corresponding to the lowest bit is less than 1, the product of the scanning cycle corresponding to each bit and the display duty cycle is the bit display duration of each bit, and the ratio of the bit display durations between each bit is equal to the ratio of its bit weights; then the display lighting duration corresponding to each brightness level is the sum of the display durations of each bit of the corresponding binary number.

[0011] In an embodiment of the first aspect of the present application, the number of scan cycles allocated to each bit decreases monotonically from high to low as the bit increases, and the display duty cycle allocated to each bit decreases monotonically as the bit decreases from high to low.

[0012] In an embodiment of the first aspect of the present application, the step of setting the display off time corresponding to all brightness levels at the end of the refresh cycle includes: starting from the starting end of the refresh cycle, allocating scanning cycles from high bit positions to low bit positions in sequence, and allocating the scanning cycle at the end of the refresh cycle to the lowest bit position.

[0013] In an embodiment of the first aspect of the present application, the number of scanning cycles allocated to the most significant bit is greater than or equal to 2.

[0014] In an embodiment of the first aspect of the present application, the image data update operation is performed at the end of the previous refresh cycle, and an open circuit detection trigger action is performed at the beginning of the current refresh cycle. After the open circuit detection trigger action is completed, an image display operation is performed to display the image data updated in the previous refresh cycle. The steps include: performing an image data update operation in the last scanning cycle of the previous refresh cycle; wherein the updated image data is the bit data displayed in the first scanning cycle of the next refresh cycle; performing an open circuit detection trigger at the beginning of the first scanning cycle of the current refresh cycle, and after the open circuit detection trigger ends, displaying the image data in the remaining time of the first scanning cycle; wherein the displayed image data is the image data updated in the last scanning cycle of the previous refresh cycle; within the first scanning cycle, no image data update is performed, and the image data that should have been updated within the first scanning cycle of the current refresh cycle is discarded.

[0015] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides an open circuit detection system based on the MBI5034 chip, including a display control module and a display screen, wherein the display control module includes the MBI5034 chip, and the display control module is used to execute any one of the methods described in the first aspect of the present application; the display screen is used to display the image data output by the control module.

[0016] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, it implements any one of the methods described in the first aspect of the present application.

[0017] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer implements any one of the methods described in the first aspect of the present application.

[0018] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement any one of the methods described in the first aspect of the present application.

[0019] As described above, the open circuit detection method, system, medium, program and electronic terminal based on the MBI5034 chip of the present application have the following beneficial effects:

[0020] This application performs grayscale scanning on the MBI5034 chip that does not have a pulse width modulation function, and uses binary rules to establish a mapping relationship between each brightness level and the display lighting duration, and makes each have a display off time in the refresh cycle; the display off time corresponding to all brightness levels is set at the end of the refresh cycle; the image data update operation is performed at the end of the previous refresh cycle, and the open circuit detection trigger action is performed at the beginning of the current refresh cycle, and the image display operation is performed after the open circuit detection is triggered to display the image data updated in the previous refresh cycle. Because for each brightness level, there is a period of display off at the end of each refresh cycle. In addition, when there is an irregular instantaneous display off in a refresh cycle of the display screen, if the display off duration reaches a certain degree, it can be captured by the human eye. The duration of the MBI5034 chip triggering the open circuit detection has reached the level that can be observed by the human eye. In addition, the triggering operation of the open circuit detection needs to temporarily turn off the display. If the display screen is in the display lighting state before the open circuit detection and the display screen is also in the display lighting state after the open circuit detection, the triggering operation of the open circuit detection will cause a black screen phenomenon that can be observed by the human eye for a moment. Therefore, setting the open circuit detection at the beginning of the current refresh cycle and leaving a period of display shutdown time at the end of the previous refresh cycle will eliminate the black screen phenomenon caused by the open circuit detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is the open circuit detection schematic of the MBI5034 chip.

[0022] Figure 2 The display is a schematic diagram of the distribution relationship between the bit position, the scanning period, and the display duty cycle in an embodiment of the present application. Figure 1 .

[0023] Figure 3 Displayed is a schematic diagram of the corresponding relationship between brightness levels and display lighting duration in one embodiment of the present application.

[0024] Figure 4 The display is a schematic diagram of the distribution relationship between the bit position, the scanning period, and the display duty cycle in an embodiment of the present application. Figure 2 .

[0025] Figure 5 The principle of open circuit detection in one embodiment of the present application is shown as follows Figure 1 .

[0026] Figure 6 The principle of open circuit detection in one embodiment of the present application is shown as follows Figure 2 .

[0027] Figure 7 Shown is a schematic diagram of an open circuit detection system in one embodiment of the present application.

[0028] Figure 8 Shown is a schematic diagram of the structure of an electronic terminal in one embodiment of the present application. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0030] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0031] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0032] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides an open circuit detection method based on the MBI5034 chip, which performs grayscale scanning on a display screen, including:

[0033] S1: Set the number of gray levels to n, then each pixel has 2 n There are 3 brightness levels, each brightness level corresponds to a different display lighting duration within the refresh cycle.

[0034] It should be understood that the refresh cycle refers to the display time of a frame of an image on the LED display screen, usually in milliseconds. This time determines how many times a frame of an image can be repeatedly displayed in one second. The refresh cycle is closely related to the refresh rate. The refresh cycle and the refresh frequency are reciprocal of each other. The refresh frequency refers to how many frames of images the display screen can display per second. For example, a refresh rate of 1000Hz means that each frame of an image can be displayed 1000 times per second. If the refresh rate is 1000Hz, then the refresh cycle T is 1 / 1000 second (1 millisecond). It should be understood that the display lighting duration refers to the length of time that the LED pixel is lit in a refresh cycle. By controlling the proportion of time that each pixel is lit in a refresh cycle, different gray levels (brightness levels) can be achieved. The display lighting duration is related to the display duty cycle (hereinafter referred to as "duty cycle"), which indicates the percentage of time that a pixel is lit in the entire refresh cycle. For example, if a pixel is lit for 50% of the time in the refresh cycle, its duty cycle is 50%, corresponding to medium brightness; if the lighting time is 80%, the brightness is higher.

[0035] It should be understood that the number of grayscale bits of a display usually refers to the number of binary bits used to control the brightness of each LED pixel, which determines the number of brightness levels that the display can display. The higher the number of grayscale bits, the more delicate the brightness of the LED display, the smoother the image, and the more natural the color gradient. The brightness level indicates the high and low brightness state of the LED pixel when it is lit. If the number of grayscale bits is n, then the LED display can have 2 n Specifically, 1-bit grayscale represents 2 brightness levels (on and off), 3-bit grayscale represents 8 brightness levels (from 0 to 7), 4-bit grayscale represents 16 brightness levels (from 0 to 15), 8-bit grayscale represents 256 brightness levels (from 0 to 255), 10-bit grayscale represents 1024 brightness levels, and 12-bit grayscale represents 4096 brightness levels.

[0036] Grayscale scanning achieves different grayscale levels by controlling the duration or intensity of the LED pixel's light emission, thereby producing different brightness. The core of this process is to use technical means to adjust the on and off time of each pixel so that the naked eye can perceive the change in brightness.

[0037] The usual implementation method of grayscale scanning of display screens is pulse width modulation (PWM). PWM simulates different brightness by controlling the ratio of the "on" and "off" time of each LED pixel in a fixed time cycle. In a time cycle, when the length of the switching time of the LED is different, due to the phenomenon of visual persistence, the brightness of the LED observed by the human eye will be different. Therefore, by sending a pulse width modulation waveform, the proportion of the LED lighting time in a time cycle to the entire cycle (duty cycle) is adjusted to achieve different brightness levels. The larger the duty cycle of the pulse width modulation waveform, the longer the LED is lit and the higher the brightness; the smaller the duty cycle, the shorter the LED is lit and the lower the brightness. For example, when the length of a time cycle is 10ms, a 100% duty cycle means that the LED is always on for 10 milliseconds, reaching the maximum brightness; a 50% duty cycle means that the LED is on for 5 milliseconds and off for 5 milliseconds in 10 milliseconds, reaching a medium brightness; a 10% duty cycle means that the LED is only on for 1 millisecond and off for 9 milliseconds in 10 milliseconds, with a lower brightness.

[0038] However, the MBI5034 chip does not have an open circuit detection function, so this application combines display scanning technology to achieve grayscale scanning. The specific principles are as follows:

[0039] S2: Use binary rules to establish a mapping relationship between each brightness level and the display lighting duration, and make each brightness level have a display off time in the refresh cycle. In an embodiment of the first aspect of the present application, specifically, the following steps are included:

[0040] The steps of using a binary rule to establish a mapping relationship between each brightness level and the display lighting duration, and making each brightness level have a display off time within a refresh cycle include: using an n-bit binary number to represent the display lighting duration corresponding to each brightness level, and the binary numbers from small to large correspond to the brightness levels from dark to bright; wherein each refresh cycle is evenly divided into x scanning cycles (x≥n), a corresponding number of scanning cycles are allocated to each bit of the binary number, and a corresponding display duty cycle is set for the scanning cycle allocated to each bit; and the display duty cycle corresponding to the lowest bit is less than 1, the product of the scanning cycle corresponding to each bit and the display duty cycle is the bit display duration of each bit, and the ratio of the bit display durations between each bit is equal to the ratio of its bit weights; then the display lighting duration corresponding to each brightness level is the sum of the display durations of each bit of the corresponding binary number.

[0041] It should be understood that in the MBI5034 chip, the display lighting and display shutdown of the display screen are controlled by the OE (output enable) signal. When OE is high, the display is shut down, and when OE is low, the display is lit.

[0042] It should be understood that the calculation formula for the sum of the display time of each bit of the binary number is: (value of bit n * number of scanning cycles corresponding to bit n * duty cycle corresponding to bit n) + (value of bit (n-1) * number of scanning cycles corresponding to bit (n-1) * duty cycle corresponding to bit (n-1)) +... + (value of bit 2 * number of scanning cycles corresponding to bit 2 * duty cycle corresponding to bit 2) + (value of bit 1 * number of scanning cycles corresponding to bit 1 * duty cycle corresponding to bit 1) ("*" is the multiplication operator symbol).

[0043] 1. When the grayscale bit is 3

[0044] For example, when the grayscale bit is 3, there are 8 (2 3 ) brightness levels, and the mapping relationship between the 8 brightness levels and the display lighting time in one refresh cycle is established using the binary rule. The binary numbers corresponding to the 8 brightness levels are: 000, 001, 010, 011, 100, 101, 110, 111. In addition, the binary numbers from small to large correspond to the brightness levels from dark to bright, that is, 000 represents the darkest brightness among the 8 brightness levels, 001 represents a brightness slightly brighter than 000, 010 represents a brightness slightly brighter than 001, and so on, 111 represents the brightest brightness among the 8 brightness levels.

[0045] Each refresh cycle is evenly divided into x scan cycles (x ≥ 3). Since the grayscale bit is 3, the refresh cycle can be evenly divided into 3 scan cycles, or evenly divided into 4, 5, 6, etc. scan cycles. Since for the grayscale bit n, each binary bit needs to be allocated no less than 1 scan cycle, the grayscale bit n is represented as a binary number with a total of n bits, so x must be greater than or equal to n.

[0046] A corresponding number of scan cycles are allocated to each bit of the binary number, and a corresponding display duty cycle is set for the scan cycle allocated to each bit; and the display duty cycle corresponding to the lowest bit is less than 1, the product of the scan cycle corresponding to each bit and the display duty cycle is the bit display duration of each bit, and the ratio of the bit durations between each bit is equal to the ratio of their bit weights.

[0047] That is, when the grayscale bit is 3, the corresponding binary number has three bits, from high to low: bit 2, bit 1, bit 0. The corresponding number of scan cycles is allocated to bit 2, bit 1, and bit 0 respectively, and the corresponding duty cycle is set for the scan cycle allocated to each bit. The allocated scan cycle and the set duty cycle should follow the following principles:

[0048] (1) The display duty cycle corresponding to the lowest bit is less than 1.

[0049] (2) If the product of the scanning period corresponding to each bit and the display duty cycle is defined as the bit display time of each bit, the ratio of the bit display time between each bit is equal to the ratio of its bit weight.

[0050] Since when the grayscale bit is 3, the bit weight is 4 (bit 2): 2 (bit 1): 1 (bit 0). Therefore:

[0051] like Figure 2 As shown, when the refresh cycle is divided into 3 scan cycles, 1 scan cycle can be allocated to bit 2, 1 scan cycle can be allocated to bit 1, and 1 scan cycle can be allocated to bit 0. In addition, the duty cycle of the scan cycle allocated to bit 2 is set to 1, the duty cycle of the scan cycle allocated to bit 1 is set to 1 / 2, and the duty cycle of the scan cycle allocated to bit 0 is set to 1 / 4. That is, the number of scan cycles corresponding to each bit {bit 2, bit 1, bit 0} is {1, 1, 1}, and the corresponding duty cycle is {1, 1 / 2, 1 / 4}. Under this allocation scheme, Figure 3 As shown, among the 8 brightness levels corresponding to the grayscale bit 3, the display lighting time corresponding to the brightness level "011" is: (0*1*1)+(1*1*(1 / 2))+(1*1*(1 / 4))=0.75 scanning cycles, the display lighting time corresponding to the brightness level "101" is: (1*1*1)+(0*1*(1 / 2))+(1*1*(1 / 4))=1.25 scanning cycles, and the display lighting time corresponding to the brightest brightness level "111" is: (1*1*1)+(1*1*(1 / 2))+(1*1*(1 / 4))=1.75 scanning cycles. It can be seen that the display lighting time of the 8 brightness levels is less than 3 scanning cycles (that is, the number of scanning cycles corresponding to the refresh cycle). Therefore, these 8 brightness levels have display off time within their corresponding refresh cycles.

[0052] When the refresh cycle is divided into 4 scan cycles, 2 scan cycles can be allocated to bit 2, 1 scan cycle can be allocated to bit 1, and 1 scan cycle can be allocated to bit 0. In addition, the duty cycle of the scan cycle allocated to bit 2 is set to 1, the duty cycle of the scan cycle allocated to bit 1 is set to 1, and the duty cycle of the scan cycle allocated to bit 0 is set to 1 / 2. That is, the number of scan cycles corresponding to each bit {bit 2, bit 1, bit 0} is {2, 1, 1}, and the corresponding duty cycle is {1, 1, 1 / 2}. Under this allocation scheme, among the 8 brightness levels corresponding to the grayscale bit 3, the display lighting time corresponding to the brightness level "011" is: (0*2*1)+(1*1*1)+(1*1*(1 / 2))=1.5 scanning cycles, the display lighting time corresponding to the brightness level "101" is: (1*2*1)+(0*1*1)+(1*1*(1 / 2))=2.5 scanning cycles, and the display lighting time corresponding to the brightest brightness level "111" is: (1*2*1)+(1*1*1)+(1*1*(1 / 2))=3.5 scanning cycles. It can be seen that the display lighting time of the 8 brightness levels is less than 4 scanning cycles (that is, the number of scanning cycles corresponding to the refresh cycle).

[0053] When the refresh cycle is divided into 4 scan cycles, 1 scan cycle can be allocated to bit 2, 2 scan cycles can be allocated to bit 1, and 1 scan cycle can be allocated to bit 0. In addition, the duty cycle of the scan cycle allocated to bit 2 is set to 1, the duty cycle of the scan cycle allocated to bit 1 is set to 1 / 4, and the duty cycle of the scan cycle allocated to bit 0 is set to 1 / 4. That is, the number of scan cycles corresponding to each bit {bit 2, bit 1, bit 0} is {1, 2, 1}, and the corresponding duty cycle is {1, 1 / 4, 1 / 4}. In this allocation scheme, the display lighting duration corresponding to the brightest brightness level "111" is 1.75 scan cycles, which is less than 4 scan cycles (that is, the number of scan cycles corresponding to the refresh cycle). However, this allocation method does not distribute the weight of grayscale values ​​reasonably. In binary grayscale scanning, high-order bits should usually have more weight because they contribute more to the overall brightness, while low-order bits play a role in fine-tuning the brightness. Since bit 1 consumes too much time resources (2 scanning cycles), the refresh cycle becomes longer and the refresh rate decreases. For display products, the refresh rate is an important indicator, so this method of sacrificing the refresh rate is not advisable.

[0054] Therefore, preferably, in an embodiment of the first aspect of the present application, the number of scan cycles allocated to each bit position decreases monotonically from high to low according to the bit position, and the display duty cycle allocated to each bit position decreases monotonically from high to low according to the bit position. Excluding the above-mentioned number of scan cycles corresponding to each bit position {bit 2, bit 1, bit 0} is {1, 2, 1}, and the corresponding duty cycle is {1, 1 / 4, 1 / 4}, which is not a monotonically decreasing number of scan cycles and duty cycle allocation scheme from high to low according to the bit position.

[0055] It should be understood that the monotonic decrease mentioned in the present invention refers to non-strict monotonic decrease, that is, it includes equal situations.

[0056] 2. When the grayscale bit is 4

[0057] For example, when the grayscale bit is 4, there are 16 (2 4 ) brightness levels, and the mapping relationship between the 16 brightness levels and the display lighting time in one refresh cycle is established using the binary rule. The binary numbers corresponding to the 16 brightness levels are: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111. In addition, the binary numbers correspond to the brightness levels from dark to bright from small to large, that is, 0000 represents the darkest brightness among the 16 brightness levels, 0001 represents a brightness slightly brighter than the brightness of 0000, 0010 represents a brightness slightly brighter than the brightness of 001, and so on, 1111 represents the brightest brightness among the 16 brightness levels.

[0058] Each refresh cycle is evenly divided into x scanning cycles (x ≥ 4). Since the grayscale bit is 4, the refresh cycle can be evenly divided into 4 scanning cycles, or evenly divided into 5, 6, 7, 8, etc. scanning cycles.

[0059] When the grayscale bit is 4, the corresponding binary number has four bits, from high to low: bit 3, bit 2, bit 1, bit 0. A corresponding number of scanning cycles are allocated to bit 3, bit 2, bit 1, and bit 0, respectively, and a corresponding duty cycle is set for the scanning cycle allocated to each bit.

[0060] Since the grayscale bit is 4, the bit weight is 8 (bit 3): 4 (bit 2): 2 (bit 1): 1 (bit 0). Therefore:

[0061] When the refresh cycle is divided into 4 scan cycles, the number of scan cycles corresponding to each bit {bit 3, bit 2, bit 1, bit 0} can be set to {1, 1, 1, 1}, and the corresponding duty cycle is {1, 1 / 2, 1 / 4, 1 / 8}. Under this allocation scheme, among the 16 brightness levels corresponding to grayscale bit 4, the display lighting time corresponding to the brightness level "0011" is: (0*1*1)+(0*1*(1 / 2))+(1*1*(1 / 4))+(1*1*(1 / 8))=0.375 scan cycles, and the display lighting time corresponding to the brightness level "1101" is: (1*1*1)+(1*1*(1 / 2))+(0*1*(1 / 4))+(1*1*(1 / 8)) =0.625 scanning cycles, the display lighting duration corresponding to the brightest brightness level "1111" is: (1*1*1)+(1*1*(1 / 2))+(1*1*(1 / 4))+(1*1*(1 / 8))=1.875 scanning cycles. It can be seen that the display lighting durations of the 16 brightness levels are all less than 4 scanning cycles (that is, the number of scanning cycles corresponding to the refresh cycle). Therefore, these 16 brightness levels all have display off time within their corresponding refresh cycles.

[0062] When the refresh cycle is divided into 5 scan cycles, the number of scan cycles corresponding to each bit {bit 3, bit 2, bit 1, bit 0} can be set to {2, 1, 1, 1}, and the corresponding duty cycle is {1, 1, 1 / 2, 1 / 4}. Under this allocation scheme, the display lighting duration corresponding to the brightest brightness level "1111" is: (1*2*1)+(1*1*1)+(1*1*(1 / 2))+(1*1*(1 / 4))=3.75 scan cycles, which is less than 5 scan cycles (i.e., the number of scan cycles corresponding to the refresh cycle).

[0063] When the refresh cycle is divided into 8 scan cycles, the number of scan cycles corresponding to each bit {bit 3, bit 2, bit 1, bit 0} can be set to {4, 2, 1, 1}, and the corresponding duty cycle is {1, 1, 1, 1 / 2}. Under this allocation scheme, the display lighting duration corresponding to the brightest brightness level "1111" is: (1*4*1)+(1*2*1)+(1*1*1)+(1*1*(1 / 2))=7.5 scan cycles, which is less than 8 scan cycles (i.e., the number of scan cycles corresponding to the refresh cycle).

[0064] Of course, when the grayscale bit position is 4 and the refresh cycle is divided into 5 (or 8), the number of scanning cycles and duty cycle allocated to each bit position can also be allocated in a non-monotonic decreasing manner, but as mentioned earlier, since this scheme will lead to the disadvantage of reduced refresh rate, this allocation scheme can be excluded in the preferred case.

[0065] Therefore, in summary, no matter how many grayscale bits n there are, the corresponding 2 n In each brightness level, according to the above allocation scheme of the number of scanning cycles and duty cycle for each bit, these brightness levels all have a period of display off time in their refresh cycles.

[0066] S3: Setting the display off time corresponding to all brightness levels at the end of the refresh cycle. In an embodiment of the first aspect of the present application, the step of setting the display off time corresponding to all brightness levels at the end of the refresh cycle includes:

[0067] Starting from the beginning of the refresh cycle, the scan cycles are assigned from the high bit to the low bit, and the scan cycle at the end of the refresh cycle is assigned to the lowest bit. For example:

[0068] like Figure 4 As shown in the figure, when the grayscale bit is 3 and the refresh cycle is divided into 3 scanning cycles, the order of these 3 scanning cycles from the beginning to the end of the refresh cycle in the refresh cycle is: {scanning cycle 1, scanning cycle 2, scanning cycle 3}. If the number of scanning cycles corresponding to each bit {bit 2, bit 1, bit 0} is {1, 1, 1}, the corresponding duty cycle is {1, 1 / 2, 1 / 4}. According to this allocation scheme, scanning cycle 1 is allocated to bit 2, scanning cycle 2 is allocated to bit 1, and scanning cycle 3 is allocated to bit 0.

[0069] When the grayscale bit is 3 and the refresh cycle is divided into 4 scan cycles, the order of these 4 scan cycles from the beginning to the end of the refresh cycle in the refresh cycle is: {scan cycle 1, scan cycle 2, scan cycle 3, scan cycle 4}. If the number of scan cycles corresponding to each bit {bit 2, bit 1, bit 0} is {2, 1, 1}, the corresponding duty cycle is {1, 1, 1 / 2}. According to this scheme, scan cycle 1 and scan cycle 2 can be assigned to bit 2, scan cycle 3 can be assigned to bit 1, and scan cycle 4 can be assigned to bit 0.

[0070] When the grayscale bit is 4 and the refresh cycle is divided into 4 scanning cycles, the order of these 4 scanning cycles from the beginning to the end of the refresh cycle in the refresh cycle is: {scanning cycle 1, scanning cycle 2, scanning cycle 3, scanning cycle 4}. If the number of scanning cycles corresponding to each bit {bit 3, bit 2, bit 1, bit 0} is {1, 1, 1, 1}, the corresponding duty cycle is {1, 1 / 2, 1 / 4, 1 / 8}. According to this scheme, scanning cycle 1 can be assigned to bit 3, scanning cycle 2 can be assigned to bit 2, scanning cycle 3 can be assigned to bit 1, and scanning cycle 4 can be assigned to bit 0.

[0071] When the grayscale bit is 4 and the refresh cycle is divided into 5 scan cycles, the order of these 5 scan cycles from the beginning to the end of the refresh cycle in the refresh cycle is: {scan cycle 1, scan cycle 2, scan cycle 3, scan cycle 4, scan cycle 5}. If the number of scan cycles corresponding to each bit {bit 3, bit 2, bit 1, bit 0} is {2, 1, 1, 1}, the corresponding duty cycle is {1, 1, 1 / 2, 1 / 4}. According to this scheme, scan cycle 1 and scan cycle 2 can be assigned to bit 3, scan cycle 3 can be assigned to bit 2, scan cycle 4 can be assigned to bit 1, and scan cycle 5 can be assigned to bit 0.

[0072] When the grayscale bit is 4 and the refresh cycle is divided into 8 scan cycles, the order of these 8 scan cycles from the beginning to the end of the refresh cycle in the refresh cycle is: {scan cycle 1, scan cycle 2, scan cycle 3, scan cycle 4, scan cycle 5, scan cycle 6, scan cycle 7, scan cycle 8}. If the number of scan cycles corresponding to each bit {bit 3, bit 2, bit 1, bit 0} is {4, 2, 1, 1}, the corresponding duty cycle is {1, 1, 1, 1 / 2}. According to this scheme, the four scan cycles of scan cycle 1, scan cycle 2, scan cycle 3 and scan cycle 4 can be all assigned to bit 3, scan cycle 5 and scan cycle 6 can be assigned to bit 2, scan cycle 7 can be assigned to bit 1, and scan cycle 8 can be assigned to bit 0.

[0073] It should be understood that, starting from the start of the refresh cycle, the scanning cycles are allocated from high bits to low bits in sequence, and the scanning cycle at the end of the refresh cycle is allocated to the lowest bit. This allocation scheme does not constitute a limitation on the protection scope of the present invention, and the technical solutions that can achieve the effect that the display off time corresponding to all brightness levels is at the end of the refresh cycle are all within the protection scope of the present invention. For example, when actually allocating scanning cycles to bits, only the last scanning cycle in the refresh cycle can be allocated to the lowest bit (bit 0), and the allocation schemes of other scanning cycles and bits can be randomly and freely combined.

[0074] S4: performing an image data update operation at the end of the previous refresh cycle, and performing an open circuit detection triggering action at the beginning of the current refresh cycle, and performing an image display operation after the open circuit detection triggering to display the image data updated in the previous refresh cycle. In an embodiment of the first aspect of the present application, this step includes:

[0075] In the last scanning cycle of the previous refresh cycle, an image data update operation is performed; wherein the updated image data is the bit data displayed in the first scanning cycle of the next refresh cycle; an open circuit detection trigger is performed at the beginning of the first scanning cycle of the current refresh cycle, and after the open circuit detection trigger ends, image data is displayed during the remaining time of the first scanning cycle; wherein the displayed image data is the image data updated in the last scanning cycle of the previous refresh cycle; within the first scanning cycle, no image data update is performed, and image data that should have been updated within the first scanning cycle of the current refresh cycle is discarded.

[0076] It should be understood that the image data here refers to the bit data corresponding to the image, and does not refer to the complete information of each pixel in a frame of image (including color and brightness, etc.). The bit data is the decomposition of the image data. The grayscale value of each pixel is composed of multiple bits, and the bit data refers to the data of one or several bits in these bits. For example, an 8-bit grayscale value can be divided into bit 0 to bit 7, and each bit will have 0 or 1, and these 0 or 1 constitute the bit data. In the image processing process of the LED display, grayscale scanning is achieved by scanning the different bits of each pixel in multiple times. For the grayscale information of each pixel, not all bits are updated at once, but they are updated, processed and displayed bit by bit. This means that the bit data of the image is transmitted and updated in sequence at each stage of the refresh cycle.

[0077] Moreover, the updating and displaying of bit data is a pipeline operation, that is, the updating and displaying of bit data are performed in an interlaced manner, and each display operation depends on the bit data that has been updated in the previous scanning cycle. Specifically, the previous scanning cycle is responsible for updating the bit data (loading a certain bit of the image data into the display controller). The next scanning cycle performs the display operation, that is, the actual display action of controlling the LED to light up or turn off, and uses the OE signal to control the on and off time.

[0078] For example, when the grayscale bit is 8 and the refresh cycle is divided into 12 scanning cycles, if the number of scanning cycles allocated to each bit is {4, 2, 1, 1, 1, 1, 1, 1}, and the duty cycle set for each bit is {1, 1, 1, 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32}. Then, the data of bit 7 is updated in the first scanning cycle, and the data of bit 0 updated in the 12th cycle of the previous frame (duty cycle 1 / 32) is displayed. The data of bit 7 is still updated in the second scanning cycle, and the data of bit 7 updated in the first cycle (duty cycle 1) is displayed. The data of bit 0 updated in the 12th scanning cycle is displayed as the data of bit 1 updated in the 11th cycle (duty cycle 1 / 16).

[0079] Since the open circuit detection process of MBI5034 can be divided into two stages, the first is the trigger detection stage, and the second is the stage of reading back the detection data. The trigger detection operation is incompatible with the image data update timing (i.e. the time sequence of the operation), and data update and detection trigger cannot be performed at the same time, while the readback detection data operation is compatible with the image data update timing, and data update and detection data readback can be performed at the same time.

[0080] Therefore, in order to overcome the incompatibility between the trigger detection operation and the image data update timing, the present invention performs the image data update operation at the end of the previous refresh cycle and performs the open circuit detection trigger action at the beginning of the current refresh cycle.

[0081] like Figure 5As shown, when the refresh cycle is evenly divided into multiple scanning cycles, that is, in the last scanning cycle of the previous refresh cycle (hereinafter referred to as "scanning cycle A"), the image data update operation is performed, and at the beginning of the first scanning cycle of the current refresh cycle (hereinafter referred to as "scanning cycle B"), the open circuit detection trigger action is performed. Since the open circuit detection is triggered at the beginning of scanning cycle B, and the end of scanning cycle A is the display off state, the display screen will not suddenly switch from the lit state to the off state, so that the human eye cannot detect the black screen caused by the open circuit detection trigger. Because the duration of the open circuit detection trigger is usually much shorter than the duration of the scanning cycle, after the open circuit detection is triggered at the beginning of scanning cycle B, the original image data (bit data) continues to be displayed in scanning cycle B. It should be understood that the image data (bit data) displayed in scanning cycle B is the image data (bit data) updated in scanning cycle A. It should be understood that because the time of setting the scanning cycle is much longer than the duration of the open circuit detection trigger, the open circuit detection in this scanning cycle has little effect on the display color of the pixel.

[0082] Since the readback test data operation is compatible with the image data update timing, data update and test data readback can be performed simultaneously. Therefore, after the open circuit detection is performed in scanning cycle A, the open circuit detection data is read back in the scanning cycle after scanning cycle A (hereinafter referred to as "scanning cycle C").

[0083] However, since scan cycle A updates the image data of scan cycle B, in scan cycle B, the data update cannot be performed because the timing of the data update and the open circuit detection trigger are not compatible. Therefore, there are two possibilities:

[0084] First, if the image data (bit data) that should be updated in scan cycle B and displayed in scan cycle C is updated in scan cycle C and displayed in the scan cycle after scan cycle C (hereinafter referred to as "scan cycle D"), this will cause a delay in data update, resulting in the following disadvantages: (1) Display delay. Since the update of bit B data is postponed to scan cycle C, the data of this bit cannot be presented in the original display period. Although the update is delayed, the updated data will still be displayed after scan cycle C. This delay usually causes the image display to be incompletely synchronized, that is, it may produce a visual lag or unsmoothness, especially when this delay occurs in the high-order bits that contribute more to the brightness. The impact is more obvious. For example, if a fast-changing dynamic picture is being displayed on the screen, the data delay may cause the image to change in time, and the visual phenomenon of "smearing" or "slight freeze" may occur. (2) The smoothness of the image brightness change is affected. The grayscale level corresponding to each bit contributes to the brightness of the pixel to varying degrees. Generally, the high-order bits have a greater impact on the brightness, and the low-order bits control the fine adjustment of the brightness. If the update of low-order bit data is delayed, the brightness fine-tuning of the image will be affected, resulting in an unsmooth brightness gradient. For example, in a grayscale gradient effect, the delayed update of low-order bits will result in an unsmooth brightness transition, which may result in a "staircase effect" or brightness jump. (3) Distortion of dynamic content. If the delay occurs when displaying dynamic video or animation, the transition between frames will no longer be accurate. Although the data within each frame will still be displayed, their display order is disrupted, which may cause visual distortion or motion blur. Especially when this delay occurs repeatedly, the image may appear "wrong frame" or lose continuity.

[0085] Second, the image data (bit data) that should be updated in scan cycle B and displayed in scan cycle C is directly discarded, and the data of the next bit is directly updated in scan cycle C, and the data updated in scan cycle C is displayed in scan cycle D. In this case, the data of bit B is not updated at all and is directly skipped. This will lead to the loss of bit data, resulting in the following defects: (1) Grayscale error. Since the data of bit B is not updated, the displayed image will lack the information of this bit. Specifically, the grayscale control is incomplete, which directly affects the brightness of the pixel. If bit B is a high-order bit (such as bit 7 or bit 6), this error will have a very significant impact on the brightness. Because the high-order bits control most of the brightness, if the data of these bits is missing, the brightness will be significantly lower, and the entire image may appear too dark or unbalanced. If bit B is a low-order bit (such as bit 0 or bit 1), although it has a smaller impact on the overall brightness, it is responsible for fine adjustment of the brightness. Therefore, the lack of low-order bit data will result in imprecise brightness adjustment, and the details and grayscale transitions of the image will appear unnatural. (2) Incomplete image display. The loss of bit B is equivalent to the loss of a certain grayscale level information of the image. Some brightness levels cannot be displayed correctly, especially in complex images, some pixels may appear brighter or darker than expected. For high-order bits, the loss of one bit of data means that the brightness difference will be doubled. For example, assuming that the original grayscale value of a pixel is 1110, if the data of bit 3 is lost, the actual displayed grayscale value will be 0110, which will halve the brightness. (3) Visual jump. If this data loss occurs frequently (especially the loss of high-order bit data), it will cause sudden changes or jumps in the brightness of the image. This phenomenon is visually manifested as sudden brightness changes, especially in gradient areas, which will appear unnatural and affect the visual smoothness and consistency of the image. (4) Image flickering or instability. In the case of data loss, the brightness of the image may flicker slightly, especially in areas with large brightness changes, where this problem may be more obvious. This flickering will reduce the stability of the screen and affect the viewing experience.

[0086] Therefore, in order to avoid the defects caused by the above two situations, in an embodiment of the first aspect of the present application, the number of scanning cycles allocated to the highest bit is set to be greater than or equal to 2.

[0087] For example, if Figure 6As shown, when the grayscale bit position is 4 and the refresh cycle is divided into 5 scanning cycles, the arrangement order of these 5 scanning cycles from the beginning of the refresh cycle to the end of the refresh cycle in the refresh cycle is: {scanning cycle 1, scanning cycle 2, scanning cycle 3, scanning cycle 4, scanning cycle 5}. If the number of scanning cycles assigned to each bit position is {2, 1, 1, 1}, and the duty cycle set for each bit position is {1, 1, 1 / 2, 1 / 4}. That is, scanning cycle 1 and scanning cycle 2 are assigned to bit position 3. It should be understood that scanning cycle 5 in the previous refresh cycle corresponds to scanning cycle A, scanning cycle 1 in the current refresh cycle corresponds to scanning cycle B, scanning cycle 2 in the current refresh cycle corresponds to scanning cycle C, and scanning cycle 3 in the current refresh cycle corresponds to scanning cycle D.

[0088] In this way, when the image data is not updated in the first scanning cycle, and the image data that should be updated in the first scanning cycle of the current refresh cycle is discarded, that is, the following scheme is adopted: "The image data (bit data) that should be updated in scanning cycle B and displayed in scanning cycle C is directly discarded, the data of the next bit is directly updated in scanning cycle C, and the data updated in scanning cycle C is displayed in scanning cycle D". The image data updated in scanning cycle A is the data of bit 3. The data that should be updated in scanning cycle B is also the data of bit 3, and the data displayed in scanning cycle B is the data of bit 3 (updated by scanning cycle A). The data updated in scanning cycle C is the data of bit 2, and the data displayed in scanning cycle C is the data of bit 3 (updated by scanning cycle A).

[0089] Since bit 3 corresponds to two scanning cycles, when the solution of discarding the bit data that should be updated in the cycle of open circuit detection is adopted, performing open circuit detection in the second update cycle corresponding to bit 3 will not actually cause the loss of bit data.

[0090] Figure 7 is a schematic block diagram of an open circuit detection system based on the MBI5034 chip provided in an embodiment of the present application. , such as Figure 7 As shown, the system includes a display control module and a display screen, wherein the display control module includes an MBI5034 chip, and the display control module is used to execute any one of the methods described in the first aspect of the present application; the display screen is used to display image data output by the control module.

[0091] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0092] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0093] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, it implements any one of the methods described in the first aspect of the present application.

[0094] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer implements any one of the methods described in the first aspect of the present application.

[0095] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement any one of the methods described in the first aspect of the present application.

[0096] Figure 8 804 is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. The electronic terminal includes: at least one processor 801, a memory 802, at least one network interface 803 and a user interface 805. The various components in the electronic terminal are coupled together through a bus system 804. It can be understood that the bus system 804 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 804 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 8 In the specification, various buses are labeled as bus systems.

[0097] The user interface 805 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0098] It is understood that the memory 802 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0099] The memory 802 in the embodiment of the present invention is used to store various categories of data to support the operation of the electronic terminal 800. Examples of these data include: any executable program used to operate on the electronic terminal 800, such as an operating system 8021 and an application 8022; the operating system 8021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 8022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The XX method provided by the embodiment of the present invention can be included in the application 8022.

[0100] The method disclosed in the above embodiment of the present invention can be applied to the processor 801, or implemented by the processor 801. The processor 801 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 801 or the instruction in the form of software. The above processor 801 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 801 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 801 can be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0101] In an exemplary embodiment, the electronic terminal 800 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD), FPGA to execute the aforementioned method.

[0102] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0103] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0104] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0105] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0106] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0107] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0108] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When loading and executing computer program instructions (programs) on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media integrations. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs), etc.).

[0109] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0110] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0111] In summary, the present invention provides an open circuit detection method, system, medium, program and electronic terminal based on the MBI5034 chip, which effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0112] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An open circuit detection method based on the MBI5034 chip performs grayscale scanning on a display screen, characterized in that: include: Set the number of gray levels to n, then each pixel has 2 n brightness levels, each brightness level corresponds to a different display lighting duration within the refresh cycle; A binary rule is used to establish a mapping relationship between each brightness level and the display lighting duration, and each brightness level has a display off time within a refresh cycle; The display off time corresponding to all brightness levels is set at the end of the refresh cycle; An image data update operation is performed at the end of a previous refresh cycle, and an open circuit detection trigger action is performed at the beginning of a current refresh cycle. An image display operation is performed after the open circuit detection trigger to display the image data updated in the previous refresh cycle.

2. According to claim 1, an open circuit detection method based on the MBI5034 chip is characterized in that: The steps of using a binary rule to establish a mapping relationship between each brightness level and the display lighting duration, and making each brightness level have a display off time in a refresh cycle include: The display lighting duration corresponding to each brightness level is represented by an n-bit binary number, and the binary numbers from small to large correspond to the brightness levels from dark to bright; Each refresh cycle is evenly divided into x scan cycles (x≥n), a corresponding number of scan cycles are allocated to each bit of the binary number, and a corresponding display duty cycle is set for the scan cycle allocated to each bit; and the display duty cycle corresponding to the lowest bit is less than 1, the product of the scan cycle corresponding to each bit and the display duty cycle is the bit display time of each bit, and the ratio of the bit display time between each bit is equal to the ratio of its bit weight; The display lighting duration corresponding to each brightness level is the sum of the display durations of each bit of the corresponding binary number.

3. The open circuit detection method based on the MBI5034 chip according to claim 2 is characterized in that: The number of scanning cycles allocated to each bit position decreases monotonically from high to low as the bit position decreases, and the display duty cycle allocated to each bit position decreases monotonically as the bit position decreases from high to low.

4. The open circuit detection method based on the MBI5034 chip according to claim 2 is characterized in that: The step of setting the display off time corresponding to all brightness levels at the end of the refresh cycle includes: Starting from the beginning of the refresh cycle, the scan cycles are allocated to the high bit positions to the low bit positions in sequence, and the scan cycle at the end of the refresh cycle is allocated to the lowest bit position.

5. The open circuit detection method based on the MBI5034 chip according to claim 4 is characterized in that: The number of scan cycles allocated to the highest bit is greater than or equal to 2.

6. The open circuit detection method based on the MBI5034 chip according to claim 5, characterized in that: The steps of performing an image data update operation at the end of the previous refresh cycle, performing an open circuit detection triggering action at the beginning of the current refresh cycle, and performing an image display operation after the open circuit detection triggering action is completed to display the image data updated in the previous refresh cycle include: In the last scanning cycle of the previous refresh cycle, an image data update operation is performed; wherein the updated image data is the bit data displayed in the first scanning cycle of the next refresh cycle; An open circuit detection trigger is performed at the beginning of the first scanning cycle of the current refresh cycle, and after the open circuit detection trigger is completed, image data is displayed during the remaining time of the first scanning cycle; wherein the displayed image data is the image data updated in the last scanning cycle of the previous refresh cycle; In the first scanning cycle, image data is not updated, and image data that should be updated in the first scanning cycle of the current refresh cycle is discarded.

7. An open circuit detection system based on the MBI5034 chip, including a display control module and a display screen, characterized in that: The display control module comprises an MBI5034 chip, and the display control module is used to execute the method according to any one of claims 1 to 6; The display screen is used to display image data output by the control module.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

9. A computer program product, characterized in that The computer program product includes computer program code, and when the computer program code is run on a computer, the computer is enabled to implement the method as described in any one of claims 1 to 6.

10. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method according to any one of claims 1 to 6.

Images