Shifting register and driving method thereof, gate driving circuit and display device

Abstract

The invention relates to a shift register and a driving method thereof, a gate driving circuit and a display device, the shift register comprises an input sub-circuit, an output sub-circuit and a first control sub-circuit, the input sub-circuit is electrically connected with a signal input end and a pull-up node and is configured to provide a signal to the pull-up node under the control of the signal of the signal input end; the output sub-circuit is electrically connected with the first output end, the pull-up node and a clock signal end, and is configured to provide a signal of the clock signal end to the first output end under the control of the signal of the pull-up node; and the first control sub-circuit is electrically connected with the control signal end and the signal input end, and is configured to provide the signal of the control signal end to the signal input end under the control of the signal of the control signal end.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and specifically to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] In recent years, flat panel displays, such as Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Active Matrix Organic Light Emitting Diode (AMOLED), have been widely used in electronic products such as televisions and mobile phones due to their advantages such as light weight, thin thickness and low power consumption.

[0003] With the advancement of technology, high-resolution, narrow-frame display panels have become a development trend. For this reason, the array substrate gate driver (GOA) technology has emerged. The GOA technology refers to the technology of setting the GOA circuit used to drive the gate line on both sides of the effective display area of ​​the array substrate in the display panel. Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a shift register, comprising: an input subcircuit, an output subcircuit and a first control subcircuit, wherein the operation process of the shift register comprises: a display phase and a non-display phase, wherein the display phase comprises: an output phase and a non-output phase;

[0006] The input subcircuit is electrically connected to the signal input terminal and the pull-up node, respectively, and is configured to provide a signal to the pull-up node under the control of the signal of the signal input terminal;

[0007] The output subcircuit is electrically connected to the first output terminal, the pull-up node and the clock signal terminal respectively, and is configured to provide a signal of the clock signal terminal to the first output terminal under the control of a signal of the pull-up node;

[0008] The first control subcircuit is electrically connected to the control signal terminal and the signal input terminal, and is configured to provide the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

[0009] In an exemplary embodiment, the shift register further includes: a first reset subcircuit;

[0010] The first reset subcircuit is electrically connected to the general reset signal terminal, the pull-up node and the first power supply terminal respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node under the control of the general reset signal terminal;

[0011] The total reset signal terminal is a valid level signal in a partial period of time in the non-display stage, and is an invalid level signal in the display stage.

[0012] In an exemplary embodiment, the control signal terminal includes: at least one of a first control signal terminal and a second control signal terminal;

[0013] The first control signal terminal is electrically connected to the general reset signal terminal, and the second control signal terminal is electrically connected to the first output terminal.

[0014] In an exemplary embodiment, in a state where the control signal terminal includes the first control signal terminal, the first control subcircuit includes: a nineteenth transistor;

[0015] The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal.

[0016] In an exemplary embodiment, in a state where the control signal terminal includes a second control signal terminal, the first control subcircuit includes: a twentieth transistor;

[0017] The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

[0018] In an exemplary embodiment, in a state where the control signal terminal includes a first control signal terminal and a second control signal terminal, the control subcircuit includes: a nineteenth transistor and a twentieth transistor;

[0019] The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal;

[0020] The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

[0021] In an exemplary embodiment, the input subcircuit includes: a first transistor;

[0022] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the pull-up node.

[0023] In an exemplary embodiment, the input subcircuit includes: a first transistor and a twenty-first transistor;

[0024] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0025] The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

[0026] In an exemplary embodiment, the output subcircuit includes: a second transistor and a capacitor;

[0027] The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal;

[0028] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output end.

[0029] In an exemplary embodiment, the output sub-circuit is further electrically connected to the second output terminal, and is configured to provide a signal of the clock signal terminal to the second output terminal under the control of a signal of the pull-up node.

[0030] In an exemplary embodiment, the output subcircuit includes: a second transistor, a third transistor, and a capacitor;

[0031] The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal;

[0032] A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal;

[0033] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output end.

[0034] In an exemplary embodiment, the first reset subcircuit includes: a fourth transistor;

[0035] The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal.

[0036] In an exemplary embodiment, the shift register further includes: a second reset subcircuit;

[0037] The second reset subcircuit is electrically connected to the first reset signal terminal, the second reset signal terminal, the pull-up node, the first output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and provide the signal of the third power supply terminal to the first output terminal under the control of the signals of the first reset signal terminal and the second reset signal terminal;

[0038] The absolute value of the voltage of the signal at the first power supply terminal is greater than the absolute value of the voltage of the signal at the third power supply terminal;

[0039] The first reset signal terminal and the second reset signal terminal are invalid level signals in the non-display stage and the output stage, and are valid level signals in a partial time period of the non-output stage.

[0040] In an exemplary embodiment, the second reset subcircuit includes: a fifth transistor and a sixth transistor;

[0041] The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal;

[0042] The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the third power supply terminal.

[0043] In an exemplary embodiment, the shift register further includes: a noise reduction subcircuit, wherein the noise reduction subcircuit includes: at least one of a first noise reduction subcircuit and a second noise reduction subcircuit;

[0044] The first noise reduction sub-circuit is electrically connected to the fourth power supply terminal, the signal input terminal, the pull-up node, the first output terminal, the second output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and the second output terminal, and provide the signal of the third power supply terminal to the pull-down node under the control of the signal of the signal input terminal, the pull-up node and the fourth power supply terminal;

[0045] The second noise reduction sub-circuit is electrically connected to the fifth power supply terminal, the signal input terminal, the pull-up node, the first output terminal, the second output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and the second output terminal, and provide the signal of the third power supply terminal to the pull-down node under the control of the signals of the signal input terminal, the pull-up node and the fifth power supply terminal.

[0046] In an exemplary embodiment, the first noise reduction sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor, and the second noise reduction sub-circuit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor;

[0047] The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal;

[0048] The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal;

[0049] The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node;

[0050] The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal;

[0051] The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal;

[0052] The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0053] The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal;

[0054] The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal;

[0055] The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal;

[0056] The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal;

[0057] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal;

[0058] The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal.

[0059] In an exemplary embodiment, the invention further comprises: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; the input subcircuit comprises: a first transistor, the output subcircuit comprises: a second transistor, a third transistor and a capacitor, the first control subcircuit comprises: at least one of a nineteenth transistor and a twenty-first transistor; the first reset subcircuit comprises: a fourth transistor, the second reset subcircuit comprises: a fifth transistor and a sixth transistor, the noise reduction subcircuit comprises: a seventh transistor to an eighteenth transistor;

[0060] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the pull-up node;

[0061] The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal;

[0062] A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal;

[0063] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal;

[0064] The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal;

[0065] The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal;

[0066] The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal;

[0067] The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal;

[0068] The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal;

[0069] The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node;

[0070] The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal;

[0071] The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal;

[0072] The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0073] The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal;

[0074] The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal;

[0075] The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal;

[0076] The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal;

[0077] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal;

[0078] The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal;

[0079] The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal;

[0080] The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

[0081] In an exemplary embodiment, the first reset subcircuit, the second reset subcircuit and the noise reduction subcircuit are also included; the input subcircuit includes the first transistor and the twenty-first transistor, the output subcircuit includes the second transistor, the third transistor and the capacitor, the first control subcircuit includes at least one of the nineteenth transistor and the twenty-first transistor; the first reset subcircuit includes the fourth transistor, the second reset subcircuit includes the fifth transistor and the sixth transistor, and the noise reduction subcircuit includes the seventh transistor to the eighteenth transistor;

[0082] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0083] The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal;

[0084] A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal;

[0085] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal;

[0086] The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal;

[0087] The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal;

[0088] The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal;

[0089] The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal;

[0090] The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal;

[0091] The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node;

[0092] The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal;

[0093] The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal;

[0094] The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0095] The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal;

[0096] The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal;

[0097] The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal;

[0098] The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal;

[0099] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal;

[0100] The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal;

[0101] The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal;

[0102] The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal;

[0103] The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

[0104] In a second aspect, the present disclosure further provides a shift register, comprising: an input subcircuit, an output subcircuit, and a second control subcircuit;

[0105] The input subcircuit is electrically connected to the signal input terminal and the control node respectively, and is configured to provide a signal to the control node under the control of the signal input terminal;

[0106] The second control subcircuit is electrically connected to the control node and the pull-up node, respectively, and is configured to provide the signal of the control node to the pull-up node under the control of the signal of the control node;

[0107] The output subcircuit is electrically connected to the first output terminal, the pull-up node and the clock signal terminal respectively, and is configured to provide a signal from the clock signal terminal to the first output terminal under the control of a signal from the pull-up node.

[0108] In an exemplary embodiment, the invention further comprises: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; the input subcircuit comprises: a first transistor, the output subcircuit comprises: a second transistor, a third transistor and a capacitor, the second control subcircuit comprises: a twenty-first transistor; the first reset subcircuit comprises: a fourth transistor, the second reset subcircuit comprises: a fifth transistor and a sixth transistor, the noise reduction subcircuit comprises: a seventh transistor to an eighteenth transistor;

[0109] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node;

[0110] The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal;

[0111] A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal;

[0112] A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal;

[0113] The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal;

[0114] The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal;

[0115] The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal;

[0116] The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal;

[0117] The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal;

[0118] The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node;

[0119] The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal;

[0120] The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal;

[0121] The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node;

[0122] The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal;

[0123] The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal;

[0124] The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal;

[0125] The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal;

[0126] The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal;

[0127] The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal;

[0128] The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

[0129] In a third aspect, the present disclosure further provides a gate driving circuit, comprising: a plurality of cascaded shift registers as described above.

[0130] In an exemplary embodiment, the gate driving circuit is provided in a display device, the display device is further provided with a gate line, and the shift register includes an output subcircuit;

[0131] When the output sub-circuit includes the first output terminal, the first output terminal of any level of shift register is electrically connected to the gate line, the first output terminal of the shift register at this level is electrically connected to the signal input terminal of the shift register at the next level, and the first output terminal of the shift register at this level is electrically connected to the first reset signal terminal or the second reset signal terminal of the shift register at the previous level.

[0132] In an exemplary embodiment, the gate driving circuit is provided in a display device, the display device is further provided with a gate line, and the shift register includes an output subcircuit;

[0133] When the output sub-circuit includes a first output terminal and a second output terminal, the first output terminal of any level of shift register is electrically connected to the gate line, the second output terminal of the current level of shift register is electrically connected to the signal input terminal of the next level of shift register, and the second output terminal of the current level of shift register is electrically connected to the first reset signal terminal or the second reset signal terminal of the previous level of shift register.

[0134] In a fourth aspect, the present disclosure further provides a display device, comprising the above-mentioned gate driving circuit.

[0135] In a fifth aspect, the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, and the method includes:

[0136] The input subcircuit provides a signal to the pull-up node under the control of the signal at the signal input terminal;

[0137] The output subcircuit provides the signal of the clock signal terminal to the first output terminal under the control of the signal of the pull-up node;

[0138] The control subcircuit provides the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

[0139] In a sixth aspect, the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, and the method comprises:

[0140] The input subcircuit provides a signal to the control node under the control of the signal input terminal;

[0141] The second control subcircuit provides the signal of the control node to the pull-up node under the control of the signal of the control node;

[0142] The output sub-circuit is configured to provide a signal of the clock signal terminal to the first output terminal under the control of a signal of the pull-up node.

[0143] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0144] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0145] Figure 1 A schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure;

[0146] Figure 2 A schematic diagram of a shift register structure provided for an exemplary embodiment Figure 1 ;

[0147] Figure 3 A schematic diagram of the connection of the first control subcircuit provided in an exemplary embodiment Figure 1 ;

[0148] Figure 4 A schematic diagram of the connection of the first control subcircuit provided in an exemplary embodiment Figure 2 ;

[0149] Figure 5 A schematic diagram of the connection of the first control subcircuit provided in an exemplary embodiment Figure 3 ;

[0150] Figure 6 An equivalent circuit of a first control subcircuit provided for an exemplary embodiment Figure 1 ;

[0151] Figure 7 An equivalent circuit of a first control subcircuit provided for an exemplary embodiment Figure 2 ;

[0152] Figure 8 An equivalent circuit of a first control subcircuit provided for an exemplary embodiment Figure 3 ;

[0153] Fig. 9 An equivalent circuit of an input subcircuit provided for an exemplary embodiment Figure 1 ;

[0154] Fig.10 An equivalent circuit of an input subcircuit provided for an exemplary embodiment Figure 2 ;

[0155] Fig.11 An equivalent circuit of an output subcircuit provided for an exemplary embodiment Figure 1 ;

[0156] Fig.12 An equivalent circuit of an output subcircuit provided for an exemplary embodiment Figure 2 ;

[0157] Fig.13 An equivalent circuit diagram of a first reset subcircuit provided as an exemplary embodiment;

[0158] Fig.14 A schematic diagram of a shift register structure provided for an exemplary embodiment Figure 2 ;

[0159] Fig.15 An equivalent circuit diagram of a second reset subcircuit provided as an exemplary embodiment;

[0160] Fig.16 An equivalent circuit diagram of a noise reduction subcircuit provided for an exemplary embodiment;

[0161] Fig.17 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 1 ;

[0162] Fig.18 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 2 ;

[0163] Fig.19 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 3 ;

[0164] Fig. 20 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 4 ;

[0165] Fig.21 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 5 ;

[0166] Fig. 22 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 6 ;

[0167] Fig.23 for Fig.17 and Fig. 20 The working timing diagram of the shift register provided;

[0168] Fig.24 for Fig.18 and Fig.21 The working timing diagram of the shift register provided;

[0169] Fig.25 for Fig.19 and Fig. 22 The working timing diagram of the shift register provided;

[0170] Fig.26 A schematic diagram of the structure of another shift register provided by an embodiment of the present disclosure;

[0171] Fig. 27 An equivalent circuit diagram of a shift register provided for another exemplary embodiment;

[0172] Fig.28 for Fig. 27 The working timing diagram of the shift register provided;

[0173] Fig.29 Schematic diagram of the cascade connection of the gate drive circuit Figure 1 ;

[0174] Fig.30 Schematic diagram of the cascade connection of the gate drive circuit Figure 2 . DETAILED DESCRIPTION

[0175] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0176] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0177] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0178] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0179] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0180] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0181] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0182] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0183] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0184] GOA technology is widely used in flat panel displays because of its advantages such as reducing the border and simplifying the binding process. As the market's requirements for the reliability of displays become higher and higher. The GOA circuit includes multiple shift registers. Some transistors in the shift register will be in a negative bias state during the operation of the shift register, that is, the voltage value of the signal at the gate electrode of the transistor is less than the voltage value of the signal at the first or second electrode of the transistor. In a high temperature and high humidity environment, the characteristics of the transistors under negative bias in the shift register will deteriorate, causing the turn-on voltage of the transistors in the negative bias state to become smaller, which increases the leakage current in the shift register, and the shift register cannot output normally, reducing the display effect of the display product.

[0185] Figure 1 Schematic diagram of the structure of the shift register provided by the embodiment of the present disclosure. Figure 1 As shown, the shift register provided by the embodiment of the present disclosure may include: an input subcircuit, an output subcircuit and a first control subcircuit.

[0186] like Figure 1 As shown, the input subcircuit is electrically connected to the signal input terminal IN and the pull-up node PU, respectively, and is configured to provide a signal to the pull-up node PU under the control of the signal of the signal input terminal IN. The output subcircuit is electrically connected to the first output terminal OUT1, the pull-up node PU and the clock signal terminal CLK, respectively, and is configured to provide the signal of the clock signal terminal CLK to the first output terminal OUT1 under the control of the signal of the pull-up node PU. The first control subcircuit is electrically connected to the control signal terminal CON and the signal input terminal IN, respectively, and is configured to provide the signal of the control signal terminal CON to the signal input terminal IN under the control of the signal of the control signal terminal CON.

[0187] In an exemplary embodiment, the operation process of the shift register includes: a display phase and a non-display phase, the display phase includes: an output phase and a non-output phase, the non-output phase may include: an input phase, and the input phase occurs before the output phase.

[0188] In an exemplary embodiment, the non-display phase may include a power-on phase, a power-off phase, and a blank phase between the display phases.

[0189] In the input stage, the signal at the signal input terminal IN is an effective level signal, wherein the effective level signal at the signal terminal refers to a signal that turns on the transistor connected to the signal terminal.

[0190] In an exemplary embodiment, the signal of the first output terminal OUT1 is a single pulse signal. The first output terminal OUT1 can output the current stage driving signal, or can output the current stage driving signal and the cascade signal.

[0191] In an exemplary embodiment, the signal at the clock signal terminal CLK is a clock signal in the display stage, and the pulse width is adjustable. The signal at the clock signal terminal CLK is a DC signal in the non-display stage.

[0192] In an exemplary embodiment, the signal at the control signal terminal CON may be a single pulse signal in the display phase or the non-display phase.

[0193] In an exemplary embodiment, the first control sub-circuit can control the signal of the signal input terminal IN so that the voltage value of the signal at the signal input terminal IN is greater than the voltage value of the signal of the pull-up node PU in a non-output stage or a partial time period of the non-display stage, or, in the output stage, the voltage value of the signal at the signal input terminal IN is less than the voltage value of the signal of the pull-up node PU, thereby improving the characteristics of some transistors in the output sub-circuit, reducing the leakage current of the shift register, ensuring the normal output of the shift register, improving the reliability of the shift register, and enhancing the display effect of the display product.

[0194] In an exemplary embodiment, Figure 2 A schematic diagram of a shift register structure provided for an exemplary embodiment Figure 1 .like Figure 2 As shown, the shift register may further include: a first reset subcircuit. The first reset subcircuit is electrically connected to the total reset signal terminal TRST, the pull-up node PU and the first power supply terminal V1, respectively, and is configured to provide a signal of the first power supply terminal V1 to the pull-up node PU under the control of the total reset signal terminal TRST.

[0195] In an exemplary embodiment, the total reset signal terminal TRST is a valid level signal in a part of the non-display phase and an invalid level signal in the display phase, wherein the invalid level signal of the signal terminal is a signal that disconnects the transistor connected to the signal terminal.

[0196] In an exemplary embodiment, the first power terminal V1 continuously provides a low level signal in the display stage and the non-display stage.

[0197] In an exemplary embodiment, Figure 3 A schematic diagram of the connection of the first control subcircuit provided in an exemplary embodiment Figure 1 , Figure 4 A schematic diagram of the connection of the first control subcircuit provided in an exemplary embodiment Figure 2 , Figure 5 A schematic diagram of the connection of the first control subcircuit provided in an exemplary embodiment Figure 3 .like Figures 3 to 5 As shown, the control signal terminal CON includes: at least one of a first control signal terminal CON1 and a second control signal terminal CON2. Figure 3 The control signal terminal CON includes: a first control signal terminal CON1 as an example for explanation, Figure 4 The control signal terminal CON includes: the second control signal terminal CON2 as an example for explanation, Figure 5 The description is made by taking an example that the control signal terminal CON includes: a first control signal terminal CON1 and a second control signal terminal CON2.

[0198] In an exemplary embodiment, Figure 3 and Figure 5 As shown, the first control signal terminal CON1 is electrically connected to the total reset signal terminal TRST, that is, the first control signal terminal CON1 can be the same signal terminal as the total reset signal terminal TRST. Exemplarily, the first control signal terminal CON1 and the total reset signal terminal TRST can be connected to the same signal line, or can be connected to different signal lines with the same signal.

[0199] In an exemplary embodiment, the signal at the first control signal terminal CON1 is a valid level signal during a partial period of the non-display phase.

[0200] In an exemplary embodiment, Figure 4 and Figure 5 As shown, the second control signal terminal CON2 is electrically connected to the first output terminal OUT1, that is, the second control signal terminal CON2 and the first output terminal OUT1 are the same signal terminal. Exemplarily, the second control signal terminal CON2 and the first output terminal OUT1 can be connected to the same signal line, or can be connected to different signal lines with the same signal.

[0201] In an exemplary embodiment, the signal of the second control signal terminal CON2 is a valid level signal in the output stage.

[0202] In an exemplary embodiment, Figure 6 An equivalent circuit of a first control subcircuit provided for an exemplary embodiment Figure 1 .like Figure 6As shown, when the control signal terminal CON includes the first control signal terminal CON1, the first control subcircuit may include: a nineteenth transistor T19. The control electrode and the first electrode of the nineteenth transistor T19 are electrically connected to the first control signal terminal CON1 respectively, and the second electrode of the nineteenth transistor T19 is electrically connected to the signal input terminal IN.

[0203] In an exemplary embodiment, Figure 7 An equivalent circuit of a first control subcircuit provided for an exemplary embodiment Figure 2 .like Figure 7 As shown, in a state where the control signal terminal CON may include the second control signal terminal CON2, the first control subcircuit includes: a twentieth transistor T20. The control electrode and the first electrode of the twentieth transistor T20 are electrically connected to the second control signal terminal CON2 respectively, and the second electrode of the twentieth transistor T20 is electrically connected to the signal input terminal IN.

[0204] In an exemplary embodiment, Figure 8 An equivalent circuit of a first control subcircuit provided for an exemplary embodiment Figure 3 .like Figure 8 As shown, in the state where the control signal terminal CON includes the first control signal terminal CON1 and the second control signal terminal CON2, the control subcircuit may include: a nineteenth transistor T19 and a twentieth transistor T20. The control electrode and the first electrode of the nineteenth transistor T19 are electrically connected to the first control signal terminal CON1, respectively, and the second electrode of the nineteenth transistor T19 is electrically connected to the signal input terminal IN; the control electrode and the first electrode of the twentieth transistor T20 are electrically connected to the second control signal terminal CON2, respectively, and the second electrode of the twentieth transistor T20 is electrically connected to the signal input terminal IN.

[0205] Figures 6 to 8 The exemplary structure of the first control subcircuit is shown. The implementation of the detection node control subcircuit is not limited to this, as long as it can achieve its function.

[0206] In an exemplary embodiment, Fig. 9 An equivalent circuit of an input subcircuit provided for an exemplary embodiment Figure 1 .like Fig. 9 As shown, the input subcircuit may include: a first transistor T1. The control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and the second electrode of the first transistor T1 is electrically connected to the pull-up node PU.

[0207] In an exemplary embodiment, Fig.10 An equivalent circuit of an input subcircuit provided for an exemplary embodiment Figure 2 .like Fig.10 As shown, the input subcircuit may include: a first transistor T1 and a twenty-first transistor T21. The control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and the second electrode of the first transistor T1 is electrically connected to the control node N; the control electrode and the first electrode of the twenty-first transistor T21 are electrically connected to the control node N respectively, and the second electrode of the twenty-first transistor T21 is electrically connected to the pull-up node PU.

[0208] In an exemplary embodiment, the second power terminal V2 continuously provides a high level signal.

[0209] In the exemplary embodiment, the twenty-first transistor corresponds to a unidirectionally conductive diode.

[0210] In an exemplary embodiment, since the voltage value of the signal of the pull-up node PU is greater than the voltage value of the signal input terminal IN in the output stage, the first transistor T1 is in a negative bias state in the output stage. Since the voltage value of the signal of the signal input terminal IN is greater than the voltage value of the signal of the pull-up node PU during a partial period of time in the non-output stage and the non-display stage, the first transistor T1 is in a forward bias state during a partial period of time in the non-output stage and the non-display stage, thereby improving the characteristics of the first transistor.

[0211] Fig. 9 and Fig.10 The exemplary structure of the input subcircuit is shown. The implementation of the input subcircuit is not limited to this, as long as its function can be achieved.

[0212] In an exemplary embodiment, Fig.11 An equivalent circuit of an output subcircuit provided for an exemplary embodiment Figure 1 .like Fig.11 As shown, when the output sub-circuit is electrically connected to the first output terminal OUT1, the output sub-circuit may include: a second transistor T2 and a capacitor C. The control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the first end of the capacitor C is electrically connected to the pull-up node PU, and the second end of the capacitor C is electrically connected to the first output terminal OUT1.

[0213] like Figures 1 to 10 As shown, the output sub-circuit can also be electrically connected to the second output terminal OUT2, and is configured to provide the signal of the clock signal terminal CLK to the second output terminal OUT2 under the control of the signal of the pull-up node PU. When the output sub-circuit is electrically connected to the first output terminal OUT1 and the second output terminal OUT2, the first output terminal OUT1 outputs the driving signal, and the second output terminal OUT2 outputs the cascade signal.

[0214] In an exemplary embodiment, the second output terminal OUT2 has the same signal as the first output terminal OUT1 .

[0215] In an exemplary embodiment, Fig.12 An equivalent circuit of an output subcircuit provided for an exemplary embodiment Figure 2 .like Fig.12 As shown, when the output subcircuit is electrically connected to the first output terminal OUT1 and the second output terminal OUT2, the output subcircuit may include: a second transistor T2, a third transistor T3 and a capacitor C. The control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the second output terminal OUT2; the first end of the capacitor C is electrically connected to the pull-up node PU, and the second end of the capacitor C is electrically connected to the first output terminal OUT1.

[0216] In an exemplary embodiment, the capacitor C can ensure the stability of the signal of the pull-up node PU, and can also ensure the stability of the signal of the first output terminal OUT1, and can improve the reliability of the shift register.

[0217] Fig.11 and Fig.12 The exemplary structure of the output subcircuit is shown. The implementation of the output subcircuit is not limited to this, as long as its function can be achieved.

[0218] In an exemplary embodiment, Fig.13 FIG. 4 is an equivalent circuit diagram of a first reset subcircuit provided in an exemplary embodiment. Fig.13 As shown, the first reset subcircuit may include: a fourth transistor T4, wherein the control electrode of the fourth transistor T4 is electrically connected to the general reset signal terminal TRST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1.

[0219] Fig.13 The exemplary structure of the first reset subcircuit is shown. The implementation of the first reset subcircuit is not limited to this, as long as its function can be achieved.

[0220] In an exemplary embodiment, Fig.14 A schematic diagram of a shift register structure provided for an exemplary embodiment Figure 2 .like Fig.14As shown, the shift register may further include: a second reset subcircuit. The second reset subcircuit is electrically connected to the first reset signal terminal RST1, the second reset signal terminal RST2, the pull-up node PU, the first output terminal OUT1, the first power supply terminal V1 and the third power supply terminal V3, respectively, and is configured to provide a signal of the first power supply terminal V1 to the pull-up node PU and a signal of the third power supply terminal V3 to the first output terminal OUT1 under the control of the signal of the first reset signal terminal RST1 and the second reset signal terminal RST2.

[0221] In an exemplary embodiment, the first reset signal terminal RST1 and the second reset signal terminal RST2 are inactive level signals in the non-display stage and the output stage, and are active level signals in a partial period of the non-output stage.

[0222] In an exemplary embodiment, the non-output stage further includes a reset stage, which occurs after the output stage. The first reset signal terminal RST1 and the second reset signal terminal RST2 are valid level signals in the reset stage and invalid level signals in the remaining stages except the reset stage.

[0223] In an exemplary embodiment, the third power terminal V3 continuously provides a low level signal.

[0224] In an exemplary embodiment, an absolute value of a voltage of a signal at the first power terminal V1 is greater than an absolute value of a voltage of a signal at the third power terminal V3 .

[0225] In an exemplary embodiment, Fig.15 FIG. 4 is an equivalent circuit diagram of a second reset subcircuit provided in an exemplary embodiment. Fig.15 As shown, the second reset subcircuit may include: a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the first reset signal terminal RST1, the first electrode of the fifth transistor T5 is electrically connected to the pull-up node PU, and the second electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1; the control electrode of the sixth transistor T6 is electrically connected to the second reset signal terminal RST2, the first electrode of the sixth transistor T6 is electrically connected to the first output terminal OUT1, and the second electrode of the sixth transistor T6 is electrically connected to the third power supply terminal V3.

[0226] Fig.15 The exemplary structure of the second reset subcircuit is shown. The implementation of the second reset subcircuit is not limited to this, as long as its function can be achieved.

[0227] In an exemplary embodiment, Fig.14As shown, the shift register may further include: a noise reduction subcircuit, which may include: at least one of a first noise reduction subcircuit and a second noise reduction subcircuit. The first noise reduction subcircuit is electrically connected to the fourth power supply terminal V4, the signal input terminal IN, the pull-up node PU, the first output terminal OUT1, the second output terminal OUT2, the first power supply terminal V1 and the third power supply terminal V3, respectively, and is configured to provide the signal of the first power supply terminal V1 to the pull-up node PU and the second output terminal OUT2 and provide the signal of the third power supply terminal V3 to the pull-down node under the control of the signal of the signal input terminal IN, the pull-up node PU and the fourth power supply terminal V4; the second noise reduction subcircuit is electrically connected to the fifth power supply terminal V5, the signal input terminal IN, the pull-up node PU, the first output terminal OUT1, the second output terminal OUT2, the first power supply terminal V1 and the third power supply terminal V3, respectively, and is configured to provide the signal of the first power supply terminal V1 to the pull-up node PU and the second output terminal OUT2 and provide the signal of the third power supply terminal V3 to the pull-down node under the control of the signal of the signal input terminal IN, the pull-up node PU and the fifth power supply terminal V5. Fig.14 The description is made by taking the example that the noise reduction sub-circuit includes: a first noise reduction sub-circuit and a second noise reduction sub-circuit.

[0228] In an exemplary embodiment, the signal of the third power supply terminal V3 is a low level signal in the display stage and the non-display stage. The absolute value of the voltage of the signal of the first power supply terminal V1 is greater than the absolute value of the voltage of the signal of the third power supply terminal V3.

[0229] In an exemplary embodiment, when the noise reduction sub-circuit includes: a first noise reduction sub-circuit, the fourth power supply terminal V4 continuously provides a high level signal. When the noise reduction sub-circuit includes: a second noise reduction sub-circuit, the fifth power supply terminal V5 continuously provides a high level signal.

[0230] In an exemplary embodiment, when the noise reduction sub-circuit includes: a first noise reduction sub-circuit and a second noise reduction sub-circuit, the fourth power supply terminal V4 and the fifth power supply terminal V5 are inverted signals to each other, and the fourth power supply terminal V4 and the fifth power supply terminal V5 are not high-level signals at the same time. Exemplarily, when the fourth power supply terminal V4 is a high-level signal, the fifth power supply terminal V5 is a low-level signal, or, when the fourth power supply terminal V4 is a low-level signal, the fifth power supply terminal V5 is a high-level signal.

[0231] In an exemplary embodiment, the display frame may include: a first display frame and a second display frame, and the first display frame and the second display frame may be alternately arranged. In the first display frame, the signal of the fourth power supply terminal V4 is a high level signal, and the signal of the fifth power supply terminal V5 is a low level signal, and in the second display frame, the signal of the fourth power supply terminal V4 is a low level signal, and the signal of the fifth power supply terminal V5 is a high level signal.

[0232] In an exemplary embodiment, the first noise reduction sub-circuit and the second noise reduction sub-circuit do not perform noise reduction at the same time, which can increase the life of transistors in the first noise reduction sub-circuit and the second noise reduction sub-circuit and improve the reliability of the shift register.

[0233] In an exemplary embodiment, Fig.16 An equivalent circuit diagram of a noise reduction subcircuit provided for an exemplary embodiment. Fig.16 The noise reduction subcircuit includes: a first noise reduction subcircuit and a second noise reduction subcircuit. Fig.16As shown, the first noise reduction sub-circuit includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a thirteenth transistor T13, a fourteenth transistor T14 and a fifteenth transistor T15, and the second noise reduction sub-circuit includes: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a sixteenth transistor T16, a seventeenth transistor T17 and an eighteenth transistor T18.Among them, the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the first pull-down node PD1, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the ninth transistor T9 are electrically connected to the fourth power supply terminal V4 respectively, and the second electrode of the ninth transistor T9 is electrically connected to the first pull-down node PD1; the control electrode of the tenth transistor T10 is electrically connected to the signal input terminal IN The first electrode of the tenth transistor T10 is electrically connected to the second pull-down node PD2, and the second electrode of the tenth transistor T10 is electrically connected to the first power supply terminal V1; the control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, the first electrode of the eleventh transistor T11 is electrically connected to the second pull-down node PD2, and the second electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the twelfth transistor T12 are electrically connected to the fifth power supply terminal V5 respectively, and the second electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; the control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, and the control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1. The first electrode of the transistor T13 is electrically connected to the pull-up node PU, and the second electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1; the control electrode of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, the first electrode of the fourteenth transistor T14 is electrically connected to the first output terminal OUT1, and the second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3; the control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, the first electrode of the fifteenth transistor T15 is electrically connected to the second output terminal OUT2, and the second electrode of the fifteenth transistor T15 is electrically connected to the first power supply terminal V1; the control electrode of the sixteenth transistor T16 is electrically connected to the first pull-down node PD1, the first electrode of the fifteenth transistor T16 is electrically connected to the second output terminal OUT2, and the second electrode of the fifteenth transistor T16 is electrically connected to the first power supply terminal V1; The first electrode of the sixteenth transistor T16 is electrically connected to the pull-up node PU, and the second electrode of the sixteenth transistor T16 is electrically connected to the first power supply terminal V1; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD2, the first electrode of the seventeenth transistor T17 is electrically connected to the first output terminal OUT1, and the second electrode of the seventeenth transistor T17 is electrically connected to the third power supply terminal V3; the control electrode of the eighteenth transistor T18 is electrically connected to the second pull-down node PD2, the first electrode of the eighteenth transistor T18 is electrically connected to the second output terminal OUT2, and the second electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1.

[0234] Fig.17 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 1 , Fig.18 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 2 , Fig.19 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 3 .like Figures 17 to 19 As shown, the input subcircuit in the shift register includes: a first transistor T1, the output subcircuit includes: a second transistor T2, a third transistor T3 and a capacitor C, the first control subcircuit includes: at least one of a nineteenth transistor T19 and a twentieth transistor T20; the first reset subcircuit includes: a fourth transistor T4, the second reset subcircuit includes: a fifth transistor T5 and a sixth transistor T6, and the noise reduction subcircuit includes: a seventh transistor T7 to an eighteenth transistor T18. Figures 17 to 19 The description is made by taking the example that the noise reduction sub-circuit includes: a first noise reduction sub-circuit and a second noise reduction sub-circuit. Fig.17 The first control sub-circuit includes: a nineteenth transistor T19 as an example for explanation, Fig.18 The first control sub-circuit includes the twentieth transistor T20. Fig.19 The description is made by taking an example where the first control subcircuit includes: a nineteenth transistor T19 and a twentieth transistor T20.

[0235] like Figures 17 to 19As shown, the control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and the second electrode of the first transistor T1 is electrically connected to the pull-up node PU; the control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the second output terminal OUT2; the first end of the capacitor C is electrically connected to the pull-up node PU , the second end of the capacitor C is electrically connected to the first output terminal OUT1; the control electrode of the fourth transistor T4 is electrically connected to the total reset signal terminal TRST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1; the control electrode of the fifth transistor T5 is electrically connected to the first reset signal terminal RST1, the first electrode of the fifth transistor T5 is electrically connected to the pull-up node PU, and the second electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1; the control electrode of the sixth transistor T6 is electrically connected to the second reset signal terminal RST2, the first electrode of the sixth transistor T6 is electrically connected to the first output terminal OUT1, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; The control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the first pull-down node PD1, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the ninth transistor T9 are electrically connected to the fourth power supply terminal V4, respectively, and the second electrode of the ninth transistor T9 is electrically connected to the first pull-down node PD1; the control electrode of the tenth transistor T10 is electrically connected to the signal input terminal IN, and the first electrode of the tenth transistor T10 is electrically connected to the second pull-down node PU D2 is electrically connected, the second electrode of the tenth transistor T10 is electrically connected to the first power supply terminal V1; the control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, the first electrode of the eleventh transistor T11 is electrically connected to the second pull-down node PD2, and the second electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the twelfth transistor T12 are electrically connected to the fifth power supply terminal V5 respectively, and the second electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; the control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, the first electrode of the thirteenth transistor T13 is electrically connected to the pull-up node PU, and the second electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1;The control electrode of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, the first electrode of the fourteenth transistor T14 is electrically connected to the first output terminal OUT1, and the second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3; the control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, the first electrode of the fifteenth transistor T15 is electrically connected to the second output terminal OUT2, and the second electrode of the fifteenth transistor T15 is electrically connected to the first power supply terminal V1; the control electrode of the sixteenth transistor T16 is electrically connected to the second pull-down node PD2, the first electrode of the sixteenth transistor T16 is electrically connected to the pull-up node PU, and the second electrode of the sixteenth transistor T16 is electrically connected to the first power supply terminal V1; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD 2, the first electrode of the seventeenth transistor T17 is electrically connected to the first output terminal OUT1, and the second electrode of the seventeenth transistor T17 is electrically connected to the third power supply terminal V3; the control electrode of the eighteenth transistor T18 is electrically connected to the second pull-down node PD2, the first electrode of the eighteenth transistor T18 is electrically connected to the second output terminal OUT2, and the second electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the nineteenth transistor T19 are electrically connected to the first control signal terminal CON1 respectively, and the second electrode of the nineteenth transistor T19 is electrically connected to the signal input terminal IN; the control electrode and the first electrode of the twentieth transistor T20 are electrically connected to the second control signal terminal CON2 respectively, and the second electrode of the twentieth transistor T20 is electrically connected to the signal input terminal IN. ;

[0236] Fig. 20 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 4 , Fig.21 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 5 , Fig. 22 An equivalent circuit of a shift register provided for an exemplary embodiment Figure 6 .like Figure 20 to Figure 22 As shown, the shift register further includes: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; the input subcircuit includes: a first transistor T1 and a twenty-first transistor T21, the output subcircuit includes: a second transistor T2, a third transistor T3 and a capacitor C, the first control subcircuit includes: at least one of the nineteenth transistor T19 and the twentieth transistor T20; the first reset subcircuit includes: a fourth transistor T4, the second reset subcircuit includes: a fifth transistor T5 and a sixth transistor T6, and the noise reduction subcircuit includes: a seventh transistor T7 to an eighteenth transistor T18. Figure 20 to Figure 22 The description is made by taking the example that the noise reduction sub-circuit includes: a first noise reduction sub-circuit and a second noise reduction sub-circuit. Fig. 20 The first control sub-circuit includes: a nineteenth transistor T19 as an example for explanation, Fig.21The first control sub-circuit includes the twentieth transistor T20. Fig. 22 The description is made by taking an example where the first control subcircuit includes: a nineteenth transistor T19 and a twentieth transistor T20.

[0237] like Figure 20 to Figure 22As shown, the control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and the second electrode of the first transistor T1 is electrically connected to the control node; the control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the second output terminal OUT2; the first end of the capacitor C is electrically connected to the pull-up node PU, and the first end of the capacitor C is electrically connected to the pull-up node PU. The second end of the capacitor C is electrically connected to the first output terminal OUT1; the control electrode of the fourth transistor T4 is electrically connected to the total reset signal terminal TRST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1; the control electrode of the fifth transistor T5 is electrically connected to the first reset signal terminal RST1, the first electrode of the fifth transistor T5 is electrically connected to the pull-up node PU, and the second electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1; the control electrode of the sixth transistor T6 is electrically connected to the second reset signal terminal RST2, the first electrode of the sixth transistor T6 is electrically connected to the first output terminal OUT1, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; The control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the first pull-down node PD1, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the ninth transistor T9 are electrically connected to the fourth power supply terminal V4, respectively, and the second electrode of the ninth transistor T9 is electrically connected to the first pull-down node PD1; the control electrode of the tenth transistor T10 is electrically connected to the signal input terminal IN, and the first electrode of the tenth transistor T10 is electrically connected to the second pull-down node PD 2, the second electrode of the tenth transistor T10 is electrically connected to the first power supply terminal V1; the control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, the first electrode of the eleventh transistor T11 is electrically connected to the second pull-down node PD2, and the second electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the twelfth transistor T12 are electrically connected to the fifth power supply terminal V5 respectively, and the second electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; the control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, the first electrode of the thirteenth transistor T13 is electrically connected to the pull-up node PU, and the second electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1;The control electrode of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, the first electrode of the fourteenth transistor T14 is electrically connected to the first output terminal OUT1, and the second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3; the control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, the first electrode of the fifteenth transistor T15 is electrically connected to the second output terminal OUT2, and the second electrode of the fifteenth transistor T15 is electrically connected to the first power supply terminal V1; the control electrode of the sixteenth transistor T16 is electrically connected to the second pull-down node PD2, the first electrode of the sixteenth transistor T16 is electrically connected to the pull-up node PU, and the second electrode of the sixteenth transistor T16 is electrically connected to the first power supply terminal V1; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD2, the first electrode of the seventeenth transistor T17 is electrically connected to the first output terminal OUT 1, the second electrode of the seventeenth transistor T17 is electrically connected to the third power supply terminal V3; the control electrode of the eighteenth transistor T18 is electrically connected to the second pull-down node PD2, the first electrode of the eighteenth transistor T18 is electrically connected to the second output terminal OUT2, and the second electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the nineteenth transistor T19 are electrically connected to the first control signal terminal CON1, respectively, and the second electrode of the nineteenth transistor T19 is electrically connected to the signal input terminal IN; the control electrode and the first electrode of the twentieth transistor T20 are electrically connected to the second control signal terminal CON2, respectively, and the second electrode of the twentieth transistor T20 is electrically connected to the signal input terminal IN; the control electrode and the first electrode of the twenty-first transistor T21 are electrically connected to the control node, respectively, and the second electrode of the twenty-first transistor T21 is electrically connected to the pull-up node PU.;

[0238] In an exemplary embodiment, the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).

[0239] In an exemplary embodiment, all transistors in the shift register are N-type transistors. For example, all transistors in the shift register may be metal oxide transistors. Since metal oxide transistors have higher mobility and lower leakage current, all transistors in the shift register are metal oxide transistors, which can improve the refresh rate of display products, realize high-frequency display, and can also realize low-frequency display, thereby reducing power consumption.

[0240] for Figures 17 to 22In any shift register provided, in the display stage and the non-display stage, the signals of the first power supply terminal V1 and the third power supply terminal V3 are low-level signals. The signal of the clock signal terminal CLK is a clock signal in the display stage, and the signal of the clock signal terminal CLK is a low-level signal in the non-display stage. The fourth power supply terminal V4 and the fifth power supply terminal V5 are constant voltage signals in any display frame, wherein, in the first display frame, the fourth power supply terminal V4 is a high-level signal, the ninth transistor T9 is continuously turned on, the fifth power supply terminal V5 is a low-level signal, and the twelfth transistor T12 is continuously turned off. In the second display frame, the fourth power supply terminal V4 is a low-level signal, the ninth transistor T9 is continuously turned off, the fifth power supply terminal V5 is a high-level signal, and the twelfth transistor T12 is continuously turned on. The fourth power terminal V4 is switched from a first level signal to a second level signal during a time period when the signal at the total reset signal terminal TRST is a valid level signal, and the fifth power terminal V5 is switched from a second level signal to a first level signal during a time period when the signal at the total reset signal terminal TRST is a valid level signal. Exemplarily, when the first level signal is a high level signal, the second level signal is a low level signal, and when the first level signal is a low level signal, the second level signal is a high level signal.

[0241] Fig.23 for Fig.17 and Fig. 20 The working timing diagram of the shift register is provided. Fig.23 The description is made by taking the case where all transistors in the shift register unit are N-type transistors as an example.

[0242] In an exemplary embodiment, Fig.23 As shown, when the signal at the total reset signal terminal TRST is a valid level signal, the signal at the second power supply terminal V2 is a low level signal, and when the signal at the total reset signal terminal TRST is an invalid level signal, the signal at the second power supply terminal V2 is a high level signal.

[0243] Combination Fig.17 and Fig.23 As shown, Fig.17 The working process of the provided shift register in the display stage may include the following stages:

[0244] In the first stage P11, ie the input stage, the signal at the signal input terminal IN is a high level signal, and the signals at the clock signal terminal CLK, the first reset signal terminal RST1, the second reset signal terminal RST2, the first control signal terminal CON1 and the total reset signal terminal TRST are low level signals. The first control signal terminal CON1 is a low level signal, the nineteenth transistor T19 is disconnected, the signal of the signal input terminal IN will not be pulled low, the signal of the signal input terminal IN is a high level signal, the first transistor T1 is turned on, the high level signal of the second power supply terminal V2 or the signal input terminal IN is written into the pull-up node PU, the pull-up node PU is pulled high, the seventh transistor T7 and the tenth transistor T10 are turned on, the low level signal of the first power supply terminal V1 is written into the first pull-down node PD1 and the second pull-down node PD2, the signal of the pull-up node PU is a high level signal, the second transistor T2 and the third transistor T3 are turned on, the low level signal of the clock signal terminal CLK is written into the first output terminal OUT1 and the second output terminal OUT2, the eighth transistor T8 and the eleventh transistor T11 are turned on, and the low level signal of the first power supply terminal V1 is continuously written into the first pull-down node PD1 and the second pull-down node PD2. The first pull-down node PD1 and the second pull-down node PD2 continue to be low-level signals, and the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are disconnected. In this stage, the signal of the pull-up node PU is a high-level signal, and the signals of the first pull-down node PD1, the second pull-down node PD2, the first output terminal OUT1 and the second output terminal OUT2 are low-level signals.

[0245] In the first stage, when the shift register is in the first display frame, the ninth transistor T9 is turned on and the twelfth transistor T12 is turned off. Although the ninth transistor T9 is turned on, the high level signal of the fourth power supply terminal V4 will pull up the signal of the first pull-down node PD1, but because the seventh transistor T7, the eighth transistor T8, the tenth transistor T10 and the eleventh transistor T11 are continuously turned on, the signal of the first pull-down node PD1 will still be pulled down to a low level signal. Similarly. When the shift register is in the second display frame, the ninth transistor T9 is turned off and the twelfth transistor T12 is turned on. Although the twelfth transistor T12 is turned on, the high level signal of the fifth power supply terminal V5 will pull up the signal of the second pull-down node PD2, but because the seventh transistor T7, the eighth transistor T8, the tenth transistor T10 and the eleventh transistor T11 are continuously turned on, the signal of the second pull-down node PD2 is still pulled down to a low level signal. Regardless of whether the shift register is in the first display frame or the second display frame, the first pull-down node PD1 and the second pull-down node PD2 continue to be low level signals in the first stage.

[0246] In the second stage P12, ie, the output stage, the clock signal terminal CLK is a high level signal, and the signals of the first control signal terminal CON1, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2 and the total reset signal terminal TRST are low level signals. The signal of the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal of the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7 and the tenth transistor T10 are disconnected, and under the bootstrap effect of the capacitor C, the pull-up node PU is pulled high, the second transistor T2 and the third transistor T3 are turned on, the high-level signal of the clock signal terminal CLK is written into the first output terminal OUT1 and the second output terminal OUT2, the eighth transistor T8 and the eleventh transistor T11 are turned on, the low-level signal of the first power supply terminal V1 is continuously written into the first pull-down node PD1 and the second pull-down node PD2, the first pull-down node PD1 and the second pull-down node PD2 are continuously low-level signals, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are disconnected. In this stage, the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 are high-level signals, and the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals.

[0247] In the second stage, when the shift register is in the first display frame, the ninth transistor T9 is turned on and the twelfth transistor T12 is turned off. Although the ninth transistor T9 is turned on, the high-level signal of the fourth power supply terminal V4 will pull up the signal of the first pull-down node PD1, but because the eighth transistor T8 and the eleventh transistor T11 are continuously turned on, the signal of the first pull-down node PD1 is still pulled down to a low-level signal. Similarly. When the shift register is in the second display frame, the ninth transistor T9 is turned off and the twelfth transistor T12 is turned on. Although the twelfth transistor T12 is turned on, the high-level signal of the fifth power supply terminal V5 will pull up the signal of the second pull-down node PD2, but because the eighth transistor T8 and the eleventh transistor T11 are continuously turned on, the signal of the second pull-down node PD2 is still pulled down to a low-level signal. Regardless of whether the shift register is in the first display frame or the second display frame, the first pull-down node PD1 and the second pull-down node PD2 continue to be low-level signals in the second stage.

[0248] In the second stage, the voltage value of the signal at the signal input terminal IN is smaller than the voltage value of the signal at the pull-up node PU, so that the first transistor T1 is in a negative bias state, and the turn-on voltage of the first transistor T1 becomes smaller.

[0249] In the third stage P13, ie, the reset stage, the first reset signal terminal RST1 and the second reset signal terminal RST2 are high level signals, and the signals of the signal input terminal IN, the first control signal terminal CON1, the total reset signal terminal TRST and the clock signal terminal CLK are low level signals. The signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, the low level signal at the first power supply terminal V1 is written into the signal at the pull-up node PU, and the signal at the pull-up node PU is pulled low, the low level signal at the third power supply terminal V3 is written into the first output terminal OUT1, and the signal at the first output terminal OUT1 is pulled low, the signal at the first control signal terminal CON1 is a low level signal, the nineteenth transistor T19 is turned off, the signal at the signal input terminal IN is a low level signal, the first transistor T1, the seventh transistor T7 and the tenth transistor T10 are turned off, the pull-up node PU is a low level signal, the eighth transistor T8 and the eleventh transistor T11 are turned off, the first pull-down node PD1 and the second pull-down node PD2 will not be pulled low by the low level signal at the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high level signal at the fourth power supply terminal V4 is written into the first pull-down node PD1, the thirteenth transistor T13 and the fourteenth transistor T The twelfth transistor T12 is turned on, the high level signal of the fifth power supply terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, and the low level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high level signal of the fifth power supply terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0250] In the fourth stage P14, ie the first noise reduction stage, the signal at the clock signal terminal CLK is a high level signal, and the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, the first control signal terminal CON1 and the total reset signal terminal TRST are low level signals. The signal at the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7 and the tenth transistor T10 are disconnected, the signal at the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written into the pull-up node PU, the signal at the pull-up node PU maintains the low-level signal of the previous stage, the second transistor T2, the third transistor T3, the eighth transistor T8 and the eleventh transistor T11 are disconnected, the first pull-down node PD1 and the second pull-down node PD2 will not be pulled down by the low-level signal at the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 is written into the first pull-down node PD1, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, and the low-level signal at the first power supply terminal V1 is written into the pull-up node PU and The second output terminal OUT2, the low level signal of the third power terminal V3 is written into the first output terminal OUT1, the twelfth transistor T12 is disconnected, the second pull-down node PD2 maintains the low level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are disconnected, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high level signal of the fifth power terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low level signal of the first power terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low level signal of the third power terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is disconnected, the first pull-down node PD1 maintains the low level signal of the previous stage, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are disconnected.

[0251] In the fifth stage P15, ie, the second noise reduction stage, the clock signal terminal CLK, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, the first control signal terminal CON1 and the total reset signal terminal TRST are low level signals. The signal at the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7 and the tenth transistor T10 are disconnected, the signal at the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written into the pull-up node PU, the signal at the pull-up node PU maintains the low-level signal of the previous stage, the second transistor T2, the third transistor T3, the eighth transistor T8 and the eleventh transistor T11 are disconnected, the first pull-down node PD1 and the second pull-down node PD2 will not be pulled down by the low-level signal at the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 is written into the first pull-down node PD1, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, and the low-level signal at the first power supply terminal V1 is written into the pull-up node PU and The second output terminal OUT2, the low level signal of the third power terminal V3 is written into the first output terminal OUT1, the twelfth transistor T12 is disconnected, the second pull-down node PD2 maintains the low level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are disconnected, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high level signal of the fifth power terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low level signal of the first power terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low level signal of the third power terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is disconnected, the first pull-down node PD1 maintains the low level signal of the previous stage, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are disconnected.

[0252] The working process of the shift register unit further includes: a plurality of fourth phases P14 and fifth phases P15, and the fourth phases P14 and the fifth phases P15 work alternately.

[0253] The fourth stage P14 and the fifth stage P15 can ensure that the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 of the shift register are continuously low-level signals, which can reduce the noise of the shift register and improve the reliability of the shift register.

[0254] like Fig.23 As shown, Fig.17 The working process of the provided shift register in the non-display stage may include the following stages:

[0255] In the sixth stage P16, the signals of the total reset signal terminal TRST and the first control signal terminal CON1 are high-level signals, the fourth transistor T4 and the nineteenth transistor T19 are turned on, the high-level signal of the first control signal terminal CON1 is written into the signal input terminal IN, the signal of the signal input terminal IN is a high-level signal, and a path is formed between the signal input terminal IN or the second power supply terminal V2 and the first power supply terminal V1, so that the voltage value of the signal of the pull-up node PU is less than the voltage value of the signal of the signal input terminal IN. In addition, since the total reset signal terminal TRST connected to all shift registers is a high-level signal at the same time, the signals of the signal input terminal IN connected to all shift registers are all high-level signals. Due to the cascade relationship of the shift registers, the second output terminal OUT2 of the shift register at this level will be electrically connected to the signal input terminal IN of the shift registers at other levels, and the first reset signal terminal RST1 and the second reset signal terminal RST2 of the shift register at this level will be electrically connected to the second output terminal OUT2 of the shift registers at other levels. Therefore, the signals of the second output terminal OUT2, the first reset signal terminal RST1 and the second reset signal terminal RST2 of all shift registers are high-level signals in the sixth stage P16, the signals of the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, the signal of the first power supply terminal V1 is written into the pull-up node PU, and the signal of the third power supply terminal V3 is written into the first output terminal OUT1, which can avoid the shift register from outputting in the non-display stage and ensure the reliability of the shift register.

[0256] Since the voltage value of the signal at the signal input terminal IN in the sixth stage is greater than the voltage value of the signal at the pull-up node PU, the first transistor T1 is in a forward bias state, and the turn-on voltage of the first transistor T1 becomes larger, which can improve the transistor characteristic drift of the first transistor T1 caused by being in a negative bias state in the second stage, and the transistor characteristics of the first transistor T1 can be restored.

[0257] In an exemplary embodiment, since the second power supply terminal V2 is a low-level signal in the sixth stage P16 and the signal at the signal input terminal IN is a high-level signal, the voltage value of the signal at the pull-up node PU of the shift register provided with the first transistor T1 connected to the second power supply terminal V2 in the sixth stage P16 is less than the voltage value of the signal at the pull-up node PU of the shift register provided with the first transistor T1 connected to the signal input terminal in the sixth stage P16, that is, the shift register provided with the first transistor T1 connected to the second power supply terminal V2 has a stronger improvement degree for the transistor characteristic drift caused by the first transistor T1 being in a negative bias state in the second stage than the shift register provided with the first transistor T1 connected to the signal input terminal.

[0258] Fig. 20 The shift registers provided with Fig.17 Compared with the shift register provided, a twenty-first transistor T21 is added, combined with Fig. 20 and Fig.23 As shown, Fig. 20 The working process of the provided shift register in the display stage may include the following stages:

[0259] Fig. 20 The shift register provided in the first stage P11 and Fig.17 Compared with the first stage P11 of the provided shift register, the working processes of the first transistor T1 to the nineteenth transistor T19 are the same, the difference is that the first transistor T1 is turned on, the high-level signal of the second power supply terminal V2 or the signal input terminal IN is written into the control node N, the twenty-first transistor T21 is turned on, the high-level signal of the control node N is written into the pull-up node PU, and the pull-up node PU is pulled high by the signal of the control node N.

[0260] Fig. 20 The shift register provided in the second stage P12 is connected to Fig.17 Compared with the shift register provided in the second stage P12, the working processes of the first transistor T1 to the nineteenth transistor T19 are the same, the difference is that the signal of the control node N maintains the high level signal of the previous stage, and the twenty-first transistor T21 is continuously turned on.

[0261] In the second stage, the voltage value of the signal at the signal input terminal IN is smaller than the voltage value of the signal at the control node N, so that the first transistor T1 is in a negative bias state, and the turn-on voltage of the first transistor T1 becomes smaller. Fig. 20 The shift registers provided with Fig.17 Compared with the shift register provided, due to the existence of the twenty-first transistor T21, the voltage value of the signal at the control node N in the second stage is smaller than the voltage value of the signal at the pull-up node PU, that is, Fig. 20 The absolute value of the difference between the voltage value of the signal at the signal input terminal of the shift register and the voltage value of the signal at the control node N is less than Fig.17 The absolute value of the difference between the voltage value of the signal at the signal input terminal of the shift register and the voltage value of the signal at the pull-up node is provided, that is, Fig. 20 Provided that the first transistor in the shift register has a negative bias voltage level less than Fig.17 providing a negative bias level for the first transistor in the shift register, Fig. 20 The provided shift register region can prevent the characteristic drift of the first transistor to a certain extent.

[0262] Fig. 20 The shift register provided in the third stage P13 is connected to Fig.17Compared with the third stage P13 of the provided shift register, the working processes of the first transistor T1 to the nineteenth transistor T19 are the same, the difference is that the control node N maintains the high-level signal of the previous stage, the twenty-first transistor T21 is turned on, and since the low-level signal of the pull-up node PU is also written into the control node N, the twenty-first transistor T21 is disconnected.

[0263] The control node N is pulled down to a low level signal in the third stage, and the twenty-first transistor T21 is turned off. Fig. 20 The shift register provided in the fourth stage P14 works in the same way as Fig.17 The shift register provided has the same working process as in the fourth stage P14, Fig. 20 The working process of the shift register in the fifth stage P15 is provided with Fig.17 The working process of the provided shift register in the fifth stage P15 is the same and will not be repeated here.

[0264] Fig. 20 The working process of the provided shift register in the non-display stage may include the following stages:

[0265] In the sixth phase P16, when the first transistor T1 is electrically connected to the signal input terminal IN, Fig. 20 The shift registers provided with Fig.17 The first transistor T1 to the nineteenth transistor T19 in the shift register provided have the same working process, except that the first transistor T1 is turned on, the high level signal of the signal input terminal IN is written into the control node N, the twenty-first transistor T21 is turned on, and a path is formed between the signal input terminal IN and the first power supply terminal V1, so that the voltage value of the signal at the control node N is less than the signal voltage value of the signal input terminal IN. When the first transistor T1 is electrically connected to the second power supply terminal V2, Fig. 20 The shift registers provided with Fig.17 The working processes of the first transistor T1 to the nineteenth transistor T19 in the provided shift register are the same, except that the first transistor T1 is turned on, the low-level signal of the second power supply terminal V2 is written to the control node N, the twenty-first transistor T21 is turned off, and the voltage value of the signal at the control node N is less than the signal voltage value of the signal input terminal IN.

[0266] Since the voltage value of the signal at the signal input terminal IN in the sixth stage is greater than the voltage value of the signal at the pull-up node PU, the first transistor T1 is in a forward bias state, and the turn-on voltage of the first transistor T1 becomes larger, which can improve the transistor characteristic drift of the first transistor T1 caused by being in a negative bias state in the second stage, and the transistor characteristics of the first transistor T1 can be restored.

[0267] when Fig.17The shift registers provided are Fig. 20 Compared with the shift register provided, when the first transistor T1 of the two is electrically connected to the signal input terminal IN, Fig. 20 The resistance of the path between the signal input terminal IN and the first power supply terminal V1 of the shift register in the sixth stage is greater than Fig.17 The resistance of the path between the signal input terminal IN and the first power supply terminal V1 of the shift register in the sixth stage is provided, so that Fig. 20 The voltage value of the signal at the control node N of the shift register provided is less than Fig.17 The voltage value of the signal at the pull-up node PU of the shift register provided, that is, Fig. 20 The forward bias voltage of the first transistor T1 in the shift register is provided to be greater than Fig.17 Provides the forward bias level of the first transistor T1 in the shift register.

[0268] Fig.24 for Fig.18 and Fig.21 The working timing diagram of the shift register is provided. Fig.24 The description is made by taking the case where all transistors in the shift register unit are N-type transistors as an example.

[0269] In an exemplary embodiment, the second power terminal V2 is a DC signal, and is a high level signal.

[0270] Combination Fig.18 and Fig.24 As shown, Fig.18 The working process of the provided shift register in the display stage may include the following stages:

[0271] In the first stage P21, i.e., the input stage, the signal at the signal input terminal IN is a high level signal, and the signals at the clock signal terminal CLK, the first reset signal terminal RST1, the second reset signal terminal RST2, the second control signal terminal CON2, and the total reset signal terminal TRST are low level signals. The second control signal terminal CON2 is a low level signal, the twentieth transistor T20 is disconnected, and the signal at the signal input terminal IN is not pulled low. The working process of the first transistor T1 to the eighteenth transistor T18 is the same as Fig.17 The operation processes of the first transistor T1 to the eighteenth transistor T18 in the first phase P11 of the shift register provided are the same and will not be described again.

[0272] In the second stage P22, i.e., the output stage, the second control signal terminal CON2 and the clock signal terminal CLK are high level signals, and the signals of the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are low level signals. The signal of the second control signal terminal CON2 is a high level signal, the twentieth transistor T20 is turned on, the signal of the signal input terminal IN is pulled high, the first transistor T1 is turned on, the high level signal of the second power supply terminal V2 or the signal input terminal IN is continuously written into the pull-up node PU, and the working process of the second transistor T2 to the eighteenth transistor T18 is the same as that of the first transistor T2. Fig.17 The operation processes of the second transistor T2 to the eighteenth transistor T18 in the second phase P12 of the shift register are the same and will not be described in detail herein.

[0273] In the second stage, since the signal at the signal input terminal IN is a high level signal, the first transistor T1 will not be in a negative bias state in the second stage P22, and the characteristics of the first transistor T1 will not drift.

[0274] In the third stage P23, i.e., the reset stage, the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, and the signals of the signal input terminal IN, the second control signal terminal CON2, the total reset signal terminal TRST and the clock signal terminal CLK are low-level signals. The signal of the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, and the signal of the second control signal terminal CON2 will not be written into the signal input terminal IN. Since the signal input terminal IN of the current-stage shift register is electrically connected to the second output terminal OUT2 of the previous-stage shift register, in this stage, the signal of the second output terminal OUT2 of the previous-stage shift register is a low-level signal. Therefore, the signal of the signal input terminal IN of the current-stage shift register will be pulled down in this stage and is a low-level signal. The working process of the first transistor T1 to the eighteenth transistor T18 is the same as that of the first transistor T1 to the eighteenth transistor T18. Fig.17 The operation process of the first transistor T1 to the eighteenth transistor T18 in the third phase P13 of the shift register is the same.

[0275] In the third stage P23, since the second output terminal OUT2 of the shift register at this stage is electrically connected to the signal input terminal IN of the shift register at the next stage, and since the signal input terminal IN of the shift register at the next stage is a high level signal at this stage, the second output terminal OUT2 of the shift register at this stage is a high level signal at this stage.

[0276] In the fourth stage P24, i.e., the first noise reduction stage, the signals at the first reset signal terminal RST1, the second reset signal terminal RST2, and the clock signal terminal CLK are high-level signals, and the signal input terminal IN, the second control signal terminal CON2, and the total reset signal terminal TRST are low-level signals. The signal at the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written into the pull-up node PU, and the signal at the pull-up node PU maintains the low-level signal of the previous stage, the signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the working process of the first transistor T1 to the fourth transistor T4 and the seventh transistor T7 to the eighteenth transistor T18 is the same as Fig.17 The operation processes of the first transistor T1 to the fourth transistor T4 and the seventh transistor T7 to the eighteenth transistor T18 in the fourth phase P14 of the provided shift register are the same and will not be described in detail herein.

[0277] In the fifth stage P25, i.e., the second noise reduction stage, the clock signal terminal CLK, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, the second control signal terminal CON2 and the total reset signal terminal TRST are low level signals. The signal of the second control signal terminal CON2 is a low level signal, the twentieth transistor T20 is disconnected, the signal of the second power supply terminal V2 or the signal input terminal IN cannot be written into the pull-up node PU, and the signal of the pull-up node PU maintains the low level signal of the previous stage, and the working process of the first transistor T1 to the eighteenth transistor T18 is the same as that of the first transistor T1 to the eighteenth transistor T18. Fig.17 The operation process of the first transistor T1 to the eighteenth transistor T18 in the fifth stage P25 of the shift register is the same and will not be repeated here.

[0278] The working process of the shift register unit further includes: a plurality of fourth phases P14 and fifth phases P15, and the fourth phases P14 and the fifth phases P15 work alternately.

[0279] The fourth stage P14 and the fifth stage P15 can ensure that the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 of the shift register are continuously low-level signals, which can reduce the noise of the shift register and improve the reliability of the shift register.

[0280] Fig.18 The working process of the provided shift register in the non-display stage may include the following stages:

[0281] In the sixth stage P26, the signal of the total reset signal terminal TRST is a high-level signal, and the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2 and the second control signal terminal CON2 are low-level signals. The signal of the total reset signal terminal TRST is a high-level signal, the fourth transistor T4 is turned on, and the low-level signal of the first power supply terminal V1 is written into the pull-up node PU, pulling the signal of the pull-up node PU low.

[0282] Fig.21 The shift registers provided with Fig.18 Compared with the shift register provided, a twenty-first transistor T21 is added, combined with Fig.21 and Fig.24 As shown, Fig.21 The working process of the provided shift register in the display stage may include the following stages:

[0283] Fig.21 The shift register provided in the first stage P21 and Fig.18 Compared with the first stage P21 of the provided shift register, the working processes of the first transistor T1 to the eighteenth transistor T18 and the twentieth transistor T20 are the same, the difference is that the first transistor T1 is turned on, the high-level signal of the second power supply terminal V2 or the signal input terminal IN is written into the control node N, the twenty-first transistor T21 is turned on, the high-level signal of the control node N is written into the pull-up node PU, and the pull-up node PU is pulled high by the signal of the control node N.

[0284] Fig.21 The shift register provided in the second stage P22 is connected to Fig.18 Compared with the shift register provided in the second stage P22, the working processes of the first transistor T1 to the eighteenth transistor T18 and the twentieth transistor T20 are the same, the difference is that the signal of the control node N maintains the high level signal of the previous stage, and the twenty-first transistor T21 is continuously turned on.

[0285] Fig.21 The shift registers provided with Fig.18 Compared with the shift register provided, due to the existence of the twenty-first transistor T21, the voltage value of the signal at the control node N in the second stage is smaller than the voltage value of the signal at the pull-up node PU, that is, Fig.21 The absolute value of the difference between the voltage value of the signal at the signal input terminal of the shift register and the voltage value of the signal at the control node N is less than Fig.18 The absolute value of the difference between the voltage value of the signal at the signal input terminal of the shift register and the voltage value of the signal at the pull-up node is provided, that is, Fig.21 Provided that the first transistor in the shift register has a negative bias voltage level less than Fig.18providing a negative bias level for the first transistor in the shift register, Fig.21 The provided shift register region can prevent the characteristic drift of the first transistor to a certain extent.

[0286] Fig.21 The shift register provided in the third stage P23 is Fig.18 The working process of the provided shift register in the third stage P23 is the same and will not be described again.

[0287] Fig.21 The shift register provided in the fourth stage P24 works in the same way as Fig.18 The working process of the provided shift register in the fourth stage P24 is the same and will not be described again.

[0288] Fig.21 The working process of the shift register in the fifth stage P25 is provided with Fig.18 The working process of the provided shift register in the fifth stage P25 is the same and will not be repeated here.

[0289] Fig.21 The shift register provided in the sixth stage P26 of the non-display stage is Fig.18 The working process of the provided shift register in the sixth stage P26 of the non-display phase is the same and will not be described again.

[0290] Fig.25 for Fig.19 and Fig. 22 The working timing diagram of the shift register is provided. Fig.25 The description is made by taking the case where all transistors in the shift register unit are N-type transistors as an example.

[0291] In an exemplary embodiment, Fig.23 As shown, when the signal at the total reset signal terminal TRST is a valid level signal, the signal at the second power supply terminal V2 is a low level signal, and when the signal at the total reset signal terminal TRST is an invalid level signal, the signal at the second power supply terminal V2 is a high level signal.

[0292] Combination Fig.19 and Fig.25 As shown, Fig.19 The working process of the provided shift register in the display stage may include the following stages:

[0293] In the first stage P31, i.e., the input stage, the signal at the signal input terminal IN is a high-level signal, and the signals at the clock signal terminal CLK, the first reset signal terminal RST1, the second reset signal terminal RST2, the first control signal terminal CON1, the second control signal terminal CON2, and the total reset signal terminal TRST are low-level signals. The first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, and the signal at the signal input terminal IN is not pulled low. The working process of the first transistor T1 to the eighteenth transistor T18 is the same as Fig.18 The operation processes of the first transistor T1 to the eighteenth transistor T18 in the first phase P21 of the shift register provided are the same and will not be described again.

[0294] In the second stage P32, i.e., the output stage, the signals at the second control signal terminal CON2 and the clock signal terminal CLK are high level signals, and the signals at the first control signal terminal CON1, the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are low level signals. The signal at the first control signal terminal CON1 is a low level signal, the nineteenth transistor T19 is turned off, the signal at the second control signal terminal CON2 is a high level signal, the twentieth transistor T20 is turned on, and the signal at the signal input terminal IN is pulled high. The working process of the first transistor T1 to the eighteenth transistor T18 is the same as Fig.18 The operation processes of the first transistor T1 to the eighteenth transistor T18 in the second phase P22 of the shift register are the same and will not be described again.

[0295] In the second stage, since the signal at the signal input terminal IN is a high level signal, the first transistor T1 will not be in a negative bias state in the second stage P22, and the characteristics of the first transistor T1 will not drift.

[0296] In the third stage P33, i.e., the reset stage, the signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high level signals, and the signals at the first control signal terminal CON1, the second control signal terminal CON2, the total reset signal terminal TRST, and the clock signal terminal CLK are low level signals. The signal at the first control signal terminal CON1 is a low level signal, the nineteenth transistor T19 is disconnected, the signal at the second control signal terminal CON2 is a low level signal, the twentieth transistor T20 is disconnected, and the signal at the signal input terminal IN is pulled low by the signal at the second output terminal of the previous stage shift register. The working process of the first transistor T1 to the eighteenth transistor T18 is the same as that of the first transistor T1. Fig.18 The operation processes of the first transistor T1 to the eighteenth transistor T18 in the third phase P23 of the shift register are the same and will not be described again.

[0297] In the fourth stage P34, i.e., the first noise reduction stage, the signals at the clock signal terminal CLK, the first reset signal terminal RST1, and the second reset signal terminal RST2 are high-level signals, and the signals at the signal input terminal IN, the first control signal terminal CON1, the second control signal terminal CON2, and the total reset signal terminal TRST are low-level signals. The signal at the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal at the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written into the pull-up node PU, and the signal at the pull-up node PU maintains the low-level signal of the previous stage, and the working process of the first transistor T1 to the eighteenth transistor T18 is the same as that of the first transistor T1 to the eighteenth transistor T18. Fig.18 The operation processes of the first transistor T1 to the eighteenth transistor T18 in the fourth stage P24 of the shift register are the same and will not be described again.

[0298] In the fifth stage P35, i.e., the second noise reduction stage, the signals at the clock signal terminal CLK, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, the first control signal terminal CON1, the second control signal terminal CON2, and the total reset signal terminal TRST are low-level signals. The signal at the first control signal terminal CON1 is a low-level signal, the nineteenth transistor T19 is disconnected, the signal at the second control signal terminal CON2 is a low-level signal, the twentieth transistor T20 is disconnected, the signal at the second power supply terminal V2 or the signal input terminal IN cannot be written into the pull-up node PU, the signal at the pull-up node PU maintains the low-level signal of the previous stage, and the working process of the first transistor T1 to the eighteenth transistor T18 is the same as that of the first transistor T1 to the eighteenth transistor T18. Fig.18 The operation process of the first transistor T1 to the eighteenth transistor T18 in the fifth stage P25 of the shift register is the same and will not be repeated here.

[0299] The working process of the shift register unit further includes: a plurality of fourth phases P14 and fifth phases P15, and the fourth phases P14 and the fifth phases P15 work alternately.

[0300] The fourth stage P14 and the fifth stage P15 can ensure that the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 of the shift register are continuously low-level signals, which can reduce the noise of the shift register and improve the reliability of the shift register.

[0301] Fig.19 The working process of the provided shift register in the non-display stage may include the following stages:

[0302] In the sixth stage P36, the signals at the total reset signal terminal TRST and the first control signal terminal CON1 are high level signals, and the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2 and the second control signal terminal CON2 are low level signals. The signal at the second control signal terminal CON2 is a low level signal, the twentieth transistor T20 is disconnected, and the operation process of the first transistor T1 and the nineteenth transistor T19 is the same as that of the first transistor T20. Fig.17 The working process of the provided shift register in the sixth stage P16 is the same and will not be described again.

[0303] Fig. 22 The shift registers provided with Fig.19 Compared with the shift register provided, a twenty-first transistor T21 is added, combined with Fig. 22 and Fig.25 As shown, Fig. 22 The working process of the provided shift register in the display stage may include the following stages:

[0304] Fig. 22 The shift register provided in the first stage P31 is connected to Fig.19 Compared with the first stage P31 of the provided shift register, the working processes of the first transistor T1 to the twentieth transistor T20 are the same, the difference is that the first transistor T1 is turned on, the high-level signal of the second power supply terminal V2 or the signal input terminal IN is written into the control node N, the twenty-first transistor T21 is turned on, the high-level signal of the control node N is written into the pull-up node PU, and the pull-up node PU is pulled high by the signal of the control node N.

[0305] Fig. 22 The shift register provided in the second stage P32 is connected to Fig.19 Compared with the shift register provided in the second stage P32, the working processes of the first transistor T1 to the twentieth transistor T20 are the same, the difference is that the signal of the control node N maintains the high level signal of the previous stage, and the twenty-first transistor T21 is continuously turned on.

[0306] Fig. 22 The shift registers provided with Fig.19 Compared with the shift register provided, due to the existence of the twenty-first transistor T21, the voltage value of the signal at the control node N in the second stage is smaller than the voltage value of the signal at the pull-up node PU, that is, Fig. 22 The absolute value of the difference between the voltage value of the signal at the signal input terminal of the shift register and the voltage value of the signal at the control node N is less than Fig.19 The absolute value of the difference between the voltage value of the signal at the signal input terminal of the shift register and the voltage value of the signal at the pull-up node is provided, that is, Fig. 22 Provided that the first transistor in the shift register has a negative bias voltage level less than Fig.19 providing a negative bias level for the first transistor in the shift register, Fig. 22 The provided shift register region can prevent the characteristic drift of the first transistor to a certain extent.

[0307] Fig. 22 The shift register provided in the third stage P33 is connected to Fig.19 The working process of the provided shift register in the third stage P33 is the same and will not be repeated here.

[0308] Fig. 22 The shift registers provided are Fig.19 Compared with the shift register provided, due to the existence of the twenty-first transistor T21, the voltage value of the signal at the control node N in the second stage is smaller than the voltage value of the signal at the pull-up node PU, that is, Fig. 22 The absolute value of the difference between the voltage value of the signal at the signal input terminal of the shift register and the voltage value of the signal at the control node N is less than Fig.18 The absolute value of the difference between the voltage value of the signal at the signal input terminal of the shift register and the voltage value of the signal at the pull-up node is provided, that is, Fig. 22 Provided that the first transistor in the shift register has a negative bias voltage level less than Fig.19 providing a negative bias level for the first transistor in the shift register, Fig. 22 The provided shift register region can prevent the characteristic drift of the first transistor to a certain extent.

[0309] Fig. 22 The working process of the shift register in the fourth stage P34 is the same as Fig.19 The working process of the provided shift register in the fourth stage P34 is the same and will not be repeated here.

[0310] Fig. 22 The working process of the shift register in the fifth stage P35 is similar to Fig.19 The working process of the provided shift register in the fifth stage P35 is the same and will not be repeated here.

[0311] Fig. 22 The working process of the provided shift register in the non-display stage may include the following stages:

[0312] In the sixth stage P36, the signals at the total reset signal terminal TRST and the first control signal terminal CON1 are high level signals, the signal at the second control signal terminal CON2 is low level signal, the signal at the second control signal terminal CON2 is low level signal, the twentieth transistor T20 is disconnected, and the operation process of the first transistor T1 to the nineteenth transistor T19 is the same as Fig.19The working processes of the first transistor T1 to the nineteenth transistor T19 in the provided shift register are the same and will not be described in detail herein.

[0313] The embodiment of the present disclosure also provides a shift register, Fig.26 FIG. 1 is a schematic diagram of another shift register structure provided by an embodiment of the present disclosure. Fig.26 As shown, the shift register provided by the embodiment of the present disclosure may include: an input subcircuit, an output subcircuit, and a second control subcircuit. The input subcircuit is electrically connected to the signal input terminal IN and the control node N, respectively, and is configured to provide a signal to the control node N under the control of the signal input terminal IN; the second control subcircuit is electrically connected to the control node N and the pull-up node PU, respectively, and is configured to provide the signal of the control node N to the pull-up node PU under the control of the signal of the control node N; the output subcircuit is electrically connected to the first output terminal OUT1, the pull-up node PU, and the clock signal terminal CLK, respectively, and is configured to provide the signal of the clock signal terminal CLK to the first output terminal OUT1 under the control of the signal of the pull-up node PU.

[0314] The setting of the second control subcircuit in the present disclosure can play a role in voltage division, so that the signal of the control node N can be smaller than the signal of the pull-up node PU in the output stage, thereby reducing the negative bias degree of some transistors in the input subcircuit and improving the reliability of the shift register.

[0315] Fig. 27 FIG. 1 is an equivalent circuit diagram of a shift register provided for another exemplary embodiment. Fig. 27As shown, the shift register may further include: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; the input subcircuit includes: a first transistor T1, the output subcircuit includes: a second transistor T2, a third transistor T3 and a capacitor, the second control subcircuit includes: a twenty-first transistor T21; the first reset subcircuit includes: a fourth transistor T4, the second reset subcircuit includes: a fifth transistor T5 and a sixth transistor T6, and the noise reduction subcircuit includes: a seventh transistor T7 to an eighteenth transistor T18. Among them, the control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN or the second power supply terminal V2, and the second electrode of the first transistor T1 is electrically connected to the control node; the control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the first output terminal OUT1. The first end of the capacitor C is electrically connected to the pull-up node PU, and the second end of the capacitor C is electrically connected to the first output terminal OUT1; the control electrode of the fourth transistor T4 is electrically connected to the total reset signal terminal TRST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1; the control electrode of the fifth transistor T5 is electrically connected to the first reset signal terminal RST1, the first electrode of the fifth transistor T5 is electrically connected to the pull-up node PU, and the second electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1; the control electrode of the sixth transistor T6 is electrically connected to the total reset signal terminal TRST, the first electrode of the fourth transistor T4 is electrically connected to the pull-up node PU, and the second electrode of the fifth transistor T6 is electrically connected to the first power supply terminal V1; The control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the first pull-down node PD1, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the pull-up node PU, the first electrode of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1. The control electrode and the first electrode of the ninth transistor T9 are electrically connected to the fourth power supply terminal V4 respectively, and the second electrode of the ninth transistor T9 is electrically connected to the first pull-down node PD1; the control electrode of the tenth transistor T10 is electrically connected to the signal input terminal IN, the first electrode of the tenth transistor T10 is electrically connected to the second pull-down node PD2, and the second electrode of the tenth transistor T10 is electrically connected to the first power supply terminal V1; the control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, the first electrode of the eleventh transistor T11 is electrically connected to the second pull-down node PD2, and the second electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V1;The control electrode and the first electrode of the twelfth transistor T12 are electrically connected to the fifth power supply terminal V5, respectively, and the second electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; the control electrode of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, the first electrode of the thirteenth transistor T13 is electrically connected to the pull-up node PU, and the second electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1; the control electrode of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, the first electrode of the fourteenth transistor T14 is electrically connected to the first output terminal OUT1, and the second electrode of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3; the control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, the first electrode of the fifteenth transistor T15 is electrically connected to the second output terminal OUT2, and the second electrode of the fifteenth transistor T15 is electrically connected to the first power supply terminal V1 The control electrode of the sixteenth transistor T16 is electrically connected to the second pull-down node PD2, the first electrode of the sixteenth transistor T16 is electrically connected to the pull-up node PU, and the second electrode of the sixteenth transistor T16 is electrically connected to the first power supply terminal V1; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD2, the first electrode of the seventeenth transistor T17 is electrically connected to the first output terminal OUT1, and the second electrode of the seventeenth transistor T17 is electrically connected to the third power supply terminal V3; the control electrode of the eighteenth transistor T18 is electrically connected to the second pull-down node PD2, the first electrode of the eighteenth transistor T18 is electrically connected to the second output terminal OUT2, and the second electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1; the control electrode and the first electrode of the twenty-first transistor T21 are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor T21 is electrically connected to the pull-up node PU.;

[0316] In an exemplary embodiment, the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).

[0317] In an exemplary embodiment, all transistors in the shift register are N-type transistors. For example, all transistors in the shift register may be metal oxide transistors. Since metal oxide transistors have higher mobility and lower leakage current, all transistors in the shift register are metal oxide transistors, which can improve the refresh rate of display products, realize high-frequency display, and can also realize low-frequency display, thereby reducing power consumption.

[0318] Fig.28 for Fig. 27 The working timing diagram of the shift register is provided. Fig.28 The description is made by taking the case where all transistors in the shift register unit are N-type transistors as an example.

[0319] Combination Fig. 27 and Fig.28 As shown, Fig. 27 The working process of the provided shift register in the display stage may include the following stages:

[0320] In the first phase P1, i.e., the input phase, the signal of the signal input terminal IN is a high-level signal, and the signals of the clock signal terminal CLK, the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are low-level signals. The signal of the signal input terminal IN is a high-level signal, the first transistor T1 is turned on, the high-level signal of the second power supply terminal V2 or the signal input terminal IN is written into the control node N, the twenty-first transistor T21 is turned on, the high-level signal of the control node N is written into the pull-up node PU, the pull-up node PU is pulled high, the seventh transistor T7 and the tenth transistor T10 are turned on, the low-level signal of the first power supply terminal V1 is written into the first pull-down node PD1 and the second pull-down node PD2, the signal of the pull-up node PU is a high-level signal, the second transistor T2 and the third transistor T3 are turned on, the low-level signal of the clock signal terminal CLK is written into the first output terminal OUT1 and the second output terminal OUT2, the eighth transistor T8 and the eleventh transistor T11 are turned on, and the low-level signal of the first power supply terminal V1 is continuously written into the first pull-down node PD1 and the second pull-down node PD2. The first pull-down node PD1 and the second pull-down node PD2 continue to be low level signals, and the thirteenth transistor T13 to the eighteenth transistor T18 are turned off. In this stage, the signal of the pull-up node PU is a high level signal, and the signals of the first pull-down node PD1, the second pull-down node PD2, the first output terminal OUT1 and the second output terminal OUT2 are low level signals.

[0321] In the first stage, when the shift register is in the first display frame, the ninth transistor T9 is turned on and the twelfth transistor T12 is turned off. Although the ninth transistor T9 is turned on, the high level signal of the fourth power supply terminal V4 will pull up the signal of the first pull-down node PD1, but because the seventh transistor T7, the eighth transistor T8, the tenth transistor T10 and the eleventh transistor T11 are continuously turned on, the signal of the first pull-down node PD1 is still pulled down to a low level signal. Similarly. When the shift register is in the second display frame, the ninth transistor T9 is turned off and the twelfth transistor T12 is turned on. Although the twelfth transistor T12 is turned on, the high level signal of the fifth power supply terminal V5 will pull up the signal of the second pull-down node PD2, but because the seventh transistor T7, the eighth transistor T8, the tenth transistor T10 and the eleventh transistor T11 are continuously turned on, the signal of the second pull-down node PD2 is still pulled down to a low level signal. Regardless of whether the shift register is in the first display frame or the second display frame, the first pull-down node PD1 and the second pull-down node PD2 continue to be low level signals in the first stage.

[0322] In the second phase P2, ie, the output phase, the signals at the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2 and the total reset signal terminal TRST are low level signals, and the clock signal terminal CLK is a high level signal. The signal at the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7 and the tenth transistor T10 are disconnected, the signal at the control node N maintains the high-level signal of the previous stage, the twenty-first transistor T21 is continuously turned on, and under the bootstrap effect of the capacitor C, the signal at the pull-up node PU is pulled high, the second transistor T2 and the third transistor T3 are turned on, the high-level signal at the clock signal terminal CLK is written into the first output terminal OUT1 and the second output terminal OUT2, the eighth transistor T8 and the eleventh transistor T11 are turned on, the low-level signal at the first power supply terminal V1 is continuously written into the first pull-down node PD1 and the second pull-down node PD2, the first pull-down node PD1 and the second pull-down node PD2 are continuously low-level signals, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are disconnected. In this stage, the signals at the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 are high-level signals, and the signals at the first pull-down node PD1 and the second pull-down node PD2 are low-level signals.

[0323] In the second stage, when the shift register is in the first display frame, the ninth transistor T9 is turned on and the twelfth transistor T12 is turned off. Although the ninth transistor T9 is turned on, the high-level signal of the fourth power supply terminal V4 will pull up the signal of the first pull-down node PD1, but because the eighth transistor T8 and the eleventh transistor T11 are continuously turned on, the signal of the first pull-down node PD1 is still pulled down to a low-level signal. Similarly. When the shift register is in the second display frame, the ninth transistor T9 is turned off and the twelfth transistor T12 is turned on. Although the twelfth transistor T12 is turned on, the high-level signal of the fifth power supply terminal V5 will pull up the signal of the second pull-down node PD2, but because the eighth transistor T8 and the eleventh transistor T11 are continuously turned on, the signal of the second pull-down node PD2 is still pulled down to a low-level signal. Regardless of whether the shift register is in the first display frame or the second display frame, the first pull-down node PD1 and the second pull-down node PD2 continue to be low-level signals in the second stage.

[0324] In the second stage, the voltage value of the signal at the signal input terminal IN is less than the voltage value of the signal at the control node N, so that the first transistor T1 is in a negative bias state, and the turn-on voltage of the first transistor T1 becomes smaller. In the present disclosure, due to the presence of the twenty-first transistor T21, the voltage value of the signal at the control node N in the second stage is less than the voltage value of the signal at the pull-up node PU, that is, Fig. 20 The absolute value of the difference between the voltage value of the signal at the signal input terminal in the provided shift register and the voltage value of the signal at the control node N is smaller than the absolute value of the difference between the voltage value of the signal at the signal input terminal in the shift register without setting the second control subcircuit and the voltage value of the signal at the pull-up node, that is, Fig. 27 The negative bias voltage level of the first transistor in the shift register provided is less than the negative bias voltage level of the first transistor in the shift register without the second control subcircuit, Fig. 27 The provided shift register can prevent the characteristic drift of the first transistor to a certain extent.

[0325] In the third phase P3, ie, the reset phase, the first reset signal terminal RST1 and the second reset signal terminal RST2 are high level signals, and the signals of the signal input terminal IN, the total reset signal terminal TRST and the clock signal terminal CLK are low level signals. The signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, the low level signal at the first power supply terminal V1 is written into the signal of the pull-up node PU, the signal of the pull-up node PU is pulled low, the signal of the control node N is pulled low by the pull-up node PU, the low level signal at the third power supply terminal V3 is written into the signal of the first output terminal OUT1, the signal of the first output terminal OUT1 is pulled low, the signal at the signal input terminal IN is a low level signal, the first transistor T1, the seventh transistor T7 and the tenth transistor T10 are disconnected, the pull-up node PU is a low level signal, the eighth transistor T8 and the eleventh transistor T11 are disconnected, the first pull-down node PD1 and the second pull-down node PD2 will not be pulled low by the low level signal at the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high level signal at the fourth power supply terminal V4 is written into the first pull-down node PD1, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off, the first pull-down node PD1 and the second pull-down node PD2 are turned off, the first pull-down node PD2 is turned off, the first pull-down node PD2 is turned off, the first pull-down node PD1 is turned off, the second pull-down node PD2 is turned off, the first pull-down node PD2 is turned off, the first pull-down node PD1 ... The transistor T15 is turned on, the low level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high level signal of the fifth power supply terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0326] In the fourth stage P4, i.e., the first noise reduction stage, the signal at the clock signal terminal CLK is a high-level signal, and the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are low-level signals. The signal at the signal input terminal IN is a low-level signal, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are disconnected, the signals at the control node N and the pull-up node PU maintain the low-level signals of the previous stage, the twenty-first transistor T21, the second transistor T2, the third transistor T3, the eighth transistor T8, and the eleventh transistor T11 are disconnected, the first pull-down node PD1 and the second pull-down node PD2 will not be pulled down by the low-level signal at the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 is written into the first pull-down node PD1, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned on, the low-level signal at the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, and the low-level signal at the third power supply terminal V3 is turned on. The first output terminal OUT1 is written, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high level signal of the fifth power supply terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0327] In the fifth stage P5, i.e., the second noise reduction stage, the clock signal terminal CLK, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2 and the total reset signal terminal TRST are low level signals. The signal at the signal input terminal IN is a low level signal, the first transistor T1, the seventh transistor T7 and the tenth transistor T10 are disconnected, the signals at the control node N and the pull-up node PU maintain the low level signals of the previous stage, the twenty-first transistor T21, the second transistor T2, the third transistor T3, the eighth transistor T8 and the eleventh transistor T11 are disconnected, the first pull-down node PD1 and the second pull-down node PD2 will not be pulled down by the low level signal of the first power supply terminal V1, when the shift register is in the first display frame, the ninth transistor T9 is turned on, the high level signal of the fourth power supply terminal V4 is written into the first pull-down node PD1, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, the low level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low level signal of the third power supply terminal V3 is turned on, and the high level signal of the fourth power supply terminal V4 is written into the first pull-down node PD1. The first output terminal OUT1 is written, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high level signal of the fifth power supply terminal V5 is written into the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low level signal of the first power supply terminal V1 is written into the pull-up node PU and the second output terminal OUT2, the low level signal of the third power supply terminal V3 is written into the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0328] The working process of the shift register unit further includes: a plurality of fourth phases P4 and fifth phases P5, and the fourth phases P4 and the fifth phases P5 work alternately.

[0329] The fourth stage P4 and the fifth stage P5 can ensure that the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 of the shift register are continuously low-level signals, which can reduce the noise of the shift register and improve the reliability of the shift register.

[0330] like Fig.28 As shown, Fig. 27 The working process of the provided shift register in the non-display stage may include the following stages:

[0331] In the sixth phase P6 , the signal at the total reset signal terminal TRST is a high level signal, the fourth transistor T4 is turned on, and the low level signal at the first power supply terminal V1 is written into the pull-up node PU.

[0332] The present disclosure also provides a driving method for a shift register, which is configured to drive a shift register as follows: Figures 17 to 22 The shift register shown, the driving method of the shift register may include the following steps:

[0333] Step 110, the input sub-circuit provides a signal to the pull-up node under the control of the signal at the signal input terminal.

[0334] Step 120: The output sub-circuit provides the signal of the clock signal terminal to the first output terminal under the control of the signal of the pull-up node.

[0335] Step 130 : The control subcircuit provides the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

[0336] The shift register is the shift register provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0337] The present disclosure also provides a driving method for a shift register, which is configured to drive a shift register as follows: Fig.23 The shift register shown, the driving method of the shift register may include the following steps:

[0338] Step 210: The input subcircuit provides a signal to the control node under the control of the signal input terminal.

[0339] Step 220: Under the control of the signal of the control node, the second control subcircuit provides the signal of the control node to the pull-up node.

[0340] Step 230 : The output sub-circuit is configured to provide the signal of the clock signal terminal to the first output terminal under the control of the signal of the pull-up node.

[0341] The embodiment of the present disclosure further provides a gate driving circuit, which includes: a plurality of cascaded shift registers.

[0342] The shift register is the shift register provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0343] In an exemplary embodiment, the gate driving circuit is provided in a display device, the display device is further provided with gate lines, and the shift register includes an output sub-circuit.

[0344] In an exemplary embodiment, the total reset signal terminals in all shift registers are connected to the same signal line, the first power supply terminals in all shift registers are connected to the same signal line, the second power supply terminals in all shift registers are connected to the same signal line, the third power supply terminals in all shift registers are connected to the same signal line, the fourth power supply terminals in all shift registers are connected to the same signal line, and the fifth power supply terminals in all shift registers are connected to the same signal line.

[0345] Fig.29 Schematic diagram of the cascade connection of the gate drive circuit Figure 1 .like Fig.29 As shown, in the state where the output sub-circuit includes the first output terminal OUT1, the first output terminal OUT1 of any stage of the shift register is electrically connected to the gate line, the first output terminal OUT1 of the shift register at this stage is electrically connected to the signal input terminal IN of the shift register at the next stage, and the first output terminal OUT1 of the shift register at this stage is electrically connected to the first reset signal terminal RST1 or the second reset signal terminal RST2 of the shift register at the previous stage.

[0346] Fig.30 Schematic diagram of the cascade connection of the gate drive circuit Figure 2 .like Fig.30 As shown, in the state where the output sub-circuit includes the first output terminal OUT1 and the second output terminal OUT2, the first output terminal OUT1 of any stage of the shift register is electrically connected to the gate line, the second output terminal OUT2 of the shift register at this stage is electrically connected to the signal input terminal IN of the next stage of the shift register, and the second output terminal OUT2 of the shift register at this stage is electrically connected to the first reset signal terminal RST1 or the second reset signal terminal RST2 of the previous stage of the shift register.

[0347] Fig.29 and Fig.30 GOA(i) in refers to the i-th stage shift register.

[0348] An embodiment of the present disclosure further provides a display device, including a gate driving circuit.

[0349] The gate driving circuit is the gate driving circuit provided by any of the aforementioned embodiments, and its implementation principle and effect are similar, which will not be described in detail here.

[0350] In an exemplary embodiment, the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device may be a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, or any other product or component having a display function.

[0351] The display device may include: a display substrate. The display substrate may include a plurality of pixel units arranged in a matrix manner, the plurality of pixel units include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and at least one third sub-pixel emitting a third color light, and the first sub-pixel, the second sub-pixel, and the third sub-pixel each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0352] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) emitting red light, the second sub-pixel may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in horizontal parallel, vertical parallel or in a herringbone manner, which is not limited in the present disclosure.

[0353] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a herringbone arrangement, which is not limited in the present disclosure.

[0354] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be a first sub-pixel, a second sub-pixel, and two third sub-pixels. The four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure.

[0355] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0356] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0357] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0358] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A shift register, characterized in that: include: an input subcircuit, an output subcircuit and a first control subcircuit; The input subcircuit is electrically connected to the signal input terminal and the pull-up node, respectively, and is configured to provide a signal to the pull-up node under the control of the signal of the signal input terminal; The output subcircuit is electrically connected to the first output terminal, the pull-up node and the clock signal terminal respectively, and is configured to provide a signal of the clock signal terminal to the first output terminal under the control of a signal of the pull-up node; The first control subcircuit is electrically connected to the control signal terminal and the signal input terminal respectively, and is configured to provide the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

2. The shift register according to claim 1, characterized in that: The shift register further includes: a first reset subcircuit; The first reset subcircuit is electrically connected to the general reset signal terminal, the pull-up node and the first power supply terminal respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node under the control of the general reset signal terminal; The total reset signal terminal is a valid level signal in a partial period of time in the non-display stage, and is an invalid level signal in the display stage.

3. The shift register according to claim 1, characterized in that: The control signal terminal includes: at least one of a first control signal terminal and a second control signal terminal; The first control signal terminal is electrically connected to the general reset signal terminal, and the second control signal terminal is electrically connected to the first output terminal.

4. The shift register according to claim 3, characterized in that: In a state where the control signal terminal includes the first control signal terminal, the first control subcircuit includes: a nineteenth transistor; The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal.

5. The shift register according to claim 3, characterized in that: In a state where the control signal terminal includes the second control signal terminal, the first control subcircuit includes: a twentieth transistor; The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

6. The shift register according to claim 3, characterized in that: In a state where the control signal terminal includes a first control signal terminal and a second control signal terminal, the control subcircuit includes: a nineteenth transistor and a twentieth transistor; The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal; The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

7. The shift register according to claim 1, characterized in that: The input subcircuit comprises: a first transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the pull-up node.

8. The shift register according to claim 1, characterized in that: The input subcircuit comprises: a first transistor and a twenty-first transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node; The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

9. The shift register according to claim 1, characterized in that: The output subcircuit includes: a second transistor and a capacitor; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output end.

10. The shift register according to claim 1, characterized in that: The output subcircuit is also electrically connected to the second output terminal, and is configured to provide the signal of the clock signal terminal to the second output terminal under the control of the signal of the pull-up node.

11. The shift register according to claim 10, characterized in that: The output subcircuit includes: a second transistor, a third transistor and a capacitor; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output end.

12. The shift register according to claim 2, characterized in that: The first reset subcircuit comprises: a fourth transistor; The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal.

13. The shift register according to claim 1, characterized in that: The shift register further includes: a second reset subcircuit; The second reset subcircuit is electrically connected to the first reset signal terminal, the second reset signal terminal, the pull-up node, the first output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and provide the signal of the third power supply terminal to the first output terminal under the control of the signals of the first reset signal terminal and the second reset signal terminal; The absolute value of the voltage of the signal at the first power supply terminal is greater than the absolute value of the voltage of the signal at the third power supply terminal; The first reset signal terminal and the second reset signal terminal are invalid level signals in the non-display stage and the output stage, and are valid level signals in a partial time period of the non-output stage.

14. The shift register according to claim 13, characterized in that: The second reset subcircuit comprises: a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal; The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the third power supply terminal.

15. The shift register according to claim 10, characterized in that: The shift register further includes: a noise reduction subcircuit, wherein the noise reduction subcircuit includes: at least one of a first noise reduction subcircuit and a second noise reduction subcircuit; The first noise reduction sub-circuit is electrically connected to the fourth power supply terminal, the signal input terminal, the pull-up node, the first output terminal, the second output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and the second output terminal, and provide the signal of the third power supply terminal to the pull-down node under the control of the signal of the signal input terminal, the pull-up node and the fourth power supply terminal; The second noise reduction sub-circuit is electrically connected to the fifth power supply terminal, the signal input terminal, the pull-up node, the first output terminal, the second output terminal, the first power supply terminal and the third power supply terminal, respectively, and is configured to provide the signal of the first power supply terminal to the pull-up node and the second output terminal, and provide the signal of the third power supply terminal to the pull-down node under the control of the signals of the signal input terminal, the pull-up node and the fifth power supply terminal.

16. The shift register according to claim 15, characterized in that: The first noise reduction sub-circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, and the second noise reduction sub-circuit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor; The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal; The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node; The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal; The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node; The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal; The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal; The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal; The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal.

17. The shift register according to claim 1, characterized in that: Also includes: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; The input subcircuit includes: a first transistor, the output subcircuit includes: a second transistor, a third transistor and a capacitor, the first control subcircuit includes: at least one of a nineteenth transistor and a twentieth transistor; the first reset subcircuit includes: a fourth transistor, the second reset subcircuit includes: a fifth transistor and a sixth transistor, and the noise reduction subcircuit includes: a seventh transistor to an eighteenth transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the pull-up node; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal; The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal; The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal; The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal; The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal; The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node; The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal; The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node; The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal; The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal; The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal; The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal; The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal.

18. The shift register according to claim 1, characterized in that: Also includes: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; The input subcircuit includes: a first transistor and a twenty-first transistor, the output subcircuit includes: a second transistor, a third transistor and a capacitor, the first control subcircuit includes: at least one of a nineteenth transistor and a twenty-first transistor; the first reset subcircuit includes: a fourth transistor, the second reset subcircuit includes: a fifth transistor and a sixth transistor, and the noise reduction subcircuit includes: a seventh transistor to an eighteenth transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal; The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal; The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal; The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal; The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal; The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node; The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal; The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node; The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal; The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal; The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal; The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the nineteenth transistor are electrically connected to the first control signal terminal respectively, and the second electrode of the nineteenth transistor is electrically connected to the signal input terminal; The control electrode and the first electrode of the twentieth transistor are electrically connected to the second control signal terminal respectively, and the second electrode of the twentieth transistor is electrically connected to the signal input terminal; The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

19. A shift register, characterized in that: include: An input subcircuit, an output subcircuit, and a second control subcircuit; The input subcircuit is electrically connected to the signal input terminal and the control node respectively, and is configured to provide a signal to the control node under the control of the signal input terminal; The second control subcircuit is electrically connected to the control node and the pull-up node, respectively, and is configured to provide the signal of the control node to the pull-up node under the control of the signal of the control node; The output subcircuit is electrically connected to the first output terminal, the pull-up node and the clock signal terminal respectively, and is configured to provide a signal from the clock signal terminal to the first output terminal under the control of a signal from the pull-up node.

20. The shift register according to claim 19, characterized in that: Also includes: a first reset subcircuit, a second reset subcircuit and a noise reduction subcircuit; The input subcircuit includes: a first transistor, the output subcircuit includes: a second transistor, a third transistor and a capacitor, the second control subcircuit includes: a twenty-first transistor; the first reset subcircuit includes: a fourth transistor, the second reset subcircuit includes: a fifth transistor and a sixth transistor, the noise reduction subcircuit includes: a seventh transistor to an eighteenth transistor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode of the first transistor is electrically connected to the signal input terminal or the second power supply terminal, and the second electrode of the first transistor is electrically connected to the control node; The control electrode of the second transistor is electrically connected to the pull-up node, the first electrode of the second transistor is electrically connected to the clock signal terminal, and the second electrode of the second transistor is electrically connected to the first output terminal; A control electrode of the third transistor is electrically connected to the pull-up node, a first electrode of the third transistor is electrically connected to the clock signal terminal, and a second electrode of the third transistor is electrically connected to the second output terminal; A first end of the capacitor is electrically connected to the pull-up node, and a second end of the capacitor is electrically connected to the first output terminal; The control electrode of the fourth transistor is electrically connected to the general reset signal terminal, the first electrode of the fourth transistor is electrically connected to the pull-up node, and the second electrode of the fourth transistor is electrically connected to the first power supply terminal; The control electrode of the fifth transistor is electrically connected to the first reset signal terminal, the first electrode of the fifth transistor is electrically connected to the pull-up node, and the second electrode of the fifth transistor is electrically connected to the first power supply terminal; The control electrode of the sixth transistor is electrically connected to the second reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first output terminal, and the second electrode of the sixth transistor is electrically connected to the first power supply terminal; The control electrode of the seventh transistor is electrically connected to the signal input terminal, the first electrode of the seventh transistor is electrically connected to the first pull-down node, and the second electrode of the seventh transistor is electrically connected to the first power supply terminal; The control electrode of the eighth transistor is electrically connected to the pull-up node, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the ninth transistor are electrically connected to the fourth power supply terminal respectively, and the second electrode of the ninth transistor is electrically connected to the first pull-down node; The control electrode of the tenth transistor is electrically connected to the signal input terminal, the first electrode of the tenth transistor is electrically connected to the second pull-down node, and the second electrode of the tenth transistor is electrically connected to the first power supply terminal; The control electrode of the eleventh transistor is electrically connected to the pull-up node, the first electrode of the eleventh transistor is electrically connected to the second pull-down node, and the second electrode of the eleventh transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twelfth transistor are electrically connected to the fifth power supply terminal respectively, and the second electrode of the twelfth transistor is electrically connected to the second pull-down node; The control electrode of the thirteenth transistor is electrically connected to the first pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the first power supply terminal; The control electrode of the fourteenth transistor is electrically connected to the first pull-down node, the first electrode of the fourteenth transistor is electrically connected to the first output terminal, and the second electrode of the fourteenth transistor is electrically connected to the third power supply terminal; The control electrode of the fifteenth transistor is electrically connected to the first pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second output terminal, and the second electrode of the fifteenth transistor is electrically connected to the first power supply terminal; The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first power supply terminal; The control electrode of the seventeenth transistor is electrically connected to the second pull-down node, the first electrode of the seventeenth transistor is electrically connected to the first output terminal, and the second electrode of the seventeenth transistor is electrically connected to the third power supply terminal; The control electrode of the eighteenth transistor is electrically connected to the second pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second output terminal, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal; The control electrode and the first electrode of the twenty-first transistor are electrically connected to the control node respectively, and the second electrode of the twenty-first transistor is electrically connected to the pull-up node.

21. A gate drive circuit, characterized in that: include: A plurality of cascaded shift registers according to any one of claims 1 to 20.

22. The gate driving circuit according to claim 21, characterized in that: The gate drive circuit is arranged in a display device, the display device is further provided with a gate line, and the shift register includes an output subcircuit; When the output sub-circuit includes the first output terminal, the first output terminal of any level of shift register is electrically connected to the gate line, the first output terminal of the shift register at this level is electrically connected to the signal input terminal of the shift register at the next level, and the first output terminal of the shift register at this level is electrically connected to the first reset signal terminal or the second reset signal terminal of the shift register at the previous level.

23. The gate driving circuit according to claim 21, characterized in that: The gate drive circuit is arranged in a display device, the display device is further provided with a gate line, and the shift register includes an output subcircuit; When the output sub-circuit includes a first output terminal and a second output terminal, the first output terminal of any level of shift register is electrically connected to the gate line, the second output terminal of the current level of shift register is electrically connected to the signal input terminal of the next level of shift register, and the second output terminal of the current level of shift register is electrically connected to the first reset signal terminal or the second reset signal terminal of the previous level of shift register.

24. A display device, characterized in that: Comprising the gate drive circuit as described in any one of claims 21 to 23.

25. A shift register driving method, characterized in that: is configured to drive a shift register as claimed in any one of claims 1 to 18, the method comprising: The input subcircuit provides a signal to the pull-up node under the control of the signal at the signal input terminal; The output subcircuit provides the signal of the clock signal terminal to the first output terminal under the control of the signal of the pull-up node; The control subcircuit provides the signal of the control signal terminal to the signal input terminal under the control of the signal of the control signal terminal.

26. A shift register driving method, characterized in that: is configured to drive a shift register as claimed in claim 19 or 20, the method comprising: The input subcircuit provides a signal to the control node under the control of the signal input terminal; The second control subcircuit provides the signal of the control node to the pull-up node under the control of the signal of the control node; The output sub-circuit is configured to provide a signal of the clock signal terminal to the first output terminal under the control of a signal of the pull-up node.

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