Display device

Abstract

Provided is a display device capable of achieving high definition. A gate driver (42) is provided with: a shift register circuit (421) in which a plurality of register circuits (SRA) are connected in series in a descending order or an ascending order in the Dy direction; and output circuits (422 - p) provided corresponding to the plurality of register circuits (SRA), respectively. The output circuit (422 - p) includes Q AND circuits that generate a logical product of an output signal (TRN (r)) of the register circuit (SRA) and an enable signal (ENBs) as a logical value of a scan signal (GATE (m)). A register circuit (SRA) inputs shift clock signals (CKV1, CKV2, CKV3), which have high potentials in a Q + 1 level period range, by shifting Q level periods in a descending order or an ascending order. An AND circuit inputs an enable signal (ENBs), which has a high potential in a two-level period range, while being shifted by one level period in a descending order or an ascending order.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] In recent years, in structures such as VR (Virtual Reality), AR (Augmented Reality), and MR (Mixed Reality) that display images by magnifying them with lenses, the display panels are being sought to be more refined. As the display panels become more refined, ensuring the charging time of pixels becomes an issue.

[0003] In the past, the following structure has been disclosed: in a dot-sequentially driven active matrix liquid crystal display device, in order to ensure the time for writing image signals to pixels on the scanning end side, the writing time of the pixels on the scanning end side is delayed by about 1 / 2H (for example, Patent Document 1). In addition, the following structure has been disclosed: in a high-resolution active matrix liquid crystal display device, in order to ensure the charging time of pixels, a logical sum signal of an output signal of a shift register and a signal obtained by delaying the output signal by 1H is supplied as a scanning signal, and a display data signal is supplied during the second half of the scanning signal (for example, Patent Document 2).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2002-023683

[0007] Patent Document 2: Japanese Patent Application Publication No. 2001-356738 Summary of the invention

[0008] In the above-mentioned patent document 1, it is necessary to set the vertical driving circuit on the left and right sides of the pixel unit. In addition, in the above-mentioned patent document 2, it is necessary to set a delay circuit and an OR circuit for each scanning signal line. As described above, in the above-mentioned prior art, there is a possibility that the scale of the circuit for driving the scanning line will increase.

[0009] An object of the present invention is to provide a display device capable of achieving high definition.

[0010] A display device of one embodiment of the present disclosure comprises: a substrate having a display area for arranging a plurality of pixels in a first direction and a second direction different from the first direction; a plurality of scanning lines connected to the pixels arranged in the first direction; a plurality of signal lines connected to the pixels arranged in the second direction; a gate driver supplying scanning signals to the scanning lines; and a signal line selection circuit supplying pixel signals to the signal lines, wherein the gate driver comprises: a shift register circuit, which is formed by connecting a plurality of register circuits in series in descending or ascending order along the second direction, wherein the outputs of the plurality of register circuits are shifted A binary signal that maintains the high potential of an input signal at the rising edge of a clock signal to the falling edge of a shift clock signal; and a plurality of output circuits, which are respectively arranged corresponding to a plurality of register circuits, the output circuits comprising Q AND circuits for generating a logical product value of an output signal of the register circuit and an enable signal as a logical value of the scanning signal, the register circuits respectively input a shift clock signal that becomes a high potential in a range of a Q+1 horizontal period in a descending or ascending order and each is staggered by Q horizontal periods, and the AND circuits respectively input an enable signal that becomes a high potential in a range of 2 horizontal periods in a descending or ascending order and each is staggered by 1 horizontal period.

[0011] A display device of one embodiment of the present disclosure comprises: a substrate having a display area for arranging a plurality of pixels in a first direction and a second direction different from the first direction; a plurality of scanning lines connected to the pixels arranged in the first direction; a plurality of signal lines connected to the pixels arranged in the second direction; a gate driver supplying scanning signals to the scanning lines; and a signal line selection circuit supplying pixel signals to the signal lines, wherein the gate driver comprises: a shift register circuit, which is formed by connecting a plurality of register circuits in series in descending or ascending order along the second direction, wherein the outputs of the plurality of register circuits are shifted A binary signal that maintains the high potential of the input signal at the falling edge of the clock signal to the rising edge of the shift clock signal; and multiple output circuits, which are respectively arranged corresponding to multiple register circuits, the output circuits include Q AND circuits that generate the logical product value of the output signal of the register circuit and the enable signal as the logical value of the scanning signal, the register circuits are respectively input with the shift clock signal that becomes a low potential in the range of Q+1 horizontal period in descending order or ascending order, and the AND circuits are respectively input with the enable signal that becomes a high potential in the range of 2 horizontal periods in descending order or ascending order, and are respectively shifted by 1 horizontal period. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing an example of a schematic structure of a display device.

[0013] Figure 2 This is a diagram showing an example of a pixel arrangement in a display area.

[0014] Figure 3 It is a cross-sectional view showing a schematic cross-sectional structure of a display device.

[0015] Figure 4 It is a plan view showing a structural example of a pixel.

[0016] Figure 5A It means along Figure 4 FIG. 1 is a diagram of a first example of a cross section taken along line A1-A2.

[0017] Figure 5B It means along Figure 4 FIG. 2 is a diagram of a second example of a cross section taken along line A1-A2.

[0018] Figure 6 This is a diagram showing an example of a driving circuit configuration.

[0019] Figure 7 This is a diagram showing an example of a conventional gate driver structure.

[0020] Figure 8 This is a timing chart of each part of the conventional example.

[0021] Fig.9A This is a diagram showing a first waveform example in the conventional example.

[0022] Fig. 9B It is a diagram showing a second waveform example in the conventional example.

[0023] Fig. 9C It is a diagram showing a third waveform example in the conventional example.

[0024] Fig.10 It is a figure which shows the example of display failure in a conventional example.

[0025] Fig.11 A diagram showing an example of a gate driver structure according to an embodiment.

[0026] Fig.12 yes Fig.11 Timing diagram of the various parts of the structure shown.

[0027] Fig.13A It is a diagram showing a first waveform example in the embodiment.

[0028] Fig. 13B It is a diagram showing a second waveform example in the embodiment.

[0029] Fig. 13C It is a diagram showing the third waveform example in the embodiment.

[0030] Fig.14It is a diagram showing an example of a gate driver structure according to a first modified example of the embodiment.

[0031] Fig.15 yes Fig.14 Timing diagram of the various parts of the structure shown.

[0032] Fig.16 This is a diagram showing an example of a gate driver structure according to a second variant of the embodiment.

[0033] Fig.17 yes Fig.16 Timing diagram of the various parts of the structure shown.

[0034] Description of Reference Numerals

[0035] 1 Display device

[0036] 4 Driver IC

[0037] 11 Display Panel

[0038] 12 Power supply unit

[0039] 13 Control Devices

[0040] 40 drive circuit

[0041] 42 Gate Driver

[0042] 43 Signal line selection circuit

[0043] 44 Display control circuit

[0044] 51 Gate line layer

[0045] 53 Signal line layer

[0046] 421 Shift Register Circuit

[0047] 422_p output circuit

[0048] AA Display Area

[0049] ASW switch circuit

[0050] CKV, CKV1, CKV2, CKV3 shift clock signals

[0051] COML Common Electrode

[0052] CS holding capacitor

[0053] DTL signal cable

[0054] ENB, ENBq, ENBs enable signal

[0055] GATE scan signal (gate signal)

[0056] MUX, MUX1, MUX2, xMUX1, xMUX2 selection control signal

[0057] Pix, Pix(n,m), Pix(n+1,m) pixels

[0058] PSIG1 1st power supply voltage signal

[0059] PSIG2 Second power supply voltage signal

[0060] PX pixel electrode

[0061] SCL scan line (gate line)

[0062] SIG pixel signal

[0063] SRA, SRB register circuit

[0064] STV start pulse signal

[0065] TRN(odd), TRN(even), TRN(r) output signals

[0066] Tr pixel transistor

[0067] Trn1, Trn2, Trp1, Trp2 switching transistors

[0068] VCOM common potential

[0069] VGH 1st potential

[0070] VGL 2nd potential

[0071] Vsig image signal DETAILED DESCRIPTION

[0072] The method (implementation method) for implementing the invention is described in detail with reference to the accompanying drawings. The present invention is not limited to the contents described in the following implementation methods. In addition, the structural elements described below include structural elements that can be easily thought of by those skilled in the art, and structural elements that are essentially the same. Moreover, the structural elements described below can be appropriately combined. In addition, the disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the main purpose of the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the accompanying drawings exist to schematically indicate the width, thickness, shape, etc. of each part compared to the actual state, but it is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, sometimes the same elements as those described above with respect to the figures that have appeared are marked with the same figure marks and detailed descriptions are appropriately omitted.

[0073] Figure 1This is a diagram showing an example of a schematic structure of a display device. Figure 2 This is a diagram showing an example of a pixel arrangement in a display area.

[0074] The display device 1 of this embodiment is, for example, a liquid crystal display device using a liquid crystal display element as a display element. In addition, in the present disclosure, as a driving method, the display device 1 can adopt, for example, a column inversion driving method or a frame inversion method. The driving method in the display device 1 is not limited to the column inversion driving method and the frame inversion method.

[0075] The display device 1 includes a display area AA on a display panel 11 , and a drive circuit 40 is provided in a peripheral area of ​​the display area AA. The display device 1 is supplied with power from a power supply device 12 .

[0076] The drive circuit 40 includes a gate driver 42, a signal line selection circuit 43, and a display control circuit 44. The gate driver 42 and the signal line selection circuit 43 are thin film transistor (TFT) circuits formed in the peripheral area of ​​the display area AA. The display control circuit 44 is included in a driver IC 4 mounted in the peripheral area of ​​the display area AA. The driver IC 4 is connected to the control device 13 via a relay substrate composed of a flexible printed circuit (FPC) or the like.

[0077] The control device 13 controls the power supply from the power supply device 12 to the display device 1. The control device 13 also controls power on and power off of the display device 1. The power supply device 12 and the control device 13 are mounted on, for example, a device (not shown) mounted on the display device 1.

[0078] A plurality of pixels Pix arranged along the Dx direction (first direction) and the Dy direction (second direction) are provided in the display area AA. In addition, a scanning line (gate line) SCL for supplying a scanning signal (gate signal) GATE to the pixel Pix, a signal line DTL for supplying a pixel signal SIG to the pixel Pix, and a common electrode COML for supplying a common potential VCOM to the pixel Pix are provided in the display area AA. In the present embodiment, the scanning line SCL is extended in the Dx direction (first direction). In addition, in the present embodiment, the signal line DTL is extended in the Dy direction (second direction).

[0079] like Figure 2As shown, each pixel Pix includes a pixel transistor Tr and a pixel electrode PX. The pixel transistor Tr is composed of a thin film transistor (TFT), for example, an n-channel MOS (Metal Oxide Semiconductor) type TFT (hereinafter also referred to as "n-type TFT"). The source of the pixel transistor Tr is connected to the signal line DTL, the gate is connected to the scanning line (gate line) SCL, and the drain is connected to the pixel electrode PX. A holding capacitor CS is formed between the pixel electrode PX and the common electrode COML.

[0080] The gates of the pixel transistors Tr of the pixels Pix arranged in the Dx direction (the first direction) are supplied with scanning signals (gate signals) GATE (1, 2, ..., m, ..., M) via scanning lines (gate lines) SCL, and the sources of the pixel transistors Tr of the pixels Pix arranged in the Dy direction (the second direction) are supplied with pixel signals SIG (1, 2, ..., n, ..., N) via signal lines DTL. Figure 2 , an example is shown in which N pixels Pix are arranged in the Dx direction (first direction) and M pixels Pix are arranged in the Dy direction (second direction), but the present invention is not limited thereto. Hereinafter, a row in which pixels Pix are arranged in the Dx direction (first direction) is also referred to as a pixel row. In addition, a column in which pixels Pix are arranged in the Dy direction (second direction) is also referred to as a pixel column.

[0081] In the present disclosure, the pixel Pix includes, for example, a red pixel for displaying red (R), a green pixel for displaying green (G), and a blue pixel for displaying blue (B). As a pixel arrangement, for example, a strip arrangement in which pixels of RGB are arranged in the Dx direction (first direction) is illustrated, but the pixel arrangement is not limited to the strip arrangement of RGB. Specifically, for example, as a pixel Pix, a white pixel for displaying white (W) can also be configured, and a strip arrangement with an inclined direction having a specified angle relative to the Dx direction (first direction) and the Dy direction (second direction), and an arrangement in which a plurality of pixel groups displaying different colors are periodically arranged in the Dx direction (first direction) and the Dy direction (second direction).

[0082] The power supply device 12 generates a positive first power supply voltage signal PSIG1 and a negative second power supply voltage signal PSIG2 to be supplied to the display device 1. The first power supply voltage signal PSIG1 is controlled to be a first potential (VGH). The second power supply voltage signal PSIG2 is controlled to be a second potential (VGL) having a potential lower than the first potential (VGH). The first potential (VGH) is set to, for example, 6V. The second potential (VGL) is set to, for example, -6V. The first potential (VGH) is not limited to 6V. In addition, the second potential (VGL) is not limited to -6V.

[0083] The control device 13 transmits an image signal, which is an original signal of an image displayed on the display device 1, to the display device 1. In addition, the control device 13 transmits a control signal for controlling the display device 1 to the display device 1. In addition, the control device 13 transmits a control signal for controlling the power supply from the power device 12 to the display device 1 to the power device 12.

[0084] The control device 13 includes, for example, a CPU (Central Processing Unit) and a storage device such as a memory. The control device 13 can realize the display function of the display device 1 by executing a program using hardware resources such as the CPU and the storage device. The control device 13 controls the driver IC 4 to process the image displayed on the display device 1 as information of the image input grayscale according to the execution result of the program.

[0085] The display control circuit 44 controls the display operation in the display area AA by controlling the gate driver 42 and the signal line selection circuit 43. The display control circuit 44 receives the image signal and various control signals from the control device 13. In addition, the display control circuit 44 converts the image signal from the control device 13 into an image signal Vsig and outputs it. The image signal Vsig is, for example, a signal obtained by time-division multiplexing pixel signals SIG corresponding to the pixel arrangement of RGB. In addition, the display control circuit 44 supplies a common potential VCOM to the common electrode COML.

[0086] In addition, the display control circuit 44 has a function as an interface (I / F) between the signal line selection circuit 43 and the control device 13 and a timing generator.

[0087] Next, refer to Figures 3 to 5B A schematic structure of the display device 1 according to the embodiment will be described. Figure 3 It is a cross-sectional view showing a schematic cross-sectional structure of a display device. Figure 4 It is a plan view showing a structural example of a pixel. Figure 5A It means along Figure 4 The first example of the cross section of the A1-A2 line. Figure 5A In the first example shown, an example in which a bottom-gate transistor is used as the pixel transistor Tr is shown. Figure 5B It means along Figure 4 The second example of the cross section of the A1-A2 line. Figure 5B In the second example shown, an example in which a top-gate transistor is used as the pixel transistor Tr is shown.

[0088] The array substrate 2 includes a first substrate 21 made of glass or transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 that insulates the pixel electrodes PX and the common electrode COML. The plurality of pixel electrodes PX are arranged in rows and columns (matrix) on the first substrate 21. The common electrode COML is provided between the first substrate 21 and the pixel electrodes PX.

[0089] The pixel electrode PX is provided corresponding to each pixel Pix. The pixel signal SIG for performing the display operation is supplied from the signal line selection circuit 43 to the pixel electrode PX via the signal line DTL and the pixel transistor Tr. In addition, during the display operation, the common potential VCOM for display as a voltage signal is supplied from the driver IC4 to the common electrode COML. The common potential VCOM is preferably a potential different from the GND potential, for example, about -0.7V. The setting value of the common potential VCOM is set to an optimal value that does not generate flicker in driving methods such as the column inversion driving method and the frame inversion driving method. In addition, the common potential VCOM is preferably a fixed potential, but it can also be a structure having a waveform composed of an AC rectangular wave.

[0090] The pixel electrode PX and the common electrode COML are made of a light-transmitting conductive material such as ITO (Indium Tin Oxide) etc. A polarizing plate 35B is provided on the lower side of the first substrate 21 via an adhesive layer (not shown).

[0091] The counter substrate 3 includes a second substrate 31 made of glass or transparent resin, and a color filter 32 and a light shielding layer (not shown) formed on one surface of the second substrate 31. A polarizing plate 35A is provided on the upper side of the second substrate 31 via an adhesive layer (not shown).

[0092] The array substrate 2 and the counter substrate 3 are arranged relative to each other with a predetermined interval (liquid crystal layer gap) set. A liquid crystal layer 6 is provided as a display function layer in the space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 changes the orientation state of the liquid crystal molecules for each pixel Pix according to the state of the electric field between each pixel electrode PX and the common electrode COML, thereby modulating the light passing through the liquid crystal layer 6. In this embodiment, for example, a liquid crystal of a transverse electric field mode such as IPS (in-plane switching) including FFS (fringe field switching technology) is used.

[0093] The array substrate 2 includes wiring such as a pixel transistor Tr of each pixel Pix, a signal line DTL for supplying a pixel signal SIG to each pixel electrode PX, and a scanning line (gate line) SCL for supplying a gate signal GATE for driving each pixel transistor Tr. The signal line DTL and the scanning line (gate line) SCL extend on a plane parallel to the surface of the first substrate 21.

[0094] like Figure 4 As shown in FIG. 1 , a region surrounded by a scanning line (gate line) SCL and a signal line DTL is a pixel Pix. The pixel electrode PX includes a plurality of strip-shaped electrodes 22a and a connecting portion 22b.

[0095] like Figure 4 As shown, the pixel transistor Tr includes a semiconductor 61 , a source electrode 62 , a drain electrode 63 and a gate electrode 64 .

[0096] like Figure 5A As shown, in a structure using a bottom-gate transistor as a pixel transistor Tr, a gate line layer 51 is provided on the first substrate 21. A gate electrode 64 (scanning line (gate line) SCL) is provided on the gate line layer 51. An insulating layer 58a (second insulating layer) is provided on the first substrate 21 in a manner covering the gate electrode 64. A semiconductor layer 52 is provided on the insulating layer 58a. A semiconductor 61 is provided on the semiconductor layer 52. On the upper side of the semiconductor layer 52, a signal line layer 53 is provided via an insulating layer 58c (first insulating layer).

[0097] like Figure 5B As shown, in a structure using a top-gate transistor as a pixel transistor Tr, a light shield LS is provided on the first substrate 21. A semiconductor layer 52 is provided on the light shield LS via an insulating layer 58f. A semiconductor 61 is provided on the semiconductor layer 52. A gate line layer 51 is provided on the upper side of the semiconductor layer 52 via an insulating layer 58c. A gate electrode 64 is provided on the gate line layer 51. An insulating layer 58a is provided on the insulating layer 58c so as to cover the gate electrode 64. A signal line layer 53 is provided on the upper side of the gate line layer 51 via an insulating layer 58a.

[0098] The signal line layer 53 is provided with a drain electrode 63 and a source electrode 62 (signal line DTL). On the upper side of the drain electrode 63 and the source electrode 62 (signal line DTL), an auxiliary wiring layer 54 is provided via an insulating layer 58d (third insulating layer). On the upper side of the auxiliary wiring layer 54, a common electrode layer 55 is provided via an insulating layer 58e. The common electrode layer 55 is provided with a common electrode COML. In addition, a structure in which the auxiliary wiring layer overlaps the common electrode layer without an insulating layer can also be adopted. On the upper side of the common electrode layer 55, a pixel electrode PX is provided via an insulating layer 24.

[0099] like Figure 4 and Figure 5A (or Figure 5B), the pixel electrode PX is connected to the drain electrode 63 of the pixel transistor Tr via the contact hole H11. The drain electrode 63 is connected to the semiconductor 61 via the contact hole H12. The semiconductor 61 intersects with the gate electrode 64 in a plan view. The gate electrode 64 is connected to the scanning line (gate line) SCL and is provided to protrude from one side of the scanning line (gate line) SCL. The semiconductor 61 extends to a position overlapping with the source electrode 62 and is electrically connected to the source electrode 62 via the contact hole H13. The source electrode 62 is connected to the signal line DTL and protrudes from one side of the signal line DTL.

[0100] As the material of the semiconductor 61, a known material such as polycrystalline silicon or an oxide semiconductor can be used. For example, by using TAOS (Transparent Amorphous Oxide Semiconductor), the ability to maintain the voltage for image display for a long time (retention rate) is good, and the display quality can be improved. In addition, the oxide semiconductor including TAOS has a small leakage current when the pixel transistor Tr is turned off.

[0101] The gate electrode 64 (scanning line (gate line) SCL) is made of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo) or an alloy thereof. The drain electrode 63 and the source electrode 62 (signal line DTL) are made of, for example, titanium aluminum (TiAl) which is an alloy of titanium and aluminum.

[0102] As the material of the insulating layer 24, 58a, 58c, 58d, 58e, 58f, a known insulating material can be used. For example, as the material of the insulating layer 58b, TEOS (Tetra Ethyl Ortho Silicate) can be used. In addition, for example, as the material of the insulating layer 58c, a silicon oxide film (SiO2) can be used. As the material of the insulating layer 58d, an organic insulating film such as acrylic resin is used. Thus, the surface on which the common electrode COML is provided is flattened.

[0103] As with the gate electrode 64 (scanning line (gate line) SCL), the auxiliary wiring layer 54 is made of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof.

[0104] Figure 6 FIG. 1 is a diagram showing an example of a drive circuit configuration. Figure 6 , an example of a circuit configuration corresponding to pixels Pix(n, m) and Pix(n+1, m) is shown. Figure 2In the pixel arrangement shown in FIG. 1 , the nth pixel Pix from the left in the figure is arranged along the Dx direction (first direction), and the mth pixel Pix from the top in the figure is arranged along the Dy direction (second direction). Figure 2 The pixel arrangement shown includes the n+1th pixel Pix from the left in the figure arranged in the Dx direction (first direction) and the mth pixel Pix from the top in the figure arranged in the Dy direction (second direction).

[0105] Each circuit element constituting the driving circuit 40 is operated by being supplied with the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 from the power supply device 12. The potential of the first power supply voltage signal PSIG1 (first potential VGH) is the high potential of the scanning signal (gate signal) GATE (m) supplied to the gate of the pixel transistor Tr. In addition, the potential of the second power supply voltage signal PSIG2 (second potential VGL) is the low potential of the scanning signal GATE (m) supplied to the gate of the pixel transistor Tr.

[0106] The display control circuit 44 (driver IC4) controls the gate driver 42 and the signal line selection circuit 43. Specifically, the display control circuit 44 (driver IC4) supplies synchronization signals such as a start pulse signal STV and a shift clock signal CKV and a scanning line drive signal ENB to the gate driver 42. In addition, the display control circuit 44 (driver IC4) supplies a selection control signal MUX to the signal line selection circuit 43. The potential of the first power supply voltage signal PSIG1 (the first potential VGH) is, for example, a high potential of the selection control signal MUX. In addition, the potential of the second power supply voltage signal PSIG2 (the second potential VGL) is, for example, a low potential of the selection control signal MUX. The present disclosure is not limited by the potential of the selection control signal MUX.

[0107] The gate driver 42 is a circuit that generates a scanning signal GATE(m) to be supplied to the gate of the pixel transistor Tr based on the start pulse signal STV, the shift clock signal CKV, and the scanning line drive signal ENB output from the display control circuit 44 (driver IC4 ).

[0108] Specifically, during the selection period of the scanning line SCL connected to the m-th pixel row, the scanning signal GATE(m) is set to a high potential (first potential VGH), thereby turning on the pixel transistors Tr of the pixels Pix(n,m) and Pix(n+1,m).

[0109] Furthermore, during the non-selection period of the scanning line SCL connected to the m-th pixel row, the scanning signal GATE(m) is set to a low potential (second potential VGL), thereby turning off the pixel transistors Tr of the pixels Pix(n,m) and Pix(n+1,m).

[0110] The signal line selection circuit 43 includes a switch circuit ASW that divides the selection period of the scanning line SCL connected to the pixel row of the mth row, supplies a pixel signal SIG(n) to the pixel Pix(n,m) and supplies a pixel signal SIG(n+1) to the pixel Pix(n+1,m). Figure 6 In the example shown, the switch circuit ASW includes switching transistors Trn1 and Trn2 formed of n-type TFTs and switching transistors Trp1 and Trp2 formed of p-type TFTs.

[0111] The signal line selection circuit 43 includes a plurality of switch circuits ASW arranged along the Dx direction (first direction) on the array substrate 2. Figure 6 In the example, the selection period of the scanning line SCL connected to the pixel row of the mth row is divided into two parts, and the corresponding pixel signals SIG(n) and SIG(n+1) are selectively output during the selection periods of the pixel Pix(n,m) and the pixel Pix(n+1,m). In this structure, the total number of switch circuits ASW arranged along the Dx direction (first direction) is N / 2.

[0112] Specifically, during the selection period of the signal line DTL connected to the pixel Pix(n,m), the selection control signal MUX1 is set to a high potential (first potential VGH), and the selection control signal xMUX1 is set to a low potential (second potential VGL). As a result, the switching transistors Trn1 and Trp1 are controlled to be turned on, and the image signal Vsig output from the display control circuit 44 (driver IC4) is selectively output as the pixel signal SIG(n).

[0113] In addition, during the selection period of the signal line DTL connected to the pixel Pix(n+1,m), the selection control signal MUX2 is set to a high potential (first potential VGH), and the selection control signal xMUX2 is set to a low potential (second potential VGL). As a result, the switching transistors Trn2 and Trp2 are controlled to be turned on, and the image signal Vsig output from the display control circuit 44 (driver IC4) is selectively output as the pixel signal SIG(n+1).

[0114] In addition, Figure 6, the switch circuit ASW is exemplified as a CMOS structure, but the present invention is not limited thereto. The switch circuit ASW may be configured by only n-type TFTs or only p-type TFTs, for example.

[0115] In addition, Figure 6 In the example, the selection period of the scan line SCL connected to the pixel row of the mth row is divided into two parts, and the corresponding pixel signals SIG(n) and SIG(n+1) are selectively output during the selection periods of the pixel Pix(n, m) and the pixel Pix(n+1, m), but it is not limited to this. For example, the selection period of the scan line SCL connected to the pixel row of the mth row may be divided into a plurality of periods of three or more parts, and the corresponding pixel signal SIG is selectively output during the selection period of each pixel Pix. When the number of divisions of the selection period of the scan line SCL connected to the pixel row of the mth row, in other words, the number of pixels sequentially selected by the switch circuit ASW during the selection period of the scan line SCL connected to the pixel row of the mth row is set to T, the total number of switch circuits ASW arranged along the Dx direction (first direction) is N / T.

[0116] Figure 7 This is a diagram showing an example of a conventional gate driver structure. Figure 8 is a time chart of each part in the previous example. Figure 8 , Fig.11 , Fig.15 , Fig.17 The time period between the single-dot chain lines in the timing chart of each portion shown is one horizontal period (1H).

[0117] exist Figure 7 In the configuration of the conventional example shown, the gate driver 42 includes a shift register circuit 421 and a plurality of output circuits 422_p (p is an integer greater than or equal to 1).

[0118] The shift register circuit 421 is constructed by alternately connecting the register circuit SRA and the register circuit SRB in series in descending order (or ascending order), wherein the register circuit SRA outputs a binary signal that maintains the high potential of the input signal at the rising edge of the shift clock signal CKV to the falling edge of the shift clock signal CKV, and the register circuit SRB outputs a binary signal that maintains the high potential of the input signal at the falling edge of the shift clock signal CKV to the rising edge of the shift clock signal CKV.

[0119] The output circuit 422_p is provided corresponding to the register circuits SRA and SRB, respectively. The output circuit 422_p includes Q (here, 4) 2-input 1-output AND circuits that generate logic values ​​of the scanning signal GATE(m) supplied to Q (here, 4) scanning lines SCL arranged along the Dy direction (the second direction). The output circuit 422_p may be a structure in which a driving circuit is provided at the subsequent stage of each AND circuit.

[0120] The shift register circuit 421 is input with a start pulse signal STV and a shift clock signal CKV. The shift clock signal CKV is at a high potential in the range of the Q horizontal period (here, 4 horizontal periods) and at a low potential in the range of the next Q horizontal period (here, 4 horizontal periods). The shift clock signal CKV is input to each register circuit SRA and SRB constituting the shift register circuit 421. The start pulse signal STV is input to the first-stage register circuit SRA arranged in descending order (or ascending order) in the shift register circuit 421. Thereafter, the output signal TRN (odd) of the register circuit SRA of the previous stage (or the output signal TRN (even) of the register circuit SRB) is input to the register circuit SRB (or the register circuit SRA) of the subsequent stage.

[0121] As the logic value of the scanning signal GATE(m), the AND circuit generates the logical product value of the output signal TRN(odd) of the register circuit SRA (or the output signal TRN(even) of the register circuit SRB) and the enable signal ENBq (q is an integer from 1 to Q (here, 4)). The enable signal ENBq that becomes a high potential during one horizontal period is input to each AND circuit in descending order (or ascending order) with each signal being shifted by one horizontal period.

[0122] According to the gate driver structure of the conventional example, the scanning signal GATE(m) which becomes a high potential for one horizontal period is supplied to the scanning lines SCL arranged in the Dy direction (second direction) in descending order (or ascending order) with each line shifted by one horizontal period.

[0123] Fig.9A This is a diagram showing a first waveform example in the conventional example. Fig. 9B It is a diagram showing a second waveform example in the conventional example. Fig. 9C It is a diagram showing a third waveform example in the conventional example. Fig.10 It is a figure which shows the example of display failure in a conventional example.

[0124] exist Fig.9A , Fig. 9B , Fig. 9C, an example is shown in which, during one horizontal period (1H) of the output scanning signal GATE(m), the pixel signal SIG(n) for the pixel Pix(n, m) and the pixel signal SIG(n+1) for the pixel Pix(n+1, m) are sequentially supplied by the display control circuit 44 (driver IC4) through the selection control signals MUX1, xMUX1, MUX2, and xMUX2. Fig.9A , Fig. 9B , Fig. 9C , an example is shown in which the potential of the pixel signal SIG(n) is the same as the potential of the pixel signal SIG(n+1).

[0125] In addition, Fig.9A , Fig. 9B , Fig. 9C , an example is shown in which the switch transistor Trn1 is turned on and the pixel signal SIG(n) is supplied in a region where the selection control signal MUX1 is higher than the potential indicated by the single-dot chain line, and the switch transistor Trn2 is turned on and the pixel signal SIG(n+1) is supplied in a region where the selection control signal MUX2 is higher than the potential indicated by the single-dot chain line. The potential at which the switch transistors Trn1 and Trn2 are turned on varies according to the potentials of the pixel signals SIG(n) and SIG(n+1).

[0126] During the period t1 during which the switching transistor Trn1 is turned on (the supply period of the pixel signal SIG(n)) overlaps with the pixel transistor Tr is turned on, the pixel electrode PX of the pixel Pix(n,m) is charged according to the potential of the pixel signal SIG(n). In addition, during the period t2 during which the switching transistor Trn2 is turned on (the supply period of the pixel signal SIG(n+1)) overlaps with the pixel transistor Tr is turned on, the pixel electrode PX of the pixel Pix(n+1,m) is charged according to the potential of the pixel signal SIG(n+1).

[0127] The turn-on timing of the pixel transistor Tr is delayed according to the time constant of the scanning line SCL. Specifically, the pixel transistor Tr is turned on at the time when the potential of the scanning signal GATE(m) exceeds the threshold voltage VTH of the pixel transistor Tr. Therefore, there is a possibility that the pixel transistor Tr is turned on later than the timing when the switching transistor Trn1 is turned on. Fig.9A As shown, the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) is shorter than the charging period t2 of the pixel electrode PX of the pixel Pix(n+1,m).

[0128] exist Fig. 9B In the example shown, the Fig.9A In a high-definition display panel, the length of one horizontal period (1H) is set to Fig.9AThe same length example. In this case, Fig.9A The time constant of the scanning line SCL becomes larger, the turn-on timing of the pixel transistor Tr is further delayed, and the charging period t1 of the pixel electrode PX of the pixel Pix (n, m) is further shortened compared with the charging period t2 of the pixel electrode PX of the pixel Pix (n+1, m).

[0129] exist Fig. 9C The example shown shows that Fig.9A In the same display panel, the length of one horizontal period (1H) is made longer than Fig.9A In this case, the conduction timing of the pixel transistor Tr is relatively delayed with respect to 1 horizontal period, and the charging period t1 of the pixel electrode PX of the pixel Pix (n, m) is relatively shortened with respect to the charging period t2 of the pixel electrode PX of the pixel Pix (n+1, m).

[0130] like Fig. 9B and Fig. 9C As shown in FIG. 1 , if the charging period t1 of the pixel electrode PX of the pixel Pix (n, m) becomes shorter than the charging period t2 of the pixel electrode PX of the pixel Pix (n+1, m) as the display panel becomes more precise and the display speed increases, it is expected that the charging potential of the pixel electrode PX of the pixel Pix (n, m) will decrease relative to the charging potential of the pixel electrode PX of the pixel Pix (n+1, m). In this case, Fig.10 As shown, the pixel row including the pixel Pix(n+1,m) is displayed darker than the pixel row including the pixel Pix(n+1,m).

[0131] Fig.11 A diagram showing an example of a gate driver structure according to an embodiment. Fig.12 yes Fig.11 The timing diagram of each part of the structure shown in FIG. Figure 7 The structural parts different from the structure of the conventional example shown in the figure are described in detail. Figure 7 The description of the same components as those of the conventional example may be omitted.

[0132] exist Fig.11 In the structure of the embodiment shown, the shift register circuit 421 is composed of multiple register circuits SRA connected in series in descending order (or ascending order), and the multiple register circuits SRA output a two-value signal that maintains the high potential of the input signal in the rising edge of the shift clock signal CKV to the falling edge of the shift clock signal CKV.

[0133] In the register circuit SRA, shift clock signals CKV1, CKV2, and CKV3 that are high potentials within the range of the Q+1 horizontal period are input in descending order (or ascending order) with each shifting the Q horizontal period. The start pulse signal STV is input to the first-stage register circuit SRA arranged in descending order (or ascending order) in the shift register circuit 421. Thereafter, the output signal TRN(r) of the register circuit SRA of the previous stage is input to the register circuit SRA of the next stage.

[0134] As the logic value of the scanning signal GATE(m), the AND circuit generates the logical product value of the output signal TRN(r) of the register circuit SRA and the enable signal ENBs (s is an integer from 1 to S (=Q+1, 5 in this case)). In each AND circuit, the enable signal ENBs that is at a high potential within a range of two horizontal periods is input in descending order (or ascending order) with each being shifted by one horizontal period.

[0135] According to the gate driver structure of the above embodiment, the scanning signal GATE(m) having a high potential within a range of two horizontal periods is supplied to the scanning lines SCL arranged in the Dy direction (second direction) in descending order (or ascending order) with each line shifted by one horizontal period.

[0136] Fig.13A It is a diagram showing a first waveform example in the embodiment. Fig. 13B It is a diagram showing a second waveform example in the embodiment. Fig. 13C It is a diagram showing the third waveform example in the embodiment.

[0137] exist Fig.13A , Fig. 13B , Fig. 13C , an example is shown in which the selection control signals MUX1, xMUX1, MUX2, and xMUX2 are controlled by the display control circuit 44 (driver IC4) in the second half of the 2-horizontal period (2H) of the output scanning signal GATE(m), thereby sequentially supplying the pixel signal SIG(n) for the pixel Pix(n, m) and the pixel signal SIG(n+1) for the pixel Pix(n+1, m). Fig.13A , Fig. 13B , Fig. 13C Also in Fig.9A , Fig. 9B , Fig. 9C Similarly, an example is shown in which the potential of the pixel signal SIG(n) is the same as the potential of the pixel signal SIG(n+1).

[0138] In addition, Fig.13A , Fig. 13B , Fig. 13CIn FIG. 1 , an example is shown in which the switch transistor Trn1 is turned on and supplies the pixel signal SIG(n) in a region where the selection control signal MUX1 is above the potential indicated by the single-dot chain line, and the switch transistor Trn2 is turned on and supplies the pixel signal SIG(n+1) in a region where the selection control signal MUX2 is above the potential indicated by the single-dot chain line. Fig.13A , Fig. 13B , Fig. 13C Also in Fig.9A , Fig. 9B , Fig. 9C Similarly, the potential at which the switching transistors Trn1 and Trn2 are turned on varies according to the potentials of the pixel signals SIG(n) and SIG(n+1).

[0139] As described above, the turn-on timing of the pixel transistor Tr is delayed by the time constant of the scanning line SCL. Specifically, the pixel transistor Tr is turned on when the potential of the scanning signal GATE(m) exceeds the threshold voltage VTH of the pixel transistor Tr.

[0140] exist Fig. 13B In the example shown, the Fig. 9B Similarly, it is shown that Fig.13A In a high-definition display panel, the length of one horizontal period (1H) is set to Fig.13A Same length example.

[0141] exist Fig. 13C In the example shown, the Fig. 9C Similarly, it is shown that Fig.13A In the same display panel, the length of one horizontal period (1H) is made longer than Fig.13A Short example.

[0142] In the structure of the embodiment, the scanning signal GATE(m) is set to a high potential within the range of 2 horizontal periods (2H), and after the potential of the scanning signal GATE(m) exceeds the threshold voltage VTH of the pixel transistor Tr and the pixel transistor Tr is turned on, the switching transistor Trn1 is turned on. Fig.13A As shown, the charging period t1 of the pixel electrode PX of the pixel Pix (n, m) and the charging period t2 of the pixel electrode PX of the pixel Pix (n+1, m) can be made substantially equal.

[0143] In addition, in Fig.13A In a high-definition display panel, the length of one horizontal period (1H) is set to Fig.13A The same length Fig. 13B In the example shown, the switching transistor Trn1 can be turned on after the pixel transistor Tr is turned on. Fig.13ASimilarly, the charging period t1 of the pixel electrode PX of the pixel Pix (n, m) and the charging period t2 of the pixel electrode PX of the pixel Pix (n+1, m) can be made substantially equal.

[0144] In addition, in Fig.13A In the same display panel, the length of one horizontal period (1H) is made longer than Fig.13A Short Fig. 13C In the example shown, the switching transistor Trn1 can be turned on after the pixel transistor Tr is turned on. Fig.13A Similarly, the charging period t1 of the pixel electrode PX of the pixel Pix (n, m) and the charging period t2 of the pixel electrode PX of the pixel Pix (n+1, m) can be made substantially equal.

[0145] As such, in the structure of the embodiment, Figure 7 and Figure 8 The additional circuit structure of the conventional example shown can avoid the delay of the conduction timing of the pixel transistor Tr caused by the time constant of the scanning line SCL by sequentially supplying the pixel signal SIG(n) for the pixel Pix(n,m) and the pixel signal SIG(n+1) for the pixel Pix(n+1,m) in the second half of the 1 horizontal period (1H) of the 2 horizontal periods (2H) of the output scanning signal GATE(m). As a result, the shortening of the charging period t1 of the pixel electrode PX of the pixel Pix(n,m) and the reduction of the charging potential of the pixel electrode PX of the pixel Pix(n,m) caused by the high definition of the display panel and the high speed of display can be suppressed.

[0146] (First Modification)

[0147] Fig.14 It is a diagram showing an example of a gate driver structure according to a first modified example of the embodiment. Fig.15 yes Fig.14 In addition, here, Fig.11 The structural parts of the embodiment shown in the figure are described in detail. Fig.11 The description of the same components as those in the embodiments shown may be omitted.

[0148] exist Fig.14 In the structure of the first variant of the embodiment shown, the shift register circuit 421 is composed of a plurality of register circuits SRB connected in series in descending order (or ascending order), and the plurality of register circuits SRB output a two-value signal that maintains the high potential of the input signal at the falling edge of the shift clock signal CKV to the rising edge of the shift clock signal CKV.

[0149] In the register circuit SRB, shift clock signals CKV1, CKV2, and CKV3 that become low potentials in the range of the Q+1 horizontal period are input in descending order (or ascending order) and are shifted by the Q horizontal period. The start pulse signal STV is input to the first-stage register circuit SRB arranged in descending order (or ascending order) in the shift register circuit 421. Thereafter, the output signal TRN(r) of the register circuit SRB of the previous stage is input to the register circuit SRB of the next stage.

[0150] In the structure of the first variant of the embodiment, relative to Fig.11 and Fig.12 The structure of the embodiment shown in the figure is different only in that the logic values ​​of the shift clock signals CKV1, CKV2, and CKV3 are inverted. Figure 7 and Figure 8 The additional circuit structure of the conventional example shown can avoid the delay of the conduction timing of the pixel transistor Tr caused by the time constant of the scanning line SCL. As a result, it is possible to suppress the shortening of the charging period t1 of the pixel electrode PX of the pixel Pix (n, m) and the reduction of the charging potential of the pixel electrode PX of the pixel Pix (n, m) caused by the high definition of the display panel and the high speed of display.

[0151] (Second Modification)

[0152] Fig.16 This is a diagram showing an example of a gate driver structure according to a second variation of the embodiment. Fig.17 yes Fig.16 The timing diagram of each part of the structure shown in FIG. Fig.11 The structural parts of the embodiment shown in the figure are described in detail. Fig.11 The description of the same components as those in the embodiments shown may be omitted.

[0153] exist Fig.16 In the structure of the second variation of the embodiment shown, the output circuit 422_p includes two 2-input 1-output AND circuits each generating a logical value of the scanning signal GATE(m) supplied to two scanning lines SCL arranged in the Dy direction (second direction).

[0154] The AND circuit generates the logical product value of the output signal TRN(r) of the register circuit SRA and the enable signal ENBs (s is an integer from 1 to 3) as the logical value of the scanning signal GATE(m). In each AND circuit, the enable signal ENBs that is at a high potential within a range of 2 horizontal periods is input in descending order (or ascending order) and is shifted by 1 horizontal period.

[0155] In the structure of the second variant of the embodiment, relative to Fig.11 and Fig.12 In the structure of the embodiment shown, the number of AND circuits included in the output circuit 422_p is different. In the structure of the second modified example of the embodiment, as in the structure of the embodiment, the delay of the conduction timing of the pixel transistor Tr caused by the time constant of the scanning line SCL can be avoided without adding a circuit to the structure of the prior art. As a result, the shortening of the charging period t1 of the pixel electrode PX of the pixel Pix (n, m) and the reduction of the charging potential of the pixel electrode PX of the pixel Pix (n, m) caused by the high definition of the display panel and the high speed of display can be suppressed.

[0156] In addition, in the structure of the second modification example, similarly to the first modification example, it is possible to Fig.16 and Fig.17 The structure of the second modified example of the embodiment shown is a structure in which the logic values ​​of the shift clock signals CKV1, CKV2, and CKV3 are inverted.

[0157] In addition, the display device 1 is not limited to a liquid crystal display device, and may be, for example, an organic EL display using an organic light emitting diode (OLED: Organic Light Emitting Diode) as a display element. In addition, the display device 1 may also be an inorganic EL display using an inorganic light emitting diode (micro LED) as a display element. In addition, the display device 1 may also be an electrophoretic display (EPD: Electrophoretic Display), or a transparent display that displays an image on a transmissive display surface.

[0158] The above describes the preferred embodiments of the present disclosure, but the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are only examples, and various changes can be made within the scope of the subject matter of the present disclosure. Appropriate changes made within the scope of the subject matter of the present disclosure are of course also within the technical scope of the present disclosure.

Claims

1. A display device, characterized in that: have: A substrate having a display area where a plurality of pixels are arranged in a first direction and a second direction different from the first direction; A plurality of scanning lines connected to pixels arranged in the first direction; a plurality of signal lines connected to pixels arranged in the second direction; a gate driver that supplies a scan signal to the scan line; and a signal line selection circuit that supplies a pixel signal to the signal line, The gate driver comprises: a shift register circuit formed by connecting a plurality of register circuits in series in descending order or ascending order along the second direction, wherein the plurality of register circuits output a binary signal that maintains a high potential of an input signal at a rising edge of a shift clock signal to a falling edge of the shift clock signal; and A plurality of output circuits are provided corresponding to the plurality of register circuits respectively. The output circuit includes Q AND circuits for generating a logical product value of the output signal of the register circuit and an enable signal as the logical value of the scan signal. The register circuit inputs a shift clock signal that becomes a high potential in the range of the Q+1 horizontal period in descending order or ascending order, each shifted by the Q horizontal period. The AND circuits are input with enable signals that are high in a range of two horizontal periods, each shifted by one horizontal period in descending order or ascending order.

2. A display device, characterized in that: have: A substrate having a display area where a plurality of pixels are arranged in a first direction and a second direction different from the first direction; A plurality of scanning lines connected to pixels arranged in the first direction; a plurality of signal lines connected to pixels arranged in the second direction; a gate driver that supplies a scan signal to the scan line; and a signal line selection circuit that supplies a pixel signal to the signal line, The gate driver comprises: a shift register circuit formed by connecting a plurality of register circuits in series in descending order or ascending order along the second direction, wherein the plurality of register circuits output a binary signal that maintains a high potential of an input signal at a falling edge of a shift clock signal to a rising edge of the shift clock signal; and A plurality of output circuits are provided corresponding to the plurality of register circuits respectively. The output circuit includes Q AND circuits for generating a logical product value of the output signal of the register circuit and an enable signal as the logical value of the scan signal. The register circuit inputs a shift clock signal that becomes a low potential in the range of the Q+1 horizontal period in descending order or ascending order, each shifted by the Q horizontal period. The AND circuits are input with enable signals that are high in a range of two horizontal periods, each shifted by one horizontal period in descending order or ascending order.

3. The display device according to claim 1 or 2, characterized in that: To the scanning lines arranged in the second direction, scanning signals having a high potential within a range of two horizontal periods are supplied in descending order or ascending order with each being shifted by one horizontal period. The signal line selection circuit time-divides one horizontal period in the second half of a scanning line selection period in which a scanning signal is at a high potential, and sequentially supplies pixel signals to a plurality of pixels connected to the selected scanning line.

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