Performing logical operations in memory

Abstract

Methods, systems, and devices related to performing logical operations in memory using multiple digital lines. At least two digital lines coupled to the same sense amplifier can be used for the logical operation. For example, two word lines on one digital line and one word line on another digital line can be substantially simultaneously activated to perform a particular logical operation. The three word lines are respectively coupled to memory cells configured to store operands of an operation or reference data values for a particular logical operation.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor memories and methods, and more particularly to apparatus, systems, and methods for performing logic operations in memories. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuit systems in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by retaining stored data when power is not applied and may include NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistance variable memory (e.g., phase change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STTRAM), etc.

[0003] An electronic system may generally include processing resources (e.g., one or more processors) that can retrieve and execute instructions and store the results of the executed instructions to appropriate locations. For example, a processor may include functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and / or combinatorial logic blocks that can be used to execute instructions by performing logical operations (e.g., AND, OR, NOT, NAND, NOR, and XOR) and inverting (e.g., reversing) logical operations on data (e.g., one or more operands). Summary of the invention

[0004] In one aspect, the present disclosure relates to a method for performing a logic operation in a memory, comprising: performing a logic operation on data values ​​respectively stored in a first memory cell and a second memory cell coupled to a first digital line coupled to a sense amplifier by: activating: a first word line coupled to the first memory cell; a second word line coupled to the second memory cell; and a third word line coupled to a third memory cell, wherein the third memory cell is coupled to the second digital line coupled to the sense amplifier; and activating the sense amplifier, wherein the data value sensed at the sense amplifier corresponds to a result of the logic operation.

[0005] On the other hand, the present disclosure relates to an apparatus for performing a logic operation in a memory, comprising: a first digital line coupled to a first plurality of memory cells, the first plurality of memory cells being coupled to corresponding first word lines; a second digital line coupled to a second plurality of memory cells, the second plurality of memory cells being coupled to corresponding second word lines; a sense amplifier coupled to the first digital line and the second digital line; and a controller configured to perform a logic operation on data values ​​stored in at least two of the first plurality of memory cells by: activating corresponding first word lines to which the at least two memory cells are coupled; activating corresponding second word lines to which memory cells in the second plurality of memory cells are coupled, wherein the memory cells in the second plurality of memory cells store voltages corresponding to reference data values; and activating the sense amplifier to store the result of the logic operation therein.

[0006] On the other hand, the present disclosure relates to an apparatus for performing a logic operation in a memory, comprising: a memory array, comprising: a plurality of memory cells coupled to a first digital line; a first memory cell coupled to a second digital line and a first word line, the first memory cell being configured to store a first reference data value having a first data value; a second memory cell coupled to the second digital line and a second word line, the second memory cell being configured to store a second reference data value having a second data value; and a sense amplifier coupled to the first digital line and the second digital line; and a controller being configured to perform the following operations in order to perform a first logic operation on data values ​​respectively stored in two memory cells of the plurality of memory cells coupled to the first digital line: activating two word lines coupled to the two memory cells; and activating the first word line substantially simultaneously with the two word lines being activated to further adjust a voltage differential sensed at the sense amplifier based on the first reference data value stored on the first memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Functional block diagrams in the form of memory systems including memory devices in which multiple digital lines are used to perform logic operations are illustrated in accordance with several embodiments of the present disclosure.

[0008] Figure 2 is a schematic diagram illustrating rows of memory cells and sense amplifiers of a memory array that can use multiple digit lines to perform logic operations according to several embodiments of the present disclosure.

[0009] Figure 3 is a schematic diagram illustrating rows of memory cells and sense amplifiers of a memory array that can use multiple digit lines to perform logic operations according to several embodiments of the present disclosure.

[0010] Figure 4 Various voltage levels are described for the voltage at which digit lines are biased when performing logic operations according to several embodiments of the present disclosure.

[0011] Figure 5 Various voltage levels of the voltage at which the digit line is biased when performing another logic operation according to several embodiments of the present disclosure are described. DETAILED DESCRIPTION

[0012] Systems, devices, and methods related to performing logic operations in memory are described. Embodiments of the present disclosure may include performing a logic operation by activating (e.g., turning on) at least three word lines, at least one of which is a reference word line (e.g., a word line coupled to a memory cell coupled to a reference digit line). In various embodiments, two of the three word lines (e.g., non-reference word lines) are respectively coupled to memory cells storing operands for the logic operation, wherein the two memory cells are coupled to the same digit line (e.g., non-reference digit line). In this example, a third word line (e.g., reference word line) is coupled to a third memory cell to which the reference digit line is coupled, wherein the reference digit line is complementary to the non-reference digit line. That is, the reference digit line and the non-reference digit line are commonly coupled to the same sense amplifier. The memory cell coupled to the reference word line and coupled to the reference digit line may be referred to as a reference memory cell and is configured to store a "reference" data value (alternatively referred to as a "reference value") for the logic operation. As used herein, the term "reference data value" refers to a data value (e.g., "0" or "1") that does not correspond to an operand of a logic operation. Rather, the reference data values ​​are used to obtain the desired output of the corresponding / specific logic operation. In some embodiments, the reference data values ​​used for different logic operations may also be different.

[0013] Some existing methods of performing logic operations in memory may include activating word lines only on the "non-reference side" of a sense amplifier, while not activating word lines on the "reference side" of the sense amplifier. As used herein, the terms "reference side" and "non-reference side" are used herein to refer to the complementary sides of a sense amplifier coupled to complementary digit lines (e.g., D and D*). It will be appreciated that in a folded digit line scheme, both complementary digit lines are located on the same physical side of the array (e.g., where the reference word line and the non-reference word line are located in the same sub-array). These existing methods may have disadvantages because the more word lines that are activated on the same side, the higher the likelihood of noise and interference among the word lines, which may lead to errors in sensing data values ​​and / or voltages on those memory cells performing the logic operation.

[0014] Various embodiments of the present disclosure address the above and other deficiencies by providing apparatus and methods for performing logic operations by activating (e.g., three) word lines on different sides (non-reference side and reference side) in order to reduce the number of word lines activated on each side of a memory array. For example, logic operations can be performed on memory cells on the non-reference side (e.g., coupled to two word lines located on the non-reference side) as well as reference memory cells on the reference side. This reduces the risk of noise and interference that may occur when more / multiple word lines on the same side are activated, and further provides better precision voltage tuning capability for reference data values ​​stored on reference memory cells (e.g., reference voltages corresponding to reference data values). This capability further enhances the ability to perform operations that are desired to be performed, rather than undesirably performing different logic operations due to poor voltage tuning capability of reference data values; thus, allowing the execution of logic operations according to embodiments of the present disclosure to be implemented in complex schemes, such as neural network schemes.

[0015] As used herein, the singular forms "a", "an", and "the" include singular and plural referents unless the context clearly indicates otherwise. In addition, the word "may" is used throughout this application in a permissive sense (e.g., likely, able to) rather than in a mandatory sense (e.g., must). The term "including" and its derivatives mean "including but not limited to". As used herein, "coupled to" or "coupled with..." generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like. The terms "data" and "data value" are used interchangeably herein and may have the same meaning, depending on the context.

[0016] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, element "108" in Figure 1 Component "8" can be represented in Figure 2 208. Similar elements within the drawings may be referenced by hyphens and additional numbers or letters. It will be appreciated that the elements shown in the various embodiments herein may be added, exchanged, and / or eliminated in order to provide several additional embodiments of the present disclosure. In addition, it should be appreciated that the proportions and relative scales of the elements provided in the drawings are intended to illustrate certain embodiments of the present invention and should not be construed in a limiting sense.

[0017] Figure 11 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 104 in which a plurality of digital lines are used to perform logic operations, according to several embodiments of the present disclosure. As used herein, a memory device 104, a memory array 106, and / or a sense amplifier 108 ( Figure 1 For clarity, computing system 100 has been simplified to focus on features that are particularly relevant to the present disclosure (e.g., providing host 102 with capabilities associated with SRAM resources via sense amplifier 108). Figure 1 The examples shown in illustrate a system having a Von Neumann architecture, but embodiments of the present disclosure may be implemented in a non-Von Neumann architecture (e.g., a Turing machine), which may not include one or more components typically associated with a Von Neumann architecture (e.g., a CPU, an ALU, etc.).

[0018] The computing system 100 includes a host 102 coupled (e.g., connected) to a memory device 104 including a memory array 106. For example, the computing system 100 may be a component or resource of a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, as well as various other types of electronic devices. The host 102 may be or include a processing device, such as a CPU. The host 102 may include a system motherboard and / or a backplane, and may include one or more processing devices (e.g., one or more processors, such as a CPU, a microprocessor, a control circuit system). The computing system 100 may include the host 102 and the memory device 104 as separate and distinct integrated circuits, or include the host 102 and the memory device 104 as components on the same (single) integrated circuit (e.g., the host 102 is located on a chip with the memory device 104). In some embodiments, the memory device 104 may include components coupled to respective substrates, and those substrates may be coupled to another substrate, such as a printed circuit board (PCB). For example, computing system 100 may be a component or resource of a server system and / or a high performance computing (HPC) system and / or a portion thereof.

[0019] For example, the memory array 106 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a FeRAM array, a NAND flash array, and / or a NOR flash array. The FeRAM array may include ferroelectric capacitors and may perform bit storage based on a voltage or amount of charge applied thereto. The memory array 106 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and in columns coupled by sense lines. Although in Figure 1A single memory array 106 is shown in FIG. 1 , but embodiments are not so limited. For example, the memory device 104 may include one or more memory arrays 106 (eg, several banks of DRAM cells).

[0020] Memory device 104 may include address circuitry 112 to latch address signals provided by I / O circuitry 116 via an I / O bus 122 (e.g., a data bus). The address signals may be received and decoded by row decoder 118 and column decoder 120 to access memory array 106. Data may be read from memory array 106 by sensing voltage and / or current changes on a digital line using sense amplifiers 108. As described herein, sense amplifiers 108 may be one or more sense amplifier strips. Sense amplifiers 108 may be used to read and latch pages (e.g., rows) of data from memory array 106. I / O circuitry 116 may be used for bidirectional data communication with host 102 via I / O bus 122. Write circuitry 124 may be used to write data to memory array 106.

[0021] The controller 110 may decode signals provided from the host 102 over the control bus 126. These signals may include chip enable signals, write enable signals, and address latch signals used to control operations performed on the memory array 106, including data read, data write, and data erase operations. In various embodiments, the controller 110 may be responsible for executing instructions from the host 102. The controller 110 may be a state machine, a sequencer, or some other type of controller.

[0022] In some embodiments, the sense amplifier 108 may be used to perform logic operations using data stored in the memory array 106 and / or data stored in the sense amplifier 108 as inputs, and store the results of the logic operations on the data stored in the memory array 106 and / or data stored in the sense amplifier 108 without transferring the data via sense line address accesses (e.g., without activating a column decode signal). Thus, the sense amplifier 108 may be used and various computational functions may be performed within the sense amplifier 108 rather than being performed by processing resources external to the sense amplifier 108 (e.g., by a processor associated with the host 102 (e.g., the controller 110 or elsewhere) and / or other processing circuitry (e.g., ALU circuitry) of the memory device 104).

[0023] Figure 22 is a schematic diagram of a row 234 of memory cells and a sense amplifier 208 of a memory array 206 illustrating the use of a plurality of digit lines 230, 231 to perform logic operations according to several embodiments of the present disclosure. The memory array 206 includes a first subset including rows 234-m, 234-(m+1), 234-(m+2), 234-(m+3), and 234-(m+4) of memory cells coupled to respective word lines (e.g., 236-m, 236-(m+1), 236-(m+2), 236-(m+3), and 236-(m+4), respectively). Memory array 206 includes a second subset portion including rows 234-k, 234-(k+1), 234-(k+2), 234-(k+3), and 234-(k+4) of memory cells coupled to respective word lines (e.g., 236-k, 236-(k+1), 236-(k+2), 236-(k+3), and 236-(k+4), respectively). As used herein, "subset" is used for identification purposes and does not necessarily imply a physical or logical characteristic (e.g., a boundary) of memory array 206. The rows of the subarrays are collectively referred to as rows 234, and the word lines of the subarrays are collectively referred to as word lines 236.

[0024] Memory array 206 includes columns of memory cells corresponding to respective complementary digit line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2). The columns of memory cells include respective sense amplifiers 208-n, 208-(n+1), and 208-(n+2) (collectively referred to as sense amplifiers 208), which may operate in a plurality of modes according to the embodiments described herein. Memory array 206 and sense amplifiers 208 may be similar to those described herein. Figure 1 Memory array 106 and sense amplifier 108 are described in association. Figure 2 Five word lines 236 (e.g., five rows 234) are illustrated coupled to local I / O lines (e.g., LIO 238-1 and LIOF 238-2) via three digital lines 230 and three sense amplifiers 208 (e.g., three columns), but embodiments may include more or less than five word lines and more or less than three digital lines coupled to local I / O lines. Additionally, Figure 2 Complementary digit line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) in an open digit line architecture are illustrated; however, embodiments may include a folded digit line architecture, for example.

[0025] In this example, memory array 206 includes 1T1C (one transistor one capacitor) DRAM memory cells, where each memory cell includes an access device (e.g., a transistor) and a storage element (e.g., a capacitor). In some embodiments, the memory cells may be destructive read memory cells (e.g., reading the data stored in the memory cell destroys the data such that the data originally stored in the memory cell is refreshed after being read).

[0026] Figure 2 An example configuration for the sense amplifier 208 described herein (illustrated schematically by sense amplifier 208-n) is illustrated. Embodiments of the present disclosure are not limited to the sense amplifier 208-n. Figure 2 An example sense amplifier configuration is illustrated, and may be, for example, a current mode sense amplifier and / or a single-ended sense amplifier (eg, a sense amplifier coupled to a single digital line).

[0027] Column decoder transistors 232-n and 233-n are coupled to sense amplifier 208-n, column decoder transistors 232-(n+1) and 233-(n+1) are coupled to sense amplifier 208-n+1, ​​and column decoder transistors 232-n+2 and 233-n+2 are coupled to sense amplifier 208-n+2. Columns of memory cells include corresponding respective column decode transistor pairs (e.g., 232-n and 233-n, 232-(n+1) and 233-(n+1), 232-(n+2) and 233-(n+2) (collectively, column decode transistors 232 and 233)) that are operable via respective column decode signals (e.g., ColDec_n, ColDec_(n+1), and ColDec_(n+2), respectively). For example, one or more of the column decode transistors 232 and 233 may be enabled to transfer data values ​​from the corresponding sense amplifier 208 to components external to the memory array 206 via the local I / O lines LIO 238-1 and LIOF 238-2, such as with Figure 1 Host 102 is described in association.

[0028] In some embodiments, memory array 206 may include one or more sub-arrays. As used herein, "sub-array" refers to a subset of a memory array (e.g., memory array 206). In some embodiments, rows and columns of a memory array coupled to local I / O lines may correspond to sub-arrays. For example, word lines 236-m, 236-(m+1), 236-(m+2), 236-(m+3), and 236-(m+4) and digit lines 230-n, 230-(n+1), and 230-(n+2) and memory cells coupled thereto may correspond to sub-arrays. Word lines 236-k, 236-(k+1), 236-(k+2), 236-(k+3), and 236-(k+4) and digit lines 231-n, 231-(n+1), and 231-(n+2) and memory cells coupled thereto may correspond to another sub-array. In some embodiments, memory array 206 may be a bank. As used herein, a "bank" refers to a memory array of a memory device, such as a Figure 1 The memory device 104 is described in association.

[0029] Although not Figure 2 206, local I / O lines LIO 238-1 and LIOF 238-2 may be coupled to one or more I / O lines (e.g., global I / O lines) that provide communication between the memory array 206 and one or more components external to the memory array 206. In some embodiments, a multiplexer may couple multiple local I / O lines of the memory array 206 to a global I / O line. In some embodiments, a multiplexer may be coupled to multiple global I / O lines. For example, eight global I / O lines may be coupled to the multiplexer, where each global I / O line coupled to the multiplexer provides a respective bit of a data byte to be transferred to or from the memory array 206.

[0030] Sense amplifier 208 may be electrically connected to LIO 238-1 via column decoder transistors 232-n, 232-(n+1), and 232-(n+2). Sense amplifier 208 may be connected to LIOF 238-2 via column decoder transistors 233-n, 233-(n+1), and 233-(n+2). In some embodiments, column decoding transistors 232 and 233 may be coupled to respective sense amplifiers 208 and respective complementary digital line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) such that disabling one or more of column decoding transistors 232 and 233 electrically connects and disconnects sense amplifier 208 from LIO 238-1 and / or LIOF 238-2. One or more of column decode transistors 232 and 233 may be enabled to communicate a signal corresponding to a state of a memory cell (e.g., a logic data value such as a logic “0” or a logic “1”) and / or a logic data value stored by sense amplifier 208 to LIO 238-1 and / or LIOF 238-2.

[0031] Column decoder transistors 232 and 233 may be coupled to a column decoder (eg, Figure 1 Sense amplifier 208 may be electrically connected to LIO 238-1 and / or LIOF 238-2 via column decoder transistors 232 and 233 in association with operating sense amplifier 208 in a sense amplifier mode.

[0032] Sense amplifier 208 may include equalization circuitry 246 and latch 247 (e.g., a static latch, such as a cross-coupled latch). Latch 247 may include a pair of cross-coupled n-channel transistors (e.g., NMOS transistors) 243-1 and 243-2, whose respective sources are selectively coupled to a reference voltage (e.g., ground). Respective source / drain regions of cross-coupled n-channel transistors 243-1 and 243-2 may be coupled to a negative control signal line that provides a negative control signal (e.g., RnlF). Cross-coupled n-channel transistor 243-1 may have a source / drain region directly coupled to a latch node of sense amplifier 208 coupled to digit line 230. Cross-coupled n-channel transistor 243-2 may have a source or drain directly coupled to a different latch node of sense amplifier 208 coupled to digit line 231.

[0033] Latch 247 may also include a pair of cross-coupled p-channel transistors (e.g., PMOS transistors) 242-1 and 242-2. Respective source / drain regions of cross-coupled p-channel transistors 242-1 and 242-2 may be coupled to a positive control signal line that provides a positive control signal (e.g., ACT). Cross-coupled p-channel transistor 242-1 may have a source / drain region directly coupled to a latch node of sense amplifier 208 coupled to digit line 230. Cross-coupled p-channel transistor 242-2 may have a source / drain region directly coupled to a different latch node of sense amplifier 208 coupled to digit line 231.

[0034] The gate of cross-coupled n-channel transistor 243-1 and the gate of cross-coupled p-channel transistor 242-1 may be coupled to a latch node of sense amplifier 208 coupled to digit line 230. The gate of cross-coupled n-channel transistor 243-2 and the gate of cross-coupled p-channel transistor 242-2 are coupled to a latch node of sense amplifier 208 coupled to digit line 231.

[0035] Equalization circuitry 246 may be configured to equalize complementary digital line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2). Equalization circuitry 246 may include transistors 241 coupled between complementary digital line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2). Equalization circuitry 246 may also include transistors 240-1 and 240-2, each having a first source / drain region coupled together. A second source / drain region of transistor 240-1 may be coupled to a corresponding digital line 230, and a second source / drain region of transistor 225-2 may be coupled to a corresponding digital line 231. The gates of transistors 241, 240-1, and 240-2 may be coupled together and to an equalization control signal line that provides an equalization control signal (EQ). Thus, activating EQ turns on transistors 241, 240-1, and 240-2, which effectively shorts the complementary digital line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) together and to an equalization voltage (e.g., V DD / 2).

[0036] In some embodiments, transistors 241, 240-1, and 240-2 are n-channel transistors. However, embodiments of the present disclosure are not limited to transistors of a particular conductivity type. For example, opposite control signals can be used with transistors of opposite conductivity types to implement the same sense amplifier functionality.

[0037] When a memory cell is sensed (e.g., read), the voltage on the digit line of one of the complementary digit line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) may be slightly greater than the voltage on the other digit line in the pair. The ACT signal may be driven high and the RnIF signal may be driven low to enable one or more of the sense amplifiers 208. The digit line with the lower voltage in the pair turns on one of the PMOS transistors 242-1 or 242-2 to a greater degree than the other of the PMOS transistors 242-1 or 242-2. Thus, the digit line with the higher voltage in the pair is driven high to a greater degree than the other digit line.

[0038] Similarly, the digit line of one of the complementary digit line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) with the higher voltage will turn on one of the NMOS transistors 243-1 or 243-2 to a greater degree than the other of the NMOS transistors 243-1 or 243-2. ​​Thus, the digit line with the lower voltage in the pair is driven low to a greater degree than the other digit line. After a short delay, the digit line with the larger voltage in the pair can be driven to the supply voltage (e.g., V DD ) and the other digital line can be driven to a voltage of a reference voltage (e.g., ground). Thus, NMOS transistors 243-1 and 243-2 and PMOS transistors 242-1 and 242-2 function as a sense amplifier pair that amplifies the voltage differential on complementary digital line pairs 230-n / 231-n, 230-(n+1) / 231-(n+1), and 230-(n+2) / 231-(n+2) and operates to latch the data value sensed from the memory cell.

[0039] The sense amplifier 208 may be used to perform a logic operation, such as a logic AND / OR operation. In some embodiments, in order to perform a logic AND operation on data (e.g., operands) stored in at least two memory cells coupled to different rows (e.g., rows 234-k and 234-k+1) and the same digital line (e.g., a non-reference digital line), the rows (e.g., rows 234-k and 234-k+1) may be activated (turned on) together with another row (e.g., row 236-m+4) of memory cells coupled to at least one memory cell (alternatively referred to as a "reference memory cell") of another row storing a logic "1" (which may be referred to as a "reference data value" (e.g., for the logic AND operation)). The memory cell storing the reference data value may be coupled to a different digital line (e.g., a reference digital line) instead of being coupled to the non-reference digital line of the two rows coupled to the two memory cells. The sense amplifiers 208 coupled to these reference and non-reference digital lines may be activated (stimulated) to sense (and store) the result of the logic AND operation. If the memory cells of a row and a different row (e.g., rows 234-k and 234-k+1) and the memory cells of another row (e.g., row 236-m+4) both store logic "1", then activating the three row and sense amplifiers causes the sense amplifiers to sense logic "1", which is the result of logic "1" AND logic "1". If either or both of the memory cells of a row and a different row (e.g., rows 234-k and 234-k+1) are storing logic "0", then activating the three row and sense amplifiers causes the sense amplifiers to sense logic "0", which is the result of logic "0" AND logic "1", logic "1" AND logic "0", and logic "0" AND logic "0".

[0040] In some embodiments, to perform a logical OR operation on data (e.g., operands) stored in at least two memory cells coupled to different rows (e.g., rows 234-k and 234-k+1) and the same digital line, the rows (e.g., rows 234-k and 234-k+1) may be activated (turned on) together with another row (e.g., row 236-m+4) of memory cells coupled to at least one memory cell of the row storing a logic "0" (which may be referred to as a "reference data value" (e.g., for the logical OR operation) (alternatively referred to as a "reference memory cell"). The memory cell storing the reference data value may be coupled to a different digital line (e.g., a reference digital line) instead of being coupled to a non-reference digital line of the two rows coupled to the two memory cells. The sense amplifiers 208 coupled to these reference and non-reference digital lines may be activated (excited) to sense (and store) the result of the logical OR operation. If either or both of the memory cells of a row and a different row (e.g., rows 234-k and 234-k+1) are storing logic “0,” then activating the three row and sense amplifiers results in the sense amplifiers sensing logic “1,” which is the result of logic “0” OR logic “1,” logic “1” OR logic “0,” and logic “1” OR logic “1.” If both of the memory cells of a row and a different row (e.g., rows 234-k and 234-k+1) are storing logic “0,” then activating the three row and sense amplifiers results in the sense amplifiers sensing logic “0,” which is the result of logic “0” OR logic “0.”

[0041] In some embodiments, multiple sense amplifiers 208 may be used to perform multiple logic operations (e.g., logical AND or OR operations) simultaneously (e.g., substantially simultaneously). For example, logic operations may be performed using data stored in all memory cells of two rows (e.g., rows 234-k, 234-k+1) coupled to one side (non-reference side) and using (e.g., in response to) reference data values ​​stored in all memory cells of one row (e.g., row 236-m+4) coupled to the other side (reference side). As used herein, "reference side" refers to one of the complementary sides including reference digit lines and / or reference word lines, and "non-reference side" refers to the other of the complementary sides including non-reference digit lines and / or non-reference word lines. As used herein, the term "substantially" means that a characteristic need not be absolute, but close enough to achieve the advantage of the characteristic. For example, "substantially simultaneously" is not limited to operations performed absolutely simultaneously, and may include timing that is expected to be simultaneous but may not be exactly simultaneous.

[0042] Although the embodiment is not limited, the reference data values ​​for logical AND and OR operations may be stored in memory cells in units of rows of memory cells. For example, while the memory cells coupled to row 236-m may all be configured to store reference data values ​​(e.g., "1") for logical AND operations, the memory cells coupled to row 236-m+1 may all be configured to store reference data values ​​(e.g., "0") for logical OR operations. Thus, in this configuration, the logical operations performed substantially simultaneously using (in response to) the reference data values ​​stored on the memory cells coupled to the same row may be the same logical (e.g., AND or OR) operation.

[0043] Although embodiments are not so limited, rows of memory cells on one side (e.g., rows 236-k, ..., 236-k+4 or 236-m, ..., 236-m+4) may be configured for reference data values. For example, while data stored on memory cells coupled to row 236-k (e.g., row 236-k, ..., 236-k+4) are used as operands for logical operations, memory cells coupled to row 236-m (e.g., row 236-m, ..., 236-m+4) may be configured to store corresponding reference data values. However, embodiments are not so limited. For example, memory cells on a row coupled to a reference digital line may store different data values, such that different logical (e.g., AND or OR) operations may be performed using (in response to) reference data values ​​stored on a single row (e.g., memory cells coupled to the single row).

[0044] Figure 3 FIG. 1 is a schematic diagram of a row 334 of a memory array 306 and a sense amplifier 308 that can use multiple digital lines 330, 331 to perform logic operations according to several embodiments of the present disclosure. The memory array 306 and the sense amplifier 308 can be similar to Figure 2 Memory array 206 and sense amplifier 208 are depicted in association.

[0045] Figure 3 Describe the embodiments of the present disclosure, which are Figure 2 The illustrated embodiment differs in the inclusion of additional transistors 344-n, 344-(n+1), and 344-(n+2) (collectively transistor 344) and transistors 345-n, 345-(n+1), and 345-(n+2) (collectively transistor 345) dedicated to isolating sense amplifier 308 from the capacitance of digit lines 330 and 331. Sense amplifier 308 may be isolated (electrically disconnected) from the capacitance of digit lines 330 and 331 via transistors 344 and 345, respectively, in association with operating sense amplifier 308 as an SRAM cache.

[0046] Each of transistors 344 has a source / drain region coupled to a corresponding one of digit lines 330, and another source / drain region coupled to one of sense amplifiers 308 coupled to the digit line. Each of transistors 345 has a source / drain region coupled to a corresponding one of digit lines 331, and another source / drain region coupled to one of sense amplifiers 308 coupled to the digit line. The gates of transistors 344 and 345 may be coupled to a signal line through which a control signal ISO may be provided.

[0047] Figure 3 Transistors 344 and 345 are illustrated as n-channel transistors (e.g., NMOS transistors). For example, driving the control signal ISO high may enable transistors 344 and 345 such that sense amplifier 308 is electrically connected to memory array 306. Driving the control signal ISO low may disable transistors 344 and 345 such that sense amplifier 308 is isolated (electrically disconnected) from the capacitance of digit lines 330 and 331, respectively. However, embodiments of the present disclosure are not limited to any of transistors 344 and / or 345 being n-channel transistors. For example, transistors 344 and 345 may be p-channel transistors (e.g., PMOS transistors). In such embodiments, driving the control signal ISO high may disable transistors 344 and 345 such that sense amplifier 308 is isolated (electrically disconnected) from the capacitance of digit lines 330 and 331.

[0048] Figure 4 Various voltage levels at which the voltages at which the digital lines are biased when performing logic operations according to several embodiments of the present disclosure are described. Although the embodiments are not so limited, Figure 4 Illustrate the voltage levels associated with performing a logical "AND" operation.

[0049] At least three memory cells, three word lines coupled to the three memory cells (e.g., Figures 2 to 3 236, 336) and two digit lines (eg, Figures 2 to 3 230, 231, 330, 331) as described in the Figure 4, and the logical AND operation described in . For example, two memory cells coupled to the same digital line (e.g., digital lines 230, 330) may respectively store operands for the logical AND operation, while one memory cell coupled to a different digital line (e.g., digital lines 231, 331) may store a reference voltage corresponding to a reference data value, the binary value of the reference data value (alternatively referred to as a logical value) being specifically used to perform the logical AND operation. For example, the reference data value used for the logical AND operation may be a binary value of "1", but the embodiments are not so limited. As described herein, the digital line coupled to the memory cell storing the reference data value may alternatively be referred to as a "reference digital line". In addition, the two digital lines may be those digital lines coupled to the same sense amplifier (e.g., sense amplifiers 208, 308). As further described herein, the reference data value operates to adjust the voltage differential sensed at the sense amplifier as needed when performing a logical AND (e.g., or OR) operation.

[0050] During phase 452, the two digital lines are equalized at a specific voltage level, such as Figure 4 During phase 454, three word lines (alternatively referred to as "rows") are activated separately. Although embodiments are not so limited, the three word lines may be activated substantially simultaneously.

[0051] When the corresponding word line is activated, each binary value "1" on the memory cell can raise the voltage level at which the corresponding digit line (two "activated" word lines are coupled to it) by 0.1V, and each binary value "1" on the memory cell can lower the voltage level at which the corresponding digit line is biased by 0.1V. Figure 4 As described in , storing two "1"s (for example, Figure 4 ) (e.g., its operands) may raise the voltage level of the digit line (e.g., the voltage level at which the digit line is biased) by 0.2V (e.g., from the equilibrium voltage of 0.5V to 0.7V), as indicated by 453-1; store "1" and "0" (e.g., as Figure 4 , (0,1) or (1,0)) may keep the voltage level of the digit line (e.g., the voltage level at which the digit line is biased) at 0.5V (e.g., 0.5V+0.1V-0.1V), as indicated by 453-2; and store two "0"s (e.g., as indicated by Figure 4 The two memory cells (“(0,0)” illustrated in ) may reduce the voltage level of the digit line (eg, the voltage level at which the digit line is biased) by 0.2V (eg, from an equilibrium voltage of 0.5V to 0.3V), as indicated by 453-3.

[0052] Assuming the reference data value is equal to the binary value "1", the reference digit line is during phase 454 and as indicated by Figure 4 451 is biased at 0.6V. Therefore, the differential voltage sensed at the sense amplifier is "negative" (e.g., the voltage level of the reference digit line is greater than the voltage level of the other digit line) unless the operands stored at both memory cells are "1". Therefore, when the two operands are (1,1), the activation (e.g., firing) of the sense amplifier during stage 456 results in the differential voltage being driven high to 1V (which corresponds to the binary value of "1"), and when the two operands are (0,1), (1,0) and / or (0,0), the differential voltage is driven low to 0V (which corresponds to the binary value of "0"). The data value sensed at the sense amplifier as a result of activating the two digit lines and the three word lines corresponds to the result of the logical AND operation.

[0053] Figure 5 Various voltage levels at which the voltages at which the digital lines are biased when performing logic operations according to several embodiments of the present disclosure are described. Although the embodiments are not so limited, Figure 5 Illustrate the voltage levels associated with performing a logical "OR" operation.

[0054] Figure 5 Roughly similar to Figure 4 , except that a reference data value of "0" (as opposed to a reference data value of logic "1" for a logical AND operation) is used to perform a logical OR operation. For example, as opposed to the reference digital line being biased at 0.6V during stage 454, a reference digital line corresponding to a reference data value of logic "0" is biased during stage 564 and as indicated by Figure 5 As indicated by 561, the differential voltage sensed at the sense amplifier is "positive" (e.g., the voltage level of the reference digit line is less than the voltage level of the other digit line) unless the operands stored at both memory cells are "0". Therefore, when the two operands are (0,0), the activation (e.g., excitation) of the sense amplifier during stage 566 results in a differential voltage driven low to 0V (which corresponds to a binary value of "0"), and when the two operands are (0,1), (1,0) and / or (1,1), the differential voltage is driven high to 1V (which corresponds to a binary value of "1"). The data value sensed at the sense amplifier as a result of activating the two digit lines and the three word lines corresponds to the result of a logical OR operation. As shown in Figure 4 and 5 As an example, logic (eg, AND and / or OR) operations may be performed with one clock cycle, wherein the corresponding word line, digit line, and / or sense amplifier is activated.

[0055] As this article combines Figures 4 to 5Performing logic operations such as AND and / or OR logic operations as described above may provide benefits over those methods that activate only one of two digit lines to perform the logic operation. For example, consider a configuration in which reference data values ​​are stored on the same side as those memory cells storing operands for the logic operation, such that performing the logic operation involves only activating three word lines on the same side (e.g., activating a single digit line). The more word lines on the same side, the higher the likelihood of noise and interference among the word lines, which may lead to errors during the execution of the logic operation. On the other hand, diversifying the number of word lines (e.g., activated to perform the logic operation) across multiple digit lines may provide more precise voltage tuning capabilities on both sides, which may reduce the risk of noise and interference when activating the word lines.

[0056] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It should be appreciated that the above description has been made in an illustrative and non-restrictive manner. After reviewing the above description, those skilled in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of the present disclosure includes other applications using the above structures and processes. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the full range of equivalents enjoyed by such claims.

[0057] In the foregoing detailed description, some features are grouped in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than those explicitly recited in each claim. Rather, as the appended claims reflect, the inventive subject matter resides in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A method for performing a logic operation in a memory, comprising: The data stored in the digital lines coupled to the first digital lines (230-n, 230-(n+1), 230-(n+2), 231-n, 231-(n+1), 231-(n+2); 330-n, 330-(n+1), 330-(n+2), 331-n, 331-(n+1), 331-(n+2)) performs a logic operation on the data values ​​in the first memory cell and the second memory cell, and the sense amplifier (108; 208-n, 208-(n+1), 208-(n+2); 308-n, 308-(n+1), 308-(n+2)) is coupled to the first digital line: activation: A first word line (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)); A second word line (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)); and A third word line (236-k, 236-(k+1), 236-(k+2), 236-(k+3), coupled to a third memory cell 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)), wherein the third memory cell is coupled to the second digital line (230-n, 230-(n+1), 230-(n+2), 231-n, 231-(n+1), 231-(n+2)) to which the sense amplifier is coupled; 330-n, 330-(n+1), 330-(n+2), 331-n, 331-(n+1), 331-(n+2)); as well as The sense amplifier is activated, wherein a data value sensed at the sense amplifier corresponds to a result of the logic operation. 2 . The method of claim 1 , wherein the third memory cell is configured to store a first reference data value or a second reference data value. 3 . The method of claim 2 , further comprising performing a logical AND operation on the data values ​​respectively stored in the first memory cell and the second memory cell in response to the third memory cell storing the first reference data value. 4 . The method of claim 2 , further comprising performing a logical OR operation on the data values ​​respectively stored in the first memory cell and the second memory cell in response to the third memory cell storing the second data value.

5. The method according to any one of claims 1 to 4, further comprising: equalizing the first word line, the second word line, and the third word line before activating the first word line, the second word line, and the third word line; as well as The sense amplifier is activated when the first word line, the second word line, and the third word line are activated.

6. The method of any one of claims 1 to 4, further comprising activating the first word line, the second word line, and the third word line simultaneously.

7. An apparatus for performing a logical operation in a memory, comprising: first digit lines (230-n, 230-(n+1), 230-(n+2), 231-n, 231-(n+1), 231-(n+2); 330-n, 330-(n+1), 330-(n+2), 331-n, 331-(n+1), 331-(n+2)) coupled to a first plurality of memory cells coupled to respective first word lines (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)); second digit lines (230-n, 230-(n+1), 230-(n+2), 231-n, 231-(n+1), 231-(n+2); 330-n, 330-(n+1), 330-(n+2), 331-n, 331-(n+1), 331-(n+2)) coupled to a second plurality of memory cells coupled to respective second word lines (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)); a sense amplifier (108; 208-n, 208-(n+1), 208-(n+2); 308-n, 308-(n+1), 308-(n+2)) coupled to the first digit line and the second digit line; and A controller (110) configured to perform a logic operation on data values ​​stored in at least two of the first plurality of memory cells by: activating the corresponding first word lines (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)); activating a corresponding second word line (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)), wherein said memory cells of said second plurality of memory cells store voltages corresponding to reference data values; as well as The sense amplifier is activated to store a result of the logic operation therein.

8. The apparatus of claim 7, wherein the controller is configured to simultaneously activate the corresponding first word line to which the at least two memory cells are coupled and the corresponding second word line to which the memory cells of the second plurality of memory cells are coupled.

9. The apparatus of claim 8, wherein the controller is configured to activate the sense amplifier when the corresponding first word line to which the at least two memory cells are coupled and the corresponding second word line to which the memory cells of the second plurality of memory cells are coupled are simultaneously activated.

10. The apparatus of claim 7, wherein the result of the logical operation is one of: in response to the reference data value being a first data value of a first reference data value; or A second data value is provided in response to the reference data value being a second reference data value.

11. The apparatus of claim 10, wherein: The result of the logical operation is in response to the reference data value being a logical AND result of the first data value; and The result of the logical operation is a logical OR result in response to the reference data value being the second data value.

12. The apparatus of claim 11, wherein the corresponding second word line to which the memory cells in the second plurality of memory cells are coupled is also coupled to a plurality of additional memory cells, wherein the plurality of additional memory cells each store a reference voltage corresponding to the reference data value.

13. An apparatus for performing a logical operation in a memory, comprising: Memory array (106; 206； 306), which includes: A plurality of memory cells coupled to a first digit line (230-n, 230-(n+1), 230-(n+2), 231-n, 231-(n+1), 231-(n+2); 330-n, 330-(n+1), 330-(n+2), 331-n, 331-(n+1), 331-(n+2)); A first memory cell coupled to a second digit line (230-n, 230-(n+1), 230-(n+2), 231-n, 231-(n+1), 231-(n+2); 330-n, 330-(n+1), 330-(n+2), 331-n, 331-(n+1), 331-(n+2)) and the first word line (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+ 2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)), the first memory cell is configured to store a first reference data value having a first data value; a second memory cell coupled to the second digit line and the second word line (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)), the second memory cell is configured to store a second reference data value having a second data value; and sense amplifiers (108; 208-n, 208-(n+1), 208-(n+2); 308-n, 308-(n+1), 308-(n+2)) coupled to the first digit line and the second digit line; and The controller (110) is configured to perform the following operations in order to perform a first logic operation on data values ​​respectively stored in two memory cells of the plurality of memory cells coupled to the first digit line: Activate two word lines (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4); 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)); and The first word line is activated substantially simultaneously with the two word lines being activated to further adjust the voltage differential sensed at the sense amplifier based on the first reference data value stored on the first memory cell.

14. The apparatus of claim 13, wherein the controller is configured to, in order to perform a second logic operation on data values ​​respectively stored in two memory cells of the plurality of memory cells coupled to the first digit line, perform the following operations: activating two word lines (236-k, 236-(k+1), 236-(k+2), 236-(k+3), 236-(k+4), 236-m, 236-(m+1), 236-(m+2), 236-(m+3), 236-(m+4)) coupled to the two memory cells; 336-k, 336-(k+1), 336-(k+2), 336-(k+3), 336-(k+4), 336-m, 336-(m+1), 336-(m+2), 336-(m+3), 336-(m+4)); and The second word line is activated substantially simultaneously with the two word lines being activated to further adjust the voltage differential sensed at the sense amplifier based on the second reference data value stored on the second memory cell.

15. Apparatus according to any one of claims 13 to 14, wherein: The first logical operation is an AND logical operation; and The activation of the first word line coupled to the first memory cell storing the first reference data value raises the voltage level at which the second digit line is biased.

16. Apparatus according to any one of claims 13 to 14, wherein: The first logical operation is an OR logical operation; and The activation of the second word line coupled to the first memory cell storing the first reference data value lowers the voltage level at which the second digit line is biased.

17. The apparatus of any one of claims 13-14, wherein the sense amplifier is one of a plurality of sense amplifiers (108; 208-n, 208-(n+1), 208-(n+2); 308-n, 308-(n+1), 308-(n+2)), and wherein the controller is configured to perform a plurality of logic operations substantially simultaneously using the plurality of sense amplifiers.

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