Circuit for tracking read-write duration of FPGA BRAM storage sequence

Abstract

According to the circuit for tracking the read-write duration of the storage sequence of the FPGA BRAM, the working duration of the storage array is obtained by simulating and tracking the working duration of the storage array, and then the pulse width of the time sequence is configured according to the working duration, so that the pulse width of the working time sequence does not need to be calculated and configured before the BRAM stores data every time, and the working time sequence is not required to be calculated. The pulse width setting error rate of the BRAM is reduced, and the development efficiency of the BRAM is improved.

Description

Technical Field

[0001] The invention belongs to the field of FPGA, and in particular relates to a circuit for tracking the reading and writing duration of an FPGA BRAM storage sequence. Background Art

[0002] Field-Programmable Gate Array (FPGA) is a general-purpose programmable logic device with high flexibility and high parallelism. It usually includes programmable logic blocks (CLB), programmable interconnect resources (CR), input and output blocks (IOB) and other IP resources, such as block RAM (BRAM), digital signal processor (DSP), etc. It provides users with system programmable or reconfigurable capabilities.

[0003] BRAM is the main block storage resource in FPGA. Its internal structure is mainly composed of static random access memory (SRAM). It not only provides a large amount of storage space for FPGA, but also has the advantages of flexible storage mode, high compatibility, and no need for periodic refresh, providing intrinsic support for the high flexibility function of FPGA.

[0004] The conventional design of FPGA BRAM timing pulse width control begins after the BRAM timing control circuit design is completed. The timing pulse width configuration is based on the different time required to write data into SRAM and read data from SRAM. Under the condition that data reading and writing can be completed, the BRAM working timing pulse width is calculated and configured. Since the pulse width of the configuration working timing must be calculated before each BRAM is used to store data, it not only increases the error rate of BRAM pulse width setting, but also limits the development efficiency of BRAM. Summary of the invention

[0005] The main problem solved by the present invention is how to configure the working timing pulse width of BRAM, and provides a circuit for tracking the reading and writing duration of FPGA BRAM storage sequence.

[0006] In order to solve the above technical problems, the technical solution adopted is: A circuit for tracking the read and write duration of an FPGA BRAM storage sequence, comprising a row decoding circuit, a row tracking simulation circuit, and a column tracking simulation circuit; The row decoding circuit is used to determine which row of unit cells in the static random access memory SRAM storage array is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the unit cells in this row; The row tracking simulation circuit uses n pairs of NMOS tubes to simulate the opening time of n unit cells in a row of a word line WL in a static random access memory SRAM storage array. The gates of the n pairs of NMOS tubes are respectively connected to a row tracking start signal. The row tracking start signal is generated by a global working clock signal after the row decoding circuit determines which row of unit cells are working and generates a high level. The source and drain of the n pairs of NMOS tubes are connected to the ground signal. After the n pairs of NMOS tubes are charged, a feedback signal of row tracking completion is given. The column tracking simulation circuit uses m NMOS tubes to simulate the read and write working time of a bit line BL in a column of m units in a static random access memory SRAM storage array, and the column tracking start signal is respectively input into the source end of the m NMOS tubes, and the gate and drain of the m NMOS tubes are connected to the ground signal; The column tracking start signal is triggered by the feedback signal of row tracking completion to give a column tracking start signal; The column tracking start signal completes the tracking after the charging of m NMOS tubes is completed, and a trigger signal of tracking completion is given.

[0007] Furthermore, when the original clock signal clk, at its rising edge, combines with the BRAM work enable signal and the power-on clear signal por_reset signal under the combinational logic switch to form the working clock signal clk1 that enables the BRAM to start working, the tracking completed trigger signal gives the working clock signal clk1 a signal that is pulled down to a low level for pulse width control.

[0008] Furthermore, after completing the tracking, the column tracking start signal passes through two stages of inverters to give a trigger signal.

[0009] By adopting the above technical solution, the present invention has the following beneficial effects: The present invention provides a circuit for tracking the read and write duration of an FPGA BRAM storage sequence. The circuit simulates and tracks the working duration of a storage array to obtain the working duration of the storage array, and then configures the timing pulse width according to the working duration. Therefore, it is not necessary to calculate the pulse width of the configured working timing before each data storage in the BRAM, thereby reducing the error rate of the BRAM pulse width setting and improving the development efficiency of the BRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the SRAM storage array; Figure 2To trace the schematic diagram of the analog circuit structure; Figure 3 It is a schematic diagram of the structure of a unit cell in the SRAM storage array; Figure 4 It is a schematic diagram of the structure of the line tracking analog circuit; Figure 5 It is a schematic diagram of the structure of the column tracking analog circuit; Figure 6 This is a schematic diagram of the operation of the row tracking start signal and the column tracking start signal. DETAILED DESCRIPTION

[0011] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0012] In this embodiment, Figures 1 to 6 The present invention shows a circuit structure for tracking the read and write duration of an FPGA BRAM storage array, which includes a row decoding circuit, a row tracking simulation circuit, and a column tracking simulation circuit; The row decoding circuit is used to determine which row of unit cells in the static random access memory SRAM storage array is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the unit cells in this row; like Figure 1 As shown, the number of rows of the static random access memory SRAM storage array in the BRAM is m, and the number of columns is n, so the number of NMOS tubes used in the tracking circuit can be determined according to the number of rows m and the number of columns n in the SRAM storage array. Figure 2 In the process, the timing circuit module 1 generates the rising edge of the working clock clk1, which passes through the row decoding circuit to obtain the cell row in the static random access memory SRAM storage array in the BRAM to be selected to work. On the one hand, the word line WL is given to turn on all the cell rows in the selected row in the SRAM. On the other hand, the row decoding circuit simultaneously gives the row tracking start signal TKWL1 to start the row tracking analog circuit to work, which is used to simulate the tracking of the working time of the word line WL, so the row tracking analog circuit is also called the WL tracking circuit.

[0013] like Figure 3The schematic diagram of the structure of a unit cell in the SRAM storage array shown in the figure, when the word line WL is high, a pair of NMOS tubes PGL0 and PGR0 in a unit cell are turned on. In order to simulate the time when the word line WL turns on all NMOS tubes in a row, there are n unit cells in a row of the static random access memory SRAM storage array according to the statistics above, so the row tracking simulation circuit is as follows Figure 4 As shown, n pairs of 2n NMOS tubes are used to simulate the opening time of n unit cells on a word line WL. The gates of the n pairs of NMOS tubes are respectively connected to the line tracking start signal TKWL1, and the source and drain of the n pairs of NMOS tubes are connected to the ground signal Tielow. When the line tracking start signal is at a high level, the n pairs of NMOS tubes start charging. When the n pairs of NMOS tubes are charged, it means that the simulation of the opening time of each unit cell is completed. In this embodiment, Figure 4 The source and drain grounding of the NMOS tube in the line tracking simulation circuit is a wiring method for simulating the cell in the SRAM storage array. This embodiment uses the capacitance between the source and the gate to simulate the parasitic capacitance at the BL bit line in the unit cell. It has no functional effect, only charging and discharging. After the line tracking simulation is completed, a feedback signal TKWLFB1 indicating the completion of the line tracking is given, such as Figure 2 As shown, the feedback signal TKWLFB1 completed by row tracking is used as the trigger signal of the column tracking start signal TKBL1. The column tracking start signal starts analog tracking of the bit line BL in the SRAM storage array, so the column tracking circuit is also called the BL tracking circuit. Figure 6 As shown, the feedback signal TKWLFB1 of the row tracking completion is passed through a two-stage inverter to provide a trigger signal of the column tracking start signal TKBL1. The two-stage inverter is used to strengthen the driving force.

[0014] In this embodiment, Figure 6 As shown, the row decoding circuit adopts the commonly used row decoding circuit, and generates the word line WL signal of the m row by the x-bit row address encoding, where the relationship between x and m is When the row decoding circuit encodes the x-bit row address to generate the word line WL signal of the m-row, the row tracking start signal TKWL1 for row tracking is triggered, so that the row tracking simulation starts when the word line WL opens a row of cells in the SRAM storage array.

[0015] Figure 1 In the example, each bit line BL is input and output from the source terminal of the NMOS tube PGL0, so the column tracking analog circuit is as follows Figure 5 As shown, m NMOS tubes are used to simulate the read and write working time of the PGL0 NMOS tube of m cells in a column and m rows in a SRAM storage array. Figure 3In the figure, BL and BLN carry a pair of opposite data, which come in at the same time and are consistent in time, so there is no need to simulate BLN and PGR0. When the SRAM is working, after the row decoding circuit selects to open all the cells in the word line WL of a certain row, the corresponding bit line BL is opened at the same time according to the number of bits of data to be written. Therefore, the read and write time of multiple columns is consistent with that of one column, so m NMOS tubes in a column can be used for simulation. The column tracking start signal TKBL1 is input to the source of the m NMOS tubes, and the gate and drain are connected to the ground signal Tielow. The reason for this design is that in this embodiment, the m NMOS tubes only use the capacitance between the source and the gate to simulate the parasitic capacitance at the BL bit line in the cell. It has no functional effect, only charging and discharging. The gate is connected to the ground signal Tielow to make the NMOS tube in a non-conducting state. Secondly, from Figure 3 It can be seen from the unit cell shown that the values ​​of the two points Q and QB in the cell must be one 0 and one 1, so the drain of one of the PGL0 NMOS tube and the PGR0 NMOS tube is always connected to 0. Since the cell is symmetrical, the PGL0 NMOS tube and the PGR0 NMOS tube are operated at the same time, so the simulation of the cell working process time only needs to simulate the NMOS tube on one side, so in the column tracking circuit, the drain of the NMOS tube is also connected to the ground signal tielow. In the SRAM storage array, the BL bit line is connected to the source of the NMOS tube, so in this embodiment, the column tracking start signal TKBL1 is connected to the source of m NMOS tubes. In addition, when the BRAM is working, only one row in the SRAM storage array will be opened at a time, that is, only one of the m PGL0 NMOS tubes on the BL bit line will be opened, and the gates of the other m-1 PGL0 NMOS are all closed at low voltage. In this embodiment, since the number of rows m of cells in the SRAM is a large value when designed, and when a large number of NMOS tubes are used, the time required for charging the source and gate capacitors when the gate of one NMOS tube is turned on and the time required for charging the source and gate capacitors when the gate of one NMOS tube is not turned on are very similar, m NMOS tube gates are connected to tielow to simulate m rows of cells. The column tracking start signal completes the tracking after the charging of the m NMOS tubes is completed, and a tracking completion trigger signal is given after the column simulation tracking is completed.

[0016] from Figure 2It can also be seen that BRAM is completely symmetrical. Before using BRAM, it is necessary to configure whether to use a single port or a dual port. In the case of a single port, the tracking circuit on the corresponding side of the port can be used for tracking. The working clock signal clk1 generated by WL, BL and the timing circuit module 1 can be used, and the working clock circuit signal clk2 generated by WR, BR and the timing circuit module 2 can also be used. If a dual port is configured, the tracking circuits on both sides need to be used to track the ports on each side respectively.

[0017] In this embodiment, when the original clock signal clk forms the working clock signal clk1 that starts the BRAM to work under the combination of the combinational logic switch at its rising edge and the BRAM working enable signal and the power-on clear signal por_reset, the tracking completed trigger signal gives the working clock signal clk1 a signal that is pulled down to a low level for pulse width control. Through the tracking circuit, the working timing pulse width of the BRAM can be obtained, so that the timing pulse width of the FPGA BRAM can be configured in real time, and it is not necessary to calculate the pulse width of the configuration working timing before each data storage in the BRAM, which reduces the error rate of the BRAM pulse width setting and improves the development efficiency of the BRAM.

[0018] In this embodiment, after the column tracking start signal completes the tracking, it passes through a two-stage inverter to give a trigger signal. The two-stage inverter is used to enhance the driving force.

[0019] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit for tracking the read and write duration of an FPGA BRAM storage sequence, characterized in that: It includes a row decoding circuit, a row tracking analog circuit, and a column tracking analog circuit; The row decoding circuit is used to determine which row of unit cells in the static random access memory SRAM storage array is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the unit cells in this row; The row tracking simulation circuit uses n pairs of NMOS tubes to simulate the opening time of n unit cells in a row of a word line WL in a static random access memory SRAM storage array. The gates of the n pairs of NMOS tubes are respectively connected to a row tracking start signal. The row tracking start signal is generated by a global working clock signal after the row decoding circuit determines which row of unit cells are working and generates a high level. The source and drain of the n pairs of NMOS tubes are connected to the ground signal. After the n pairs of NMOS tubes are charged, a feedback signal of row tracking completion is given. The column tracking simulation circuit uses m NMOS tubes to simulate the read and write working time of a bit line BL in a column of m units in a static random access memory SRAM storage array, and the column tracking start signal is respectively input into the source terminals of the m NMOS tubes, and the gates and drains of the m NMOS tubes are connected to the ground signal; the column tracking start signal is triggered by the feedback signal of the row tracking completion to give the column tracking start signal; the column tracking start signal completes the tracking after the charging of the m NMOS tubes is completed, and gives a trigger signal of tracking completion.

2. A circuit for tracking the read and write duration of an FPGA BRAM storage sequence according to claim 1, characterized in that: When the original clock signal clk, at its rising edge, combines with the BRAM work enable signal and the power-on clear signal por_reset signal under the combinational logic switch to form the working clock signal clk1 that enables the BRAM to start working, the tracking completed trigger signal gives the working clock signal clk1 a signal that is pulled down to a low level for pulse width control.

3. A circuit for tracking the read and write duration of an FPGA BRAM storage sequence according to claim 2, characterized in that: After completing the tracking, the column tracking start signal passes through two stages of inverters to give a trigger signal.

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