Memory programming method, memory and memory system

Abstract

The invention provides a programming method of a memory, the memory and a memory system, and relates to the technical field of semiconductor chips. The programming method includes: applying a programming voltage to a first word line coupled to a plurality of memory cells of a first memory cell slice and a plurality of memory cells of a second memory cell slice; in a stage of applying a program voltage to the first word line, turn-on voltages are sequentially applied to a first selection line coupled to a selection transistor of the first memory cell sheet and a second selection line coupled to a selection transistor of the second memory cell sheet. According to the method and the device, the time for programming the memory process is shortened.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor chip technology, and in particular, relates to a memory programming method, a memory, and a memory system. Background Art

[0002] NAND flash memory has the characteristics of non-volatility, fast read and write speed, low power consumption, and long service life, and is widely used in various electronic products, such as mobile phones, computers, smart sensors, and positioning devices. As consumers' requirements for the performance and reliability of electronic products increase, the market has put forward higher requirements for the reading speed, writing (also known as programming) speed, and service life of NAND flash memory. Summary of the invention

[0003] The embodiments disclosed in the present application provide a memory programming method, a memory and a memory system, which are used to shorten the time required for programming the memory and improve the writing speed of NAND flash memory.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a memory programming method is provided, the programming method comprising: applying a programming voltage to a first word line, the first word line is coupled to a plurality of memory cells of a first memory cell slice and a plurality of memory cells of a second memory cell slice; in the stage of applying the programming voltage to the first word line, applying a conduction voltage to a first selection line and a second selection line in sequence, the first selection line is coupled to a selection transistor of the first memory cell slice, and the second selection line is coupled to a selection transistor of the second memory cell slice. In the stage of applying the programming voltage to the first word line, by applying a conduction voltage to the first selection line and the second selection line in sequence, a plurality of memory cells coupled to the first word line in the first memory cell slice and a plurality of memory cells coupled to the first word line in the second memory cell slice are continuously programmed. Programming the first memory cell slice and the second memory cell slice by one programming voltage reduces the number of times the programming voltage is ramped up / down to a certain extent, reduces the time required for the programming voltage to be ramped up / down, and shortens the time required for programming the memory.

[0006] In some embodiments, after applying the programming voltage to the first word line, the method further includes: applying a verification voltage to the first word line; and applying a turn-on voltage to the first selection line and the second selection line in sequence during the stage of applying the verification voltage to the first word line. During the stage of applying the verification voltage to the first word line, the turn-on voltage is applied to the first selection line and the second selection line in sequence, thereby continuously verifying a plurality of memory cells coupled to the first word line in the first memory cell slice and a plurality of memory cells coupled to the first word line in the second memory cell slice. Verifying the first memory cell slice and the second memory cell slice by one verification voltage reduces the number of times the verification voltage is ramped up / down to a certain extent, reduces the time required for the verification voltage to be ramped up / down, and shortens the time required for programming the memory.

[0007] In some embodiments, in the stage of applying the turn-on voltage to the first selection line, the first pass voltage is applied to the second word line; the second word line is coupled to the other multiple memory cells of the first memory cell slice and the other multiple memory cells of the second memory cell slice; in the stage of applying the turn-on voltage to the second selection line, the second pass voltage is applied to the second word line. For a three-dimensional (3D) NAND flash memory, by continuously applying the first pass voltage and the second pass voltage to the second word line, the other multiple memory cells are turned on, thereby ensuring that the programming voltage can program the multiple memory cells coupled to the first word line, and the verification voltage can verify the multiple memory cells coupled to the first word line.

[0008] In some embodiments, the second pass voltage is greater than the first pass voltage. In the stage of applying the on-voltage to the second selection line, the second pass voltage can increase the channel potential of all memory cell strings in the first memory cell slice through gate voltage and capacitive coupling. This reduces the potential difference between the control gate potential and the channel potential of the memory cell in the first memory cell slice, making it difficult for charges to tunnel into the floating gate of the memory cell in the first memory cell slice, thereby prohibiting programming of the first memory cell slice in the stage of applying the on-voltage to the second selection line.

[0009] In some embodiments, the programming method further includes: applying a third pass voltage to a third word line during the stage of applying a turn-on voltage to the first selection line; coupling the third word line to a plurality of dummy memory cells of the first memory cell slice and a plurality of dummy memory cells of the second memory cell slice; applying a fourth pass voltage to the third word line during the stage of applying a turn-on voltage to the second selection line. The memory cell string often also includes a dummy memory cell coupled to a pseudo word line, and the dummy memory cell is turned on by continuously applying the third pass voltage and the fourth pass voltage to the third word line, thereby ensuring that the programming voltage can program the plurality of memory cells coupled to the first word line, and the verification voltage can verify the plurality of memory cells coupled to the first word line.

[0010] In some embodiments, the fourth pass voltage is greater than the third pass voltage. Similarly, the fourth pass voltage can increase the channel potential of all memory cell strings in the first memory cell slice, thereby reducing the potential difference between the control gate potential and the channel potential of the memory cell in the first memory cell slice, making it difficult for charges to tunnel into the floating gate of the memory cell in the first memory cell slice, thereby prohibiting programming of the first memory cell slice during the stage of applying the on-voltage to the second selection line.

[0011] In some embodiments, the programming method further includes: in the stage of applying the programming voltage to the first word line, applying the first bit line voltage to the first bit line and applying the second bit line voltage to the second bit line; the first bit line is coupled to one storage cell string in the first storage cell slice and one storage cell string in the second storage cell slice, and the second bit line is coupled to another storage cell string in the first storage cell slice and another storage cell string in the second storage cell slice. The first bit line is a selection bit line, and the first bit line voltage is a programming selection voltage; the second bit line is a non-selection bit line, and the second bit line voltage is a programming inhibition voltage.

[0012] In some embodiments, the memory cells in the memory are single-level cells (SLCs). Since the number of programming cycles when programming single-level cells (SLCs) is small, the number of memory cells in the erased state is relatively large, so program disturbance is low.

[0013] In a second aspect, a memory is provided, which includes a memory cell array, a first word line, a first selection line, a second selection line and a peripheral circuit; the memory cell array includes a first memory cell chip and a second memory cell chip, the first word line is coupled to multiple memory cells of the first memory cell chip and multiple memory cells of the second memory cell chip, the first selection line is coupled to the selection transistor of the first memory cell chip, and the second selection line is coupled to the selection transistor of the second memory cell chip; the peripheral circuit is coupled to the first word line, the first selection line and the second selection line, respectively, and is configured to: apply a programming voltage to the first word line; and in the stage of applying the programming voltage to the first word line, apply a turn-on voltage to the first selection line and the second selection line in sequence.

[0014] In some embodiments, the peripheral circuit is configured to, after applying a programming voltage to the first word line, further include: applying a verification voltage to the first word line; and applying a turn-on voltage to the first selection line and the second selection line in sequence during the stage of applying the verification voltage to the first word line.

[0015] In some embodiments, the memory also includes a second word line, which is coupled to another plurality of memory cells of the first memory cell slice and another plurality of memory cells of the second memory cell slice; the peripheral circuit is also configured to apply a first pass voltage to the second word line during a stage of applying a turn-on voltage to the first selection line; and to apply a second pass voltage to the second word line during a stage of applying a turn-on voltage to the second selection line.

[0016] In some embodiments, the second pass voltage is greater than the first pass voltage.

[0017] In some embodiments, the memory also includes a third word line, which is coupled to multiple dummy memory cells of the first memory cell slice and multiple dummy memory cells of the second memory cell slice; the peripheral circuit is also configured to: apply a third pass voltage to the third word line in the stage of applying a turn-on voltage to the first selection line; and apply a fourth pass voltage to the third word line in the stage of applying a turn-on voltage to the second selection line.

[0018] In some embodiments, the fourth pass voltage is greater than the third pass voltage.

[0019] In some embodiments, the memory also includes a first bit line and a second bit line, the first bit line is coupled to a memory cell string in the first memory cell slice and a memory cell string in the second memory cell slice, and the second bit line is coupled to another memory cell string in the first memory cell slice and another memory cell string in the second memory cell slice; the peripheral circuit is also configured to apply a first bit line voltage to the first bit line and a second bit line voltage to the second bit line in the stage of applying a programming voltage to the first word line.

[0020] In some embodiments, the memory cells in the memory are single-level cells (SLC).

[0021] According to a third aspect, a memory system is provided, comprising a memory controller and the memory according to the second aspect, wherein the memory controller is configured to control the memory.

[0022] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the first aspect above can be implemented.

[0023] In a fifth aspect, a computer device is provided, comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any one of the methods in the first aspect can be implemented.

[0024] In a sixth aspect, another memory programming method is provided, comprising: applying a programming voltage to a first word line, the first word line being coupled to multiple memory cells of each memory cell slice in a plurality of memory cell slices; in the stage of applying the programming voltage to the first word line, applying a turn-on voltage to multiple selection lines in sequence; each of the multiple selection lines being coupled to a selection transistor of a corresponding one of the multiple memory cell slices.

[0025] In some embodiments, in the stage of applying a turn-on voltage to a first selection line among multiple selection lines, a first pass voltage is applied to a second word line, and the second word line is coupled to another plurality of memory cells of each memory cell slice among multiple memory cell slices; in the stage of applying a turn-on voltage to a second selection line among multiple selection lines, a second pass voltage is applied to the second word line; wherein, the stage of applying the turn-on voltage to the second selection line is after the stage of applying the turn-on voltage to the first selection line.

[0026] It can be understood that the technical effects of the second to sixth aspects refer to the technical effects of the first aspect and any embodiment thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0028] Figure 1 A possible flowchart for programming the memory is shown;

[0029] Figure 2 Schematic diagram of the voltage waveform of the selected word line for ISSP programming;

[0030] Figure 3 A schematic diagram of a memory system provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of the structure of a memory and a storage cell array provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of the connection structure of a storage cell array provided in an embodiment of the present application;

[0033] Figure 6 A partial cross-sectional view of a possible cross-section of a memory cell array provided in an embodiment of the present application;

[0034] Figure 7 A schematic diagram of a memory programming process provided by an embodiment of the present application;

[0035] Figure 8 A schematic diagram of programming a first storage cell slice by a peripheral circuit provided in an embodiment of the present application;

[0036] Fig. 9 A schematic diagram of programming a second storage cell chip by a peripheral circuit provided in an embodiment of the present application;

[0037] Fig.10 A schematic diagram of the structure of the memory and peripheral circuits provided in the embodiment of the present application;

[0038] Fig.11 A schematic diagram of a flow chart of programming a memory cell chip by a peripheral circuit provided in an embodiment of the present application;

[0039] Fig.12 A schematic diagram of a memory programming method according to an embodiment of the present application;

[0040] Fig.13 A possible voltage waveform schematic diagram for programming a memory is provided for an embodiment of the present application;

[0041] Fig.14 A schematic diagram of a specific flow chart of step S1 in the programming method provided in an embodiment of the present application;

[0042] Fig.15 An embodiment of the present application provides a schematic diagram of a possible programming result of a memory.

[0043] Figure numerals: 300, memory system; 310, memory controller; 320, memory; 400, memory cell array; 410, first memory cell slice; 411, memory cell string; 412, top selection transistor; 413, dummy memory cell; 414, memory cell; 415, bottom selection transistor; 420, second memory cell slice; 430, third memory cell slice; 440, fourth memory cell slice; 510, memory stack layer; 511, gate conductive layer; 512, dielectric layer; 520, substrate; 530, top selection line; 540, word line; 550, bottom selection line; 600, peripheral circuit; 610, I / O interface; 620, control logic unit; 630, row decoder; 640, voltage generator; 650, column decoder; 660, page buffer; 670, data bus; 680, register. DETAILED DESCRIPTION

[0044] The following will be combined Figure 1-Figure 15 , the technical solutions in some embodiments of the present application are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0045] Unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0047] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0048] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0049] NAND flash memory is a non-volatile random access storage medium. NAND flash memory usually uses floating gate transistors as memory cells. Unlike traditional transistors, the gate of a floating gate transistor includes a floating gate that can store charge in addition to a control gate.

[0050] An insulating layer is disposed between the floating gate and the control gate, and a tunneling layer (eg, a silicon dioxide layer) is disposed between the floating gate and the substrate.

[0051] Based on the tunneling (Fowler-Nordheim, FN) effect, when a high voltage (i.e., programming voltage, exemplary, programming voltage is 20V) is applied to the control gate, a conductive channel (referred to as a channel) can be formed between the source (source, S) and drain (drain, D) of the floating gate transistor, and when a low voltage (i.e., programming selection voltage, exemplary programming selection voltage is 0V) is applied to the substrate, a large potential difference is formed between the control gate and the channel, so that the charge in the channel passes through the tunneling layer and enters the floating gate. This process is called a programming operation. At the same time, since the tunneling layer isolates the floating gate from the substrate, and the insulating layer isolates the floating gate from the control gate, the floating gate can maintain the charge for a long time without losing the charge even in the case of power failure, thereby achieving power failure without losing the data. Only when a high voltage is applied to the substrate and a low voltage is applied to the control gate, can the charge in the floating gate pass through the tunneling layer and enter the substrate. This process is called an erase operation.

[0052] The electric field generated by the charge stored in the floating gate further affects the threshold voltage of the floating gate transistor. The more charge stored in the floating gate, the greater the threshold voltage of the floating gate transistor. When the threshold voltage of the floating gate transistor is greater than a threshold, it is recognized as data "0", and when the threshold voltage is less than a threshold, it is recognized as data "1", thereby being able to represent different storage information.

[0053] Figure 1 A possible flow chart of programming the memory is shown in FIG. Figure 1 As shown, multiple memory cell slices (also referred to as memory cell groups) in the memory are programmed sequentially, and programming of each memory cell slice may include multiple programming cycles, and each programming cycle may include a programming phase and a verification phase. For example, see Figure 1 , firstly, programming the memory cell group 1 may include multiple programming cycles, for example, Figure 1 Two programming cycles (i.e., programming cycle n) are shown. group1 and programming cycle n group1 +1), each programming cycle can include a programming phase and a verification phase. After the programming operation is completed for the current storage cell slice, the programming operation is performed on the next storage cell slice (for example, group 2). Similarly, the programming operation performed on the next storage cell slice can also include multiple programming cycles (for example, programming cycle n group2 and programming cycle n group2 +1), each programming cycle may include a programming phase and a verification phase.

[0054] like Figure 2 As shown, in the programming phase, the memory cell is programmed by applying a programming voltage Vpgm to the selected word line (selected WL); in the verification phase, the memory cell is verified by applying a verification voltage Vvfy to the selected word line. If the programming operation is unsuccessful (for example, the number of failed bits (Fail Bit Count, FBC) is greater than the threshold) and the number of cycles of the programming cycle does not reach the maximum value, the next programming cycle is entered. In the programming phase of the next programming cycle, the programming voltage Vpgm is increased by an incremental voltage Vispp and applied to the selected word line to program at least the memory cells that have not passed the verification; then the verification phase of the next programming cycle is entered, and the verification voltage Vvfy is applied to the selected word line to verify at least some of the memory cells that have not passed the verification in the verification phase of the previous programming cycle. If the programming operation is successful (for example, FBC is less than or equal to the threshold), or the number of cycles of the programming cycle reaches the maximum value (at this time, it is considered that the programming operation has failed), the programming operation of the current memory cell slice is terminated.

[0055] Usually, in the same programming cycle, the voltage applied to the selected word line between the programming stage and the verification stage needs to be reduced from the programming voltage Vpgm to zero, and then increased to the verification voltage Vvfy; in two adjacent programming cycles, the voltage applied to the selected word line between the verification stage of the current programming cycle and the next programming cycle needs to be reduced from the verification voltage Vvfy to zero, and then increased to the sum of the programming voltage Vpgm and the incremental voltage Vispp. However, due to the influence of the inherent parameters of the voltage transmission line (resistance, parasitic inductance, parasitic capacitance, etc.), the voltage applied to the selected word line cannot be immediately raised or lowered, that is, the voltage applied to the selected word line needs to take time to ramp up the voltage / ramp down the voltage. Programming of multiple memory cells often requires multiple cycles of ramping up the voltage / ramp down the voltage, and thus programming the memory takes a long time.

[0056] The embodiments of the present application continuously programs multiple memory cell chips during the programming phase of a programming cycle, that is, continuously programs multiple memory cell chips with one programming voltage, thereby reducing the number of times the programming voltage is ramped up / down to a certain extent, reducing the time required to ramp up / down the voltage, and shortening the time required to program the memory.

[0057] like Figure 3 As shown, the embodiment of the present application provides a memory system 300, including a memory controller 310 and a memory 320, wherein the memory controller 310 is used to control the data storage operation of the memory 320. The memory system 300 can be applied to and packaged in different types of electronic devices, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, servers, and any other electronic devices that can store data.

[0058] Of course, the storage controller 310 may also perform any other suitable functions, such as formatting the memory 320; for example, the storage controller 310 may communicate with an external device (e.g., a host) through at least one of various interface protocols. The interface protocol may include at least one of a universal serial bus (USB) protocol, a multi-media card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-E protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0059] Specifically, Figure 4 As shown, the memory 320 includes a memory cell array 400 and a peripheral circuit 600 , and the memory cell array 400 is coupled to the peripheral circuit 600 .

[0060] The memory cell array 400 may include a plurality of memory cell blocks, each of which may include N memory cell slices arranged along the Y axis, where N is a positive integer greater than or equal to 2; exemplary, N=4. Each memory cell slice includes M memory cell strings 411 arranged along the X axis, where M is a positive integer greater than or equal to 2; exemplary, N=6. Each memory cell string 411 may include a top select gate (TSG) 412, a dummy (DMY) memory cell 413, a plurality of memory cells 414, and a bottom select gate (BSG) 415 stacked in series along the Z axis. The X axis, the Y axis, and the Z axis are the horizontal axis, the vertical axis, and the vertical axis of the spatial rectangular coordinate system, respectively.

[0061] The memory cell string 411 in the memory cell slice can be coupled to the peripheral circuit 600 through a top select line (string select line, SSL), a word line (word line, WL), a bit line (bit line, BL), a bottom select line (ground select line, GSL), a source line (Source line, SL), etc.

[0062] like Figure 4 and Figure 5 As shown, for the M memory cell strings 411 in the same memory cell slice, the gate of the top selection transistor 412 in each memory cell string 411 is coupled to the same top selection line; the gate of the bottom selection transistor 415 in each memory cell string 411 is coupled to the same bottom selection line.

[0063] For N*M memory cell strings 411 in N memory cell slices, the control gate of the memory cell 414 in any memory cell string 411 is coupled to the same word line as the control gate of the memory cell 414 at the corresponding position in the other (N*M-1) memory cell strings 411. Also, the control gate of the dummy memory cell 413 in any memory cell string 411 is coupled to the same dummy word line (DWL) as the control gate of the dummy memory cell 413 at the corresponding position in the other (N*M-1) memory cell strings 411.

[0064] The M memory cell strings 411 in the memory cell slice are coupled to the peripheral circuit through M bit lines corresponding to each other. For example, the drain of the top selection transistor 412 in the memory cell string 411 is coupled to the bit line. In order to reduce the number of bit lines, the memory cell strings 411 in the N memory cell slices can share M bit lines, that is, the memory cell string 411 in any memory cell slice is coupled to the same bit line as the memory cell strings 411 at corresponding positions in other (N-1) memory cell slices.

[0065] The source of the bottom selection transistor 415 in the N*M memory cell strings 411 can be coupled to a common source line (CSL), which can also be called an array common source (ACS). It should be noted that the drawings of the present application only illustrate the structure of the memory of some embodiments, but in practice, the structure of the memory can also be other ways. For example, the source of the bottom selection transistor 415 in the N*M memory cell strings 411 can be similar to the drain, and the memory cell strings 411 in N memory cell slices can share M source lines, that is, the memory cell string 411 in any memory cell slice is coupled to the same source line as the memory cell string 411 at the corresponding position in other (N-1) memory cell slices.

[0066] Figure 6A partial cross-sectional view of a cross section of a possible memory cell string of the present application is shown. The memory cell string 411 may extend vertically through the memory stack layer 510 above the substrate 520. The substrate 520 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0067] The memory stack layer 510 may include alternating gate conductive layers 511 and dielectric layers 512 . The number of pairs of gate conductive layers 511 and dielectric layers 512 in the memory stack layer 510 may determine the number of memory cells 414 in the memory cell array 400 .

[0068] The gate conductive layer 511 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 511 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 511 includes a doped polysilicon layer. Each gate conductive layer 511 may include a control gate surrounding the memory cell 414, and the gate conductive layer 511 at the top of the memory stack 510 may extend laterally as a top select line 530, the gate conductive layer 511 at the bottom of the memory stack 510 may extend laterally as a bottom select line (ground select line, GSL) 550, or the gate conductive layer 511 between the top select line 530 and the bottom select line 550 may extend laterally as a word line 540.

[0069] It should be understood that although Figure 6 Not shown, but additional components of the memory cell array 400 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0070] like Figure 7 As shown, the peripheral circuit 600 continuously programs multiple memory cells in the programming phase of a programming cycle. Correspondingly, the peripheral circuit 600 continuously verifies multiple memory cells programmed in the programming phase in the verification phase after the programming phase of a programming cycle.

[0071] Optionally, the memory cell 414 in the memory 320 is a single-level memory cell SLC. That is, the memory cell 414 in the memory cell array 400 is a single-level memory cell SLC; that is, one memory cell 414 stores 1 bit of data, which only stores 0 and 1. Therefore, compared with multi-level memory cells, the number of programming cycle cycles when programming SLC is small (that is, the number of times the programming voltage is applied to the first word line is small), and the number of memory cells in the erased state in the SLC (memory cells whose target state is the erased state do not need to be programmed) is relatively large, so that the programming interference is low.

[0072] Of course, the present application is not limited to the application in SLC programming, but can also be applied to multi-level cell (MLC) type, trinary-level cell (TLC) type, quad-level cell (QLC) type, etc.

[0073] Exemplarily, the memory cell array 400 includes at least one memory cell block; wherein the memory cell block may include a first memory cell group 1 410 and a second memory cell group 2 420. That is, in a programming phase of a programming cycle, the peripheral circuit 600 couples to the first word line (the first word line is a selection word line, for example) of the plurality of memory cells 414 of the first memory cell group 410 and the plurality of memory cells 414 of the second memory cell group 420. Figure 4 While applying the programming voltage Vpgm to the WL1 in the figure, the turn-on voltage Von is first applied to the first selection line coupled to the first memory cell piece 410, and then the turn-on voltage Von is applied to the second selection line coupled to the second memory cell piece 420.

[0074] The present application takes the example that the first selection line is the first top selection line SSL1 and the second selection line is the second top selection line SSL2 for explanation. It should be understood that the first selection line may also be the first bottom selection line GSL1 and the second selection line may also be the second bottom selection line GSL2.

[0075] The first word line is coupled to a plurality of memory cells 414 of the first memory cell slice 410 and a plurality of memory cells of the second memory cell slice 420. The first word line WL1 is coupled to the first memory cell slice 410 ( Figure 4 The control gates of the first memory cells 414 in all memory cell strings 411 in the first memory cell slice along the Y-axis direction in the second memory cell slice 420 ( Figure 4The control gate of the first memory cell 414 in all memory cell strings 411 in the second memory cell slice along the Y-axis direction.

[0076] The first top selection line SSL1 is coupled to the gates of the top selection transistors 412 in all the memory cell strings 411 in the first memory cell slice 410 , and the second top selection line SSL2 is coupled to the gates of the top selection transistors 412 in all the memory cell strings 411 in the second memory cell slice 420 .

[0077] It should be understood that in a programming phase of a programming cycle, the peripheral circuit 600 also needs to provide a plurality of bit lines (eg, Figure 4 A program selection voltage Vss (exemplarily, the program selection voltage Vss is 0V) or a program inhibition voltage Vinhibit (exemplarily, the program inhibition voltage Vinhibit is 3V) is applied to BL1-BL5 in the figure.

[0078] like Figure 4 As shown, the bit line BL1 is coupled to the first one of the first memory cell slices 410 (along Figure 4 The storage cell string 411 in the X-axis direction, and the first one of the second storage cell slices 420 (along the Figure 4 The coupling structure of the bit lines BL2 to BL5 and the first memory cell 410 and the second memory cell 420 is shown in FIG. Figure 4 The description of the coupling structure between the bit line BL1 and the first memory cell 410 and the second memory cell 420 will not be repeated in this application.

[0079] In addition, the embodiment of the present application also continuously verifies multiple memory cell chips during the verification phase of a programming cycle, that is, continuously verifies multiple memory cell chips by one verification voltage, thereby reducing the number of times the verification voltage is ramped up / down to a certain extent, further reducing the time required to ramp up / down the voltage, and shortening the time required to program the memory.

[0080] Different from the programming stage, in the verification stage after the programming stage of a programming cycle, the peripheral circuit 600 applies a verification voltage to the first word line, and applies a verification-related bit line voltage to the bit line coupled to the first memory cell 410 and the second memory cell 420. That is, in the verification stage after the programming stage of a programming cycle, the peripheral circuit 600 applies a turn-on voltage to the first top selection line SSL1 and then applies a turn-on voltage to the second top selection line SSL2 while applying a verification voltage to the first word line.

[0081] For a 3D NAND flash memory, the peripheral circuit 600 applies a turn-on voltage Von to the first top selection line SSL1 (eg, Figure 8 As shown), a first pass voltage Vpass1 is also applied to the second word line (the second word line is a non-selected word line, such as WL2-WL5). The second word line is coupled to another plurality of memory cells 414 of the first memory cell slice 410 and another plurality of memory cells 414 of the second memory cell slice 420. Taking one of the second word lines WL2 as an example, in the order from the top selection transistor 412 to the bottom selection transistor 415, the second word line WL2 is coupled to the control gate of the second memory cell 414 in all the memory cell strings 411 in the first memory cell slice 410, and the control gate of the second memory cell 414 in all the memory cell strings 411 in the second memory cell slice 420. The peripheral circuit 600 is in the stage of applying a turn-on voltage to the second top selection line SSL2 (as shown). Fig. 9 As shown), a second pass voltage Vpass2 is also applied to the second word line.

[0082] In addition, the memory cell string 411 often includes a dummy memory cell 413 coupled to the dummy word line. The dummy word line can be controlled similarly to the second word line. Therefore, the peripheral circuit 600 applies the on-voltage Von to the first top selection line SSL1 (e.g. Figure 8 As shown), a third pass voltage Vpass3 is also applied to the third word line (the third word line is a pseudo word line, such as DWL1 and DWL2); the peripheral circuit 600 is in the stage of applying the turn-on voltage Von to the second top selection line SSL2 (such as Fig. 9 As shown), a fourth pass voltage Vpass4 is also applied to the third word line.

[0083] The third word line is coupled to the plurality of dummy memory cells 413 of the first memory cell slice 410 and the plurality of dummy memory cells 413 of the second memory cell slice 420. Taking one of the dummy word lines DWL1 among the third word lines as an example, in the order from the top selection transistor 412 to the bottom selection transistor 415, the third word line DWL1 is coupled to the control gate of the first dummy memory cell 413 in all the memory cell strings 411 in the first memory cell slice 410, and the control gate of the first dummy memory cell 413 in all the memory cell strings 411 in the second memory cell slice 420.

[0084] Fig.10 Shows a schematic diagram of the structure of the memory and peripheral circuits. Fig.10In the embodiment, the peripheral circuit 600 includes an I / O interface 610, a control logic unit 620, a row decoder 630, a voltage generator 640, a column decoder 650, a page buffer 660, a data bus 670, and a register 680. It should be understood that in some examples, the peripheral circuit 600 may also include Fig.10 Additional circuitry not shown.

[0085] The I / O interface 610 may be coupled to the control logic unit 620 and act as a control buffer to buffer data from a storage controller (eg, Figure 3 The I / O interface 610 may receive control commands received from the memory controller 310 in the memory cell array 400 and relay them to the control logic unit 620, and buffer status information received from the control logic unit 620 and relay them to the host. The I / O interface 610 may also be coupled to the page buffer 660 via the data bus 670, and act as a data I / O interface 610 and a data buffer to buffer data and relay them to or from the memory cell array 400.

[0086] The control logic unit 620 may be coupled to the voltage generator 640, the page buffer 660, the column decoder 650, the row decoder 630, the I / O interface 610, etc., and is configured to control the operation of each peripheral circuit. The control logic unit 620 may generate an operation signal to control the operation of the row decoder 630, the column decoder 650, the page buffer 660, and the voltage generator 640 in response to a command (CMD) or a control signal from the memory controller 310; wherein the command may be a program command, a read command, etc.

[0087] The row decoder 630 may supply the word line voltage generated from the voltage generator 640 to the selected word lines and the unselected word lines of the memory cell array 400 in response to the control of the control logic unit 620. As described in detail below, the row decoder 630 is configured to perform a program operation on the memory cells coupled to one or more selected word lines in the memory cell array 400.

[0088] The voltage generator 640 can use an external power supply voltage or an internal power supply voltage to generate various voltages for performing operations such as erasing, programming, reading and verifying on the memory cell array 400, such as a programming voltage Vpgm, a pass voltage Vpass, a read voltage Vread and a verification voltage Vvfy applied to the word line, and a programming inhibit voltage Vinhibit, a programming select voltage Vss, etc. applied to the bit line, and their combinations.

[0089] The column decoder 650 may be controlled in response to the control logic unit 620 , and select one or more memory cell strings 411 in the memory cell array 400 by applying a bit line voltage generated from the voltage generator 640 .

[0090] The page buffer 660 may read data from the memory cell array 400 and program (write) data to the memory cell array 400 according to a control signal from the control logic unit 620. In one example, the page buffer 660 may store programming data (write data) to be programmed into the memory cell array 400. In another example, the page buffer 660 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 414 coupled to the selected word line. In yet another example, the page buffer 660 may also detect a low-power signal from a bit line representing a data bit stored in the memory cell 414, and amplify a small voltage swing to a recognizable logic level in a read operation.

[0091] The register 680 may be coupled to the control logic unit 620 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0092] Those skilled in the art should understand that the operations performed by the row decoder 630, the page buffer 660, the control logic unit 620, and the voltage generator 640 described in the present application may be performed by a processing circuit, wherein the processing circuit may include but is not limited to hardware of a logic circuit or a hardware / software combination of a processor that executes software.

[0093] like Fig.11 As shown, in the programming phase of a programming cycle, the peripheral circuit 600 continuously programs multiple memory cells; in the verification phase after the programming phase of a programming cycle, the peripheral circuit 600 continuously verifies the multiple memory cells programmed in the programming phase.

[0094] Specifically, when the peripheral circuit 600 works, the following steps are performed: Fig.12 The programming method shown is implemented Fig.11 The programming flow shown, the programming method includes steps S1-S2, and at least one step of S1 or S2 can be executed.

[0095] S1. In a programming phase of a programming cycle, a plurality of memory cells coupled to a first word line are programmed continuously.

[0096] like Fig.13As shown, the control logic unit 620 controls the row decoder 630 to provide the programming voltage Vpgm generated by the voltage generator 640 to the first word line (the first word line is the selection word line), and also controls the row decoder 630 to sequentially provide the on-voltage Von generated by the voltage generator 640 to multiple top selection lines SSL, and to provide the off-voltage Voff to the bottom selection line GSL. It should be noted that at the same time, only one top selection line among the multiple top selection lines will be applied with the on-voltage Von, and the remaining top selection lines among the multiple top selection lines will be applied with the off-voltage Voff. It should be understood that when the selection line is the bottom selection line, the control logic unit 620 controls the row decoder 630 to sequentially provide the on-voltage Von generated by the voltage generator 640 to multiple bottom selection lines GSL, and to provide the off-voltage Voff to the top selection line SSL.

[0097] Exemplarily, in the programming phase of a programming cycle, when the row decoder 630 provides the programming voltage Vpgm to the first word line, it also provides the on-voltage Von to the first top selection line SSL1 and the second top selection line SSL2 in sequence (provides the off-voltage Voff to the second top selection line SSL2 and the first top selection line SSL1 in sequence). That is, in the programming phase of a programming cycle, the row decoder 630 applies the same programming voltage Vpgm to the first word line (i.e., does not ramp up / down the programming voltage Vpgm), and first programs the multiple storage cells 414 coupled to the first word line in the first storage cell slice 410, and then programs the multiple storage cells 414 coupled to the first word line in the second storage cell slice 420. Therefore, as Fig.14 As shown, step S1 at least includes sub-steps S11 and S12.

[0098] S11 , programming a plurality of memory cells 414 coupled to a first word line in a first memory cell slice 410 .

[0099] Continue to refer to Fig.13 , the row decoder 630 provides the programming voltage Vpgm to the first word line, and provides the on-voltage Von to the first top selection line SSL1, while the control logic unit 620 also controls the page buffer 660 to provide the first bit line voltage generated by the voltage generator 640 to the first bit line, and the second bit line voltage to the second bit line. It should be noted that the first bit line voltage is the programming selection voltage Vss, and the first bit line can also be called a selection bit line; the second bit line voltage is the programming inhibition voltage Vinhibit, and the second bit line can also be called a non-selection bit line.

[0100] Furthermore, the control logic unit 620 controls the row decoder 630 to provide the first pass voltage Vpass1 generated by the voltage generator 640 to the second word line (the second word line is the non-selected word line), and controls the row decoder 630 to provide the third pass voltage Vpass3 generated by the voltage generator 640 to the third word line (the third word line is the pseudo word line).

[0101] That is, in the stage where the control logic unit 620 controls the row decoder 630 to apply the programming voltage Vpgm to the first word line and the turn-on voltage Von to the first top selection line SSL1, the control logic unit 620 also controls the row decoder 630 to apply the first pass voltage Vpass1 to the second word line; at the same time, the page buffer 660 is controlled to apply the first bit line voltage to the first bit line and the second bit line voltage to the second bit line, thereby programming the memory cell 414 coupled to the first word line in the first memory cell slice 410.

[0102] It should be emphasized that the first bit line and the second bit line in this application do not refer to a specific bit line. Fig.13 As shown, in the stage where the row decoder 630 applies the on voltage Von to the first top selection line SSL1, the bit line BL1 is the first bit line and the bit line BL2 is the second bit line. Thus, the memory cell 414 coupled to the bit line BL1 in the first memory cell slice 410 is programmed to a programming state (such as Fig.15 The memory cell 414 coupled to the bit line BL2 in the first memory cell slice 410 is kept in an erased state (as shown); Fig.15 shown).

[0103] S12 , programming the plurality of memory cells 414 coupled to the first word line in the second memory cell slice 420 .

[0104] The row decoder 630 provides the programming voltage Vpgm to the first word line, and provides the turn-on voltage Von to the second top selection line SSL2; similar to sub-step S11, the control logic unit 620 also controls the page buffer 660 to provide the first bit line voltage generated by the voltage generator 640 to the first bit line, and provides the second bit line voltage to the second bit line.

[0105] Different from sub-step S11 , the control logic unit 620 controls the row decoder 630 to provide the second pass voltage Vpass2 generated by the voltage generator 640 to the second word line, and controls the row decoder 630 to provide the fourth pass voltage Vpass4 generated by the voltage generator 640 to the third word line.

[0106] That is, when the control logic unit 620 controls the row decoder 630 to apply the programming voltage Vpgm to the first word line and the turn-on voltage Von to the second top selection line SSL2, the control logic unit 620 also controls the row decoder 630 to apply the second pass voltage Vpass2 to the second word line; at the same time, the page buffer 660 is controlled to apply the first bit line voltage to the first bit line and the second bit line voltage to the second bit line. Thus, the memory cell 414 coupled to the first word line in the second memory cell slice 420 is programmed. However, if Fig.13 As shown, in the stage where the row decoder 630 applies the on-voltage Von to the second top selection line SSL2, the bit line BL1 is the second bit line and the bit line BL2 is the first bit line. Thus, the memory cell 414 coupled to the bit line BL2 in the second memory cell slice 420 is programmed to a programming state (such as Fig.15 The memory cell 414 coupled to the bit line BL1 in the second memory cell slice 420 is kept in an erased state (as shown); Fig.15 shown).

[0107] One difference between the above sub-step S11 and sub-step S12 is that the row decoder 630 applies the first pass voltage Vpass1 to the second word line and the third pass voltage Vpass3 to the third word line when applying the turn-on voltage Von to the first top selection line SSL1. The row decoder 630 applies the second pass voltage Vpass2 to the second word line and the fourth pass voltage Vpass4 to the third word line when applying the turn-on voltage Von to the second selection line SSL2.

[0108] In the embodiment of the present application, the second pass voltage Vpass2 is greater than the first pass voltage Vpass1. The row decoder 630 provides the off voltage Voff to the first top selection line SSL1 at the stage of applying the on voltage Von to the second top selection line SSL2. At this time, the top selection transistors 412 of all the memory cell strings 411 in the first memory cell slice 410 are turned off. Based on the self-boosting program inhibit (SBPI) mechanism, when the row decoder 630 applies the second pass voltage Vpass2 with a higher voltage value than the previous stage (the stage of applying the on voltage Von to the first top selection line SSL1 by the row decoder 630) to the second word line, the channel potential of all the memory cell strings 411 in the first memory cell slice 410 can be increased through gate voltage and capacitive coupling. In addition, the potential difference between the control gate potential and the channel potential of the memory cell 414 in the first memory cell slice 410 is reduced, making it difficult for charges to tunnel into the floating gate of the memory cell 414 in the first memory cell slice 410, thereby prohibiting programming of the first memory cell. Likewise, the fourth pass voltage Vpass4 is greater than the third pass voltage Vpass3 .

[0109] That is, when the control logic unit 620 controls the row decoder 630 to apply the programming voltage Vpgm to the first word line (selection word line), it also controls the row decoder 630 to apply the turn-on voltage Von to multiple top selection lines in sequence, and to apply a pass voltage with increasing voltage value to the second word line (non-selection word line), and to apply a pass voltage with increasing voltage value to the third word line (pseudo word line).

[0110] It should be understood that the programming method provided in the embodiment of the present application can also program the plurality of storage cells 414 coupled to the first word line in the third storage cell slice (group 3) 430 and the plurality of storage cells 414 coupled to the first word line in the fourth storage cell slice (group 4) 440 in sequence after sub-step S12. Fig.13As shown, in the stage where the row decoder 630 applies the turn-on voltage Von to the third top selection line SSL3 among the plurality of top selection lines, the row decoder 630 also applies the fifth pass voltage Vpass5 to the second word line and the seventh pass voltage Vpass7 to the third word line; in the stage where the row decoder 630 applies the turn-on voltage Von to the fourth top selection line SSL4 among the plurality of top selection lines, the row decoder 630 also applies the sixth pass voltage Vpass6 to the second word line and the eighth pass voltage Vpass8 to the third word line. The sixth pass voltage Vpass6 is greater than the fifth pass voltage Vpass5 and the second pass voltage Vpass2, and the eighth pass voltage Vpass8 is greater than the seventh pass voltage Vpass7 and the fourth pass voltage Vpass4.

[0111] S2. In a verification phase of a programming cycle, a plurality of memory cell slices coupled to a first word line are verified continuously.

[0112] Different from step S1, in step S2, the control logic unit 620 controls the row decoder 630 to provide the verification voltage generated by the voltage generator 640 to the first word line. That is, in the verification phase of a programming cycle, the row decoder 630 applies the same verification voltage to the first word line (i.e., does not ramp up / down the programming voltage).

[0113] It should be noted that the multiple memory cell slices continuously verified in step S2 are the multiple memory cell slices continuously programmed in step S1. That is, step S2 at least includes continuously verifying the multiple memory cells 414 coupled to the first word line in the first memory cell slice 410 and the multiple memory cells 414 coupled to the first word line in the second memory cell slice 420.

[0114] The embodiments of the present application provide a memory programming method, a memory, and a memory system, which continuously programs multiple memory cells in the programming phase of a programming cycle, and programs the multiple memory cells with a programming voltage; continuously verifies multiple memory cells in the verification phase of a programming cycle, and verifies the multiple memory cells with a verification voltage; thereby reducing the number of ramp-up / ramp-down voltages to a certain extent, thereby reducing the time required to ramp up / ramp down the voltage in the programming cycle, and shortening the time required to program the memory.

[0115] The present application embodiment provides a computer-readable storage medium, which stores computer-executable instructions; after the computer-executable instructions are executed, the following can be achieved: Fig.12 The method in .

[0116] The present application provides a computer device, including a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, Fig.12 The method in .

[0117] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and for the parts not described in detail in a certain embodiment, reference can be made to the corresponding processes in the aforementioned method embodiments, which will not be repeated here.

[0118] In the several embodiments provided in the present application, it should be understood that the provided programming method, memory and memory system can be implemented in other ways. For example, the division of a module is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0119] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0120] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for programming a memory, characterized in that: include: applying a programming voltage to a first word line coupled to a plurality of memory cells of a first memory cell slice and a plurality of memory cells of a second memory cell slice; In the stage of applying the programming voltage to the first word line, a turn-on voltage is applied to a first selection line and a second selection line in sequence, the first selection line is coupled to a selection transistor of the first memory cell, and the second selection line is coupled to a selection transistor of the second memory cell.

2. The programming method according to claim 1, characterized in that: After applying the programming voltage to the first word line, the method further comprises: applying a verification voltage to the first word line; In the stage of applying the verification voltage to the first word line, a turn-on voltage is sequentially applied to the first selection line and the second selection line.

3. The programming method according to claim 1, characterized in that: In the stage of applying the conduction voltage to the first selection line, applying a first pass voltage to a second word line; the second word line is coupled to another plurality of memory cells of the first memory cell slice and another plurality of memory cells of the second memory cell slice; In the phase of applying the turn-on voltage to the second selection line, a second pass voltage is applied to the second word line.

4. The programming method according to claim 3, characterized in that: The second pass voltage is greater than the first pass voltage.

5. The programming method according to claim 1, characterized in that: The programming method also includes: In the stage of applying the turn-on voltage to the first selection line, applying a third pass voltage to a third word line; the third word line is coupled to a plurality of dummy memory cells of the first memory cell slice and a plurality of dummy memory cells of the second memory cell slice; In the phase of applying the turn-on voltage to the second selection line, a fourth pass voltage is applied to the third word line.

6. The programming method according to claim 5, characterized in that: The fourth pass voltage is greater than the third pass voltage.

7. The programming method according to any one of claims 1 to 6, characterized in that: The programming method also includes: In the stage of applying the programming voltage to the first word line, a first bit line voltage is applied to the first bit line, and a second bit line voltage is applied to the second bit line; the first bit line is coupled to a memory cell string in the first memory cell slice and a memory cell string in the second memory cell slice, and the second bit line is coupled to another memory cell string in the first memory cell slice and another memory cell string in the second memory cell slice.

8. The programming method according to claim 1, characterized in that: The storage unit in the memory is a single-level storage unit SLC.

9. A memory, characterized in that: include: A memory cell array includes a first memory cell slice and a second memory cell slice; A first word line coupled to a plurality of memory cells of the first memory cell slice and a plurality of memory cells of the second memory cell slice; A first selection line coupled to a selection transistor of the first memory cell; A second selection line coupled to a selection transistor of the second memory cell; The peripheral circuit is respectively coupled to the first word line, the first selection line and the second selection line, and is configured as follows: applying a programming voltage to the first word line; In the stage of applying the programming voltage to the first word line, a turn-on voltage is sequentially applied to the first selection line and the second selection line.

10. The memory according to claim 9, characterized in that: The peripheral circuit is configured to, at the stage of applying the programming voltage to the first word line, further include: applying a verification voltage to the first word line; In the stage of applying the verification voltage to the first word line, a turn-on voltage is sequentially applied to the first selection line and the second selection line.

11. The memory according to claim 9, characterized in that: Also includes: a second word line coupled to another plurality of memory cells of the first memory cell slice and another plurality of memory cells of the second memory cell slice; The peripheral circuit is further configured as: In the stage of applying the turn-on voltage to the first selection line, applying a first pass voltage to the second word line; In the phase of applying the turn-on voltage to the second selection line, a second pass voltage is applied to the second word line.

12. The memory according to claim 11, characterized in that: The second pass voltage is greater than the first pass voltage.

13. The memory according to claim 9, characterized in that: Also includes: a third word line coupled to a plurality of dummy memory cells of the first memory cell slice and a plurality of dummy memory cells of the second memory cell slice; The peripheral circuit is further configured as: In the stage of applying the turn-on voltage to the first selection line, applying a third pass voltage to the third word line; In the phase of applying the turn-on voltage to the second selection line, a fourth pass voltage is applied to the third word line.

14. The memory according to claim 13, characterized in that: The fourth pass voltage is greater than the third pass voltage.

15. The memory according to any one of claims 9 to 14, characterized in that: Also includes: A first bit line coupled to a memory cell string in the first memory cell slice and a memory cell string in the second memory cell slice; a second bit line coupled to another memory cell string in the first memory cell slice and another memory cell string in the second memory cell slice; and the peripheral circuit is further configured as follows: In the phase of applying the programming voltage to the first word line, a first bit line voltage is applied to the first bit line, and a second bit line voltage is applied to the second bit line.

16. The memory according to claim 9, characterized in that: The storage unit in the memory is a single-level storage unit SLC.

17. A memory system, characterized in that: The invention comprises a storage controller and the memory according to any one of claims 9 to 16, wherein the storage controller is configured to control the memory.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, the method provided in any one of claims 1 to 8 can be implemented.

19. A computer device, characterized in that: The invention comprises a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, the method according to any one of claims 1 to 8 can be implemented.

20. A method for programming a memory, characterized in that: include: applying a programming voltage to a first word line coupled to a plurality of memory cells of each memory cell slice of a plurality of memory cell slices; In the stage of applying the programming voltage to the first word line, a turn-on voltage is applied to a plurality of selection lines in sequence; each of the plurality of selection lines is coupled to a selection transistor of a corresponding one of the plurality of storage cells.

21. The programming method according to claim 20, characterized in that ； In the stage of applying the on-voltage to a first selection line among the plurality of selection lines, applying a first pass voltage to a second word line coupled to another plurality of memory cells of each memory cell slice among the plurality of memory cell slices; In the stage of applying the turn-on voltage to a second selection line among the plurality of selection lines, applying a second pass voltage to the second word line; The stage of applying the turn-on voltage to the second selection line is after the stage of applying the turn-on voltage to the first selection line.

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