Preparation method of readable and writable memory device with OTP structure

Abstract

The invention discloses a preparation method of a readable and writable memory device with an OTP (One Time Programmable) structure, and relates to the technical field of integrated circuits, the method comprises the following steps: based on a conduction rule of an OTP unit, controlling a read-write state of a memory unit, and constructing a memory circuit; according to the storage circuit, a storage tube structure is determined, and the storage tube structure comprises an upper electrode, a resistive layer and a lower electrode; and calculating conductive current based on the storage tube structure, and preparing the storage device. The characteristic that the threshold voltage needs to be exceeded when the storage unit rewrites the data is utilized, the write-in / non-write-in state of the storage unit is controlled by setting the conduction state of the OTP unit, the setting of multiple read-write / read-only functions of the data in the storage device is realized, the preparation process is simple, the manufacturing cost is low, the data read-in / write-in speed is high, and the reliability of the storage device is improved. The defect that a traditional OTP memory device can only be rewritten once and cannot be rewritten for the second time is overcome.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a method for preparing a readable and writable storage device containing an OTP structure. Background Art

[0002] With the rapid development of information technology, memory, as one of the core components of computer systems, has been continuously improving in performance and function. Among the many types of memory, non-volatile memory (NVM) is widely used in storage units of various passive devices and safe storage of important data due to its ability to store information for a long time. In recent years, memristors, as a nonlinear resistor with memory function, have attracted widespread attention. Memristors are passive circuit elements whose resistance value depends on the magnitude, polarity and time of the applied voltage, and this change is reversible. Resistive random access memory (RRAM) developed based on the principle of memristors has excellent performance in important performance indicators such as storage density, power consumption, read and write speed, number of erasable times and data retention time, and is considered to be a highly potential next-generation general-purpose memory.

[0003] In the family of non-volatile memories, one-time programmable (OTP) memory has attracted wide attention due to its simple preparation process and good stability. OTP memory allows users to permanently burn programs or data into the memory, and once written, it cannot be changed or cleared. This feature makes OTP memory particularly suitable for storing information that does not need to be changed frequently, such as software version numbers, hardware version numbers, encryption keys, etc.; therefore, OTP memory has been widely used in various passive chips and passive tags; however, the limitation of traditional OTP memory is that its storage unit can only be rewritten once, which may cause inconvenience in some application scenarios that require flexibility.

[0004] The main drawback of traditional OTP memory devices is that their storage cells can only be rewritten once. Once rewritten, they will be permanently retained and cannot be rewritten a second time. This inherent limitation brings several obvious problems: First, in application scenarios where data needs to be updated frequently, OTP memory is not flexible enough to meet the needs of dynamic data storage; second, since the storage space cannot be reused, it may lead to waste of storage resources, especially in small devices with limited storage capacity; in addition, during the product development and testing phase, the one-time programming feature may increase the difficulty of debugging and verification, because any errors or data that needs to be updated require the use of new storage cells, which not only increases costs but also reduces development efficiency.

[0005] Currently, no effective solution has been proposed for the problems in the related technologies. Summary of the invention

[0006] 1. Technical issues to be resolved

[0007] In view of the shortcomings of the prior art, the present invention provides a method for preparing a readable and writable storage device containing an OTP structure, which has the advantages of simple process, low production cost, fast data reading / writing speed, and long-term information storage under active / passive conditions, thereby solving the problem in the prior art that traditional OTP storage devices can only be rewritten once, and once rewritten, they will be permanently retained and cannot be rewritten a second time.

[0008] (II) Technical solution

[0009] In order to achieve the advantages of simple process, low production cost, fast data reading / writing speed, and long-term information storage under active / passive conditions, the specific technical solution adopted by the present invention is as follows:

[0010] A method for preparing a readable and writable storage device containing an OTP structure, the method for preparing a readable and writable storage device containing an OTP structure comprising the following steps:

[0011] S1. Based on the conduction rule of the OTP unit, the read and write state of the storage unit is controlled, and the storage circuit is constructed;

[0012] S2. Determine a storage tube structure according to the storage circuit, wherein the storage tube structure includes an upper electrode, a resistive switching layer and a lower electrode;

[0013] S3. Based on the storage tube structure, the conduction current is calculated and a storage device is prepared.

[0014] Furthermore, the OTP unit includes a conducting state and a non-conducting state, and the self-resistance of the OTP unit when it is in the conducting state is smaller than the self-resistance when it is in the non-conducting state.

[0015] Furthermore, the memory cell is set with a threshold voltage. If the voltage on both sides of the memory cell is lower than the threshold voltage, the memory cell can only perform data reading operations. If the voltage on both sides of the memory cell is higher than the threshold voltage, the memory cell can perform data reading operations and data writing operations.

[0016] The data state of the storage unit includes a logic gate state, a resistance state, a capacitance state and a magnetization state.

[0017] Furthermore, the conduction rule of the OTP unit includes a write rule and a read rule. The control of the read and write state of the storage unit based on the conduction rule of the OTP unit and the construction of the storage circuit include the following steps:

[0018] S11, according to the decoder, setting the connection mode between the OTP unit and the storage unit;

[0019] S12, based on the data writing operation, construct a writing circuit and set a writing rule;

[0020] S13, based on the data reading operation, construct a reading circuit and set a reading rule;

[0021] S14. Establish a storage circuit according to the write circuit and the read circuit.

[0022] Further, one end of the OTP unit is connected to the storage unit, and the other end is connected to the decoder; one end of the storage unit is connected to the OTP unit and the decoder at the same time, and the other end is connected to the decoder;

[0023] The decoder includes a row decoder and a column decoder.

[0024] Further, the write circuit includes an access potential of the write circuit, an OTP unit, a storage unit and a zero potential;

[0025] The write rules include: when the write circuit is working, the OTP unit is set to the on state, and the potential difference on both sides of the storage unit is higher than the threshold voltage; when the OTP unit is connected to the setting voltage signal, the current passes through the resistive medium in the forward direction, and the storage tube is changed to a low resistance state; when the OTP unit is connected to the reset voltage signal, the current passes through the resistive medium in the reverse direction, and the storage tube is changed to a high resistance state.

[0026] Further, the read circuit includes a read circuit access potential, a storage unit and a zero potential;

[0027] The reading rules include: when the reading circuit is working, the potential difference between the two sides of the storage unit is lower than the threshold voltage; when the storage tube is in a low-resistance state, the reading circuit is turned on, and when the storage tube is in a high-resistance state, the reading circuit is turned off.

[0028] Furthermore, the storage tube structure is a sandwich structure including an upper electrode, a resistive layer and a lower electrode, the resistive layer material includes binary oxides, sulfur compounds and perovskite compounds, and the upper electrode and lower electrode materials include inert electrodes.

[0029] Further, based on the storage tube structure, the conduction current is calculated, and the storage device is prepared, including the following steps:

[0030] S31, calculating the conduction current according to the voltage and dielectric constant of the resistive switching layer;

[0031] S32, based on the active area substrate, using magnetron sputtering technology, growing the lower electrode and preparing the resistive switching layer film;

[0032] S33. Based on the resistive layer film, the upper electrode is grown using magnetron sputtering technology.

[0033] Furthermore, according to the voltage and dielectric constant of the resistive switching layer, the expression for calculating the conduction current is:

[0034]

[0035] In the formula, I represents the current, T represents the operating temperature, q represents the amount of electrons, V represents the voltage across the resistive switching layer, and ε i represents the dielectric constant of the resistive layer, ε0 represents the dielectric constant of vacuum, d represents the thickness of the resistive layer, and k represents the Boltzmann constant.

[0036] (III) Beneficial effects

[0037] Compared with the prior art, the present invention provides a method for preparing a readable and writable storage device having an OTP structure, which has the following beneficial effects:

[0038] (1) The present invention utilizes the characteristic that the threshold voltage must be exceeded when rewriting data in a storage unit, and controls the write / non-write state of the storage unit by setting the conduction state of the OTP unit. When the OTP unit is in the conduction state, the data of the storage unit can be written / read, and when the OTP unit is in the non-conduction state, the data can only be read, thereby realizing the setting of multiple read / write / read-only functions of data in the storage device.

[0039] (2) The storage device of the present invention has a simple manufacturing process, low manufacturing cost, fast data reading / writing speed, and can store information for a long time under active / passive conditions. It also solves the defect that traditional OTP storage devices can only be rewritten once, and once rewritten, they will be permanently retained and cannot be rewritten a second time. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 It is a flow chart of a method for preparing a readable and writable memory device having an OTP structure according to an embodiment of the present invention;

[0042] Figure 2 is a flow chart of a write / read-only operation of a storage circuit according to an embodiment of the present invention;

[0043] Figure 3 is a schematic diagram of a storage circuit according to an embodiment of the present invention;

[0044] Figure 4 is a schematic diagram of a storage tube structure according to an embodiment of the present invention;

[0045] Figure 5 is a cross-sectional view of a storage circuit according to an embodiment of the present invention;

[0046] Figure 6 is a specific storage circuit according to an embodiment of the present invention;

[0047] Figure 7 A memory array unit according to an embodiment of the present invention;

[0048] Figure 8 is an m×n memory array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention and are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in the field should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0050] According to an embodiment of the present invention, a method for preparing a readable and writable storage device having an OTP structure is provided.

[0051] The present invention is further described with reference to the accompanying drawings and specific embodiments. Figure 1 As shown, a method for preparing a readable and writable memory device having an OTP structure according to an embodiment of the present invention includes:

[0052] S1. Based on the conduction rule of the OTP unit, the read and write state of the storage unit is controlled, and the storage circuit is constructed;

[0053] S2. Determine a storage tube structure according to the storage circuit, wherein the storage tube structure includes an upper electrode, a resistive switching layer and a lower electrode;

[0054] S3. Based on the storage tube structure, the conduction current is calculated and a storage device is prepared.

[0055] In one embodiment, the OTP unit includes a conducting state and a non-conducting state, and the resistance of the OTP unit in the conducting state is smaller than the resistance of the OTP unit in the non-conducting state.

[0056] Specifically, the OTP unit has two states: conductive / non-conductive. Its own resistance in the conductive state is much smaller than its own resistance in the non-conductive state. When the side of the OTP unit connected to the row / column decoder is connected to a potential, its own conductive state has a significant impact on the potential difference on both sides of the storage unit connected to it.

[0057] In one embodiment, a threshold voltage is set for the memory cell. If the voltage on both sides of the memory cell is lower than the threshold voltage, the memory cell can only perform data reading operations. If the voltage on both sides of the memory cell is higher than the threshold voltage, the memory cell can perform data reading operations and data writing operations.

[0058] The data state of the storage unit includes a logic gate state, a resistance state, a capacitance state and a magnetization state.

[0059] Specifically, the storage unit may be composed of a single structure or several smaller structures, and the connection between the OTP unit and the storage unit is not limited to one side of the storage unit, but may also be connected between several smaller structures inside the storage unit.

[0060] Specifically, the memory cell has a threshold voltage. When the voltage on both sides of the memory cell is lower than the threshold voltage, the data state of the memory cell (including but not limited to the logic gate state / resistance / capacitance / magnetization state) cannot change fundamentally. When the voltage on both sides of the memory cell is higher than the threshold voltage, the data state of the memory cell (including but not limited to the logic gate state / resistance / capacitance / magnetization state) may change fundamentally.

[0061] Specifically, whether the data state of the storage unit can be fundamentally changed can be determined based on the conduction state of the OTP unit itself. When the OTP unit is in the conduction state, the data state of the storage unit can be read and changed. When the OTP unit is not in the conduction state, the data state of the storage unit can only be read, and the data state of the storage unit cannot be changed.

[0062] In one embodiment, the conduction rule of the OTP unit includes a write rule and a read rule. The control of the read and write state of the storage unit based on the conduction rule of the OTP unit and the construction of the storage circuit include the following steps:

[0063] S11, according to the decoder, setting the connection mode between the OTP unit and the storage unit;

[0064] S12, based on the data writing operation, construct a writing circuit and set a writing rule;

[0065] S13, based on the data reading operation, construct a reading circuit and set a reading rule;

[0066] S14. Establish a storage circuit according to the write circuit and the read circuit.

[0067] Specifically, Figure 3As shown, it is a schematic diagram of the storage circuit of the present invention, which corresponds to different circuits when performing data write / read-only operations, including ① write circuit: Vset / Vreset—OTP unit—storage unit—VBL; ② read circuit: VSL—storage unit—VBL; in the figure, Vset / Vreset is the access potential of the write circuit, VSL is the access potential of the read circuit, and VBL is the zero potential.

[0068] In one embodiment, one end of the OTP unit is connected to the storage unit, and the other end is connected to the decoder; one end of the storage unit is connected to the OTP unit and the decoder at the same time, and the other end is connected to the decoder;

[0069] The decoder includes a row decoder and a column decoder.

[0070] Specifically, in each memory array unit, one side of the OTP unit is connected to the storage unit, and the other side is connected to the row / column decoder; one side of the storage unit is connected to the OTP unit and the row / column decoder at the same time, and the other side is connected to the row / column decoder.

[0071] In one embodiment, the write circuit includes an access potential of the write circuit, an OTP unit, a storage unit, and a zero potential;

[0072] The write rules include: when the write circuit is working, the OTP unit is set to the on state, and the potential difference on both sides of the storage unit is higher than the threshold voltage; when the OTP unit is connected to the setting voltage signal, the current passes through the resistive medium in the forward direction, and the storage tube is changed to a low resistance state; when the OTP unit is connected to the reset voltage signal, the current passes through the resistive medium in the reverse direction, and the storage tube is changed to a high resistance state.

[0073] It should be noted that Vset and Vreset are potential signals used to control the change of the state of the memory cell. Usually, Vset and Vreset represent different voltage levels and are used to realize two different states of the memory cell. Among them, Vset (set voltage signal) is used to change the memory cell from a high-resistance state (OFF-state) to a low-resistance state (ON-state), which usually corresponds to writing data "0" or programming operations; Vreset (reset voltage signal) is used to change the memory cell from a low-resistance state (ON-state) back to a high-resistance state (OFF-state), which usually corresponds to writing data "1" or erasing operations.

[0074] Specifically, when the write circuit is working, the OTP unit is set to be in the on state, and different potentials Vset / Vreset are connected to the OTP terminal, then the potential difference between the two sides of the storage unit is close to the potential difference between Vset / Vreset and VBL, and this potential difference is higher than the threshold voltage that changes the resistance state of the storage unit. When the OTP terminal is connected to the potential Vset, the current is forward (assuming that the current direction is forward) through the resistive medium, and the storage tube is changed to a low resistance state; when the OTP terminal is connected to the potential Vreset, the current is reversed through the resistive medium, and the storage tube is changed to a high resistance state.

[0075] In one embodiment, the read circuit includes a read circuit access potential, a storage unit, and a zero potential;

[0076] The reading rules include: when the reading circuit is working, the potential difference between the two sides of the storage unit is lower than the threshold voltage; when the storage tube is in a low-resistance state, the reading circuit is turned on, and when the storage tube is in a high-resistance state, the reading circuit is turned off.

[0077] Specifically, when the read circuit is working, the potential difference between the two sides of the storage unit is close to the potential difference between VSL and VBL, which is lower than the threshold voltage that changes the resistance state of the storage unit. When the storage tube is in a low resistance state, the read circuit is turned on, corresponding to the circuit logic state 1; when the storage tube is in a high resistance state, the read circuit is turned off, corresponding to the circuit logic state 0.

[0078] Specifically, Figure 2 As shown, for a single memory array unit, when the OTP unit in the memory array unit is in a conducting state, data writing / data reading operations can be performed on the memory unit; when the OTP unit in the memory unit is in a non-conducting state, only data reading operations can be performed on the memory unit.

[0079] In one embodiment, the storage tube structure is a sandwich structure including an upper electrode, a resistive layer and a lower electrode, the resistive layer material includes binary oxides, sulfide compounds and perovskite compounds, and the upper electrode and lower electrode materials include inert electrodes.

[0080] Specifically, Figure 4 As shown, the storage tube is composed of a sandwich structure of an upper electrode, a resistive layer and a lower electrode. The resistive layer material can use binary oxides with memristive properties (including but not limited to CuOx, TiOx, HfOx), sulfur compounds, and perovskite compounds ABOx. The upper and lower electrode materials use inert electrodes.

[0081] In one embodiment, based on the storage tube structure, calculating the conduction current and preparing the storage device includes the following steps:

[0082] S31, calculating the conduction current according to the voltage and dielectric constant of the resistive switching layer;

[0083] S32, based on the active area substrate, using magnetron sputtering technology, growing the lower electrode and preparing the resistive switching layer film;

[0084] S33. Based on the resistive layer film, the upper electrode is grown using magnetron sputtering technology.

[0085] Specifically, the storage tube has a threshold voltage. The resistance state of the storage tube will change only when the voltage across the storage tube is higher than the threshold voltage. If the voltage is lower than the threshold voltage, the storage tube can be turned on but the resistance state does not change.

[0086] Specifically, the preparation of the storage tube includes growing a lower electrode on the substrate of the active area by magnetron sputtering technology, and then preparing a resistive layer film by EBL process and overlay process respectively, and also growing an upper electrode by magnetron sputtering technology.

[0087] It should be added that in the preparation process of the storage tube, the term "growing" the upper and lower electrodes refers to the process of forming an electrode layer on the substrate using physical vapor deposition (PVD) technology, such as magnetron sputtering technology. This method uses the magnetic field and electric field inside the vacuum chamber to bombard atoms or molecules on the surface of the target material and deposit them on the substrate, thereby forming a thin film electrode; this process is often called "growth" in materials science because it involves "growing" a new layer of material on the substrate.

[0088] In one embodiment, according to the voltage of the resistive switching layer and the dielectric constant, the expression for calculating the conduction current is:

[0089]

[0090] In the formula, I represents the current, T represents the operating temperature, q represents the amount of electrons, V represents the voltage across the resistive switching layer, and ε i represents the dielectric constant of the resistive layer, ε0 represents the dielectric constant of vacuum, d represents the thickness of the resistive layer, and k represents the Boltzmann constant.

[0091] In order to facilitate understanding of the above technical solution of the present invention, the memory device prepared by the present invention is taken as an example for specific description as follows:

[0092] like Figure 5-Figure 8 As shown, the memory device prepared by the present invention has a memory circuit including an OTP unit part 011 and a memory unit part 012 .

[0093] like Figure 5As shown, the OTP unit part 011 is composed of two MOS tubes connected in series, adopting a 1.5T structure with a common source region 003. The left MOS is a gate tube, including source regions 001, 003 and a control gate 002. The right MOS adopts a floating gate structure 004, including source regions 003, 005 and a floating gate region 004.

[0094] The storage unit part 012 is composed of a gate MOS and a storage tube 007. The gate MOS includes source regions 008, 010 and a control gate 009. The source region 010 is connected to VSL. The lower electrode of the storage tube can be directly grown on the source region 008 of the gate MOS. The upper and lower electrodes of the storage tube 007 use inert electrodes, and different metal materials can be selected as needed. The upper and lower electrode layers are filled with an insulating layer. The resistive variable medium passes through the insulating layer to connect the two electrodes. The lower electrode is respectively connected to the gate tube source region 008 and the OTP unit 006 of the storage unit part 012.

[0095] The floating gate structure 004 of the OTP part can store hot carriers, and the write / non-write state of the memory cell can be controlled by the floating gate structure 004 .

[0096] The following is an example of a specific circuit structure. Figure 6 As shown, the OTP unit consists of two PMOS tubes 021 and 022 connected in series. The left PMOS 021 is a gate tube, and the right PMOS structure 022 with a floating gate has a high withstand voltage. The gate oxide layer of the PMOS gate has a high withstand voltage. Accordingly, the source regions 001, 003, and 005 are P-type doped, with a doping concentration of 5×1019 to 5×1021, and the well region 013 is set as an N well with a doping concentration of 5×1017 to 5×1018.

[0097] The storage unit selection tube 023 adopts an NMOS structure. The carrier migration rate of NMOS is high and the reading speed is fast. Correspondingly, the source regions 008 and 010 adopt N-type doping with a doping concentration of 5×1019~5×1021, and the well region 014 is set as a P well with a doping concentration of 5×1017~5×1018. According to the above conductive formula, the resistive layer material of the storage tube 024 preferably uses a metal oxide with a high dielectric constant, such as CuxO, the upper electrode material preferably uses an active metal compound, such as titanium nitride, and the lower electrode material preferably uses an inert metal material, such as platinum, gold, etc. The thickness of the upper and lower electrodes is 41~62nm, and the thickness of the resistive layer is 33~46nm. The specific structure is as follows Figure 4 shown.

[0098] The access potentials of the storage circuit are VSL = 0.3 V, Vset = -1.2 V, and Vreset = 1.2 V. The threshold voltage of the storage transistor 024 is 0.5 V, and the write / erase test pulse period T = 50 ns.

[0099] After the storage device is prepared, the present invention performs a read test and a write / erase test.

[0100] ① Read test: The read voltage is set to 0.3V, and the storage tube is volatile. The DC resistance of the low-resistance device is very stable when working, and it can be considered that the resistance state has not changed; the number of reads of the DC resistance state transition in the high-resistance state is more than 105 times.

[0101] ② Write / erase test (SET / RESET): Use a 50ns pulse voltage of -1.2V Vset to write the memory cell, and a 50ns pulse voltage of 1.2V Vreset to erase the memory cell. The memory tube is turned on in a non-volatile manner. The resistance state of the memory tube can be maintained for a long time. The resistance change range of the memory tube is 104Ω (low resistance state) to 106Ω (high resistance state), and the resistance ratio R1 / R2≈1 / 100.

[0102] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a readable and writable storage device having an OTP structure, wherein the storage device comprises an OTP unit and a storage unit, wherein: The method for preparing the readable and writable storage device containing the OTP structure comprises the following steps: S1. Based on the conduction rule of the OTP unit, the read and write state of the storage unit is controlled, and the storage circuit is constructed; S2. Determine a storage tube structure according to the storage circuit, wherein the storage tube structure includes an upper electrode, a resistive switching layer and a lower electrode; S3. Based on the storage tube structure, the conduction current is calculated and a storage device is prepared.

2. The method for preparing a readable and writable memory device having an OTP structure according to claim 1, characterized in that: The OTP unit includes a conducting state and a non-conducting state, and the self-resistance of the OTP unit when it is in the conducting state is smaller than the self-resistance when it is in the non-conducting state.

3. The method for preparing a readable and writable storage device having an OTP structure according to claim 1, characterized in that: The memory cell is set with a threshold voltage. If the voltage on both sides of the memory cell is lower than the threshold voltage, the memory cell can only perform data reading operations. If the voltage on both sides of the memory cell is higher than the threshold voltage, the memory cell can perform data reading operations and data writing operations. The data state of the storage unit includes a logic gate state, a resistance state, a capacitance state and a magnetization state.

4. The method for preparing a readable and writable memory device having an OTP structure according to claim 1, characterized in that: The conduction rule of the OTP unit includes a write rule and a read rule. The control of the read and write state of the storage unit based on the conduction rule of the OTP unit and the construction of the storage circuit include the following steps: S11, according to the decoder, setting the connection mode between the OTP unit and the storage unit; S12, based on the data writing operation, construct a writing circuit and set a writing rule; S13, based on the data reading operation, construct a reading circuit and set a reading rule; S14. Establish a storage circuit according to the write circuit and the read circuit.

5. The method for preparing a readable and writable memory device having an OTP structure according to claim 4, characterized in that: One end of the OTP unit is connected to the storage unit, and the other end is connected to the decoder; one end of the storage unit is connected to the OTP unit and the decoder at the same time, and the other end is connected to the decoder; The decoder includes a row decoder and a column decoder.

6. The method for preparing a readable and writable memory device having an OTP structure according to claim 4, characterized in that: The write circuit includes an access potential of the write circuit, an OTP unit, a storage unit and a zero potential; The write rules include: when the write circuit is working, the OTP unit is set to the on state, and the potential difference on both sides of the storage unit is higher than the threshold voltage; when the OTP unit is connected to the setting voltage signal, the current passes through the resistive medium in the forward direction, and the storage tube is changed to a low resistance state; when the OTP unit is connected to the reset voltage signal, the current passes through the resistive medium in the reverse direction, and the storage tube is changed to a high resistance state.

7. The method for preparing a readable and writable memory device having an OTP structure according to claim 4, characterized in that: The read circuit includes a read circuit access potential, a storage unit and a zero potential; The reading rules include: when the reading circuit is working, the potential difference between the two sides of the storage unit is lower than the threshold voltage; when the storage tube is in a low-resistance state, the reading circuit is turned on, and when the storage tube is in a high-resistance state, the reading circuit is turned off.

8. The method for preparing a readable and writable memory device having an OTP structure according to claim 1, characterized in that: The storage tube structure is a sandwich structure including an upper electrode, a resistive switching layer and a lower electrode. The resistive switching layer material includes binary oxides, sulfur compounds and perovskite compounds. The upper electrode and lower electrode materials include inert electrodes.

9. The method for preparing a readable and writable memory device having an OTP structure according to claim 1, characterized in that: The method of calculating the conduction current based on the storage tube structure and preparing the storage device comprises the following steps: S31, calculating the conduction current according to the voltage and dielectric constant of the resistive switching layer; S32, based on the active area substrate, using magnetron sputtering technology, growing the lower electrode and preparing the resistive switching layer film; S33. Based on the resistive layer film, the upper electrode is grown using magnetron sputtering technology.

10. The method for preparing a readable and writable memory device having an OTP structure according to claim 9, characterized in that: The expression for calculating the conduction current according to the resistance switching layer voltage and the dielectric constant is: In the formula, I represents the current, T represents the operating temperature, q represents the amount of electrons, V represents the voltage across the resistive switching layer, and ε i represents the dielectric constant of the resistive layer, ε0 represents the dielectric constant of vacuum, d represents the thickness of the resistive layer, and k represents the Boltzmann constant.

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