Erase and program operations for memory devices with multiple memory modes

Abstract

The invention relates to erase and program operations for memory devices with multiple memory modes. Methods, systems, and apparatus, including computer programs encoded onto a computer storage medium, are provided for operating a memory device having multiple storage modes. In one example method, a portion of a memory array is selected, where the portion of the memory array is programmable in a first memory mode or a second memory mode. The second memory mode has a lower memory density than the first memory mode, and the first memory mode corresponds to a first erase operation. A switching erase operation is performed to switch the portion of the memory array from the first memory mode to a switched second memory mode, where the switched second memory mode has the same memory density as the second memory mode and corresponds to the switching erase operation. The switched erase operation is different from a first erase operation performed on the memory array in the first memory mode.

Description

Technical Field

[0001] The present disclosure relates generally to memory systems and, more particularly, to operating a memory device having multiple storage modes. Background Art

[0002] The memory system may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory system to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0003] The present disclosure describes the operation of a memory device having multiple storage modes.

[0004] In one aspect, for example, the present disclosure describes a method for operating a memory device. The method includes selecting a portion of a memory array and performing a switching erase operation to switch the portion of the memory array from a first storage mode to a switched second storage mode. The portion of the memory array is programmable in the first storage mode or the second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation. The switched second storage mode has the same storage density as the second storage mode and corresponds to a switching erase operation. The switching erase operation is different from a first erase operation performed on the memory array in the first storage mode.

[0005] In another aspect, the present disclosure describes a memory device. The memory device includes: a memory array; and a peripheral circuit coupled to the memory array and configured to perform an operation, the operation including: selecting a portion of the memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode; and performing a switching erase operation to switch the portion of the memory array from the first storage mode to the switched second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation using a first effective erase voltage. The switched second storage mode has the same storage density as the second storage mode and corresponds to a switching erase operation, and after performing the switching erase operation, the threshold voltage of the memory cells of the portion of the memory array is higher than the threshold voltage of the memory cells of the portion of the memory array after performing the first erase operation.

[0006] In another aspect, the present disclosure describes one or more non-transitory computer-readable storage media. The one or more non-transitory computer-readable storage media store instructions that, when executed by one or more machines, cause the one or more machines to perform operations, the operations comprising: selecting a portion of a memory array, and performing a switching erase operation, thereby switching the portion of the memory array from a first storage mode to a switched second storage mode. The portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode and the first storage mode corresponds to a first erase operation. The switched second storage mode has the same storage density as the second storage mode and corresponds to a switching erase operation, and after performing the switching erase operation, the threshold voltage of the memory cells of the portion of the memory array is higher than the threshold voltage of the memory cells of the portion of the memory array after performing the first erase operation.

[0007] In another aspect, the present disclosure describes another method for operating a memory device. The method includes selecting a portion of a memory array and performing a switching programming operation to switch the portion of the memory array in a first storage mode to a second storage mode after switching. The portion of the memory array is programmable in the first storage mode or the second storage mode. The second storage mode has a lower storage density than the first storage mode, and the second storage mode corresponds to a second programming operation. The switched second storage mode has the same storage density as the second storage mode and corresponds to the switching programming operation. The switching programming operation is different from the second programming operation of the second storage mode.

[0008] In another aspect, the present disclosure describes a memory device. The memory device includes: a memory array; and a peripheral circuit coupled to the memory array and configured to perform an operation, the operation including: selecting a portion of the memory array, and performing a switching programming operation, thereby switching the portion of the memory array in a first storage mode to a second storage mode after switching. The portion of the memory array is programmable in the first storage mode or the second storage mode. The second storage mode has a lower storage density than the first storage mode, the first storage mode corresponds to a first programming operation, and the second storage mode corresponds to a second programming operation. The switched second storage mode has the same storage density as the second storage mode and corresponds to a switching programming operation. The switching programming operation is different from the second programming operation of the second storage mode.

[0009] In another aspect, the present disclosure describes one or more non-transitory computer-readable storage media. The one or more non-transitory computer-readable storage media store instructions that, when executed by one or more machines, cause the one or more machines to perform operations, the operations comprising: selecting a portion of a memory array, and performing a switching programming operation, thereby switching the portion of the memory array in a first storage mode to a second storage mode after switching. The portion of the memory array is programmable in a first storage mode or a second storage mode. The second storage mode has a lower storage density than the first storage mode, the first storage mode corresponds to a first programming operation, and the second storage mode corresponds to a second programming operation. The switched second storage mode has the same storage density as the second storage mode and corresponds to a switching programming operation. The switching programming operation is different from the second programming operation of the second storage mode.

[0010] In yet another aspect, the present disclosure describes a memory system. The memory system includes: a controller; a memory device including a memory array; and a peripheral circuit coupled to the memory array and configured to perform operations, the operations including: selecting a portion of the memory array, and performing a switching programming operation, thereby switching the portion of the memory array in a first storage mode to a second storage mode after switching. The portion of the memory array is programmable in the first storage mode or the second storage mode. The second storage mode has a lower storage density than the first storage mode, the first storage mode corresponds to a first programming operation, and the second storage mode corresponds to a second programming operation. The switched second storage mode has the same storage density as the second storage mode and corresponds to a switching programming operation. The switching programming operation is different from the second programming operation of the second storage mode.

[0011] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic circuit diagram of an exemplary memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0013] Figure 2 A side view of a cross section of an exemplary memory cell array including NAND memory strings according to some aspects of the present disclosure is shown.

[0014] Figure 3 A block diagram of an exemplary memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure is shown.

[0015] Figure 4A flow chart is shown of an exemplary process for performing a toggle erase operation according to some aspects of the present disclosure.

[0016] Figure 5 Waveform diagrams of different erase operations in different storage modes according to some aspects of the present disclosure are shown.

[0017] Figure 6 Execution of a block of a memory device according to some aspects of the present disclosure is shown. Figure 4 An exemplary process of a switching erase operation.

[0018] Figure 7 Execution of a block of a memory device according to some aspects of the present disclosure is shown. Figure 4 Another exemplary technique for switching erase operations.

[0019] Figure 8 Execution of a half block of a memory device according to some aspects of the present disclosure is shown. Figure 4 An exemplary technique for switching erase operations.

[0020] Fig. 9 Execution of a half block according to some aspects of the present disclosure is shown. Figure 4 Another exemplary technique for switching erase operations.

[0021] Fig.10 Waveform diagrams of different bias voltage values ​​and erase voltage values ​​for an erase operation and a toggle erase operation according to some aspects of the present disclosure are shown.

[0022] Fig.11 Exemplary threshold voltage distributions for memory cells in QLC and SLC modes, respectively, are shown according to aspects of the present disclosure.

[0023] Fig.12 Exemplary waveform diagrams of different bias voltage values ​​and erase voltage values ​​for an erase operation and a toggle erase operation performed on a portion of a block (eg, half a block) according to aspects of the present disclosure are shown.

[0024] Fig.13 A flow chart is shown of an exemplary process for performing a toggle programming operation according to some aspects of the present disclosure.

[0025] Fig.14 Waveform diagrams of different programming operations in different storage modes according to some aspects of the present disclosure are shown.

[0026] Fig.15 Execution of a block of a memory device according to some aspects of the present disclosure is shown. Fig.13 An exemplary process of switching programming operation.

[0027] Fig.16 Execution of a block of a memory device according to some aspects of the present disclosure is shown. Fig.13 Another exemplary technique for switching programming operations.

[0028] Fig.17 Execution of a half block of a memory device according to some aspects of the present disclosure is shown. Fig.13 An exemplary technique for switching programming operations.

[0029] Fig.18 Execution of a half block according to some aspects of the present disclosure is shown. Fig.13 Another exemplary technique for switching programming operations.

[0030] Fig.19 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation.

[0031] Fig. 20 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation.

[0032] Fig.21 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation.

[0033] Fig. 22 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation.

[0034] Fig.23 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation.

[0035] Fig.24 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation.

[0036] Fig.25 A block diagram of an exemplary system having a memory device according to some aspects of the present disclosure is shown.

[0037] Fig.26A A diagram of an exemplary memory card having a memory device according to some aspects of the present disclosure is shown.

[0038] Fig.26B A diagram of an exemplary solid-state drive (SSD) having a memory device according to some aspects of the present disclosure is shown.

[0039] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0040] The memory system can be a storage device, a memory module, or a mixture of a storage device and a memory module. In general, a host system can employ a memory system that includes one or more memory components (e.g., a memory device that stores data). The host system can provide data to be stored on the memory device and can request data to be retrieved from the memory device.

[0041] A memory system may include a high-density non-volatile memory device where it is desirable to retain data when the memory device is not powered. For example, NAND memory (e.g., three-dimensional (3D) flash NAND memory) provides storage in a compact, high-density configuration. For some types of non-volatile memory devices (e.g., NAND memory), each storage plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells. A memory cell is an electronic circuit that stores information.

[0042] A single-level cell (SLC) can store only one bit per memory element / cell, while a multi-level cell (MLC) is a memory cell that can store more than a single bit of information. An SLC has two possible memory states corresponding to one bit of information. An MLC has more than two memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)), or even more bits per cell. In some embodiments, in the QLC mode, a pseudo word line can be used as a core word line for storing data and thereby increasing storage capacity. On the other hand, in the SLC mode, the pseudo word line is not used to store data, thereby reducing its impact on the ESUM (sum of voltage state intervals) of the memory device. In the present disclosure, "MLC" is used to refer to cells that store two or more bits of data, including bipolar cells, three-level cells (TLC), four-level cells (QLC), and other higher-level cells.

[0043] Due to the nature of the operation of NAND cells, data in NAND flash memory cannot generally be overwritten, so the cell must be erased before new data is written into the cell. Although data in flash memory can be read and written at the page level, erasure is done at the block level or half-block level. Therefore, data can be written only to pages in a block or half-block that has been previously erased.

[0044] In the present disclosure, storage mode switching techniques are described that allow a memory device to change or switch the storage mode of a memory cell. For example, in some embodiments, SLC cells can be switched to MLC cells, or vice versa, or one type of MLC cell (e.g., TLC) can be switched to another type of MLC cell (e.g., QLC), or vice versa. In some embodiments, the storage mode switching techniques support switching any block from a higher-level MLC mode (e.g., QLC) to an SLC mode or a lower-level MLC mode (e.g., TLC), thereby (e.g.) taking advantage of the higher access speed or reliability of the SLC mode or the lower-level MLC mode to achieve faster erase and program operations, or doing so when (multiple) read failures are detected or otherwise identified as blocks for such storage mode switching. As an exemplary scenario, instead of discarding a worn block composed of MLC cells, a worn block composed of MLC cells can be switched to SLC mode. Thereafter, these worn blocks composed of MLC cells can be programmed and accessed as if they were SLC cells (with certain modifications, as needed, as discussed in more detail below). By allowing the storage mode of the block to be switched to the SLC mode or lower level MLC mode, blocks that might otherwise be unusable in a higher level storage mode are allowed to continue to be utilized and the life of the memory device may be extended.

[0045] During a programming operation, a programming voltage Vpgm may be applied to a selected word line, and a pass voltage Vpass may be applied to an unselected word line. During an erase operation, a bias voltage Vbias may be applied to both the selected word line and the unselected word line, and an erase voltage Verase may be applied to the P-well (e.g., in a P-well erase mode) or to the source line and / or bit line of a selected block (e.g., in a GIDL erase mode). Programming operations and erase operations of memory cells in different storage modes may use different voltage values. For example, an erase operation in an SLC mode or a lower-level MLC mode generally uses a lower erase voltage level than an erase operation in a higher-level MLC mode.

[0046] In order to implement the storage mode switching technology, a specific switching operation is designed to ensure the functionality and performance of the memory device. The switching operation may include switching erase operations and specific programming operations. The voltage applied in the switching operation is not a trivial choice, because applying a typical programming or erasing voltage in SLC or MCL mode may cause performance degradation after mode switching. For example, when a block of memory cells (also referred to as a selected block) is switched from a higher-level MLC mode (e.g., QLC) to an SLC mode or a lower-level MLC mode (e.g., TLC), continuing to use a (higher) MLC erase voltage value to perform an erase operation on the block may cause the threshold voltage of the memory cell to drop a lot, causing the cell to undershoot relative to its expected threshold voltage even after multiple programming pulses. This may cause some memory cells, especially memory cells on a pseudo word line (i.e., a word line that is not used to store host data by default), to become under-programmed (e.g., under-programmed relative to a more stringent programming verification threshold voltage), and will accordingly fail to pass the programming verification operation. Similarly, performing an erase operation on the block using a (lower) SLC erase voltage value may cause the threshold voltage of a memory cell to drop so slightly that the cell later overshoots relative to its intended threshold voltage even on an initial programming pulse and may become overprogrammed (e.g., overprogrammed relative to a more stringent program verify threshold voltage). In either case, unrecoverable read errors may occur, resulting in degradation of block performance.

[0047] Specific switching operations that help solve the above problems are described in the present disclosure. One or more of the following advantages can be achieved by implementing specific embodiments of the subject matter described in the present disclosure. For example, in some embodiments, the performance of the memory system can be improved, thereby allowing the memory cells in the multi-level cell (MLC) mode to switch to the single-level cell (SLC) mode or the lower-level MLC mode, thereby achieving more reliable performance and extending the usable life of the memory device. In addition, the described technology allows the SLC mode or the lower-level MLC mode to switch to the higher-level MLC mode in some cases, thereby increasing the storage capacity of the memory device, in a manner that utilizes the memory cells on the pseudo word line without increasing the hardware cost. By accessing such blocks using the designed switching erase voltage or switching programming voltage, the voltage distribution of each memory cell in the block can be kept within the expected range and exempted from excessive or too small offsets. The described technology can improve the reliability of the memory system and reduce the error rate.

[0048] Figure 1A schematic circuit diagram of an exemplary memory device 100 including a peripheral circuit 102 according to some aspects of the present disclosure is shown. The memory device 100 may include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. The memory cell array 101 may be, for example, a NAND flash memory cell array, wherein the memory cells 106 are provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically above a substrate. In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and arranged in a vertical stack. Each memory cell 106 is capable of holding a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the area of ​​the memory cell 106. Each memory cell 106 may be a "floating gate" type memory cell including a floating gate transistor, or may be a "charge trap" type memory cell including a charge trap transistor.

[0049] In some embodiments, each memory cell 106 may have a corresponding storage mode, such as a single-level cell (SLC) or a multi-level cell (MLC). The SLC has two possible memory states and is thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. The MLC is capable of storing more than a single bit of data in more than two memory states. For example, the MLC is capable of storing two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may have a variety of possible memory states and may be programmed to present a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may have four possible memory states and may be programmed to present four nominal storage values; the MLC may be programmed from an erased state to present one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. The fourth nominal storage value may be used as an erased state.

[0050] like Figure 1As shown in , each NAND memory string 108 may also include a source select gate (SSG) transistor 110 at its source end and a drain select gate (DSG) transistor 112 at its drain end. The SSG transistor 110 and the DSG transistor 112 may be configured to activate a selected NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 108 in the same block 104 are coupled through the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 108 is coupled to a corresponding bit line 116, and data can be read from or written to the bit line 116 via an output bus. In some embodiments, each NAND memory string 108 is configured to be selected or deselected by applying a DSG select voltage or a DSG deselect voltage to the gate of a corresponding DSG transistor 112 via one or more DSG lines 113 and / or by applying an SSG select voltage or an SSG deselect voltage to the gate of a corresponding SSG transistor 110 via one or more SSG lines 115.

[0051] like Figure 1 As shown in , the NAND memory strings 108 can be organized into a plurality of blocks 104, each of which can have a common source line 114, for example, coupled to one ACS. In some embodiments, each block 104 is the basic data unit of an erase operation, i.e., all memory cells 106 on the same block 104 are erased at the same time. The memory cells 106 of adjacent NAND memory strings 108 can be coupled by word lines 118, which select which row of memory cells 106 are affected by read and program operations. In some embodiments, each word line 118 is coupled to the memory cells 106 of a page 120. The size of a page 120 measured in bits can relate to the number of NAND memory strings 108 in a block 104 coupled by word lines 118. Each word line 118 can include a plurality of control gates (gate electrodes) at each memory cell 106 on a corresponding page 120 and a gate line coupling the control gates.

[0052] Figure 2 Some aspects of the present disclosure include Figure 1 1 is a side view of a cross section of an exemplary memory cell array 101 of NAND memory strings 108 shown in FIG. Figure 2As shown in , the NAND memory string 108 can extend vertically through the memory stack 204 above the substrate 202. The substrate 202 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. Here, in Figure 2 The x-axis, y-axis, and z-axis are included to further illustrate the spatial relationship of the components in the memory device. The substrate 202 includes two lateral surfaces extending laterally in the xy plane: a top surface on the front side of the wafer on which the memory device can be formed, and a bottom surface on the back side opposite to the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when the substrate 202 is in the lowest storage plane of the memory device in the z-direction (perpendicular to the vertical direction of the xy plane), whether a component (e.g., a layer or a device) of the memory device is "on", "above", or "below" another component (e.g., a layer or a device) is determined relative to the substrate 202 of the memory device along the z-direction. The same concepts will be used throughout the present disclosure to describe spatial relationships.

[0053] The memory stack 204 may include alternating gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 may determine the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate of the memory cell 106, a gate of the DSG transistor 112, or a gate of the SSG transistor 110, and may extend laterally as a DSG line 113 in the upper portion of the memory stack 204, as an SSG line 115 in the lower portion of the memory stack 204, or as a word line 118 between the DSG line 113 and the SSG line 115. Figure 2 One SSG line 115 and one DSG line 113 are shown in FIG. 1 , but the number of SSG lines 115 and the number of DSG lines 113 (and the number of SSG transistors 110 and DSG transistors 112 coupled to the SSG lines 115 and the DSG lines 113 , respectively) may vary in other examples.

[0054] like Figure 2As shown in , the NAND memory string 108 includes a channel structure 212 extending vertically through the memory stack 204. In some embodiments, the channel structure 212 includes a channel opening filled with (multiple) semiconductor materials (e.g., as semiconductor channels 220) and (multiple) dielectric materials (e.g., as storage films 218). In some embodiments, the semiconductor channel 220 includes silicon, such as polysilicon. In some embodiments, the memory film 218 is a composite dielectric layer including a tunneling layer 226, a storage layer 224 (also called a "charge trapping layer"), and a barrier layer 222. The channel structure 212 can have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the semiconductor channel 220, the tunneling layer 226, the storage layer 224, and the barrier layer 222 are radially arranged in this order from the center of the column to the outer surface of the column. The tunneling layer 226 can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 224 can include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 222 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 218 may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0055] According to some embodiments, Figure 2 As shown in , a well 214 (e.g., a P-well (P-type doped region) and / or an N-well) is formed in the substrate 202, and the source of the NAND memory string 108 is in contact with the well 214. The source line 114 and / or the bit line 116 of each of the one or more blocks 104 may be coupled to the well 214. As described above, during or after the discharge of the programming voltage in response to an interrupt in a programming operation, holes may be attracted out of the well 214 (e.g., the P-well) and accumulated in the semiconductor channel 220 and the storage layer 224 due to coupling to the negative potential in the semiconductor channel 220. In some embodiments, the NAND memory string 108 further includes a channel plug 216 at the drain end of the NAND memory string 108, for example, to be part of the drain of the NAND memory string 108.

[0056] Re-reference Figure 1, the peripheral circuit 102 may be coupled to the memory cell array 101 through the bit line 116, the word line 118, the source line 114, the SSG line 115, and the DSG line 113. The peripheral circuit 102 may include any suitable analog, digital, and mixed signal circuits to facilitate the operation of the memory cell array 101 by applying a voltage signal and / or a current signal to each target (selected) memory cell 106 and sensing a voltage signal and / or a current signal from each target (selected) memory cell 106 through the bit line 116, the word line 118, the source line 114, the SSG line 115, and the DSG line 113. The peripheral circuit 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0057] Figure 3 1 is a block diagram of an exemplary memory device 300 including a memory cell array 101 and a peripheral circuit 102 according to some aspects of the present disclosure. Specifically, Figure 3 An exemplary peripheral circuit 102 is shown, including a page buffer / sense amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, a control logic 312, a register 314, an interface 316, and a data bus 318. In some examples, it may also include Figure 3 Other peripheral circuits not shown.

[0058] The page buffer / sense amplifier 304 can be configured to read data from the memory cell array 101 and program (write) data to the memory cell array 101 according to a control signal from the control logic 312. In one example, the page buffer / sense amplifier 304 can store a page of programming data (write data) to be programmed into one page 120 of the memory cell array 101. In another example, the page buffer / sense amplifier 304 can perform a program verification operation to ensure that the data has been correctly programmed into the selected memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 can also sense a low-power signal representing a data bit stored in the memory cell 106 from the bit line 116 in a read operation and amplify the small voltage swing to a recognizable logic level. The column decoder / bit line driver 306 can be configured to be controlled by the control logic 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated by the voltage generator 310.

[0059] The row decoder / word line driver 308 may be configured to be controlled by the control logic 312 according to the control signal, and select / deselect the block 104 of the memory cell array 101, and select / deselect the word line 118 of the block 104. The row decoder / word line driver 308 may be further configured to drive the word line 118 using the word line voltage generated by the voltage generator 310. In some embodiments, the row decoder / word line driver 308 may also select / deselect and drive the SSG line 115 and the DSG line 113 using the SSG voltage and the DSG voltage generated by the voltage generator 310.

[0060] The voltage generator 310 can be configured to be controlled by the control logic 312 and generate various word line voltages (e.g., erase voltage, read voltage, program voltage, pass voltage, verification voltage), SSG voltage (e.g., select / deselect voltage), DSG voltage (e.g., select / deselect voltage), bit line voltage (e.g., ground voltage) and source line voltage (e.g., ground voltage) to be provided to the memory cell array 101.

[0061] The control logic 312 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 314 may be coupled to the control logic 312 and include a status register, a command register, and an address register to store status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0062] In some cases, control logic 312 may receive a request from a memory controller (e.g., Fig.25 and Figures 26A-26B The memory controller 3000 in the embodiment of the present invention receives an erase command issued by the memory controller 3000, and sends control signals to various peripheral circuits such as the row decoder / word line driver 308, the column decoder / bit line driver 306 and the voltage generator 310 to initiate an erase operation on the memory cells 106 coupled to both the selected word line 118 and the unselected word lines 118.

[0063] Similarly, in some cases, control logic 312 may receive a signal from a memory controller (e.g., Fig.25 and Figures 26A-26B The memory controller 3000 in the memory controller 3000 receives a program command and sends control signals to various peripheral circuits such as the row decoder / word line driver 308, the column decoder / bit line driver 306 and the voltage generator 310 to initiate a programming operation on the memory cell 106 coupled to the selected word line 118.

[0064] Interface 316 may be coupled to control logic 312 and act as a control buffer to buffer data received from a memory controller (eg, Fig.25 and Figures 26A-26B The interface 316 receives control commands from the memory controller 3000 in the memory cell array 101 and forwards them to the control logic 312, and buffers the status information received from the control logic 312 and forwards it to the memory controller. The interface 316 can also be coupled to the column decoder / bit line driver 306 via the data bus 318, and acts as a data input / output (I / O) interface and data buffer, thereby buffering and forwarding data to and from the memory cell array 101.

[0065] Figure 4 A flow chart of an exemplary process 400 for performing a toggle erase operation according to some aspects of the present disclosure is shown. The process 400 may be implemented by one or more computer programs installed in one or more computers located in one or more locations and programmed according to the present disclosure. For example, the process 400 may be implemented by Figure 1 For convenience, process 400 is described as being performed by a memory system including a memory device (e.g., memory device 100). The memory device includes a memory cell array and peripheral circuits (e.g., memory cell array 101 and peripheral circuits 102). The peripheral circuits include control logic of the memory device (e.g., Figure 3 In some implementations, some or all of the operations in the exemplary process 400 may be based on a relationship Figure 1-3 and Figure 5-12 The operations shown in process 400 may not be exclusive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Figure 4 Executed in the order shown.

[0066] The memory system selects a portion of the memory cell array (402) to, for example, perform a toggle erase operation. In some embodiments, this selection may be due to some signal and / or command issued by control logic in the peripheral circuitry of the memory device and / or the memory controller. In some embodiments, this selection may be due to a surpassing threshold number of unrecoverable read errors or a certain number of read retries of data reads from the memory device. In some embodiments, this selection may be due to some other indication of unreliability or wear in the memory device.

[0067] In general, the memory system can select any portion of the memory cell array to perform the switching erase operation. In some cases, the memory system can select the memory cells of a block included in the plurality of blocks included in the memory array. In some cases, the memory system can select the memory cells of a half block, which includes a portion of each page of a block, for example, half (e.g., the upper half or the lower half) or another number of pages of a block in the plurality of blocks included in the memory array. In other cases, the memory system can select a sub-block, which includes any portion of each page of a block, for example, a quarter block.

[0068] The portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode. For example, the first storage mode may be a QLC mode, wherein the memory cells store two bits of data per cell, and the second storage mode may be an SLC mode, wherein the memory cells store a single bit of data per cell. More generally, the first storage mode may be an MLC mode, wherein the memory cells store two, three, four or more bits of data per cell. Each storage mode corresponds to a corresponding erase operation and programming operation. For example, the first storage mode corresponds to a first erase operation, and the second storage mode corresponds to a second erase operation. The difference between the first erase operation and the second erase operation lies at least in the voltage value of the erase voltage pulse, i.e., the amplitude of the erase voltage pulse.

[0069] Figure 5 2 shows waveform diagrams of different erase operations in different storage modes according to some aspects of the present disclosure. Figure 5 As shown in the bottom half of , an erase operation corresponding to the QLC mode may use an erase voltage pulse having a higher voltage value (QLCVERASE), while an erase operation corresponding to the SLC mode may use an erase voltage pulse having a lower voltage value (SLCVERASE).

[0070] Re-reference Figure 4, the memory system performs a switching erase operation, thereby switching the portion of the memory array from the first storage mode to the switched second storage mode (404). The switched second storage mode has the same storage density as the second storage mode, but different erase operations and / or programming operations may be required in the switched second storage mode. For example, in an example where the second storage mode is the SLC mode, the switched second storage mode is the switched SLC mode. Similar to the conventional SLC mode, the switched SLC mode stores only one bit of data per cell. However, the erase operation in the switched SLC mode may have a voltage different from the erase operation in the conventional SLC mode, while the programming operation in the switched SLC mode may have the same voltage as the programming operation in the conventional SLC mode. In other words, after the switching erase operation, the memory system will continue to program and access the selected portion of the memory array as if the portion was in the second storage mode (even if the portion was in the first storage mode with a higher storage density in step 402), by using erase operations and programming operations corresponding to the switched SLC mode to store only one bit of data per cell, rather than blindly reusing the same erase operations and programming operations corresponding to the conventional SLC mode.

[0071] In some embodiments, the switching erase operation is different from both a conventional erase operation corresponding to the first storage mode (e.g., QLC mode) and a conventional erase operation corresponding to the second storage mode (e.g., SLC mode). In other words, in order to program and access the selected portion of the memory array as if it were in the second storage mode instead of the first storage mode, the selected portion of the memory array is erased by a switching erase operation that is different from both an erase operation corresponding to the first storage mode and an erase operation corresponding to the second storage mode.

[0072] like Figure 5 As shown in the bottom half of FIG. 1 , a toggle erase operation may use an erase voltage pulse having a voltage value (toggle VERASE) that is lower than the QLC erase voltage value (QLCVERASE) but higher than the SLC erase voltage value (SLC VERASE), all relative to the same bias voltage (vbiaslv) on the word line. Figure 5 The three voltage pulses are shown as having different pulse lengths, ie, having different durations, but in some embodiments, this is not required. In fact, in some embodiments, two or more of the three erase voltage pulses may have the same duration.

[0073] Re-reference Figure 4In some cases, after the portion of the memory array is switched to the switched second storage mode, the memory system performs a programming operation on the portion of the memory array in the switched second storage mode (406). The programming operation can be the same as a regular programming operation that the memory system would perform on any portion of the memory array in the second storage mode (e.g., SLC mode). In other words, once the memory system has performed steps 402-404 to switch the portion of the memory array from the first storage mode to the switched second storage mode, the memory system can continue to program and access the portion of the memory array as if it were in the second storage mode by using regular programming operations corresponding to the second storage mode.

[0074] In some cases, the memory system again performs a switching erase operation on the portion of the memory array in the switched second storage mode (408). The switching erase operation can be the same as the switching erase operation performed in step 404, and in particular, the same switching erase voltage value can be used. Unlike the case where the programming operation can be the same as the conventional programming operation corresponding to the second storage mode, once switched to the switched second storage mode, the erase operation to be performed on the portion of the memory array will generally be different from the conventional second erase operation corresponding to the second storage mode.

[0075] In some cases, the memory system can switch the portion of the memory array from the switched second storage mode back to the first storage mode. To do so, in some cases, the memory system performs a first erase operation on the portion of the memory array, thereby switching from the switched second storage mode back to the first storage mode (410). The first erase operation is a regular first erase operation corresponding to the first storage mode. Doing so switches the portion of the memory array back to the original storage mode it was in before step 402 was performed. In other words, performing a regular first erase operation (rather than a switched erase operation) to erase the portion of the memory array enables the memory system to continue to program and access the portion of the memory array using program and erase operations corresponding to the first storage mode.

[0076] Figure 6 Execution of a block of a memory device according to some aspects of the present disclosure is shown. Figure 4 6. The block may include one or more pages of memory cells. At 602, the block begins to be programmed in the QLC mode (referred to as a "QLC programmed block" or in a "QLC programmed state"). At 604, a switching erase operation is performed on the block, thereby erasing the block and entering an SLC erased state that mimics the erased state of the conventional SLC mode, which prepares the block to be later programmed according to the SLC mode. As shown in FIG. Figure 4 As discussed, performing a toggle erase operation includes using a specially designed toggle erase voltage (eg, toggle VERASE) to prevent over-erasing the memory cell and later causing the memory cell to undershoot relative to its intended threshold voltage even after multiple programming pulses in SLC mode.

[0077] After the switching erase operation, in 606, the block is erased and is in an SLC erased state (referred to as an SLC erased block) having characteristics similar to the erased state in the conventional SLC mode (e.g., including threshold voltage characteristics and ESUM characteristics). In addition, the block is now switched from the QLC mode to the switched SLC mode, so that the memory cells in the block have a lower storage density than in the QLC mode. In 608, an SLC programming operation is performed on the block (e.g., a selected page thereof). The SLC programming operation may use a conventional programming voltage value corresponding to a conventional programming operation of the SLC mode in the memory device. After the SLC programming operation, in 610, the block is programmed according to the SLC mode. The block is in the SLC mode (treated as if it is in the SLC mode). The block may be further erased by the switching erase operation, and may be programmed by the SLC programming operation in the switching SLC mode.

[0078] Figure 7 Execution of a block of a memory device according to some aspects of the present disclosure is shown. Figure 4 Another exemplary technique of a switching erase operation of the block. The block may include one or more pages of memory cells. In 702, the block begins to be programmed in the QLC programming mode. In 704, a switching erase operation is performed on the block, thereby erasing the block and causing the block to switch from the QLC mode to the switched SLC mode. From 704 to 716, the block can now be programmed and accessed as if the block is in the SLC mode. Specifically, in 706, an SLC programming operation is performed to program the block. The SLC programming operation can use a programming voltage value corresponding to a conventional programming operation of the SLC mode in the memory device. In 708, a switching erase operation is performed to erase the block that was programmed using the SLC programming operation performed in 706. In 710 and 712, another iteration of the SLC programming operation and the switching erase operation can be performed. In 714, the erased block is in the SLC mode (treated as if it is in the SLC mode). To erase the block, and in particular to switch the mode of the block from the SLC mode back to the QLC mode, in 716, a conventional QLC erase operation corresponding to the QLC mode in the memory device is performed (rather than a switching erase operation).

[0079] Returning to 702 where the block begins being programmed in the QLC mode, in 718, assuming a conventional QLC erase operation is performed, the block will be erased and remain in the QLC mode. In other words, after both 716 and 718, the block will become an erased block in the QLC mode. Thus, in 720, a QLC programming operation may be performed on the block, thereby programming the block. Following the QLC programming operation, in step 722, a QLC erase operation may be performed on the block, thereby erasing the block according to the QLC mode. In 720 and 722, the QLC programming operation and the QLC erase operation may use programming voltage values ​​and erase voltage values, respectively, corresponding to conventional programming operations and erase operations of the QLC mode in the memory device.

[0080] Figure 8 Execution of a half block of a memory device according to some aspects of the present disclosure is shown. Figure 4 An exemplary technique for switching erase operations of the memory device. The half block may include a portion of a memory cell of a block of the memory device. Figure 8 In the example of , the half block is the upper half of the block, but in other examples, the half block can alternatively be the lower half of the block or be at another position within the block. In 802A and 802B, the block including its upper half block and lower half block begins to be programmed in the QLC programming mode. In 804, a switching erase operation is performed on the upper half block to erase the upper half block. In some embodiments, this operation is completed by allowing the word lines of the unselected lower half of the block to float while applying the switching bias voltage of the switching erase operation to the word lines of the selected upper half of the block. Since the word lines of the unselected lower half of the block remain floating, the word line voltage level is pulled up, so that the memory cells in the unselected lower half of the block are not erased.

[0081] After the switch erase operation, in 806A, the upper half of the block is erased and is now in SLC mode. In contrast, in 806B, the lower half of the block is still programmed in QLC mode (unchanged from 802B). In 808, an SLC programming operation is performed on the upper half of the block, thereby programming the upper half of the block. The SLC programming operation can use programming voltage values ​​corresponding to conventional programming operations of the SLC mode in the memory device. After the SLC programming operation, in 810A, the upper half of the block that was in SLC mode (treated as if it was in SLC mode) is now programmed. In 810B, the lower half of the block is still programmed in QLC mode (unchanged from 802B).

[0082] Fig. 9 Execution of a half block according to some aspects of the present disclosure is shown. Figure 4Another exemplary technique for switching erase operations of the memory device is shown in FIG. 1 . The half block may include half of the memory cells of a block of the memory device. Fig. 9 In the example of , the half block is the upper half of the block (including the dummy word line), but in other examples, the half block may alternatively be the lower half of the block or be at another location within the block.

[0083] In 902A and 902B, a block including its upper half block and lower half block begins to be programmed in QLC mode. In 903, a switching erase operation is performed on the upper half block to erase the upper half block. After the switching erase operation, in 904A, the upper half of the block is erased and is now in SLC mode. In 905, an SLC programming operation is performed on the upper half block to program the upper half block. After the SLC programming operation, in 906A, the upper half of the block, which is now in SLC mode (treated as if in SLC mode), is programmed according to the SLC mode. In 907, a QLC erase operation is performed on the upper half block to erase the upper half block. After the QLC erase operation, in 908A, the upper half of the block is erased. In addition, since a conventional QLC erase operation is performed instead of a switching erase operation, the upper half of the block is switched back from SLC mode to QLC mode. In 909, a QLC programming operation is performed on the upper half of the block in the QLC mode, thereby programming the upper half of the block. After the QLC programming operation, in 910A, the upper half of the block is programmed and in the QLC mode.

[0084] In contrast, the lower half of the block is not affected by the operations in 903, 905, 907 and 909, and thus 904B, 906B, 908B to 910B remain programmed in the QLC mode (no change compared to 902B). Accordingly, the threshold voltage distribution of the lower half of the block is not changed.

[0085] Re-reference Figure 4 In some embodiments, each erase operation uses a single erase voltage pulse, while in other embodiments, each erase operation can use a sequence of multiple erase voltage pulses. The sequence of erase voltage pulses can have increasing values, starting with an initial pulse having an initial erase voltage value. Thus, if a sequence of multiple erase voltage pulses is used, the switching erase operation can differ from the first and second erase operations in the first and second modes, and they differ in at least the initial voltage value of their respective initial erase voltage pulses in the sequence.

[0086] The memory system can perform a switching erase operation by applying an effective switching erase voltage that is lower than a first effective erase voltage of a first erase operation corresponding to a first storage mode. In some embodiments, the effective switching erase voltage is also higher than a second effective erase voltage of a second erase operation corresponding to a second storage mode.

[0087] In some embodiments, the memory system can perform a switching erase operation in any of at least two different ways, for example, according to P-well erase or gate-induced drain leakage (GIDL) erase.

[0088] As an example, the erase operation may be a P-well erase operation, such as Figure 5 As shown in . For a first erase operation (corresponding to a first storage mode), the memory system applies a first effective erase voltage by, for example, applying a first bias voltage (vbiaslv) on a word line (e.g., a word line of a selected block) and applying a first erase voltage in a P-well in a substrate. Therefore, the first effective erase voltage is the difference between the first erase voltage applied to the P-well and the first bias voltage applied to the word line. In contrast, for a second switching erase operation, the memory system applies an effective switching erase voltage by, for example, applying a switching bias voltage on the word line row and applying a switching erase voltage on the P-well in a substrate. Accordingly, the effective switching erase voltage is the difference between the switching erase voltage on the P-well and the switching bias voltage on the word line. Different implementations may be used to make the effective switching erase voltage lower than the first effective erase voltage.

[0089] As an exemplary embodiment of making the effective switching erase voltage lower than the first effective erase voltage, the first bias voltage and the switching bias voltage may have the same value, while the switching erase voltage value is set to be lower than the first erase voltage value (e.g., Figure 5 When a lower switching erase voltage is applied to the selected block, its effective erase voltage is correspondingly reduced, thereby reducing the erase stress on the memory cells of the selected block.

[0090] As another exemplary embodiment of making the effective switching erase voltage lower than the first effective erase voltage, the first erase voltage and the switching erase voltage can have the same value, while the switching bias voltage value is set to be higher than the first bias voltage value. When the higher switching bias voltage is applied to the word line, its effective erase voltage is effectively reduced, thereby similarly reducing the erase stress on the memory cells of the selected block. For example, in MLC mode, the same bias voltage is applied to the pseudo word line and the core word line, while in SLC mode, the pseudo word line is set to float. In this exemplary embodiment, although the first erase voltage and the switching erase voltage have the same value, the bias voltage on the pseudo word line is set to be higher than the bias voltage on the core word line, thereby achieving light erase.

[0091] Other implementations may be used to make the effective switched erase voltage lower than the first effective erase voltage.

[0092] In some implementations, the memory system can apply different switching bias voltage values ​​to different word lines of the block. Fig.10 Waveform diagrams of different bias voltage values ​​and erase voltage values ​​for erase operations and switched erase operations according to some aspects of the present disclosure are shown. As shown, the memory system can apply a first switching bias voltage (Vbiaslv1) on a pseudo word line (on the upper half of the block or the lower half of the block) of a block in SLC mode, and can apply a second switching bias voltage (Vbiaslv2) on a core word line in the block. The first switching bias voltage (Vbiaslv1) applied to the pseudo word line is higher than the second switching bias voltage (Vbiaslv2) applied to the core word line. The switching bias voltage (Vbiaslv2) applied to the QLC core word line can be the same or different (e.g., higher) than the switching bias voltage (Vbiaslv3) applied to the TLC core word line, and both are lower than the first switching bias voltage (Vbiaslv1) on the pseudo word line in the block.

[0093] In addition, in some embodiments, the switching bias voltages applied to different pseudo word lines in the block may have different values. In some embodiments, the switching bias voltage applied to the pseudo word lines in the upper half of a block is higher than the switching bias voltage applied to the pseudo word lines in the lower half of the block.

[0094] Fig.11 2 shows exemplary threshold voltage distributions for memory cells in QLC and SLC modes, respectively, according to some aspects of the present disclosure. Fig.11In the top half of the , a first threshold voltage distribution of the portion of memory cells is shown (e.g., before a switching erase voltage is applied to the portion of the memory array). The memory cells of the portion are in a QLC mode including sixteen voltage states. The sum of the intervals between the sixteen voltage states is ESUM (sum of voltage state intervals). The first threshold voltage distribution includes the distribution of the sixteen voltage states and the corresponding ESUM characteristics of the sixteen voltage states. In some embodiments, in order to ensure that the memory device meets reliability requirements, it is desirable to keep each of the sixteen voltage states within a small range, and further ensure that the sum of the sixteen voltage distribution intervals is large enough, that is, to ensure that the ESUM is large enough to distinguish the sixteen voltage states. Fig.11 An example is shown in which the portion of memory cells is in a QLC mode including sixteen voltage states, but more generally, the portion of memory cells may be in an MLC mode including four or more voltage states.

[0095] exist Fig.11 In the bottom half of the diagram, a second threshold voltage distribution of the memory cells of the portion is shown (e.g., after a switching erase voltage is applied to the memory cells of the portion). The memory cells of the portion are in an SLC mode including two voltage states. The second threshold voltage distribution includes a distribution of the two voltage states and corresponding ESUM characteristics of the two voltage states. In some embodiments, in order to ensure that the memory device meets reliability requirements, it is desirable to maintain the threshold voltage distribution in the switched SLC mode (including the two voltage states and the ESUM (sum of voltage state intervals) of the two voltage states) similar to the threshold voltage distribution in the conventional SLC mode. In some embodiments, by performing a switching erase operation on the memory cells of the portion, the threshold voltage distribution of the switched SLC mode is more similar to the threshold voltage distribution of the conventional SLC mode (compared to the threshold voltage distribution that would be obtained if a conventional QLC erase operation were performed). In some embodiments, the erase depth or level of the switching erase operation is higher than the erase depth or level of the conventional QLC erase operation. Accordingly, the threshold voltage of the memory cells of the portion of the memory array after performing the switching erase operation will be higher than the threshold voltage of the memory cells of the portion of the memory array after performing the conventional QLC erase operation, thereby achieving lighter erase. For example, the threshold voltage of the memory cells of the portion of the memory array after performing the switching erase operation may be -1v, while the threshold voltage of the memory cells of the portion of the memory array after performing the conventional QLC erase operation may be -2v.

[0096] In some embodiments, the value of the effective switching erase voltage is generally configured to be close to or mimic the erased state of the second storage mode having the second threshold voltage distribution. Thus, the effective switching erase voltage allows the threshold voltage of the memory cell to be more effectively changed to the expected erased state of the second storage mode. The second storage mode facilitates the subsequent programming operation of the portion of memory cells according to the second storage mode.

[0097] Fig.12 Exemplary waveform diagrams of different bias voltage values ​​and erase voltage values ​​for an erase operation and a toggle erase operation performed on a portion of a block (eg, half a block) according to some aspects of the present disclosure are shown. Fig.12 In the example of , the half block is the upper half of the page constituting the block, but in other examples, the half block may alternatively be the lower half of the page constituting the block. As shown, the memory system may apply a first switching bias voltage (Vbiaslv1) to the pseudo word line in the upper half of the block in the SLC mode, a second switching bias voltage (Vbiaslv2) to the core word line (also referred to as QLC WL) in the upper half of the block in the QLC mode, and a third switching bias voltage (Vbiaslv3) to the core word line (also referred to as TLC WL) in the upper half of the block in the TLC mode. The first switching bias voltage (Vbiaslv1) applied to the top pseudo word line is higher than the second switching bias voltage (Vbiaslv2) applied to the core QLC word line, and the second switching bias voltage (Vbiaslv2) is higher than the third switching bias voltage (Vbiaslv3) applied to the core TLC word line. At the same time, the word lines of the unselected lower half of the block (including the dummy word lines, core QLC word lines, and core TLC word lines in the lower half of the block) remain floating.

[0098] Re-reference Figure 4 , in some embodiments, the erase operation may be a GIDL erase operation. Different from the P-well erase operation in which an erase voltage is applied to the P-well, under the GIDL erase operation, for a first erase operation (corresponding to a first storage mode), the memory system applies a first effective erase voltage for the first erase operation (corresponding to a first storage mode) by applying a first bias voltage (vbiaslv) to a word line of a selected block and applying a first erase voltage to a source line and / or a bit line of a selected block. In contrast, for a switching erase operation, in some embodiments, the memory system applies an effective switching erase voltage by applying a switching bias voltage to a word line of a selected block and applying a switching erase voltage to a source line and / or a bit line of a selected block.

[0099] Similar to the P-well erase operation, in some of these embodiments, although the first bias voltage and the switching bias voltage may have the same value, the switching erase voltage value will be lower than the first erase voltage value. When a lower switching erase voltage is applied to the source line and / or bit line of the selected block, its effective erase voltage is correspondingly reduced, thereby reducing the erase stress on the memory cell of the selected block. In other embodiments of these embodiments, although the first erase voltage and the switching erase voltage may have the same value, the switching bias voltage value will be higher than the first bias voltage value. When a higher switching bias voltage is applied to the word line of the selected block, its effective erase voltage is effectively reduced, thereby similarly reducing the erase stress on the memory cell of the selected block. In these embodiments, the voltages applied to the word line and the pseudo word line may be similar to those applied in the P-well erase operation, as discussed above. Similarly, other embodiments may be used to make the effective switching erase voltage lower than the first effective erase voltage.

[0100] Fig.13 A flowchart of an exemplary process 1300 for performing a switching programming operation according to some aspects of the present disclosure is shown. The process 1300 may be implemented by one or more computer programs installed in one or more computers located in one or more locations and programmed according to the present disclosure. For example, the process 1300 may be implemented by Figure 1 For convenience, process 1300 is described as being performed by a memory system including a memory device (e.g., memory device 100). The memory device includes a memory cell array and peripheral circuits (e.g., memory cell array 101 and peripheral circuits 102). The peripheral circuits include control logic for the memory device. In some embodiments, some or all of the operations in exemplary process 1300 may be based on a connection Figure 1-3 and Figure 14-24 The operations shown in process 1300 may not be exclusive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Fig.13 Executed in the order shown.

[0101] The memory system selects a portion (1302) of a memory cell array to, for example, perform a switching programming operation. In some embodiments, this selection may be attributed to some signal and / or command issued by control logic in the peripheral circuitry and / or memory controller of the memory device. In some embodiments, this selection may be attributed to an over-threshold number of unrecoverable read errors or a certain number of read retries of data reads from the memory device. In some embodiments, this selection may be attributed to some other indication of unreliability or loss in the memory device. In general, the memory system may select any portion of the memory cell array to perform a switching programming operation. For example, the memory system may select any word line of memory cells contained in a block in the memory array. For example, the memory system may select a pseudo word line or a core word line (e.g., a QLC word line, a TLC word line, etc.).

[0102] The portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode. For example, the first storage mode may be a QLC mode, wherein the memory cells store two bits of data per cell, and the second storage mode may be an SLC mode, wherein the memory cells store a single bit of data per cell. More generally, the first storage mode may be an MLC mode, wherein the memory cells store two, three, four or more bits of data per cell. Each storage mode corresponds to a corresponding programming operation and an erase operation. For example, the first storage mode corresponds to a first programming operation using a first programming voltage value and the second storage mode corresponds to a second programming operation using a second programming voltage value. The difference between the first programming operation and the second programming operation lies at least in the voltage value of the programming voltage pulse, i.e., the amplitude of the programming voltage pulse.

[0103] Fig.14 1 shows waveform diagrams of different programming operations in different storage modes according to some aspects of the present disclosure. Fig.14 As shown in , a program operation corresponding to the QLC mode may use a program voltage pulse having a higher voltage value (QLC Vpgm), while a program operation corresponding to the SLC mode may use a program voltage pulse having a lower voltage value (SLC Vpgm).

[0104] The memory system performs a switching programming operation, thereby switching the portion of the memory array from the first storage mode to the switched second storage mode (1304). The switched second storage mode has the same storage density as the second storage mode, but different programming operations and / or erasing operations may be required in the switched second storage mode. For example, in the case where the second storage mode is the SLC mode, the switched second storage mode is the switched SLC mode. Similar to the conventional SLC mode, the switched SLC mode stores only one bit of data per cell. However, the programming operation in the switched SLC mode may have a voltage different from the programming operation in the conventional SLC mode, and the erasing operation in the switched SLC mode may have the same voltage as the erasing operation in the conventional SLC mode. In other words, after the switching programming operation, the memory system will continue to access and erase the selected portion of the memory array as if the portion was in the second storage mode (even if the portion was in the first storage mode with a higher storage density in step 1302), by using the erase operation and programming operation corresponding to the switched SLC mode to store only one bit of data per cell, rather than blindly reusing the same erase operation and programming operation corresponding to the conventional SLC mode.

[0105] In some embodiments, the switching programming operation is different from both the conventional programming operation corresponding to the first storage mode (e.g., QLC mode) and the conventional programming operation corresponding to the second storage mode (e.g., SLC mode). That is, in order to access and erase the selected portion of the memory array as if it were in the second storage mode rather than the first storage mode, the selected portion of the memory array is programmed by a switching programming operation that is different from both the programming operation corresponding to the first storage mode and the programming operation corresponding to the second storage mode. In the case where the selected portion of the memory array is located on a dummy word line, the switching programming operation can use a switching programming voltage that is higher than the second programming voltage value, and in some embodiments, the switching programming voltage value is also lower than the first programming voltage.

[0106] like Fig.14 As shown in , the switching program operation may use a program voltage pulse having a voltage value (switching Vpgm) that is lower than the QLC program voltage value (QLC Vpgm) but higher than the SLC program voltage value (SLC Vpgm). Fig.14 The three voltage pulses are shown as having different pulse lengths, ie, having different durations, but this is not required. In fact, in some embodiments, two or more of the three programming voltage pulses may have the same duration.

[0107] In some cases, the memory system performs an erase operation on the portion of the memory array in the switched second storage mode (1306). The erase operation can be the same as a regular erase operation that the memory system would perform on any portion of the memory array in the second storage mode (e.g., SLC mode). In other words, once the memory system has performed steps 1302-1304, thereby switching the portion of the memory array from the first storage mode to the switched second storage mode, the memory system can continue to access and erase the portion of the memory array by using regular erase operations corresponding to the second storage mode, as if it were in the second storage mode.

[0108] In some cases, the memory system again performs a switching programming operation on the portion of the memory array in the switched second storage mode (1308). The switching programming operation can be the same as the switching programming operation performed in step 1304, and in particular, the same switching programming voltage value can be used. Unlike the case where the erase operation can be the same as the conventional erase operation corresponding to the second storage mode, once switched to the switched second storage mode, the programming operation to be performed on the portion of the memory array will generally be different from the conventional second programming operation corresponding to the conventional second storage mode.

[0109] Fig.15 Execution of a block of a memory device according to some aspects of the present disclosure is shown. Fig.13 1502, the block begins to be erased in QLC mode. In 1504, a switching programming operation is performed on the block, thereby programming selected pages in the block and entering an SLC programming state that approximates or mimics a programming state of a conventional SLC mode, which prepares the block to be later erased according to the SLC mode. As similarly discussed above, performing a switching programming operation includes using a specially designed switching programming voltage (e.g., switching Vpgm) to avoid under-programming memory cells.

[0110] After the switching programming operation, in 1506, the selected pages in the block are programmed and are in an SLC programming state having characteristics similar to the programming state in the conventional SLC mode (e.g., including threshold voltage characteristics and ESUM characteristics) (referred to as an SLC programmed block). In addition, the block is now switched from the QLC mode to the switched SLC mode, so that the memory cells in the block have a lower storage density than in the QLC mode. In 1508, an SLC erase operation is performed on the block. The SLC erase operation can use a default erase voltage value for a conventional erase operation corresponding to the SLC mode in the memory device. After the SLC erase operation, in 1510, the block is erased according to the SLC mode. The block is in the SLC mode (treated as if it is in the SLC mode). In 1512, an SLC programming operation corresponding to the SLC mode in the memory device (rather than a switching erase operation) is performed to program the selected pages in the block. Here, the selected page in the block may be the same or different from the page in the block that was programmed in 1506 using a switching programming operation. After the SLC programming operation, in 1514, the selected page in the block is programmed. In addition, the block is now switched from QLC mode to SLC mode. In 1516, a QLC erase operation is performed on the block. The QLC erase operation may use an erase voltage value corresponding to a conventional erase operation of the QLC mode in the memory device. After the QLC erase operation, in 1518, the block is erased. The block continues to be in QLC mode.

[0111] Fig.16 Execution of a block of a memory device according to some aspects of the present disclosure is shown. Fig.13Another exemplary technique for a switching programming operation of the block. The block may include one or more pages of memory cells. The switching programming operation may be performed on any page in the block. In 1602, the block begins to be erased in QLC mode (referred to as a "QLC erase block" or in a "QLC erase state"). In 1604, a switching programming operation is performed on selected pages in the block, thereby programming the selected pages in the block and facilitating switching the block from QLC mode to switched SLC mode. From 1604 to 1616, the block can now be accessed and erased as if the block was in SLC mode. Specifically, in 1606, an SLC erase operation is performed to erase the block. The SLC erase operation may use an erase voltage value corresponding to a conventional erase operation of the SLC mode in the memory device. In 1608, a switching programming operation is performed to program the selected page in the block that was erased using the SLC erase operation performed in 1616. Another iteration of the SLC erase operation and the switch programming operation may be performed in 1610 and 1612. The block being programmed is in SLC mode (treated as if in SLC mode) in 1614. To erase the block, and in particular to switch the mode of the block from SLC mode back to QLC mode, a conventional QLC erase operation corresponding to the QLC mode in the memory device is performed in 1616.

[0112] Returning to 1602 where the block begins to be erased in QLC mode, in 1618, assuming that a conventional QLC programming operation is performed on selected pages in the block, the block remains in QLC mode while having programmed the selected pages in the block. In 1620, a conventional QLC erase operation is performed, thereby erasing the block according to the conventional QLC mode. The QLC erase operation may use an erase voltage value corresponding to a conventional erase operation of the QLC mode in the memory device. In other words, after both 1616 and 1620, the block will become an erased block in QLC mode. Thus, in 1622, a QLC programming operation may be performed on selected pages in the block, thereby programming the block. The QLC programming operation may use a programming voltage value corresponding to a conventional programming operation of the QLC mode in the memory device.

[0113] Fig.17 Execution of a half block of a memory device according to some aspects of the present disclosure is shown. Fig.13 An exemplary technique for switching programming operations of the memory device. The half block may include half of the memory cells of a block of the memory device. Fig.17In the example of , the half block is the upper half of the block, and the switching programming operation can be performed on any page in the upper half block, but in other examples, the half block can alternatively be the lower half of the block or be at another position within the block. In 1702A and 1702B, the block including its upper half block and lower half block begins to be erased in QLC erase mode. In 1704, the switching programming operation is performed on the upper half block, thereby programming the selected page in the upper half block. After the switching programming operation, in 1706A, the page in the upper half block is programmed and is now in SLC mode. In contrast, in 1706B, the lower half of the block is still erased in QLC mode (no change compared to 1702B). In 1708, an SLC erase operation is performed on the upper half block to erase the upper half block. The SLC erase operation can use a programming voltage value corresponding to a conventional erase operation of the SLC mode in the memory device. After the SLC erase operation, in 1710A, the upper half block that was in SLC mode (treated as if in SLC mode) is now erased. In 1710B, the lower half block is still erased in QLC mode (unchanged from 1702B).

[0114] Fig.18 Execution of a half block according to some aspects of the present disclosure is shown. Fig.13 Another exemplary technique for switching programming operations. The half block may include half of the memory cells of a block of the memory device. Fig.18 In the example of , the half block is the upper half of the block, and the switching programming operation can be performed on any page in the upper half of the block, but in other examples, the half block can alternatively be the lower half of the block or be at another location within the block.

[0115] In 1802A and 1802B, a block including its upper half block and lower half block begins to be erased in QLC erase mode. In 1803, a switch programming operation is performed on the upper half block, thereby programming the selected word line in the upper half block. After the switch programming operation, in 1804A, the selected word line in the upper half block is programmed, and the upper half block is now in SLC mode. In 1805, an SLC erase operation is performed on the upper half block to erase the upper half block. After the SLC erase operation, in 1806A, the upper half of the block, which is now in SLC mode (treated as if in SLC mode), is erased according to the SLC mode. In 1807, an SLC programming operation is performed on the selected page in the upper half block, thereby programming the selected page in the upper half block. After the SLC programming operation, in 1808A, the selected page in the upper half block is programmed. In addition, since a normal SLC program operation is performed instead of a switching program operation, the upper half block is switched back from the SLC mode to the QLC mode. In 1809, a QLC erase operation is performed on the upper half block in the QLC mode, thereby erasing the upper half block. After the QLC erase operation, in 1810A, the upper half block is erased and is in the QLC mode.

[0116] In contrast, the lower half of the block is not affected by the operations in 1803, 1805, 1807 and 1809, and thus remains erased in QLC mode from 1804A, 1806B, 1808B to 1810B (unchanged compared to 1802B). Accordingly, the threshold voltage distribution of the lower half of the block is not changed.

[0117] Re-reference Fig.13 In some embodiments, each programming operation uses a single programming voltage pulse, while in other embodiments, each programming operation can use a sequence of multiple programming voltage pulses. The sequence of programming voltage pulses can have increasing values, starting with an initial pulse having an initial programming voltage value. Thus, if a sequence of multiple programming voltage pulses is used, the switching programming operation can differ from the first and second programming operations in the first and second modes, and they differ in at least the initial voltage value of their respective initial programming voltage pulses in the sequence.

[0118] In order to program (or write data to) a target memory cell, a programming voltage (Vpgm) may be applied to one or more selected word lines including the target memory cell, and thus to the control gate of each memory cell coupled to the selected word line. Given that the programming voltage is applied to the selected word line, a potential such as a ground potential (e.g., Vss) may be applied to the bit line and substrate (and thus to the channel between the source and the drain) of the memory cell locked as the programming target, thereby obtaining a charge transfer from the channel to the floating gate of the target memory cell. Similar to the effective erase voltage discussed above, the effective programming voltage is the difference between the programming voltage and the voltage of the potential.

[0119] At the same time, a pass voltage (Vpass) may be applied to one or more unselected word lines having memory cells that are not locked as programming targets, or an inhibit voltage (e.g., Vcc) may be applied to bit lines having memory cells that are not locked as programming targets, thereby (e.g.) inhibiting charge transfer from the channel to the floating gate of such non-target memory cells. The pass voltage may be variable, depending on (e.g.) the proximity of the applied pass voltage to the word lines that are locked as programming targets. The inhibit voltage may include a power supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external power supply or an external power supply device (e.g., a battery, an AC to AC converter, etc.).

[0120] Fig.19 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation. Fig.19 In the example of , the target memory cells are in SLC mode; these target memory cells are located on selected pseudo word lines among blocks in the memory device. As shown in the figure, the memory system can apply a switching programming voltage (Vpgm_dmy) on the selected pseudo word line, a pass voltage (Vpass_qlc) on the unselected core QLC word line, and a pass voltage (Vpass_tlc) on the unselected core TLC word line. As shown in this example, the switching programming voltage (Vpgm_dmy) applied on the selected pseudo word line is higher than the pass voltage (Vpass_qlc) applied on the unselected core QLC word line, and the pass voltage (Vpass_qlc) applied on the unselected core QLC word line is higher than the pass voltage (Vpass_tlc) applied on the unselected core TLC word line.

[0121] Fig. 20 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation. Fig. 20In the example of , the target memory cells are in QLC mode; these target memory cells are located on a selected core word line among a block in a memory device. As shown in the figure, the memory system can apply a switching programming voltage (Vpgm_qlc) on the selected core word line, a pass voltage (Vpass_dmy) on an unselected pseudo word line, and a pass voltage (Vpass_tlc) on an unselected core TLC word line. As shown in this example, the switching programming voltage (Vpgm_qlc) applied on the selected core word line is higher than the pass voltage (Vpass_dmy) applied on the unselected pseudo SLC word line, and the pass voltage (Vpass_dmy) applied on the unselected pseudo SLC word line is higher than the pass voltage (Vpass_tlc) applied on the unselected core TLC word line.

[0122] Fig.21 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation. Fig.21 In the example of , the target memory cells are in TLC mode; these target memory cells are located on a selected core word line among a block in a memory device. As shown in the figure, the memory system can apply a switching programming voltage (Vpgm_tlc) on the selected core word line, a pass voltage (Vpass_dmy) on an unselected pseudo word line, and a pass voltage (Vpass_qlc) on an unselected core QLC word line. As shown in this example, the switching programming voltage (Vpgm_tlc) applied to the selected core word line is higher than the pass voltage (Vpass_dmy) applied to the unselected pseudo word line, and the pass voltage (Vpass_dmy) applied to the unselected pseudo word line is higher than the pass voltage (Vpass_qlc) applied to the unselected core QLC word line. In a typical embodiment, the switching programming voltage (Vpgm_dmy) applied to the selected pseudo word line has a lower value than the switching programming voltage (Vpgm_qlc or Vpgm_tlc) applied to the selected core word line.

[0123] Fig. 22 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation. Fig. 22In the example of , the target memory cells are in SLC mode; the target memory cells are located on a selected pseudo word line in the upper half block in the memory device. As shown, on the upper half block including the selected pseudo word line, the memory system can apply a switching programming voltage (Vpgm_dmy) on the selected pseudo word line, a pass voltage (Vpass_qlc) on the unselected core QLC word line, and a pass voltage (Vpass_tlc) on the unselected core TLC word line. As shown in this example, the switching programming voltage (Vpgm_dmy) applied on the selected pseudo word line is higher than the pass voltage (Vpass_qlc) applied on the unselected core QLC word line, and the pass voltage (Vpass_qlc) applied on the unselected core QLC word line is higher than the pass voltage (Vpass_tlc) applied on the unselected core TLC word line. In addition, on the lower half of the block not including the selected pseudo word line, the memory system may apply a pass voltage (Vpass_dmy) on the unselected pseudo word line, a pass voltage (Vpass_qlc) on the unselected core QLC word line, and a pass voltage (Vpass_tlc) on the unselected core TLC word line. As shown in this example, the pass voltage (Vpass_dmy) applied to the unselected pseudo word line is higher than the pass voltage (Vpass_qlc) applied to the unselected core QLC word line, which in turn is higher than the pass voltage (Vpass_tlc) applied to the unselected core TLC word line.

[0124] Fig.23 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation. Fig.23In the example of , the target memory cells are in QLC mode; the target memory cells are located on a selected core word line in the upper half block in the memory device. As shown, on the upper half block including the selected core word line, the memory system can apply a switching programming voltage (Vpgm_qlc) on the selected core word line, a pass voltage (Vpass_dmy) on an unselected pseudo word line, and a pass voltage (Vpass_tlc) on an unselected core TLC word line. As shown in this example, the pass voltage (Vpass_dmy) applied on the unselected pseudo word line is higher than the programming voltage (Vpgm_qlc) applied on the selected core QLC word line, which in turn is higher than the pass voltage (Vpass_tlc) applied on the unselected core TLC word line. In addition, on the lower half of the block not including the selected core word line, the memory system may apply a pass voltage (Vpass_dmy) on an unselected dummy word line, a pass voltage (Vpass_qlc) on an unselected core QLC word line, and a pass voltage (Vpass_tlc) on an unselected core TLC word line. As shown in this example, the pass voltage (Vpass_dmy) applied to the unselected dummy word line is higher than the pass voltage (Vpass_qlc) applied to the unselected core QLC word line, which in turn is higher than the pass voltage (Vpass_tlc) applied to the unselected core TLC word line.

[0125] Fig.24 According to some aspects of the present disclosure Fig.13 Other waveform diagrams of different programming voltages and pass voltages for the switching programming operation. Fig.24In the example of , the target memory cells are in TLC mode; the target memory cells are located on a selected core word line in the upper half block in the memory device. As shown, on the upper half block including the selected core word line, the memory system can apply a switching programming voltage (Vpgm_tlc) on the selected core word line, a pass voltage (Vpass_dmy) on an unselected pseudo word line, and a pass voltage (Vpass_qlc) on an unselected core QLC word line. As shown in this example, the switching programming voltage (Vpgm_tlc) applied on the selected core word line is higher than the pass voltage (Vpass_dmy) applied on the unselected pseudo word line, and the pass voltage (Vpass_dmy) applied on the unselected pseudo word line is higher than the pass voltage (Vpass_qlc) applied on the unselected QLC word line. In addition, on the lower half of the block not including the selected pseudo word line, the memory system may apply a pass voltage (Vpass_dmy) on the unselected pseudo word line, a pass voltage (Vpass_qlc) on the unselected core QLC word line, and a pass voltage (Vpass_tlc) on the unselected core TLC word line. As shown in this example, the pass voltage (Vpass_dmy) applied to the unselected pseudo word line is higher than the pass voltage (Vpass_qlc) applied to the unselected core QLC word line, which in turn is higher than the pass voltage (Vpass_tlc) applied to the unselected core TLC word line.

[0126] Fig.25 2500 includes one or more memory devices 2000 and a memory controller 3000. The one or more memory devices 2000 may operate in response to the control of the memory controller 3000. Figure 2-3 The structure of the memory device 2000 is described in more detail.

[0127] The memory device 2000 may receive commands, addresses, and data from the memory controller 3000. The memory device 2000 may perform operations corresponding to the commands on the regions selected according to the addresses received from the memory controller 3000. For example, the memory device 2000 may perform write operations (programming operations), read operations, and erase operations. During the programming operation, the memory device 2000 may program data into the regions selected according to the addresses. During the read operation, the memory device 2000 may read data from the regions selected according to the addresses. During the erase operation, the memory device 2000 may erase data stored in the regions selected according to the addresses.

[0128] The memory controller 3000 may be used to control the operation of the memory device 2000. For example, the memory controller 3000 may control the operation of the memory device 2000 in response to a request received from the host 4000. Of course, in some cases, the memory controller 3000 may also control the operation of the memory device 2000 without receiving a request from the host 4000.

[0129] For example, the memory controller 3000 may control the memory device 2000 to perform a program operation, a read operation, or an erase operation in response to a request from the host 4000. During a program operation, the memory controller 3000 may provide a program command, a physical address, and data to the memory device 2000. During a read operation, the memory controller 3000 may provide a read command and a physical address to the memory device 2000. During an erase operation, the memory controller 3000 may provide an erase command and a physical address to the memory device 2000.

[0130] In an example, the memory controller 3000 may generate a program command, address, and data and transfer them to the memory device 2000 without a request from the host 4000. For example, the memory controller 3000 may provide commands, addresses, and data to the memory device 2000 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0131] The host 4000 may be a processor of an electronic device, for example, a central processing unit (CPU) or a system on chip (SoC), for example, an application processor (AP). The host 4000 may be communicatively coupled to the memory system 2500 .

[0132] The memory device 2000 and the memory controller 3000 may be integrated into one semiconductor device. Exemplarily, the memory device 2000 and the memory controller 3000 may be integrated into a single semiconductor device to form a memory card. Exemplarily, the memory device 2000 and the memory controller 3000 may be integrated into a single semiconductor device to form a solid state drive (SSD). The SSD may include a memory system 2500 for storing data in the memory device 2000. When the memory system 2500 is used in the SSD, the operation rate of the host 4000 connected to the memory system 2500 may be significantly improved.

[0133] In an example, the memory system 2500 can be used as one of several elements of various electronic devices, for example, the electronic device can be: a computer, an ultra-portable computer, a workstation, a netbook, a personal digital assistant, a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player, a portable game console, a navigation system, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a wearable electronic device, a smart sensor, a virtual reality device, an augmented reality device, a device for sending / receiving information in a wireless environment, a device for a home network, a device for a computer network, a device for a telematics network, a radio frequency identification (RFID) device, or other electronic devices with a storage system, etc.

[0134] Fig.26A A diagram of an exemplary memory card having a memory device according to some aspects of the present disclosure is shown. Fig.26A As shown, the memory controller 3000 and the single memory device 2000 may be integrated into the memory card 1500. The memory card 1500 includes, but is not limited to, a PC (Personal Computer Memory Card International Association, referred to as PC) card, a CF (Compact Flash) card, a SM (Smart Media) card, a memory stick, an MMC (Multimedia Card), RS-MMC (Reduced Size MMC, Mini Multimedia Card), an MMCmicro (Micro Multimedia Card), an SD (Secure Digital Memory Card), a miniSD (Small Secure Digital Memory Card), a microSD (Micro Secure Digital Memory Card), an SDHC (Secure Digital High Capacity), and a UFS (Universal Flash Memory) card, etc. The memory card 1500 may also include a processor that enables the memory card 1500 to communicate with a host (e.g., Fig.25 A memory card connector 1510 coupled to a host 4000).

[0135] Fig.26B A diagram of an exemplary solid state drive (SSD) having a memory device according to some aspects of the present disclosure is shown. Fig.26B As shown, the memory controller 3000 and the plurality of memory devices 2000 may be integrated into the solid-state drive 1600. The solid-state drive 1600 may also include a processor that enables the solid-state drive 1600 to communicate with a host (eg, Fig.25 The solid-state drive connector 1610 is coupled to the host 4000 in the memory card 1500. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 1600 is higher than the storage capacity and / or operating speed of the memory card 1500.

[0136] The described examples of the subject matter may include one or more features alone or in combination.

[0137] According to one aspect of the present disclosure, a method for operating a memory device is disclosed. The method includes: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation; and performing a switching erase operation to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching erase operation, and wherein the switching erase operation is different from the first erase operation performed on the memory array in the first storage mode.

[0138] According to another aspect of the present disclosure, a memory device is disclosed. The memory device includes: a memory array; and a peripheral circuit coupled to the memory array and configured to perform an operation, the operation including: selecting a portion of the memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation using a first effective erase voltage; and performing a switching erase operation to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching erase operation, and after performing the switching erase operation, the threshold voltage of the memory cells of the portion of the memory array is higher than the threshold voltage of the memory cells of the portion of the memory array after performing the first erase operation.

[0139] According to another aspect of the present disclosure, one or more non-transitory computer-readable storage media are disclosed. The one or more non-transitory computer-readable storage media store instructions that, when executed by one or more machines, cause the one or more machines to perform operations, the operations comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation; and performing a switching erase operation to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching erase operation, and after performing the switching erase operation, the threshold voltage of the memory cells of the portion of the memory array is higher than the threshold voltage of the memory cells of the portion of the memory array after performing the first erase operation.

[0140] According to another aspect of the present disclosure, a memory system is disclosed. The memory system includes: a controller; a memory device including a memory array; and a peripheral circuit coupled to the memory array and configured to perform an operation, the operation including: selecting a portion of the memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation; and performing a switching erase operation to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching erase operation, and after performing the switching erase operation, the threshold voltage of the memory cells of the portion of the memory array is higher than the threshold voltage of the memory cells of the portion of the memory array after performing the first erase operation.

[0141] The foregoing examples and other examples may each optionally include one or more of the following features:

[0142] In some implementations, the memory array includes a three-dimensional NAND array.

[0143] In some embodiments, the switching erase operation differs from the first erase operation in at least a voltage value.

[0144] In some embodiments, performing the first erase operation includes applying a first effective erase voltage, and wherein performing the switching erase operation includes applying an effective switching erase voltage that is lower than the first effective erase voltage.

[0145] In some implementations, performing the switching erase operation includes performing the switching erase operation according to a P-well erase or a gate-induced drain leakage (GIDL) erase.

[0146] In some embodiments, a first erase operation and a switching erase operation are performed according to a P-well erase operation, and applying a first effective erase voltage includes applying a first bias voltage on a word line and applying a first erase voltage on the P-well, wherein applying the effective switching erase voltage includes applying a switching bias voltage on the word line and applying a switching erase voltage on the P-well, and wherein the switching erase voltage is lower than the first erase voltage.

[0147] In some embodiments, applying a switching bias voltage on a word line includes: applying a first switching bias voltage on a dummy word line; and applying a second switching bias voltage on a core word line, wherein the first switching bias voltage applied on the dummy word line is higher than the second switching bias voltage applied on the core word line.

[0148] In some embodiments, the first erase operation and the switching erase operation are performed according to a gate induced drain leakage (GIDL) erase operation. Applying a first effective erase voltage includes applying a first bias voltage on a word line and applying a first erase voltage on a source line and / or a bit line, wherein applying an effective switching erase voltage includes applying a switching bias voltage on the word line and applying a switching erase voltage on the source line and / or the bit line, and wherein the switching bias voltage is different from the first bias voltage.

[0149] In some implementations, applying the first effective erase voltage includes applying a first bias voltage on the word line, wherein applying the effective switched erase voltage includes applying a switched bias voltage on the word line, and wherein the switched bias voltage is different from the first bias voltage.

[0150] In some implementations, applying the first bias voltage on the word line includes applying the first bias voltage on a dummy word line, and wherein applying the switching bias voltage on the word line includes applying the switching bias voltage on the dummy word line.

[0151] In some implementations, the switching bias voltage on the dummy word line is higher than the first bias voltage applied to the dummy word line.

[0152] In some embodiments, the first storage mode is a multi-level cell (MLC) mode, and the second storage mode is a single-level cell (SLC) mode.

[0153] In some embodiments, performing the switching erase operation includes performing a switching erase operation from a first storage mode to a switched second storage mode on memory cells of one of a plurality of blocks included in a memory array.

[0154] In some embodiments, performing the switching erase operation includes performing the switching erase operation from the first storage mode to the switched second storage mode on memory cells of half of the blocks included in the plurality of blocks in the memory array.

[0155] In some embodiments, the first storage mode includes four or more voltage states corresponding to a first threshold voltage distribution; the second storage mode includes two voltage states corresponding to a second threshold voltage distribution; and the value of the switching erase voltage is configured to be close to an erase state of the second threshold voltage distribution after the switching erase voltage is applied to the portion of the memory array.

[0156] In some embodiments, the method further includes: performing a program operation on the portion of the memory array in the switched second storage mode; and performing the switching erase operation again on the portion of the memory array in the switched second storage mode.

[0157] In some embodiments, the method further includes performing a first erase operation on the portion of the memory array by applying a first effective erase voltage to switch from the switched second storage mode to the first storage mode.

[0158] According to another aspect of the present disclosure, a method for operating a memory device is disclosed. The method includes: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode, and the second storage mode corresponds to a second programming operation; and performing a switching programming operation to switch the portion of the memory array in the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching programming operation, and wherein the switching programming operation is different from the second programming operation of the second storage mode.

[0159] According to another aspect of the present disclosure, a memory device is disclosed. The memory device includes: a memory array; and a peripheral circuit coupled to the memory array and configured to perform an operation, the operation including: selecting a portion of the memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode, the first storage mode corresponds to a first programming operation and the second storage mode corresponds to a second programming operation; and performing a switching programming operation to switch the portion of the memory array in the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching programming operation, and wherein the switching programming operation is different from the second programming operation of the second storage mode.

[0160] According to another aspect of the present disclosure, one or more non-transitory computer-readable storage media are disclosed. The one or more non-transitory computer-readable storage media store instructions that, when executed by one or more machines, cause the one or more machines to perform operations, the operations comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode, the first storage mode corresponds to a first programming operation and the second storage mode corresponds to a second programming operation; and performing a switching programming operation to switch the portion of the memory array in the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching programming operation, and wherein the switching programming operation is different from the second programming operation of the second storage mode.

[0161] According to another aspect of the present disclosure, a memory system is disclosed. The memory system includes: a controller; a memory device including a memory array; and a peripheral circuit coupled to the memory array and configured to perform an operation, the operation including: selecting a portion of the memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein the second storage mode has a lower storage density than the first storage mode, the first storage mode corresponds to a first programming operation and the second storage mode corresponds to a second programming operation; and performing a switching programming operation to switch the portion of the memory array in the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching programming operation, and wherein the switching programming operation is different from the second programming operation of the second storage mode.

[0162] The foregoing examples and other examples can each optionally include one or more of the following features.

[0163] In some embodiments, the switch programming operation differs from the second programming operation at least in voltage.

[0164] In some embodiments, the second programming operation uses a second programming voltage, and wherein the toggle programming operation uses a toggle programming voltage that is higher than the second programming voltage.

[0165] In some embodiments, the first storage mode corresponds to a first programming operation, the first programming operation uses a first programming voltage, and the switching programming operation for the selected dummy word line uses a switching programming voltage lower than the first programming voltage.

[0166] In some embodiments, performing the switching programming operation includes: programming the core word line to the switched second storage mode; and programming the dummy word line to a designated voltage.

[0167] In some embodiments, performing a switching programming operation includes: applying a first switching programming voltage to a selected core word line; and applying a second switching programming voltage to a selected dummy word line, wherein the first switching programming voltage applied to the selected dummy word line is lower than the second switching programming voltage applied to the selected core word line.

[0168] In some implementations, performing a toggle programming operation includes applying a pass voltage value on an unselected word line.

[0169] In some embodiments, performing the switching programming operation includes: performing an erase operation on the portion of the memory array in the switched second storage mode; and performing the switching programming operation again on the portion of the memory array.

[0170] The description of the above specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teaching and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning and equivalents of the disclosed embodiments.

[0171] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. Accordingly, other embodiments are also within the scope of the claims.

Claims

1. A method for operating a memory device, comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein: The second storage mode has a lower storage density than the first storage mode, and The first storage mode corresponds to a first erase operation; and A switching erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching erase operation, and wherein the switching erase operation is different from the first erase operation performed on the memory array in the first storage mode.

2. The method according to claim 1, wherein: The switching erase operation is different from the first erase operation in at least a voltage value.

3. The method according to any one of claims 1 to 2, wherein: Performing the first erase operation includes applying a first effective erase voltage, and Wherein, performing the switching erase operation includes applying an effective switching erase voltage lower than the first effective erase voltage.

4. The method according to claim 3, wherein: Performing the switching erase operation includes performing the switching erase operation according to P-well erase or gate-induced drain leakage (GIDL) erase.

5. The method according to claim 3, wherein: performing the first erasing operation and the switching erasing operation according to a P-well erasing operation, Wherein, applying the first effective erase voltage includes applying a first bias voltage on the word line and applying a first erase voltage on the P well, Wherein, applying the effective switching erase voltage comprises applying a switching bias voltage on the word line and applying a switching erase voltage on the P well, and Wherein, the switching erase voltage is lower than the first erase voltage.

6. The method according to claim 5, wherein: Applying the switching bias voltage on the word line includes: applying a first switching bias voltage on the dummy word line; and A second switching bias voltage is applied to the core word line, wherein the first switching bias voltage applied to the dummy word line is higher than the second switching bias voltage applied to the core word line.

7. The method according to claim 3, wherein: performing the first erase operation and the switching erase operation according to a gate induced drain leakage (GIDL) erase operation, Wherein, applying the first effective erase voltage includes applying a first bias voltage on a word line and applying a first erase voltage on at least one of a source line or a bit line, wherein applying the effective switching erase voltage comprises applying a switching bias voltage on the word line and applying a switching erase voltage on at least one of the source line or the bit line, and The switching bias voltage is different from the first bias voltage.

8. The method according to claim 4, in, Applying the first effective erase voltage includes applying a first bias voltage on the word line, wherein applying the effective switching erase voltage comprises applying a switching bias voltage on the word line, and The switching bias voltage is different from the first bias voltage.

9. The method according to claim 8, wherein: Applying the first bias voltage on the word line includes applying the first bias voltage on a dummy word line, and wherein applying the switched bias voltage on the word line includes applying the switched bias voltage on the dummy word line.

10. The method according to claim 9, wherein: The switching bias voltage on the dummy word line is higher than the first bias voltage applied to the dummy word line.

11. The method according to any one of claims 1 to 10, wherein: The first storage mode is a multi-level cell (MLC) mode, and the second storage mode is a single-level cell (SLC) mode.

12. The method according to any one of claims 1 to 11, wherein: Performing the switching erase operation includes performing the switching erase operation from the first storage mode to the switched second storage mode on memory cells of one block among a plurality of blocks included in the memory array.

13. The method according to any one of claims 1 to 11, wherein: Performing the switching erase operation includes performing the switching erase operation from the first storage mode to the switched second storage mode on memory cells of half of a block among a plurality of blocks included in the memory array.

14. The method according to any one of claims 1 to 13, wherein: the first storage mode comprising four or more voltage states, the four or more voltage states corresponding to a first threshold voltage distribution; The second storage mode includes two voltage states corresponding to a second threshold voltage distribution; and The value of the switched erase voltage is configured to approximate an erased state of the second threshold voltage distribution after the switched erase voltage is applied to the portion of the memory array.

15. The method according to any one of claims 1 to 14, further comprising: performing a programming operation on the portion of the memory array in the switched second storage mode; as well as The switching erase operation is performed again on the portion of the memory array in the switched second storage mode.

16. The method according to any one of claims 1 to 15, further comprising: The first erasing operation is performed on the portion of the memory array by applying a first effective erasing voltage, thereby switching from the switched second storage mode to the first storage mode.

17. A memory device comprising: Memory array; as well as A peripheral circuit is coupled to the memory array and configured to perform operations, the operations comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein: The second storage mode has a lower storage density than the first storage mode, and The first storage mode corresponds to a first erase operation using a first effective erase voltage; and A switching erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching erase operation, and wherein, after performing the switching erase operation, a threshold voltage of memory cells of the portion of the memory array is higher than a threshold voltage of the memory cells of the portion of the memory array after performing the first erase operation.

18. The memory device of claim 17, wherein: The memory array includes a three-dimensional NAND array.

19. One or more non-transitory computer-readable storage media for storing instructions that, when executed by one or more machines, cause the one or more machines to perform operations comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein: The second storage mode has a lower storage density than the first storage mode, and The first storage mode corresponds to a first erase operation; and A switching erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching erase operation, and wherein, after performing the switching erase operation, a threshold voltage of memory cells of the portion of the memory array is higher than a threshold voltage of the memory cells of the portion of the memory array after performing the first erase operation.

20. A memory system comprising: Controller; A memory device including a memory array; as well as A peripheral circuit coupled to the memory array and configured to perform operations, the operations comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein: The second storage mode has a lower storage density than the first storage mode, and The first storage mode corresponds to a first erase operation; and A switching erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching erase operation, and wherein, after performing the switching erase operation, a threshold voltage of memory cells of the portion of the memory array is higher than a threshold voltage of the memory cells of the portion of the memory array after performing the first erase operation.

21. A method for operating a memory device, comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein: The second storage mode has a lower storage density than the first storage mode, and The second storage mode corresponds to a second programming operation; and A switching programming operation is performed to switch the portion of the memory array in the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching programming operation, and wherein the switching programming operation is different from the second programming operation of the second storage mode.

22. The method according to claim 21, wherein: The switching programming operation is different from the second programming operation at least in voltage.

23. The method according to any one of claims 21-22, wherein: The second programming operation uses a second programming voltage, and wherein the toggle programming operation uses a toggle programming voltage higher than the second programming voltage.

24. The method according to any one of claims 21 to 23, wherein: The first storage mode corresponds to a first programming operation, The first programming operation uses a first programming voltage, and The toggle programming operation for a selected dummy word line uses a toggle programming voltage that is lower than the first programming voltage.

25. The method according to any one of claims 21 to 24, wherein: Executing the switching programming operation includes: Programming the core word line to the switched second storage mode; and Program the dummy word line to a specified voltage.

26. The method according to any one of claims 21 to 25, wherein: Executing the switching programming operation includes: applying a first switched programming voltage to the selected core word line; and A second switching programming voltage is applied to a selected dummy word line, wherein the first switching programming voltage applied to the selected dummy word line is lower than the second switching programming voltage applied to the selected core word line.

27. The method of claim 26, further comprising applying a pass voltage value to unselected word lines.

28. The method according to any one of claims 21 to 27, further comprising: performing an erase operation on the portion of the memory array in the switched second storage mode; as well as The toggle programming operation is performed again on the portion of the memory array.

29. A memory device comprising: Memory array; as well as A peripheral circuit is coupled to the memory array and configured to perform operations, the operations comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein: the second storage mode has a lower storage density than the first storage mode, The first storage mode corresponds to a first programming operation, and The second storage mode corresponds to a second programming operation; and A switching programming operation is performed to switch the portion of the memory array in the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching programming operation, and wherein the switching programming operation is different from the second programming operation of the second storage mode.

30. One or more non-transitory computer-readable storage media for storing instructions that, when executed by one or more machines, cause the one or more machines to perform operations comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein: the second storage mode has a lower storage density than the first storage mode, The first storage mode corresponds to a first programming operation, and The second storage mode corresponds to a second programming operation; and A switching programming operation is performed to switch the portion of the memory array in the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching programming operation, and wherein the switching programming operation is different from the second programming operation of the second storage mode.

31. A memory system comprising: Controller; A memory device including a memory array; as well as A peripheral circuit coupled to the memory array and configured to perform operations, the operations comprising: selecting a portion of a memory array, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode, wherein: the second storage mode has a lower storage density than the first storage mode, The first storage mode corresponds to a first programming operation, and The second storage mode corresponds to a second programming operation; and A switching programming operation is performed to switch the portion of the memory array in the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switching programming operation, and wherein the switching programming operation is different from the second programming operation of the second storage mode.

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