Multi-time programming circuit of one-time programmable memory
By configuring the revocation flag bit for each target data bit of the one-time programmable memory and performing logical processing, the problem of the memory being unable to be programmed multiple times is solved and higher flexibility and reusability are achieved.
Patent Information
- Application Number
- CN202310882014.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-18
- Publication Date
- 2025-01-21
AI Technical Summary
One-time programmable memory cannot implement multiple programming, resulting in lack of flexibility and modifiability when program updates or repairs are required.
Design a multiple programming circuit to achieve multiple programming of the memory by configuring a revocation flag bit for each target data bit and performing logical processing in the logic module.
Multiple programming of one-time programmable memory is realized, the flexibility and reusability of the memory are improved, and unnecessary programming errors are avoided.
Smart Images
Figure CN119339771A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of memory technology, and in particular to a multiple programming circuit of a one-time programmable memory. Background Art
[0002] One-time programmable (OTP) memory is a one-time programmable non-volatile memory, which is often used to store calibration values of the analog part of the chip, chip keys, chip modes, memory repair and other functions. It has the advantages of low area consumption and no need for additional processes, so it is widely used.
[0003] The one-time programming circuit can only be programmed once and cannot be cleared after programming, which is the one-time programmable feature. Once the chip is programmed after leaving the factory, it cannot be changed or reconfigured again. The functions of some chips will switch the chip configuration according to the data in the OTP.
[0004] The way this memory is used is that after the chip is manufactured, the data is written into the OTP memory through a special device. The written data can be burned according to market demand to meet the needs of different customers. Once the data is written into the OTP memory, it will be permanently stored in the chip and cannot be modified or erased.
[0005] However, due to the unmodifiable nature of one-time programmable memory, it is not suitable for situations where a program needs to be patched. When a program needs to be updated or repaired, one-time programmable memory does not provide flexibility and modifiability. In addition, one-time programmable memory is not suitable for situations where different programming requirements are required for different packages.
[0006] In view of this, it is urgent to design a multi-time programming circuit of a one-time programmable memory to solve the above problems. Summary of the invention
[0007] In order to solve the above technical problems, the present invention provides a multiple programming circuit of a one-time programmable memory.
[0008] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:
[0009] A multiple programming circuit of a one-time programmable memory, comprising:
[0010] A configuration module, configured to respectively configure a revocation identification bit for each of the at least one target data bit in the one-time programmable memory;
[0011] A logic module, used for performing logic processing on the target data bit and the corresponding revocation identification bit to obtain a target logic;
[0012] Wherein, when the target data bit is programmed from an initial state to a target state and the revocation identification bit is valid, the target logic is the initial state of the target data bit.
[0013] Preferably, when the revocation identification bit is invalid, the target logic is the logic state of the target data bit, and the logic state of the target data bit is the initial state or the target state.
[0014] Preferably, when the target data bit has not been programmed or is in the initial state, the current writing of the revocation flag bit is an invalid writing.
[0015] Preferably, a definition rule is preset in the logic module, and the definition rule is that when the target data bit has not been programmed or is in the initial state, the current writing of the cancellation identification bit is invalid writing; or
[0016] It also includes: a control module, which is used to read the logic state of the corresponding target data bit when the revocation mark is written, and turn off the programming voltage of the one-time programmable memory when the read target data bit is the initial state, so that the revocation mark cannot be written.
[0017] Preferably, the target logic is obtained by performing an exclusive OR logic process on the target data bit and the corresponding revocation identification bit.
[0018] Preferably, the logic module comprises an XOR gate.
[0019] Preferably, it also includes: a trigger connected to the output end of the logic module and used to save the target logic output by the logic module.
[0020] Preferably, the one-time programmable memory comprises a storage module, and the storage module comprises:
[0021] A first storage unit, used to store the at least one target data bit;
[0022] The second storage unit is used to store the revocation identification bit corresponding to each of the target data bits one by one.
[0023] Preferably, it also includes:
[0024] An address mapping module, connected to the logic module, for reading an address mapping table, and performing address mapping on part or all of the revocation identification bits corresponding to the plurality of target data bits of the one-time programmable memory according to the address mapping table;
[0025] The logic module performs logic processing on the revocation identification bit obtained after address mapping and the corresponding target data bit to obtain the target logic.
[0026] Preferably, the address mapping module includes:
[0027] A selector is used to perform address mapping on a sequence of the revocation identification bits corresponding to a plurality of the target data bits according to the address mapping table.
[0028] The advantages or beneficial effects of the technical solution of the present invention are:
[0029] The present invention configures an additional revocation identification bit for each target data bit of the one-time programmable memory, and by configuring the state of the revocation identification bit, it is possible to realize repeated programming of the one-time programmable memory after programming, thereby improving the flexibility and reusability of the memory; at the same time, through the configuration and logical processing of the revocation identification bit, the precision and accuracy of the programming operation can be effectively controlled, thereby avoiding unnecessary programming errors. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A structural block diagram of a multiple-time programming circuit of a one-time programmable memory in a preferred embodiment of the present invention;
[0031] Figure 2 This is a schematic structural diagram of a specific implementation of a circuit for multiple programming of a single bit of a one-time programmable memory in a preferred embodiment of the present invention;
[0032] Figure 3 This is a schematic diagram of the structure of a one-time programmable memory multi-bit multiple-time programming circuit specifically implemented in a preferred embodiment of the present invention;
[0033] Figure 4 This is a schematic diagram of the structure of the control module turning on and off the programming voltage in a preferred embodiment of the present invention;
[0034] Figure 5 In a preferred embodiment of the present invention, Figure 4 The state transition pie chart of the write of the undo flag bit;
[0035] Figure 6 A schematic diagram of the structure of multi-bit address mapping in a preferred embodiment of the present invention;
[0036] Figure 7 In a preferred embodiment of the present invention, a state transition pie chart is shown when a multi-bit address is mapped to read a target data bit. DETAILED DESCRIPTION
[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0038] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0039] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.
[0040] See also Figure 1 In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a multi-time programming circuit of a one-time programmable memory is provided, comprising:
[0041] A configuration module 1, configured to respectively configure a revocation flag bit (revoke) for each target data bit (tagret) in at least one target data bit in the one-time programmable memory 100;
[0042] Logic module 2, used for performing logic processing on the target data bit and the corresponding revocation flag bit to obtain a target logic (OL);
[0043] When the target data bit is programmed from an initial state to a target state and the cancellation flag bit is valid, the target logic is the initial state of the target data bit.
[0044] Specifically, in this embodiment, the configuration module 1 configures an additional revocation flag bit for each target data bit of the one-time programmable memory 100. By configuring the state of the revocation flag bit, after the target data bit is programmed to the target state, if the revocation flag bit is valid, the target data bit can be restored to the initial state, providing more options for the flexibility and reusability of the memory. The above scheme is equivalent to a data regret mechanism after a write, so that the one-time programmable memory 100 supports multiple programming capabilities, not limited to single programming, and can avoid re-manufacturing a new memory when the memory content needs to be updated or modified, thereby saving costs and resources and improving the flexibility and reusability of the memory.
[0045] Furthermore, the logic module 2 performs logic processing on the target data bit and the cancellation flag bit to generate the target logic. This logic processing can be implemented using software, or it can be implemented by customizing the circuit according to specific needs, for example, it can realize functions such as logical operations, comparisons, and judgments. In this way, the memory can be more finely controlled and managed according to the actual application scenario. At the same time, through the configuration and logic processing of the cancellation flag bit, the precision and accuracy of the programming operation can be effectively controlled, avoiding unnecessary programming errors.
[0046] Furthermore, the target data bit can be a single bit or multiple bits. Figure 2 As shown, the multi-bit multiple programming circuit is as follows Figure 3 shown.
[0047] Furthermore, the revocation flag bit may be represented by a single bit, or may be represented in combination with certain bits of the target data bits.
[0048] Furthermore, during the programming process, for each target data bit, whether to reprogram the target data bit is determined according to the state of the cancel flag. If the cancel flag is high level valid, when the cancel flag is 1, it means that the target data bit needs to be canceled after programming, and reset to the initial state to achieve subsequent secondary or multiple programming operations; when the cancel flag is 0, it means that the target data bit does not need to be canceled and is saved in the original state.
[0049] If the revocation flag is valid at a low level, then when the revocation flag is 0, it means that the target data bit needs to be revoked after being programmed, and it is reset to its initial state to achieve subsequent secondary or multiple programming operations; when the revocation flag is 1, it means that the target data bit does not need to be revoked, and the original programming result is maintained.
[0050] As a preferred implementation, when the revocation flag bit is invalid, the target logic is the logic state of the target data bit, and the logic state of the target data bit is an initial state or a target state.
[0051] Specifically, in this embodiment, when the revocation flag is invalid, the original programming result of the target data bit is maintained, that is, if the target data bit has not been programmed, the target logic is in the initial state; if the target data has been programmed, the target logic is in the target state.
[0052] Furthermore, the one-time programmable memory 100 can be a memory that writes "1" to "0" or a memory that writes "0" to "1". If the one-time programmable memory 100 is a memory that writes "1" to "0", the initial state is 1 and becomes 0 after programming; similarly, if the memory is a memory that writes "0" to "1", the initial state is 0 and becomes 1 after programming.
[0053] In the embodiment of the present invention, an OTP memory in which "0" is written as "1" and the cancellation flag bit is high level effective is taken as an example, and its corresponding state is shown in the following Table 1:
[0054] Table 1 Combination status table of revocation flag bit and target data bit
[0055] Revoke flag Target data bit tagret Remark 0 0 The cancellation flag is invalid. 0 1 The cancellation flag is invalid. 1 0 Invalid instruction 1 1 Cancel flag is valid
[0056] As a preferred implementation, when the target data bit has not been programmed or is in an initial state, the current writing of the cancellation identification bit is invalid writing.
[0057] Specifically, in this embodiment, when the one-time programmable memory 100 has not been programmed, or is currently in an initial state (such as being revoked after programming), at this time, if the configuration revocation flag is valid, the current write is invalid, which means that this is an invalid instruction, thereby preventing the one-time programmable memory 100 that has not been programmed or revoked from being mistakenly revoked, and avoiding the execution of invalid instructions, thereby reducing the occupancy of system processors, memory and other resources, and improving the operating efficiency of the system.
[0058] As a preferred implementation, a definition rule is pre-set in the logic module 2, and the definition rule is that when the target data bit has not been programmed or is in an initial state, the current writing of the cancellation identification bit is invalid writing.
[0059] Specifically, in the present embodiment, the above-mentioned invalid instructions can be implemented by software by defining rules as invalid rules. When the conditions of the defined rules are met, it indicates that the current instruction is invalid, and writing is invalid or writing is prohibited, thereby avoiding the execution of invalid instructions and causing waste of system resources and processing time, which can reduce the waste of system resources and improve the overall performance of the system; and no additional circuits are required, so the cost is low.
[0060] In some cases, the user may accidentally write the revocation flag to be valid, resulting in memory data corruption. The above definition rules can prevent these erroneous operations from happening and protect the stability and data integrity of the memory.
[0061] As a preferred embodiment, wherein Figure 4As shown, it also includes: a control module 4, which is used to read the logic state of the corresponding target data bit when the cancel identification bit is written, and turn off the programming voltage program POWER of the one-time programmable memory 100 when the read target data bit is in the initial state, so that the cancel identification bit cannot be written.
[0062] Specifically, in this embodiment, in addition to implementing the above-mentioned invalid instructions through software, it can also be implemented through a combination of software and hardware. Through the control module 4, the logical state of the target data bit corresponding to the revocation identification bit can be read; when the read target data bit is in the initial state, the control module 4 can turn off the programming voltage of the one-time programmable memory 100 to prevent invalid instructions from being written, thereby protecting the integrity and security of the target data bit.
[0063] like Figure 5 As shown, it is a state transition pie chart of canceling the writing of the flag bit; the reset state is IDLE, the control module 4 writes the bit operation of the cancel flag bit through the APB bus, jumps to the REVORK state, and checks whether the written bit is invalid:
[0064] If it is in an invalid state, it will jump back to the IDLE state and wait for the next APB bus operation;
[0065] If it is valid data, it jumps to PROG_GATE state, PROG_GATE executes to turn on the programming voltage, and jumps to WAIT_DONE state. WAIT_DONE state waits for programming to be completed, and jumps back to IDLE state to complete the process. The control module 4 ensures that no unnecessary data will be written, thereby protecting the integrity and security of the target data bit.
[0066] Furthermore, the control module 4 can realize the on and off of the programming voltage of the one-time programmable memory 100 through a switch device. In some embodiments, the control module 4 can adopt a microcontroller unit (MCU), a central processing unit (CPU), a microprocessor (MPU), etc., which can be selected according to actual needs. In some embodiments, the switch device can adopt other electronic devices such as switches and transistors to realize the on and off function, which can be selected according to actual needs.
[0067] As a preferred implementation, the target logic is obtained by performing an XOR logic process on the target data bit and the corresponding revocation identification bit.
[0068] Specifically, in this embodiment, taking the one-time programmable memory 100 writing data from "0" to "1" as an example, the above-mentioned logic module 2 can perform an XOR operation on the target data bit and the corresponding revocation identification bit, and through the XOR logic processing, the one-time programmable memory 100 supports multiple programming.
[0069] As a preferred implementation, the logic module 2 includes an XOR gate 21 .
[0070] Specifically, in this embodiment, the XOR gate is a basic logic gate that can implement the XOR operation in the logic operation. It receives two input signals and generates a corresponding output signal according to the difference of the input signals. Further, the combination of multiple logic gates can be simplified into an XOR gate, thereby reducing the complexity and cost of the circuit.
[0071] As a preferred implementation, it further includes: a trigger 4 connected to the output end of the logic module 2 and used to store the target logic output by the logic module 2.
[0072] Specifically, in this embodiment, the target logic output by the logic module 2 is saved and controlled by the trigger 4, thereby improving the efficiency and function of the circuit.
[0073] As a preferred embodiment, the one-time programmable memory 100 includes a storage module, and the storage module includes:
[0074] A first storage unit 101, used to store at least one target data bit;
[0075] The second storage unit 102 is used to store a revocation identification bit corresponding to each target data bit.
[0076] Furthermore, the above-mentioned revocation identification bit can be stored separately from the target data bit, or can be stored in combination with the target data bit.
[0077] As a preferred embodiment, the invention further comprises:
[0078] An address mapping module (not shown in the figure), connected to the logic module 2, is used to read the address mapping table 6, and perform address mapping on part or all of the revocation identification bits corresponding to the multiple target data bits of the one-time programmable memory 100 according to the address mapping table 6;
[0079] The logic module 2 performs logic processing on the revocation flag bit obtained after address mapping and the corresponding target data bit to obtain the target logic.
[0080] Specifically, in this embodiment, by reading the address mapping table 6, multiple target data bits of the one-time programmable memory 100 can be mapped according to the mapping relationship in the address mapping table 6, and the revocation identification bit can be partially or fully addressed as needed, thereby improving flexibility and scalability and being able to adapt to different application scenarios and needs.
[0081] As a preferred embodiment, wherein Figure 6 As shown, the address mapping module includes:
[0082] The selector 5 is used to perform address mapping on a sequence of revocation identification bits corresponding to a plurality of target data bits according to the address mapping table 6.
[0083] Specifically, in the present embodiment, when reading the target data bit, the address mapping table 6 is read first. To speed up the reading speed, the default sequence in the second storage unit 102 is read at the same time. The sequence is composed of revocation identification bits corresponding to multiple target data bits, and all revocation identification bits have default values. Generally, the default value indicates that the revocation identification bit is valid. By reading the address mapping table 6, the address of the address mapping table 6 corresponds to the position of the revocation identification bit one by one. If the corresponding address is configured, the corresponding offset address in the default sequence stored in the second storage unit 102 in the OTP is read again. Then, the selector is used to switch to the array 7 composed of the revocation identification bits corresponding to the new multiple target data bits, so as to achieve remapping.
[0084] like Figure 7 As shown, it is a state transition pie chart when reading the target data bit. Initially, it is in the reset state IDLE. After power-on or when the control module 4 writes to the APB bus, it will be triggered, thereby jumping to the RD_TARGET state. The RD_TARGET state will read the bit of the target data bit in the OTP; after reading the data, it jumps to the RD_DEFAULT_REVOKE_CFG state, which will read the address mapping table 6 (REVOKE_CFG_ADDR). Further, if the address mapping table 6 is not configured, the address is 0, and there is no need to re-read, then jump back to the reset state IDLE; if the address is not 0, then read the bit value of the revoked data bit of the remapped address, and after reading, the new value is selected and replaced using the selector 5, and then jump back to the reset state IDLE.
[0085] The advantages or beneficial effects of adopting the above technical solution are: the present invention configures an additional revocation identification bit for each target data bit of the one-time programmable memory, and by configuring the state of the revocation identification bit, it is possible to realize repeated programming of the one-time programmable memory after programming, thereby improving the flexibility and reusability of the memory; at the same time, through the configuration and logical processing of the revocation identification bit, the precision and accuracy of the programming operation can be effectively controlled, avoiding unnecessary programming errors.
[0086] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.
Claims
1. A multi-programming circuit for a one-time programmable memory, characterized in that: include: A configuration module, configured to respectively configure a revocation identification bit for each of the at least one target data bit in the one-time programmable memory; A logic module, used for performing logic processing on the target data bit and the corresponding revocation identification bit to obtain a target logic; Wherein, when the target data bit is programmed from an initial state to a target state and the revocation identification bit is valid, the target logic is the initial state of the target data bit.
2. The multi-time programming circuit of a one-time programmable memory according to claim 1, characterized in that: When the revocation identification bit is invalid, the target logic is the logic state of the target data bit, and the logic state of the target data bit is the initial state or the target state.
3. The multi-time programming circuit of a one-time programmable memory according to claim 1, characterized in that: When the target data bit has not been programmed or is in the initial state, the current writing of the revocation flag bit is an invalid writing.
4. The multi-time programming circuit of a one-time programmable memory according to claim 3, characterized in that: A definition rule is preset in the logic module, and the definition rule is that when the target data bit has not been programmed or is in the initial state, the current writing of the cancellation flag bit is invalid writing; or It also includes: a control module, which is used to read the logic state of the corresponding target data bit when the revocation mark is written, and turn off the programming voltage of the one-time programmable memory when the read target data bit is the initial state, so that the revocation mark cannot be written.
5. The multi-time programming circuit of a one-time programmable memory according to claim 1, characterized in that: The target logic is obtained by performing an exclusive OR logic process on the target data bit and the corresponding revocation identification bit.
6. The multi-time programming circuit of a one-time programmable memory according to claim 5, characterized in that: The logic module includes an XOR gate.
7. The multi-time programming circuit of a one-time programmable memory according to claim 1, characterized in that: Also includes: A trigger is connected to the output end of the logic module and is used to store the target logic output by the logic module.
8. The multi-time programming circuit of a one-time programmable memory according to claim 1, characterized in that: The one-time programming circuit includes a storage module, and the storage module includes: A first storage unit, used to store the at least one target data bit; The second storage unit is used to store the revocation identification bit corresponding to each of the target data bits one by one.
9. The multi-time programming circuit of a one-time programmable memory according to claim 1, characterized in that: Also includes: An address mapping module, connected to the logic module, for reading an address mapping table, and performing address mapping on part or all of the revocation identification bits corresponding to the plurality of target data bits of the one-time programmable memory according to the address mapping table; The logic module performs logic processing on the revocation identification bit obtained after address mapping and the corresponding target data bit to obtain the target logic.
10. The multi-time programming circuit of a one-time programmable memory according to claim 9, characterized in that: The address mapping module comprises: A selector is used to perform address mapping on a sequence of the revocation identification bits corresponding to a plurality of the target data bits according to the address mapping table.