Shift register, gate drive circuit and display device

Abstract

The invention relates to the technical field of display, particularly provides a shift register, a gate drive circuit and a display device, and aims to solve the problem that the undershoot strength of an undershoot waveform is affected due to the fact that an output circuit cannot be completely closed when an existing shift register configured with an undershoot forming circuit outputs the undershoot waveform. In order to achieve the purpose, the shift register comprises a shift register unit, an undershoot forming unit and a node control unit, the shift register unit is used for outputting a driving signal; the undershoot forming unit is coupled with the driving signal output end of the shifting register unit and is used for responding to a first lower-level driving signal and converting the driving signal from an effective potential to an undershoot ineffective potential; the shifting register unit comprises an output circuit and is further used for responding to the first lower-level driving signal and controlling the output circuit to be closed in combination with the node control unit. The downward punching strength of the falling edge is guaranteed, and the falling edge time is effectively shortened.

Description

Technical Field

[0001] The present application relates to the field of display technology, and specifically provides a shift register, a gate drive circuit and a display device. Background Art

[0002] The high-frequency refresh display panel has the problem of insufficient charging time and prone to charging crosstalk. To address this, a shift register is provided in the related art. It can form an undershoot waveform with a voltage value less than the low level by configuring an undershoot forming circuit, accelerate the generation of the falling edge of the driving signal, shorten the falling edge time, and ensure that the transistors of the corresponding row pixel electrodes are quickly turned off, effectively avoiding charging crosstalk. However, the shift register provided in the related art cannot ensure that the transistors in its output circuit are completely turned off when outputting the undershoot waveform, so that the generated undershoot waveform cannot be directly pulled down to the undershoot invalid potential, affecting the undershoot strength of the falling edge. Summary of the invention

[0003] The present application aims to solve the above technical problem, that is, to solve the problem that the existing shift register equipped with an undershoot forming circuit cannot ensure that its output circuit is completely closed when outputting an undershoot waveform, thereby affecting the undershoot strength of the undershoot waveform.

[0004] In a first aspect, the present application provides a shift register, which includes a shift register unit, an undershoot forming unit and a node control unit;

[0005] The shift register unit is used to output a driving signal;

[0006] The undershoot forming unit is coupled to the driving signal output terminal of the shift register unit, and is used to convert the driving signal from an effective potential to an undershoot invalid potential in response to a first lower-level driving signal; the voltage difference between the undershoot invalid potential and the effective potential is greater than the voltage difference between the invalid potential and the effective potential;

[0007] The shift register unit includes an output circuit, and the shift register unit is further used to respond to the first lower-level driving signal and control the output circuit to be turned off in conjunction with the node control unit.

[0008] In some embodiments, the shift register unit further includes a reset circuit, a first pull-up node, a pull-down node, and a processing circuit;

[0009] The reset circuit is used for controlling the first pull-up node to be the invalid potential in response to the first lower-level driving signal;

[0010] The node control unit and the processing circuit jointly control the pull-down node, and the node control unit is used to control the pull-down node to maintain the invalid potential when the first pull-up node is at the invalid potential;

[0011] The output circuit is configured to be turned off in response to the invalid potential of the first pull-up node and the invalid potential of the pull-down node.

[0012] In some embodiments, the node control unit includes a charging circuit, a second pull-up node, and an auxiliary pull-down circuit;

[0013] The charging circuit is used for controlling the second pull-up node to be an effective potential in response to a signal at the input end of the shift register unit;

[0014] The auxiliary pull-down circuit is used for controlling the pull-down node to maintain the invalid potential in response to the effective potential of the second pull-up node.

[0015] In some embodiments, the node control unit further includes a control circuit, the control circuit being used to control the second pull-up node to be converted from a valid potential to an invalid potential in response to a second lower-level driving signal;

[0016] The auxiliary pull-down circuit is further configured to be turned off in response to an invalid potential of the second pull-up node;

[0017] When the auxiliary pull-down circuit is turned off, the pull-down node is converted from the invalid potential to the valid potential; the output circuit is further used to output a driving signal of an invalid potential based on the valid potential of the pull-down node.

[0018] In some embodiments, the charging circuit includes a first transistor and a first capacitor;

[0019] The control end of the first transistor is connected to the input end, the first end of the first transistor is connected to the first level signal control end, and the second end of the first transistor is connected to the second pull-up node;

[0020] A first end of the first capacitor is connected to the second pull-up node, and a second end of the first capacitor is connected to a second level signal input node of the processing circuit.

[0021] In some embodiments, the auxiliary pull-down circuit includes a second transistor;

[0022] The control end of the second transistor is connected to the second pull-up node, the first end of the second transistor is connected to the pull-down node, and the second end of the second transistor is connected to the second level signal input node of the processing circuit.

[0023] In some embodiments, the control circuit includes a third transistor;

[0024] The control end of the third transistor is connected to the second lower-level driving signal output end, the first end of the third transistor is connected to the second pull-up node, and the second end of the third transistor is connected to the second level signal control end.

[0025] In some embodiments, the shift register unit further includes an input circuit, a first stabilization circuit, and a second stabilization circuit;

[0026] The input circuit is used to control the signal of the first pull-up node in response to the start frame signal or the upper drive signal provided by the input terminal;

[0027] The first stabilization circuit is used to stably transmit the signal of the first pull-up node to the output circuit;

[0028] The second stabilizing circuit is used to stably transmit the signal of the second pull-up node to the output circuit.

[0029] In some embodiments, the input circuit includes a fourth transistor, the control end of the fourth transistor is connected to the start frame signal end or the upper drive signal output end through the input end, the first end of the fourth transistor is connected to the third level signal control end, and the second end of the fourth transistor is connected to the first pull-up node.

[0030] In some embodiments, the reset circuit includes a fifth transistor, the control end of the fifth transistor is connected to the first lower-level drive signal output end, the first end of the fifth transistor is connected to the first pull-up node, and the second end of the fifth transistor is connected to the fourth level signal control end.

[0031] In some embodiments, the processing circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a second capacitor;

[0032] The control end of the sixth transistor is connected to the pull-down node, the first end of the sixth transistor is connected to the first pull-up node, and the second end of the sixth transistor is connected to the second level signal input node;

[0033] The control terminal and the first terminal of the seventh transistor are connected to the first level signal control terminal, and the second terminal of the seventh transistor is connected to the control terminal of the eighth transistor;

[0034] The first end of the eighth transistor is connected to the first level signal control end, and the second end of the eighth transistor is connected to the pull-down node;

[0035] The control end of the ninth transistor is connected to the first pull-up node, the first end of the ninth transistor is connected to the pull-down node, and the second end of the ninth transistor is connected to the second level signal input node;

[0036] The control terminal of the tenth transistor is connected to the driving signal output terminal, the first terminal of the tenth transistor is connected to the pull-down node, and the second terminal of the tenth transistor is connected to the second level signal input node;

[0037] The control terminal and the first terminal of the eleventh transistor are connected to the reset signal terminal, and the second terminal of the eleventh transistor is connected to the pull-down node;

[0038] A first end of the second capacitor is connected to the pull-down node, and a second end of the second capacitor is connected to the second level signal input node.

[0039] In some embodiments, the first stabilization circuit includes a twelfth transistor, the control end of the twelfth transistor is connected to the first level signal control end, the first end of the twelfth transistor is connected to the drive signal output end through the output circuit, and the second end of the twelfth transistor is connected to the first pull-up node.

[0040] In some embodiments, the second stabilization circuit includes a thirteenth transistor, a control terminal of the thirteenth transistor is connected to the reset signal terminal, a first terminal of the thirteenth transistor is connected to the second pull-up node, and a second terminal of the thirteenth transistor is connected to the second level signal input node.

[0041] In some embodiments, the output circuit includes a fourteenth transistor, a fifteenth transistor, and a third capacitor;

[0042] The control end of the fourteenth transistor is connected to the first pull-up node through the first stabilization circuit, the first end of the fourteenth transistor is connected to the timing control signal end, and the second end of the fourteenth transistor is connected to the driving signal output end;

[0043] A first end of the third capacitor is connected to the control end of the fourteenth transistor, and a second end of the third capacitor is connected to the second end of the fourteenth transistor;

[0044] The control end of the fifteenth transistor is connected to the pull-down node, the first end of the fifteenth transistor is connected to the driving signal output end, and the second end of the fifteenth transistor is connected to the second level signal input node.

[0045] In some embodiments, the undershoot forming unit includes a sixteenth transistor, the control end of the sixteenth transistor is connected to the first lower-level drive signal output end, the first end of the sixteenth transistor is connected to the drive signal output end, and the second end of the sixteenth transistor is connected to the undershoot signal end.

[0046] In a second aspect, the present application provides a gate drive circuit, which includes a plurality of shift registers as described in any one of the above items, and the plurality of shift registers are cascaded.

[0047] In some embodiments, in the plurality of shift registers arranged in cascade, the input end of the first shift register is configured to be coupled to the start frame signal end; the output end of the previous shift register in two adjacent shift registers is coupled to the input end of the next shift register; and the effective values ​​of the drive signals output by the shift registers of different stages do not overlap in timing;

[0048] The control end of the reset circuit in the Nth stage shift register and the control end of the undershoot forming unit are coupled to the output end of the N+1th stage shift register, and the control end of the control circuit in the node control unit is coupled to the output end of the N+2th stage shift register.

[0049] In some embodiments, in the plurality of shift registers arranged in cascade, the input end of the first shift register is configured to be coupled to the start frame signal end; the output end of the previous shift register in two adjacent shift registers is coupled to the input end of the next shift register; and the effective values ​​of the drive signals output by the shift registers of different stages overlap in timing;

[0050] The control end of the reset circuit in the Nth stage shift register and the control end of the undershoot forming unit are coupled to the output end of the N+2th stage shift register, and the control end of the control circuit in the node control unit is coupled to the output end of the N+3th stage shift register.

[0051] In a third aspect, the present application provides a display device, comprising the gate driving circuit described in any one of the above items.

[0052] In a fourth aspect, the present application provides a shift register driving method, comprising:

[0053] outputting a driving signal through a shift register unit;

[0054] The shift register unit responds to the first lower-level driving signal and is combined with a node control unit to control the output circuit of the shift register unit to be closed, and the undershoot forming unit responds to the first lower-level driving signal to convert the driving signal from an effective potential to an undershoot invalid potential; the voltage difference between the undershoot invalid potential and the effective potential is greater than the voltage difference between the invalid potential and the effective potential.

[0055] In the case of adopting the above technical solution, the present application can provide a shift register, which includes a shift register unit, an undershoot forming unit and a node control unit; the shift register unit is used to output a driving signal; the undershoot forming unit is coupled to the driving signal output end of the shift register unit, and is used to respond to the first lower-level driving signal and convert the driving signal from an effective potential to an undershoot invalid potential; the voltage difference between the undershoot invalid potential and the effective potential is greater than the voltage difference between the invalid potential and the effective potential; the shift register unit includes an output circuit, and the shift register unit is also used to respond to the first lower-level driving signal and control the output circuit to be closed in combination with the node control unit. This solution is beneficial to ensure that the transistors in the output circuit of the shift register unit are completely turned off when the undershoot forming unit converts the effective potential to the undershoot invalid potential, and is beneficial to the generated undershoot waveform to directly reach the undershoot invalid potential, ensuring the undershoot strength of the falling edge, and effectively reducing the falling edge time. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The preferred embodiments of the present application are described below in conjunction with the accompanying drawings, in which:

[0057] Figure 1 It is a schematic diagram of a driving signal output by a shift register when the undershoot forming circuit provided by the present application is not configured;

[0058] Figure 2 It is a schematic diagram of a driving signal output by a shift register when configuring an undershoot forming circuit provided in the present application;

[0059] Figure 3 is a schematic diagram of a shift register structure provided in an embodiment of the present application;

[0060] Figure 4 is a schematic diagram of a shift register structure provided by another embodiment of the present application;

[0061] Figure 5 is a schematic diagram of a shift register structure provided by another embodiment of the present application;

[0062] Figure 6 is a circuit diagram of a shift register provided in an embodiment of the present application;

[0063] Figure 7 is a timing diagram of a shift register provided in an embodiment of the present application;

[0064] Figure 8 is a circuit diagram of a non-precharge type display device provided in an embodiment of the present application;

[0065] Fig. 9 is a timing diagram of a non-precharge type display device provided in an embodiment of the present application;

[0066] Fig.10 is a circuit diagram of a pre-charge type display device provided in an embodiment of the present application;

[0067] Fig.11 is a timing diagram of a pre-charge type display device provided in an embodiment of the present application;

[0068] Fig.12 This is a timing diagram of a pre-charge type display device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0070] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0071] It should be noted that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present application, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first end, the other electrode is called the second end, and the gate is called the control end. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with N-type transistors. When N-type transistors are used, the first end is the drain of the N-type transistor, and the second end is the source of the N-type transistor. When the gate inputs a high level, the source and drain are turned on, the high level is the effective potential, and the low level is the invalid potential; P-type transistors are the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative labor, so it is also within the scope of protection of the embodiments of the present application.

[0072] Based on the description of the background technology part, it can be known that the shift register provided in the related art cannot ensure that the transistor in its output circuit is completely turned off when outputting the undershoot waveform. Specifically, the shift register can respond to the signal of the pull-up node and output the effective potential through its output circuit when working, and can respond to the signal of the pull-down node and output the invalid potential through its output circuit. Therefore, the shift register can output a driving signal in which the effective potential and the invalid potential appear alternately and are in a pulse waveform, such as Figure 1 As shown, Figure 1 This is a schematic diagram of the drive signal output by the shift register when the undershoot forming circuit is not configured. The effective potential is high level, represented by VGH; the invalid potential is low level, represented by VGL. In order to shorten the falling edge time t when the drive signal is converted from the effective potential VGH to the invalid potential VGL f When the undershoot forming circuit is configured for the shift register, the undershoot forming circuit is configured to convert the driving signal from the effective potential VGH to the undershoot invalid potential VGL1. However, since some transistors in the output circuit of the shift register are still turned on in response to the pull-down node and output signals of invalid potential, the generated undershoot waveform may not be directly pulled down to the target undershoot invalid potential VGL1, see Figure 2 As shown, Figure 2 A schematic diagram of the drive signal output by the shift register when the undershoot formation circuit is configured for the present application, wherein the voltage difference between the actual undershoot invalid potential VGL2 and the effective potential VGH is greater than the voltage difference between the invalid potential VGL and the effective potential VGH, and the actual undershoot invalid potential VGL2 is between the invalid potential VGL and the target undershoot invalid potential VGL1. The opening of the output circuit affects the undershoot strength of the falling edge of the drive signal, and it is impossible to effectively reduce the falling edge time, ensure the effective charging time, and effectively avoid the effect of charging crosstalk of the display panel.

[0073] Based on this, the present application provides a shift register, which, by further configuring a node control unit, can control the pull-down node when the undershoot forming unit converts the effective potential to the undershoot invalid potential, thereby ensuring that the transistor in the output circuit of the shift register unit is completely turned off, which is beneficial for the generated undershoot waveform to directly reach the undershoot invalid potential, thereby ensuring the undershoot strength of the falling edge and effectively reducing the falling edge time.

[0074] See also Figure 3 As shown, Figure 3It is a schematic diagram of a shift register structure provided in an embodiment of the present application, which may include a shift register unit, an undershoot forming unit and a node control unit; the shift register unit is used to output a drive signal G-OUTN; the undershoot forming unit is coupled to the drive signal output terminal OUTN of the shift register unit, and is used to respond to the first lower-level drive signal G-OUT(N+M) to convert the drive signal from an effective potential to an undershoot invalid potential; the voltage difference between the undershoot invalid potential and the effective potential is greater than the voltage difference between the invalid potential and the effective potential; the shift register unit includes an output circuit, and the shift register unit is also used to respond to the first lower-level drive signal G-OUT(N+M), and control the output circuit to be closed in combination with the node control unit.

[0075] In the embodiment of the present application, the duration of the undershoot formation unit controlling the drive signal output terminal OUTN to output the undershoot invalid potential is shorter than the duration of the output valid potential, and the undershoot formation unit can also be used to convert the undershoot invalid potential to the invalid potential. The M in the first lower-level drive signal G-OUT(N+M) can be a positive integer, that is, the "lower level" here can be the next level adjacent to the current Nth level, or the next two levels, the next three levels, etc. of the current Nth level, which is not limited here and can be set based on actual needs.

[0076] In some embodiments, see Figure 4 As shown, Figure 4 is a schematic diagram of a shift register structure provided by another embodiment of the present application. The shift register can be based on Figure 3 On the basis of this, the shift register unit may also include a reset circuit, a first pull-up node PU1, a pull-down node PD and a processing circuit; the reset circuit is used to control the first pull-up node PU1 to be an invalid potential in response to the first lower-level driving signal G-OUT(N+M); the node control unit and the processing circuit jointly control the pull-down node PD, and the node control unit is used to control the pull-down node PD to maintain an invalid potential when the first pull-up node PU1 is an invalid potential; the output circuit is used to shut down in response to the invalid potential of the first pull-up node PU1 and the invalid potential of the pull-down node PD.

[0077] In this embodiment, the node control unit can be used to control the pull-down node PD, thereby ensuring that when the undershoot forming unit provides the undershoot invalid potential to the driving signal output terminal OUTN, the output circuit of the shift register unit is closed and will not affect the undershoot invalid potential.

[0078] In some embodiments, see Figure 5 As shown, Figure 5 is a schematic diagram of a shift register structure provided by another embodiment of the present application. In this embodiment, the shift register can be based on Figure 4 Get, its in Figure 4The basic node control unit may include a charging circuit, a second pull-up node PU2 and an auxiliary pull-down circuit; the charging circuit is used to control the second pull-up node PU2 to be a valid potential in response to the signal of the input terminal InputN of the shift register unit; the auxiliary pull-down circuit is used to control the pull-down node PD to maintain an invalid potential in response to the effective potential of the second pull-up node PU2.

[0079] In some embodiments, see Figure 5 As shown, the node control unit also includes a control circuit, which is used to control the second pull-up node PU2 to be converted from a valid potential to an invalid potential in response to a second lower-level driving signal G-OUT(N+L); the auxiliary pull-down circuit is also used to be turned off in response to the invalid potential of the second pull-up node PU2; when the auxiliary pull-down circuit is turned off, the pull-down node PD is converted from an invalid potential to a valid potential; the output circuit is also used to output a driving signal of an invalid potential based on the effective potential of the pull-down node PD.

[0080] In an embodiment of the present application, L in the second lower-level driving signal G-OUT(N+L) can be a positive integer and greater than M, that is, the "lower level" here can be the lower two levels, lower three levels, etc. of the current Nth level, which is not limited here and can be set based on actual needs.

[0081] In some embodiments, see Figure 6 As shown, Figure 6 It is a circuit diagram of a shift register provided in an embodiment of the present application.

[0082] Wherein, the charging circuit includes a first transistor T1 and a first capacitor C1;

[0083] The control end of the first transistor T1 is connected to the input end InputN, the first end of the first transistor T1 is connected to the first level signal control end, namely the VGH end, and the output end of the first transistor T1 is connected to the second pull-up node PU2;

[0084] A first end of the first capacitor C1 is connected to the second pull-up node PU2 , and a second end of the first capacitor C1 is connected to the second level signal input node PL of the processing circuit.

[0085] In some embodiments, the auxiliary pull-down circuit includes a second transistor T2, the control end of the second transistor T2 is connected to the second pull-up node PU2, the first end of the second transistor T2 is connected to the pull-down node PD, and the second end of the second transistor T2 is connected to the second level signal input node PL of the processing circuit.

[0086] In some embodiments, the control circuit includes a third transistor T3, the control end of the third transistor T3 is connected to the second lower-level drive signal output end, i.e., the OUT(N+L) end, the first end of the third transistor T3 is connected to the second pull-up node PU2, and the second end of the third transistor T3 is connected to the second level signal control end, i.e., the VGL end.

[0087] In some embodiments, the shift register unit also includes an input circuit, a first stabilization circuit, and a second stabilization circuit; the input circuit is used to control the signal of the first pull-up node PU1 in response to the start frame signal STV or the upper drive signal OUT(N-1) provided by the input terminal InputN; the first stabilization circuit is used to stably transmit the signal of the first pull-up node PU1 to the output circuit; the second stabilization circuit is used to stably transmit the signal of the second pull-up node PU2 to the output circuit.

[0088] In some embodiments, the input circuit includes a fourth transistor T4, the control end of the fourth transistor T4 is connected to the start frame signal end, i.e., the STV end, or the upper drive signal output end, i.e., the OUT(N-1) end, through the input end InputN, the first end of the fourth transistor T4 is connected to the third level signal control end, i.e., the CN end, and the second end of the fourth transistor T4 is connected to the first pull-up node PU1.

[0089] In some embodiments, the reset circuit includes a fifth transistor T5, the control end of the fifth transistor T5 is connected to the first lower-level drive signal output end, i.e., the OUT(N+M) end, the first end of the fifth transistor T5 is connected to the first pull-up node PU1, and the second end of the fifth transistor T5 is connected to the fourth level signal control end, i.e., the CNB end.

[0090] In some embodiments, the processing circuit includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a second capacitor C2;

[0091] A control end of the sixth transistor T6 is connected to the pull-down node PD, a first end of the sixth transistor T6 is connected to the first pull-up node PU1, and a second end of the sixth transistor T6 is connected to the second level signal input node PL;

[0092] The control terminal and the first terminal of the seventh transistor T7 are connected to the first level signal control terminal, namely the VGH terminal, and the second terminal of the seventh transistor T7 is connected to the control terminal of the eighth transistor T8;

[0093] A first end of the eighth transistor T8 is connected to the first level signal control end, namely, the VGH end, and a second end of the eighth transistor T8 is connected to the pull-down node PD;

[0094] The control end of the ninth transistor T9 is connected to the first pull-up node PU1, the first end of the ninth transistor T9 is connected to the pull-down node PD, and the second end of the ninth transistor T9 is connected to the second level signal input node PL;

[0095] The control end of the tenth transistor T10 is connected to the driving signal output end OUTN, the first end of the tenth transistor T10 is connected to the pull-down node PD, and the second end of the tenth transistor T10 is connected to the second level signal input node PL;

[0096] The control terminal and the first terminal of the eleventh transistor T11 are connected to the reset signal terminal, namely, the RESET terminal, and the second terminal of the eleventh transistor T11 is connected to the pull-down node PD;

[0097] A first end of the second capacitor C2 is connected to the pull-down node PD, and a second end of the second capacitor C2 is connected to the second level signal input node PL.

[0098] In some embodiments, the first stabilization circuit includes a twelfth transistor T12, the control end of the twelfth transistor T12 is connected to the first level signal control end, i.e., the VGH end, the first end of the twelfth transistor T12 is connected to the drive signal output end OUTN through the output circuit, and the second end of the twelfth transistor T12 is connected to the first pull-up node PU1.

[0099] In some embodiments, the second stabilization circuit includes a thirteenth transistor T13, the control end of the thirteenth transistor T13 is connected to the reset signal end, i.e., the RESET end, the first end of the thirteenth transistor T13 is connected to the second pull-up node PU, and the second end of the thirteenth transistor T13 is connected to the second level signal input node PL.

[0100] In some embodiments, the output circuit includes a fourteenth transistor T14, a fifteenth transistor T15, and a third capacitor C3;

[0101] The control end of the fourteenth transistor T14 is connected to the first pull-up node PU1 through the first stabilization circuit, the first end of the fourteenth transistor T14 is connected to the timing control signal end, namely, the CK end, and the second end of the fourteenth transistor T14 is connected to the driving signal output end OUTN;

[0102] A first end of the third capacitor C3 is connected to the control end of the fourteenth transistor T14, and a second end of the third capacitor C3 is connected to the second end of the fourteenth transistor T14;

[0103] A control terminal of the fifteenth transistor T15 is connected to the pull-down node PD, a first terminal of the fifteenth transistor T15 is connected to the driving signal output terminal, and a second terminal of the fifteenth transistor T15 is connected to the second level signal input node PL.

[0104] In some embodiments, the undershoot forming unit includes a sixteenth transistor T16, the control end of the sixteenth transistor T16 is connected to the first lower-level drive signal output end, i.e., the OUT(N+M) end, the first end of the sixteenth transistor T16 is connected to the undershoot signal end, i.e., the MLC end, and the second end of the sixteenth transistor T16 is connected to the drive signal output end OUTN.

[0105] Combine the following Figure 6 and Figure 7 Describe the working process of the shift register of the present application, wherein: Figure 7 It is a timing diagram of the shift register provided by the embodiment of the present application. It can be configured as N=1, M=1, L=2, the input terminal InputN of the shift register is connected to the start frame signal terminal, that is, the STV terminal, for inputting the start frame signal STV, and can provide a first level signal VGH for the first level signal control terminal, that is, the VGH terminal, provide a second level signal VGL for the second level signal control terminal, that is, the VGL terminal, provide a third level signal CN for the third level signal control terminal, that is, the CN terminal, provide a fourth level signal CNB for the fourth level signal control terminal (CNB), provide a timing control signal CK for the timing control signal terminal, that is, the CK terminal, provide an undershoot signal MLC for the undershoot signal terminal, that is, the MLC terminal, and the undershoot signal MLC is a pulse waveform consisting of an undershoot invalid potential and an invalid potential alternately appearing. And provide a second-level drive signal G-OUT2 for the current first lower-level drive signal output terminal, that is, the OUT(N+M) terminal, and provide a third-level drive signal G-OUT3 for the second lower-level drive signal output terminal, that is, the OUT(N+L) terminal.

[0106] In the t1 phase, STV is at a high level, and CK, G-OUT2, and G-OUT3 are all at a low level.

[0107] STV is at a high level, the first transistor T1 and the fourth transistor T4 are turned on, the second pull-up node PU2 and the first pull-up node PU1 are both pulled up to a high level, the second transistor T2 and the ninth transistor T9 are both turned on, and the seventh transistor T7 and the eighth transistor T8 are normally open, and the pull-down node PD is pulled down to a low level. The pull-down node PD is connected to the control end of the sixth transistor T6 and the fifteenth transistor T15, and the sixth transistor T6 and the fifteenth transistor T15 are turned off. G-OUT2 and G-OUT3 are both low levels, and the fifth transistor T5, the sixteenth transistor T16 and the third transistor T3 are all turned off. The control end of the twelfth transistor T12 is connected to a high level and is normally open, the first pull-up node PU1 turns on the fourteenth transistor T14, and the fourteenth transistor T14 transmits the low-level timing control signal CK to the drive signal output terminal OUT1, and the output drive signal G-OUT1 is low.

[0108] In the t2 phase, STV is converted to a low level, CK is converted to a high level, and G-OUT2 and G-OUT3 are both low levels.

[0109] STV is at a low level, the first transistor T1 and the fourth transistor T4 are turned off, the timing control signal CK is at a high level, the output drive signal G-OUT1 is converted from a low level to a high level, and under the bootstrap effect of the third capacitor C3, the first pull-up node PU1 is raised to a higher level to ensure that at time t2, the gate voltage of the fourteenth transistor T14 is high enough to ensure that the fourteenth transistor T14 is fully turned on to output a high level in the t2 stage. The second pull-up node PU2 maintains a high level in the t1 stage, the second transistor T2 and the ninth transistor T9 are still turned on, the pull-down node PD node maintains a low level in the t1 stage, and the sixth transistor T6 and the fifteenth transistor T15 are turned off. G-OUT2 and G-OUT3 are both at a low level, and the fifth transistor T5, the sixteenth transistor T16 and the third transistor T3 are all turned off.

[0110] In the t3 phase, G-OUT2 is converted to a high level, CNB is a low level, and STV and G-OUT3 are both low levels.

[0111] G-OUT2 is at a high level, the fifth transistor T5 and the sixteenth transistor 16 are both turned on, when the fifth transistor T5 is turned on, CNB pulls the first pull-up node PU1 down to a low level, and the ninth transistor T9 and the fourteenth transistor T14 are both turned off. G-OUT3 is at a low level, the third transistor T3 is turned off, the first capacitor C1 keeps the second pull-up node PU2 at a high level in the t2 stage, the second transistor T2 is turned on, the pull-down node PD is kept at a low level, the sixth transistor T6 and the fifteenth transistor T15 are turned off. The sixteenth transistor 16 is turned on, and MLC pulls G-OUT1 down to the undershoot invalid potential VGL1, VGL1<VGL.

[0112] In the t4 phase, G-OUT2 maintains the high level of the t3 phase, MLC is converted from the undershoot invalid potential to the invalid potential, i.e., the low level VGL, and STV, G-OUT3 and CNB are at low levels.

[0113] G-OUT2 is at a high level, the fifth transistor T5 and the sixteenth transistor 16 are both turned on, when the fifth transistor T5 is turned on, CNB pulls the first pull-up node PU1 down to a low level, and the ninth transistor T9 and the fourteenth transistor T14 are both turned off. G-OUT3 is at a low level, the third transistor T3 is turned off, the first capacitor C1 keeps the second pull-up node PU2 at a high level in the t2 stage, the second transistor T2 is turned on, the pull-down node PD is kept at a low level, and the sixth transistor T6 and the fifteenth transistor T15 are turned off. The sixteenth transistor 16 is turned on, the MLC is converted from an undershoot invalid potential to an invalid potential, and G-OUT1 is converted from an undershoot invalid potential to an invalid potential.

[0114] In the t5 phase, G-OUT3 is converted to a high level, G-OUT2 is converted to a low level, and STV is a low level.

[0115] STV and G-OUT2 are at a low level, the fourth transistor T4, the first transistor T1, the fifth transistor T5 and the sixteenth transistor T16 are all turned off, the first pull-up node PU1 maintains a low level, and the ninth transistor T9 is turned off. G-OUT3 is at a high level, the third transistor T3 is turned on, the second pull-up node PU2 is pulled down to a low level, and the second transistor T2 is turned off. The second transistor T2 and the ninth transistor T9 are both turned off, the pull-down node PD is converted to a high level, the sixth transistor T6 and the fifteenth transistor T15 are turned on, and the fifteenth transistor T15 is turned on to provide the second level signal VGL to the drive signal output terminal OUT1, and the output drive signal G-OUT1 is at a low level.

[0116] It should be noted that the eleventh transistor T11 is normally off.

[0117] In another aspect of the present application, a gate driving circuit is provided, which includes a plurality of shift registers as described in any of the above embodiments, and the plurality of shift registers are cascaded.

[0118] The above gate driving circuit can be applied to a liquid crystal display panel.

[0119] The gate driving circuit provided in the embodiment of the present application can be applied to a display device. Another aspect of the present application provides a display device, which may include the above-mentioned gate driving circuit, a plurality of gate lines, a display area and a control signal unit. The display area includes a plurality of rows of pixel units PixelN, where N is an integer greater than or equal to 1. The control signal unit is used to provide signals for each level of shift register. Figure 8-11 As shown, Figure 8 is a circuit diagram of a non-precharge type display device provided in an embodiment of the present application, Fig. 9 This is a timing diagram of a non-pre-charge type display device provided in an embodiment of the present application. Fig.10is a circuit diagram of a pre-charge type display device provided in an embodiment of the present application, Fig.11 This is a timing diagram of a pre-charge type display device provided in an embodiment of the present application.

[0120] In some embodiments, Figure 8 and 10 As shown, among the multiple cascaded shift registers, the odd-numbered shift registers are used to provide driving signals to the pixel units in odd rows, and the even-numbered shift registers are used to provide driving signals to the pixel units in even rows. The shift registers, gate lines and pixel units are arranged in a one-to-one correspondence. The odd-numbered shift registers can be arranged on the left side of the display area, and the even-numbered shift registers can be arranged on the right side of the display area.

[0121] In the multiple shift registers located on the left side of the display area, the clock signal end, i.e., the CK end, of each shift register alternately inputs two signals CKL and CKBL at each timing, and when the CK end of one of the two adjacent shift registers in the column direction inputs the CKL signal, the CK end of the other shift register inputs the CKBL signal.

[0122] In the multiple shift registers located on the right side of the display area, the clock signal end, i.e., the CK end, of each shift register alternately inputs two signals CKR and CKBR at each timing, and when the CK end of one of the two adjacent shift registers in the column direction inputs the CKR signal, the CK end of the other shift register inputs the CKBR signal.

[0123] In non-precharge type display devices, such as Figure 8 As shown, in the multiple shift registers arranged in cascade, the input end of the first-stage shift register is configured to be coupled to the start frame signal end; the output end of the previous-stage shift register in two adjacent stages of shift registers is coupled to the input end of the next-stage shift register; the effective values ​​of the drive signals output by the shift registers of different stages have no overlap in timing; the control end of the reset circuit and the control end of the undershoot forming unit in the Nth-stage shift register are both coupled to the output end of the N+1th-stage shift register, and the control end of the control circuit in the node control unit is coupled to the output end of the N+2th-stage shift register.

[0124] exist Figure 8In the embodiment, the STVL terminal corresponds to the input terminal of each odd-numbered shift register, the STVR terminal corresponds to the input terminal of each even-numbered shift register, the input terminal of the first-level shift register is configured to be coupled to the start frame signal terminal, i.e., the STVL terminal, and the input terminals of the other-level shift registers except the first-level are configured to be coupled to the output terminal of the previous-level shift register adjacent to the current-level shift register. For example, the input terminal of the N-th-level shift register is configured to be coupled to the output terminal of the N-1-th-level shift register, i.e., the OUT(N-1) terminal, where N is an integer greater than 1. The Rst terminal is the control terminal of the reset circuit, i.e., the control terminal of the fifth transistor T5, and the MLCLG terminal is the control terminal of the undershoot forming unit, i.e., the control terminal of the sixteenth transistor T16. The Rst terminal and the MLCLG terminal of the Nth stage shift register are both configured to be coupled to the output terminal of the N+1th stage shift register, i.e., the OUT(N+1) terminal. PDN is the control terminal of the control circuit in the node control unit, i.e., the control terminal of the third transistor T3, and is configured to be coupled to the output terminal of the N+2th stage shift register, i.e., the OUT(N+2) terminal. Here, N is an integer greater than or equal to 1.

[0125] See also Fig. 9 As shown, the timing of the non-precharge type display device is similar to the timing of the shift register in the above embodiment of the present application. The specific process is as follows:

[0126] In the t1 phase, STV is at a high level, the first pull-up node PU1 and the second pull-up node PU2 are charged to a high level, the low level of CKBL is transmitted to the drive signal output terminal OUT1, and the output drive signal G-OUT1 is at a low level. G-OUT2 and G-OUT3 are both at low levels, and the pull-down node PD is pulled down to a low level.

[0127] In the t2 stage, STV is converted to a low level, G-OUT2 and G-OUT3 are still at a low level, the second pull-up node PU2 maintains the high level of the t1 stage, the pull-down node PD maintains the low level of the t1 stage, CKL is a high level, G-OUT1 is converted from a low level to a high level, and under the bootstrap effect of the third capacitor C3, the first pull-up node PU1 is raised to a higher level.

[0128] In the t3 stage, G-OUT2 is converted to a high level, the first pull-up node PU1 is converted to a low level, G-OUT3 is still a low level, PU2 maintains the high level of the t2 stage, the pull-down node PD maintains the low level of the t2 stage, and the MLC pulls G-OUT1 down to the undershoot invalid potential VGL1, VGL1<VGL.

[0129] In stage t4, G-OUT2 maintains the high level of stage t3, the first pull-up node PU1 maintains the low level of stage t3, G-OUT3 is still at a low level, the second pull-up node PU2 maintains the high level of stage t2, the pull-down node PD maintains the low level of stage t2, MLC is converted from the undershoot invalid potential to the invalid potential, and G-OUT1 is converted from the undershoot invalid potential to the invalid potential.

[0130] In phase t5, G-OUT3 is converted to a high level, the second pull-up node PU2 is pulled down to a low level, the pull-down node PD is converted from a low level to a high level, G-OUT2 is converted to a low level, the first pull-up node PU1 is a low level, and G-OUT1 outputs a low level.

[0131] In a pre-charge type display device, such as Fig.10 As shown, in the multiple shift registers arranged in cascade, the input end of the first-stage shift register is configured to be coupled to the start frame signal end; the output end of the previous-stage shift register in two adjacent stages of shift registers is coupled to the input end of the next-stage shift register; the effective values ​​of the drive signals output by the shift registers of different stages overlap in timing; the control end of the reset circuit and the control end of the undershoot forming unit in the Nth-stage shift register are both coupled to the output end of the N+2th-stage shift register, and the control end of the control circuit in the node control unit is coupled to the output end of the N+3th-stage shift register.

[0132] exist Fig.10 In the embodiment, the STVL terminal corresponds to the input terminal of each odd-numbered shift register, the STVR terminal corresponds to the input terminal of each even-numbered shift register, the input terminal of the first-level shift register is configured to be coupled to the start frame signal terminal, i.e., the STVL terminal, and the input terminals of the other-level shift registers except the first-level are configured to be coupled to the output terminal of the previous-level shift register adjacent to the current-level shift register. For example, the input terminal of the N-th-level shift register is configured to be coupled to the output terminal of the N-1-th-level shift register, i.e., the OUT(N-1) terminal, where N is an integer greater than 1. The Rst terminal is the control terminal of the reset circuit, i.e., the control terminal of the fifth transistor T5, and the MLCLG terminal is the control terminal of the undershoot forming unit, i.e., the control terminal of the sixteenth transistor T16. The Rst terminal and the MLCLG terminal of the Nth stage shift register are both configured to be coupled to the output terminal of the N+2th stage shift register, i.e., the OUT(N+2) terminal. PDN is the control terminal of the control circuit in the node control unit, i.e., the control terminal of the third transistor T3, and is configured to be coupled to the output terminal of the N+3th stage shift register, i.e., the OUT(N+3) terminal. Here, N is an integer greater than or equal to 1.

[0133] See also Fig.11As shown, in a pre-charge type display device, the effective potentials of the drive signals of adjacent shift registers overlap in timing. When the drive signal of the previous shift register in two adjacent shift registers is provided to the input end of the next shift register, the next shift register has a corresponding pre-charge process.

[0134] Take the first-level shift register as an example for description, see Fig.12 As shown, Fig.12 This is a timing diagram of a pre-charge type display device provided by another embodiment of the present application. The specific process is as follows:

[0135] In the t1 phase, STV is at a high level, and G-OUT3, G-OUT4, and CKBL are all at a low level.

[0136] STV is at a high level, the first transistor T1 and the fourth transistor T4 are turned on, the second pull-up node PU2 and the first pull-up node PU1 are both pulled up to a high level, the second transistor T2 and the ninth transistor T9 are both turned on, and the seventh transistor T7 and the eighth transistor T8 are normally open, and the pull-down node PD is pulled down to a low level. The pull-down node PD is connected to the control end of the sixth transistor T6 and the fifteenth transistor T15, and the sixth transistor T6 and the fifteenth transistor T15 are turned off. G-OUT3 and G-OUT4 are both low levels, and the fifth transistor T5, the sixteenth transistor T16 and the third transistor T3 are all turned off. The control end of the twelfth transistor T12 is connected to a high level and is normally open, the first pull-up node PU1 turns on the fourteenth transistor T14, and the fourteenth transistor T14 transmits the low-level CKBL to the drive signal output terminal OUT1, and the output drive signal G-OUT1 is low.

[0137] In the t2 phase, STV switches to a low level, CKL is a high level, and G-OUT3 and G-OUT4 are both low levels.

[0138] STV is low level, the first transistor T1 and the fourth transistor T4 are turned off, G-OUT3 and G-OUT4 are both low level, the fifth transistor T5, the sixteenth transistor T16 and the third transistor T3, the second pull-up node PU2 maintains the high level of the t1 stage, the pull-down node PD maintains the low level of the t1 stage, the fourteenth transistor T14 is turned on, and the high level CKL is provided to the output terminal, and G-OUT1 is converted from a low level to a high level. Under the bootstrap effect of the third capacitor C3, the first pull-up node PU1 is raised to a higher level to ensure that at the t2 node, the gate voltage of the fourteenth transistor T14 is high enough and can be fully opened at the t2 node.

[0139] In the t3 phase, G-OUT3 switches to high level, CNB is low level, and STV and G-OUT4 are still low level.

[0140] G-OUT3 is at a high level, the fifth transistor T5 and the sixteenth transistor T16 are both turned on, and when the fifth transistor T5 is turned on, CNB pulls the first pull-up node PU1 down to a low level, and the ninth transistor T9 and the fourteenth transistor T14 are both turned off. G-OUT4 is at a low level, the third transistor T3 is turned off, the first capacitor C1 keeps the second pull-up node PU2 at a high level in the t2 stage, the second transistor T2 is turned on, the pull-down node PD is kept at a low level, the sixth transistor T6 and the fifteenth transistor T15 are turned off. The sixteenth transistor 16 is turned on, and the MLC pulls G-OUT1 down to the undershoot invalid potential VGL1, VGL1<VGL.

[0141] In the t4 stage, G-OUT3 maintains the high level of the t3 stage, MLC is converted from the undershoot invalid potential to the invalid potential, i.e., the low level, STV and CNB are low levels, and G-OUT4 outputs the high level of the first half under the action of pre-charging.

[0142] G-OUT3 is at a high level, the first pull-up node PU1 maintains the low level of the node t3, G-OUT4 is at a high level, the third transistor T3 is turned on, and the second level signal, namely VGL, is provided to the second pull-up node PU2, and the second pull-up node PU2 is converted to a low level. At this time, the second transistor T2 and the ninth transistor T9 are both turned off, the seventh transistor T7 and the eighth transistor T8 are normally turned on, and the pull-down node PD is converted to a high level. The pull-down node PD is coupled to the control end of the sixth transistor T6 and the fifteenth transistor T15, the sixth transistor T6 and the fifteenth transistor T15 are turned on, and the fifteenth transistor T15 is turned on to provide the second level signal VGL to the drive signal output terminal OUT1, and the output drive signal G-OUT1 is at a low level.

[0143] In the T5 stage, G-OUT4 outputs the high level of the second half, G-OUT3 is converted to a low level through the undershoot invalid level, and STV is still a low level.

[0144] G-OUT4 is at a high level, the second pull-up node PU2 maintains a low level in stage t4, the pull-down node PD maintains a high level in stage t4, the sixth transistor T6 and the fifteenth transistor T15 are turned on, the fifteenth transistor T15 is turned on to provide the second level signal VGL to the drive signal output terminal OUT1, and the output drive signal G-OUT1 is a low level.

[0145] The first pull-up node UP1 is at a low level, STV and G-OUT3 are at a low level, and the fourteenth transistor T14, the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the sixteenth transistor T16 are all turned off.

[0146] In another aspect of the present application, a display device is provided, which may include a gate drive circuit of any of the above embodiments. In some embodiments, the display device may use and Figure 8 or Fig.10 The same configuration as in the corresponding embodiment.

[0147] In some embodiments, the display device may include, but is not limited to, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo album, and the like.

[0148] Another aspect of the present application further provides a shift register driving method, which may include:

[0149] outputting a driving signal through a shift register unit;

[0150] The shift register unit responds to the first lower-level driving signal and is combined with the node control unit to control the output circuit of the shift register unit to be closed, and the undershoot forming unit responds to the first lower-level driving signal to convert the driving signal from the effective potential to the undershoot invalid potential; the voltage difference between the undershoot invalid potential and the effective potential is greater than the voltage difference between the invalid potential and the effective potential.

[0151] In some embodiments, see above Figure 7 , Fig. 9 or Fig.12 In the t2 phase, outputting the driving signal through the shift register unit may specifically be that the output circuit of the shift register unit outputs a high-level driving signal based on a high-level timing control signal.

[0152] In some embodiments, see above Figure 7 , Fig. 9 or Fig.12 In the t3 phase, the shift register unit responds to the first lower-level driving signal, the node control unit controls the output circuit of the shift register unit to be closed, and the undershoot forming unit responds to the first lower-level driving signal to convert the driving signal from the effective potential to the undershoot invalid potential. Specifically, the following steps can be performed:

[0153] The reset circuit of the shift register unit responds to the first lower-level driving signal to control the first pull-up node PU1 to be an invalid potential, i.e., a low level; the node control unit and the processing circuit of the shift register unit jointly control the pull-down node PD to maintain an invalid potential, and the output circuit of the shift register is controlled to be closed based on the invalid potential of the first pull-up node PU1 and the invalid potential of the pull-down node PD; and, the high-level driving signal output by the shift register unit in the t2 stage is converted to an undershoot invalid potential in response to the first lower-level driving signal through the undershoot forming unit.

[0154] In some embodiments, see above Figure 7 , Fig. 9 or Fig.12 In the t1 phase, the method may further include the charging circuit of the node control unit controlling the second pull-up node PU2 to be a valid potential in response to a signal at the input end of the shift register unit, the auxiliary pull-down circuit of the node control unit controlling the pull-down node PD to maintain an invalid potential in response to the valid potential of the second pull-up node PU2; and the shift register unit controlling the first pull-up node PU1 to be a valid potential in response to a signal at its input end.

[0155] In some embodiments, for non-precharge mode, see above Figure 7 or Fig. 9 In the t4 phase, the method may further include, in response to the first lower-level driving signal, converting the driving signal from the undershoot invalid potential to the invalid potential by the undershoot forming unit, wherein the duration of the undershoot invalid potential and the duration of the invalid potential are both shorter than the duration of the driving signal at the effective potential. For the pre-charging mode, see the above Fig.12 In the t4 phase, the method may further include the control circuit of the node control unit controlling the second pull-up node to be converted from a valid potential to an invalid potential in response to the high level of the first half of the second lower-level driving signal; the auxiliary pull-down circuit of the node control unit is turned off in response to the invalid potential of the second pull-up node PU2; the pull-down node PD is controlled to be converted from an invalid potential to a valid potential based on the invalid potential of the second pull-up node PU2; the output circuit of the shift register unit controls the output of a driving signal of an invalid potential based on the effective potential of the pull-down node; and the undershoot forming unit controls the output end to output a driving signal of an invalid potential based on the invalid potential of the undershoot signal end.

[0156] In some embodiments, see above Figure 7 , Fig. 9 or Fig.12 In the t5 stage, the method may further include the control circuit of the node control unit controlling the second pull-up node to be an invalid potential in response to the second lower-level driving signal; the auxiliary pull-down circuit of the node control unit is turned off in response to the invalid potential of the second pull-up node PU2; the pull-down node PD is controlled to be a valid potential based on the invalid potential of the second pull-up node PU2; and the output circuit of the shift register unit outputs a driving signal of an invalid potential based on the valid potential of the pull-down node.

[0157] The method can be implemented based on the shift register, gate drive circuit or display device of any of the above embodiments, and achieve the same beneficial effects.

[0158] So far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present application.

Claims

1. A shift register, characterized in that: It includes a shift register unit, an undershoot forming unit and a node control unit; The shift register unit is used to output a driving signal; The undershoot forming unit is coupled to the driving signal output terminal of the shift register unit, and is used to convert the driving signal from an effective potential to an undershoot invalid potential in response to a first lower-level driving signal; the voltage difference between the undershoot invalid potential and the effective potential is greater than the voltage difference between the invalid potential and the effective potential; The shift register unit includes an output circuit, and the shift register unit is further used to respond to the first lower-level driving signal and control the output circuit to be turned off in conjunction with the node control unit.

2. The shift register according to claim 1, characterized in that: The shift register unit further includes a reset circuit, a first pull-up node, a pull-down node and a processing circuit; The reset circuit is used for controlling the first pull-up node to be the invalid potential in response to the first lower-level driving signal; The node control unit and the processing circuit jointly control the pull-down node, and the node control unit is used to control the pull-down node to maintain the invalid potential when the first pull-up node is at the invalid potential; The output circuit is configured to be turned off in response to the invalid potential of the first pull-up node and the invalid potential of the pull-down node.

3. The shift register according to claim 2, characterized in that: The node control unit includes a charging circuit, a second pull-up node and an auxiliary pull-down circuit; The charging circuit is used for controlling the second pull-up node to be an effective potential in response to a signal at the input end of the shift register unit; The auxiliary pull-down circuit is used for controlling the pull-down node to maintain the invalid potential in response to the effective potential of the second pull-up node.

4. The shift register according to claim 3, characterized in that: The node control unit further comprises a control circuit, wherein the control circuit is used to control the second pull-up node to be converted from a valid potential to an invalid potential in response to a second lower-level driving signal; The auxiliary pull-down circuit is further configured to be turned off in response to an invalid potential of the second pull-up node; When the auxiliary pull-down circuit is turned off, the pull-down node is converted from the invalid potential to the valid potential; The output circuit is further configured to output a driving signal of an invalid potential based on the valid potential of the pull-down node.

5. The shift register according to claim 4, characterized in that: The charging circuit includes a first transistor and a first capacitor; The control end of the first transistor is connected to the input end, the first end of the first transistor is connected to the first level signal control end, and the second end of the first transistor is connected to the second pull-up node; A first end of the first capacitor is connected to the second pull-up node, and a second end of the first capacitor is connected to a second level signal input node of the processing circuit.

6. The shift register according to claim 4, characterized in that: The auxiliary pull-down circuit includes a second transistor; The control end of the second transistor is connected to the second pull-up node, the first end of the second transistor is connected to the pull-down node, and the second end of the second transistor is connected to the second level signal input node of the processing circuit.

7. The shift register according to claim 4, characterized in that: The control circuit includes a third transistor; The control end of the third transistor is connected to the second lower-level driving signal output end, the first end of the third transistor is connected to the second pull-up node, and the second end of the third transistor is connected to the second level signal control end.

8. The shift register according to any one of claims 2 to 7, characterized in that: The shift register unit further includes an input circuit, a first stabilization circuit and a second stabilization circuit; The input circuit is used to control the signal of the first pull-up node in response to the start frame signal or the upper drive signal provided by the input terminal; The first stabilization circuit is used to stably transmit the signal of the first pull-up node to the output circuit; The second stabilizing circuit is used to stably transmit the signal of the second pull-up node to the output circuit.

9. The shift register according to claim 8, characterized in that: The input circuit includes a fourth transistor, the control end of the fourth transistor is connected to the start frame signal end or the upper drive signal output end through the input end, the first end of the fourth transistor is connected to the third level signal control end, and the second end of the fourth transistor is connected to the first pull-up node.

10. The shift register according to claim 8, characterized in that: The reset circuit includes a fifth transistor, a control terminal of the fifth transistor is connected to the first lower-level driving signal output terminal, a first terminal of the fifth transistor is connected to the first pull-up node, and a second terminal of the fifth transistor is connected to the fourth level signal control terminal.

11. The shift register according to claim 8, characterized in that: The processing circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a second capacitor; The control end of the sixth transistor is connected to the pull-down node, the first end of the sixth transistor is connected to the first pull-up node, and the second end of the sixth transistor is connected to the second level signal input node; The control terminal and the first terminal of the seventh transistor are connected to the first level signal control terminal, and the second terminal of the seventh transistor is connected to the control terminal of the eighth transistor; The first end of the eighth transistor is connected to the first level signal control end, and the second end of the eighth transistor is connected to the pull-down node; The control end of the ninth transistor is connected to the first pull-up node, the first end of the ninth transistor is connected to the pull-down node, and the second end of the ninth transistor is connected to the second level signal input node; The control terminal of the tenth transistor is connected to the driving signal output terminal, the first terminal of the tenth transistor is connected to the pull-down node, and the second terminal of the tenth transistor is connected to the second level signal input node; The control terminal and the first terminal of the eleventh transistor are connected to the reset signal terminal, and the second terminal of the eleventh transistor is connected to the pull-down node; A first end of the second capacitor is connected to the pull-down node, and a second end of the second capacitor is connected to the second level signal input node.

12. The shift register according to claim 8, characterized in that: The first stabilization circuit includes a twelfth transistor, a control end of the twelfth transistor is connected to the first level signal control end, a first end of the twelfth transistor is connected to the drive signal output end through the output circuit, and a second end of the twelfth transistor is connected to the first pull-up node.

13. The shift register according to claim 8, characterized in that: The second stabilizing circuit includes a thirteenth transistor, a control terminal of the thirteenth transistor is connected to the reset signal terminal, a first terminal of the thirteenth transistor is connected to the second pull-up node, and a second terminal of the thirteenth transistor is connected to the second level signal input node.

14. The shift register according to claim 8, characterized in that: The output circuit includes a fourteenth transistor, a fifteenth transistor and a third capacitor; The control end of the fourteenth transistor is connected to the first pull-up node through the first stabilization circuit, the first end of the fourteenth transistor is connected to the timing control signal end, and the second end of the fourteenth transistor is connected to the driving signal output end; A first end of the third capacitor is connected to the control end of the fourteenth transistor, and a second end of the third capacitor is connected to the second end of the fourteenth transistor; The control end of the fifteenth transistor is connected to the pull-down node, the first end of the fifteenth transistor is connected to the driving signal output end, and the second end of the fifteenth transistor is connected to the second level signal input node.

15. The shift register according to claim 1, characterized in that: The undershoot forming unit includes a sixteenth transistor, a control terminal of the sixteenth transistor is connected to the first lower-level driving signal output terminal, a first terminal of the sixteenth transistor is connected to the driving signal output terminal, and a second terminal of the sixteenth transistor is connected to the undershoot signal terminal.

16. A gate drive circuit, characterized in that: The invention comprises a plurality of shift registers according to any one of claims 1 to 15, wherein the plurality of shift registers are arranged in cascade connection.

17. The gate driving circuit according to claim 16, characterized in that: In the plurality of shift registers arranged in cascade, the input end of the first shift register is configured to be coupled to the start frame signal end; the output end of the previous shift register in two adjacent shift registers is coupled to the input end of the next shift register; and the effective values ​​of the drive signals output by the shift registers of different stages do not overlap in timing; The control end of the reset circuit in the Nth stage shift register and the control end of the undershoot forming unit are coupled to the output end of the N+1th stage shift register, and the control end of the control circuit in the node control unit is coupled to the output end of the N+2th stage shift register.

18. The gate driving circuit according to claim 16, characterized in that: In the plurality of shift registers arranged in cascade, the input end of the first shift register is configured to be coupled to the start frame signal end; the output end of the previous shift register in two adjacent shift registers is coupled to the input end of the next shift register; and the effective values ​​of the drive signals output by the shift registers of different stages overlap in timing; The control end of the reset circuit in the Nth stage shift register and the control end of the undershoot forming unit are coupled to the output end of the N+2th stage shift register, and the control end of the control circuit in the node control unit is coupled to the output end of the N+3th stage shift register.

19. A display device, characterized in that: The gate drive circuit comprises the gate drive circuit as claimed in any one of claims 16 to 18.

20. A shift register driving method, characterized in that: include: outputting a driving signal through a shift register unit; The shift register unit responds to the first lower-level driving signal and is combined with a node control unit to control the output circuit of the shift register unit to be closed, and the undershoot forming unit responds to the first lower-level driving signal to convert the driving signal from an effective potential to an undershoot invalid potential; the voltage difference between the undershoot invalid potential and the effective potential is greater than the voltage difference between the invalid potential and the effective potential.

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