Three-dimensional integration process method of bump-free interface

Abstract

The invention discloses a three-dimensional integration process method of a bump-free interface, which is characterized in that a bump-free three-dimensional integration structure is constructed based on a silicon adapter plate, micro bumps and heterogeneous interfaces thereof are eliminated, many problems existing in a bump bonding process are avoided, three-dimensional stacking can obtain better electrical and mechanical properties, and meanwhile, more compact device layout is realized; the manufacturing method is beneficial to reducing the size of a device, and solves the problems of welding spot fatigue, resistance increase or electromigration caused by the challenges of large temperature change, high current density and the like by using a solder ball bump, so that the reliability and the performance stability are influenced, and the manufacturing cost is relatively high and accurate process control is needed by using a copper column bump. And the reliability problem of bonding fracture, pressure reduction or electrical performance degradation is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor process technology, and in particular to a three-dimensional integration process method without a bump interface. Background Art

[0002] Silicon interposer technology is a key technology developed to achieve high-density interconnection between chips, and is mainly used in advanced packaging and three-dimensional integration technologies. It allows multiple chips to be stacked vertically and interconnected through TSV (Through-Silicon Via), thereby promoting high-speed signal transmission and electrical interconnection, and improving system performance and reliability.

[0003] In recent years, with the increasing demand for high-density interconnects, bump bonding technology in silicon interposers is moving towards smaller pitches. As the bump pitch decreases, the need for solder is also decreasing, and solder may even be avoided completely to avoid the risk of bridging between bumps during solder melting.

[0004] There are two main existing technical methods:

[0005] One method is to use tin or tin alloy to form tiny solder balls, i.e., bumps, and then heat and press these bumps with the corresponding pads to achieve electrical connection. However, this method may cause problems such as solder joint fatigue, increased resistance or electromigration when faced with challenges such as large temperature changes and high current density, thus affecting reliability and performance stability.

[0006] Another method is to use copper as the bump material, form fine copper pillars on the chip or substrate by electroplating or other processing methods, and then connect them by welding or pressing. Although this method can meet the needs of high-density and high-speed interconnection, it has high manufacturing costs, requires precise process control (such as controlling pressure and temperature), and faces reliability issues such as bond breakage, pressure reduction, or electrical performance degradation. Summary of the invention

[0007] The present application provides a three-dimensional integrated process method without a bump interface, which solves the problem that the use of tin ball bumps will cause solder joint fatigue, increased resistance or electromigration when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The manufacturing cost of copper pillar bumps is high, precise process control is required, and there are reliability issues such as bond breakage, pressure reduction or electrical performance degradation.

[0008] In view of this, the present application provides a three-dimensional integration process method without a bump interface, the method comprising:

[0009] Step S1, preparing an insulating layer on the front side, the back side and the TSV corresponding side of the silicon adapter plate containing the TSV;

[0010] Step S2, preparing a mask barrier layer of a target pattern on the front and back sides of the silicon adapter plate and the front side of the corresponding substrate based on a lift-off process and a photolithography process;

[0011] Step S3, sequentially preparing a barrier layer and a metal seed layer on the front side, the back side and the TSV corresponding side of the silicon adapter plate;

[0012] Step S4, aligning and bonding the silicon adapter plate and the substrate to the target pattern through a permanent bonding process;

[0013] Step S5: achieving metal interconnection between the silicon adapter plate and the substrate through an electroplating process.

[0014] Optionally, the step S2 specifically includes:

[0015] The silicon wafer is bonded to the front and back surfaces of the silicon transfer plate simultaneously by using a temporary bonding adhesive;

[0016] Spin-coat photoresist on the front and back surfaces of the silicon adapter plate by a coating machine;

[0017] After the silicon adapter plate and the silicon wafer are debonded by thermal slip, the silicon adapter plate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process and a developing process to prepare a mask barrier layer of a target image on the front and back surfaces of the silicon adapter plate.

[0018] Optionally, the step S2 further includes:

[0019] Temporarily bonding the silicon wafer to the front side of the substrate by using a temporary bonding adhesive;

[0020] Spin coating photoresist on the front side of the substrate by a coating machine;

[0021] After the substrate and the silicon wafer are debonded by thermal slip, the substrate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process and a developing process to prepare a mask barrier layer of a target image on the front side of the substrate.

[0022] Optionally, the step S3 specifically includes:

[0023] Depositing a barrier layer on the front side, the back side and the TSV corresponding side of the silicon adapter by metal physical vapor deposition;

[0024] A metal seed layer is deposited on the barrier layer by metal physical vapor deposition.

[0025] Optionally, the step S3 further includes:

[0026] A metal seed layer is deposited on the front side of the substrate by metal physical vapor deposition.

[0027] Optionally, after step S3, the following steps are further included:

[0028] The mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate are removed by using a degumming liquid.

[0029] Optionally, after removing the mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate by using a degumming liquid, the method further comprises:

[0030] A bonding pattern of a target pattern is prepared on the substrate using a permanent bonding adhesive through an overlay process.

[0031] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0032] In the present application, a three-dimensional integration process method without a bump interface is provided, and a bump-free three-dimensional integrated structure is constructed based on a silicon adapter plate, which eliminates micro-bumps and their heterogeneous interfaces, avoids many problems existing in the bump bonding process, enables the three-dimensional stacking to obtain better electrical and mechanical performance, and at the same time realizes a more compact device layout, which is conducive to reducing the device size, and solves the problem that the use of tin ball bumps will cause solder joint fatigue, increased resistance or electromigration when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The use of copper pillar bumps has a high manufacturing cost, requires precise process control, and faces reliability problems such as bond breakage, pressure reduction or electrical performance degradation. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a method flow chart of a three-dimensional integration process method without a bump interface in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] The present application designs a three-dimensional integrated process method without a bump interface, which solves the problem that the use of tin ball bumps will cause solder joint fatigue, increased resistance or electromigration when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The manufacturing cost of copper pillar bumps is high, precise process control is required, and there are reliability issues such as bond breakage, pressure reduction or electrical performance degradation.

[0036] For easier understanding, see Figure 1 , Figure 1 Flow chart of the method of the three-dimensional integration process method without bump interface in the embodiment of the present application. Figure 1 As shown, specifically:

[0037] Step S1, preparing an insulating layer on the front side, the back side and the TSV corresponding side of the silicon adapter plate containing the TSV;

[0038] It should be noted that insulating layers are prepared on the front and back sides of the silicon adapter board and the surface corresponding to the TSV (Through-Silicon Via) to prevent electrical short circuits and provide mechanical support.

[0039] Insulating materials such as silicon dioxide (SiO2) or polyimide (PI) are usually deposited on designated areas of the silicon interposer using chemical vapor deposition (CVD) or physical vapor deposition (PVD) techniques.

[0040] Step S2, preparing a mask barrier layer of a target pattern on the front and back sides of the silicon adapter and the front side of the corresponding substrate based on a lift-off process and a photolithography process;

[0041] It should be noted that a mask barrier layer of a target pattern is prepared on the front and back sides of the silicon adapter and the front side of the corresponding substrate to control the subsequent metal deposition and form the required circuit pattern.

[0042] Lift-off process: First, a layer of photosensitive resin (photoresist) is coated on the surface of the silicon adapter plate and the substrate, and then the desired pattern is formed through mask exposure. The unexposed part is removed during the development process, leaving the desired pattern.

[0043] Photolithography process: Use a photolithography machine to transfer the pattern on the mask to the photoresist layer on the silicon adapter and substrate, and then use a developer to remove the unexposed photoresist to form a mask barrier layer.

[0044] Step S3, sequentially preparing a barrier layer and a metal seed layer on the front side, the back side and the TSV corresponding side of the silicon adapter plate;

[0045] It should be noted that the barrier layer and the metal seed layer are sequentially prepared on the front side, the back side and the TSV corresponding side of the silicon adapter to achieve good metal filling and electrical connection.

[0046] Barrier layer: A thin layer of metal or metal alloy, such as titanium (Ti) or tantalum (Ta), is deposited on the insulating layer, usually using PVD or CVD techniques, to prevent reaction between the metal and silicon.

[0047] Metal seed layer: A metal seed layer, such as copper (Cu) or nickel (Ni), is deposited on the barrier layer to provide conductivity for the subsequent electroplating process.

[0048] Step S4, aligning and bonding the silicon adapter plate and the substrate to the target pattern through a permanent bonding process;

[0049] It should be noted that the silicon adapter plate and the substrate are aligned and bonded to the target pattern through a permanent bonding process to achieve precise inter-layer alignment.

[0050] Using heat-activated or UV-activated bonding technology, the silicon interposer is tightly attached to the corresponding surface of the substrate to form a stable physical connection.

[0051] Step S5: achieving metal interconnection between the silicon adapter plate and the substrate through an electroplating process.

[0052] It should be noted that the metal interconnection between the silicon adapter plate and the substrate is achieved through the electroplating process to complete the three-dimensional integration.

[0053] The silicon interposer and substrate are placed in an electroplating tank, and metal is deposited on the metal seed layer through an electrochemical process to form the required circuit connections.

[0054] After electroplating is complete, excess metal and photoresist are removed, leaving behind a precise metal interconnect structure.

[0055] Furthermore, step S2 specifically includes:

[0056] The silicon wafer is bonded to the front and back surfaces of the silicon transfer board simultaneously by using a temporary bonding adhesive;

[0057] Spin-coat photoresist on the front and back sides of the silicon transfer board using a coating machine;

[0058] After the silicon adapter plate and the silicon wafer are debonded by thermal slip, the silicon adapter plate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process and a developing process to prepare a mask barrier layer of a target image on the front and back sides of the silicon adapter plate.

[0059] It should be noted that step S2 is a key step in the bumpless interface three-dimensional integration process, which involves temporary bonding of the silicon adapter and the silicon wafer, coating of photoresist, and preparation of mask barrier layers on the front and back sides of the silicon adapter through exposure and development processes. The following is a detailed description of this step:

[0060] Temporary bonding: First, use temporary bonding adhesive to temporarily bond the silicon wafer to the front and back of the silicon transfer board. This step is to provide necessary support and protection for the silicon transfer board in the subsequent process. The temporary bonding adhesive needs to have good bonding strength and controllable debonding characteristics to ensure that it can be debonded smoothly in the subsequent process without damaging the silicon transfer board or silicon wafer.

[0061] Spin coating photoresist: Next, the photoresist is spin coated on the front and back of the silicon adapter by a coating machine. Spin coating is a commonly used photoresist coating method that uses centrifugal force to evenly coat the photoresist on the surface of the silicon adapter. During the spin coating process, factors such as the viscosity of the photoresist, the centrifugal speed, the ambient temperature and humidity will affect the uniformity and thickness of the film.

[0062] Hot Slip Debonding: After the silicon interposer and the silicon wafer are bonded by temporary bonding adhesive, the two are debonded by hot slip debonding process. This step is to release the silicon wafer in the subsequent process for other process operations. Hot slip debonding is a commonly used debonding method that can soften the bonding material under specific temperature conditions to achieve debonding.

[0063] Pre-baking process: After the photoresist is coated, the pre-baking process is carried out. The purpose of pre-baking is to remove the solvent in the photoresist and make the photoresist drier and tougher. Pre-baking requires precise control of temperature and time to ensure that the photoresist reaches the best state.

[0064] Exposure process: After pre-baking, the exposure process is carried out. Exposure is to transfer the pattern on the mask to the photoresist on the surface of the silicon adapter through the light source. During the exposure process, the photosensitivity of the photoresist will change, thus forming a pattern corresponding to the mask.

[0065] Post-baking process: After exposure, post-baking process is carried out. The purpose of post-baking is to further solidify the photoresist, improve the chemical resistance and thermal stability of the photoresist, and prepare for the subsequent development process.

[0066] Development process: Finally, the development process is carried out. Development is to use a developer to dissolve the part of the photoresist that has changed due to exposure, thereby forming the desired pattern. The development process requires precise control of the developer concentration, temperature and development time to ensure accurate transfer of the pattern.

[0067] Through the above steps, a mask barrier layer of the target image can be prepared on the front and back sides of the silicon adapter, laying the foundation for subsequent metal interconnection and three-dimensional integration.

[0068] Furthermore, step S2 further includes:

[0069] Temporarily bonding the silicon wafer to the front side of the substrate by using a temporary bonding adhesive;

[0070] Spin-coat the photoresist on the front side of the substrate by a coating machine;

[0071] After the substrate and the silicon wafer are debonded by thermal slip, the substrate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process and a developing process to prepare a mask barrier layer of a target image on the front side of the substrate.

[0072] Furthermore, step S3 specifically includes:

[0073] Depositing a barrier layer on the front side, the back side and the TSV corresponding side of the silicon interposer by metal physical vapor deposition;

[0074] A metal seed layer is deposited on the barrier layer by metal physical vapor deposition.

[0075] It should be noted that step S3 is a key step in the bumpless interface three-dimensional integration process, which involves depositing a barrier layer and a metal seed layer on the front and back sides of the silicon adapter and the corresponding surface of the TSV (Through-Silicon Via). The following is a detailed description of this step:

[0076] Deposition barrier layer:

[0077] Purpose: The main function of the barrier layer is to prevent the metal from diffusing into the dielectric layer at high temperatures, so it must have high stability and good adhesion to the copper and dielectric layers.

[0078] Method: The barrier layer is deposited on the front and back sides of the silicon adapter and the TSV corresponding surface by metal physical vapor deposition (PVD). The physical vapor deposition process generally includes three process steps: (1) vaporization of the plating material: that is, the plating material evaporates, sublimates or is sputtered, that is, through the plating material vaporization source; (2) migration of plating atoms, molecules or ions: atoms, molecules or ions supplied by the vaporization source collide and produce various reactions; (3) plating atoms, molecules or ions are deposited on the substrate. In the through silicon via 3D packaging technology, the technologies for depositing barrier layers such as Ti-TiN, Ti-TiW and Ta-TaN follow the manufacturing technology of integrated circuits.

[0079] Deposition of metal seed layer:

[0080] Purpose: The main function of the metal seed layer is to provide a starting point for metal deposition in the subsequent electroplating process and ensure uniform growth of the metal layer.

[0081] Method: A metal seed layer is deposited on the barrier layer by metal physical vapor deposition (PVD). Usually TiC or TiN is deposited, argon (Ar) is filled under vacuum conditions, and the argon gas is glow discharged under high voltage, which can ionize argon (Ar) atoms into argon ions (Ar+). Under the action of the electric field force, the argon ions are accelerated to bombard the cathode target made of plating material, and the target material will be sputtered and deposited on the surface of the workpiece. For copper-filled TSV, the seed layer generally selects copper material to achieve a good electroplating effect.

[0082] In actual operation, physical vapor deposition (PVD) is a thin film preparation technology that physically transforms materials into gas phase in a vacuum environment and deposits them on the surface of the substrate. During the entire process, the vacuum environment can reduce the interference of gas molecules and ensure the quality and uniformity of the film. This method has the advantages of low deposition temperature and fast deposition speed, and is suitable for large-scale industrial production applications.

[0083] In addition, physical vapor deposition (PVD) technology has the advantages of high purity, uniformity and good adhesion in the preparation of high-quality films. Its vacuum deposition process effectively reduces impurities, improves material purity, and achieves precise thickness control and uniform distribution, ensuring the consistency of the film on a large area substrate. The strong adhesion of PVD films reduces the risk of peeling and damage, and is particularly suitable for the preparation of copper conductive and diffusion barrier layers, and has important application value.

[0084] Furthermore, step S3 also includes:

[0085] A metal seed layer is deposited on the front side of the substrate by metal physical vapor deposition.

[0086] Furthermore, after step S3, the following steps are further included:

[0087] The mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter and the substrate are removed by the degumming liquid.

[0088] It should be noted that in the semiconductor packaging process, debonding is a key step, which involves removing the mask barrier layer, excess barrier layer and metal seed layer on the silicon transfer board and substrate. The following is a detailed description of this process:

[0089] The degumming liquid (also called stripping liquid) is a solvent or solution used to remove the photoresist. The choice of degumming agent depends on the type of photoresist and the chemical stability of the substrate material. Common degumming liquids include acetone, NMP (1-methyl-2-pyrrolidone), NEP (nitroethylpyrrolidone), DMSO (dimethyl sulfoxide), etc.

[0090] Glue removal process:

[0091] Wet stripping: Use organic solvents or alkaline solutions to remove photoresists. Organic solvent stripping is achieved by dissolving the photoresist, while alkaline solutions remove the photoresist through chemical action. For example, 4% KOH solution can quickly remove phenolic resin-based photoresists.

[0092] Dry stripping: Use plasma to remove the photoresist. This method can remove the photoresist without contact with solvents, but there may be contamination problems caused by reaction residues.

[0093] Treatment after degumming:

[0094] After stripping, the silicon interposer and substrate are usually cleaned to remove any residual photoresist and stripping solution. This step is critical to ensure the quality of subsequent processes and avoid contamination.

[0095] Furthermore, after removing the mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate by the degumming liquid, the method further includes:

[0096] The bonding pattern of the target pattern is prepared on the substrate using a permanent bonding adhesive through an overlay process.

[0097] It should be noted that after the stripping process, a bonding pattern of the target pattern is prepared on the substrate using a permanent bonding adhesive through an overlay process. The overlay process is a precision alignment technology that ensures that the bonding pattern is accurately matched with the design drawing. This process usually involves using photolithography to form a pattern of permanent bonding adhesive on the substrate, and then curing the adhesive through heat treatment or ultraviolet light irradiation to form the desired bonding pattern.

[0098] Choice of permanent bonding adhesive:

[0099] Permanent bonding adhesive must have good thermal and chemical stability to withstand subsequent high temperature and chemical processes. In addition, the bonding adhesive should also have good fluidity and bonding strength to ensure the precise formation of the bonding pattern and a strong bond with the substrate.

[0100] Through the above steps, the mask blocking layer, excess barrier layer and metal seed layer on the silicon adapter and the substrate can be effectively removed, and a precise bonding pattern can be formed on the substrate, laying the foundation for the subsequent three-dimensional integration process.

[0101] In an embodiment of the present application, a three-dimensional integration process method with a bump-free interface is provided, and a bump-free three-dimensional integrated structure is constructed based on a silicon adapter plate, eliminating micro-bumps and their heterogeneous interfaces, avoiding many problems existing in the bump bonding process, enabling the three-dimensional stacking to obtain better electrical and mechanical performance, while achieving a more compact device layout, which is conducive to reducing the device size, and solving the problem of solder joint fatigue, increased resistance or electromigration caused by the use of tin ball bumps when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The manufacturing cost of copper pillar bumps is high, requires precise process control, and faces reliability problems such as bond breakage, pressure reduction or electrical performance degradation.

[0102] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0103] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0104] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0105] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0106] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0107] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0108] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (full name in English: Read-Only Memory, English abbreviation: ROM), random access memory (full name in English: Random Access Memory, English abbreviation: RAM), disk or optical disk and other media that can store program codes.

[0109] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A three-dimensional integration process method without a bump interface, characterized in that: include: Step S1, preparing an insulating layer on the front side, the back side and the TSV corresponding side of the silicon adapter plate containing the TSV; Step S2, preparing a mask barrier layer of a target pattern on the front and back sides of the silicon adapter plate and the front side of the corresponding substrate based on a lift-off process and a photolithography process; Step S3, sequentially preparing a barrier layer and a metal seed layer on the front side, the back side and the TSV corresponding side of the silicon adapter plate; Step S4, aligning and bonding the silicon adapter plate and the substrate to the target pattern through a permanent bonding process; Step S5: achieving metal interconnection between the silicon adapter plate and the substrate through an electroplating process.

2. The three-dimensional integration process method without bump interface according to claim 1, characterized in that: The step S2 specifically includes: The silicon wafer is bonded to the front and back surfaces of the silicon transfer plate simultaneously by using a temporary bonding adhesive; Spin-coat photoresist on the front and back surfaces of the silicon adapter plate by a coating machine; After the silicon adapter plate and the silicon wafer are debonded by thermal slip, the silicon adapter plate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process and a developing process to prepare a mask barrier layer of a target image on the front and back surfaces of the silicon adapter plate.

3. The three-dimensional integration process method without bump interface according to claim 2, characterized in that: The step S2 further comprises: Temporarily bonding the silicon wafer to the front side of the substrate by using a temporary bonding adhesive; Spin coating photoresist on the front side of the substrate by a coating machine; After the substrate and the silicon wafer are debonded by thermal slip, the substrate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process and a developing process to prepare a mask barrier layer of a target image on the front side of the substrate.

4. The three-dimensional integration process method without bump interface according to claim 1, characterized in that: The step S3 specifically includes: Depositing a barrier layer on the front side, the back side and the TSV corresponding side of the silicon adapter by metal physical vapor deposition; A metal seed layer is deposited on the barrier layer by metal physical vapor deposition.

5. The three-dimensional integration process method without bump interface according to claim 4, characterized in that: The step S3 further comprises: A metal seed layer is deposited on the front side of the substrate by metal physical vapor deposition.

6. The three-dimensional integration process method without bump interface according to claim 5, characterized in that: After step S3, the following steps are also included: The mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate are removed by using a degumming liquid.

7. The three-dimensional integration process method without bump interface according to claim 6, characterized in that: After removing the mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate by the degumming liquid, the method further comprises: A bonding pattern of a target pattern is prepared on the substrate using a permanent bonding adhesive through an overlay process.

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