Preparation method of chip packaging structure and chip packaging structure

Abstract

The invention provides a preparation method of a chip packaging structure and the chip packaging structure. The chip packaging structure comprises a first chip, a second protection layer, a second chip, a third protection layer, a first metal layer, a metal frame, a conductive connection structure and a polyimide layer, the second protection layer is located on one side, close to the second chip, of the first chip, and the polyimide layer is located on the side wall of the first chip; the second protection layer comprises a first opening and a second opening, the first conductive connection structure is arranged in the first opening, the second conductive connection structure is arranged in the second opening, the metal frames cover the second conductive connection structure, the third protection layer is located between the metal frames, and the second chip is in flip connection with the first chip through the first conductive connection structure. The first metal layer is electrically connected with the first chip through the metal frame and the second conductive connection structure. According to the invention, the size of the QFN packaging structure can be reduced, and the integration level is high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology and related technical fields, and in particular to a preparation method for a chip packaging structure and a chip packaging structure. Background Art

[0002] With the development of integrated circuit technology, there are requirements for high integration and high reliability of semiconductor chip packaging structures.

[0003] In the prior art, one packaging method for semiconductor chips is QFN packaging (Quad Flat No-leads Package). In this method, the semiconductor chip on the wafer is first cut and then packaged with a metal frame, and then the metal frame is connected to the Bonding Pad to achieve electrical connection with the external PCB circuit board. The volume of the semiconductor chip packaged with the metal frame is at least increased by 20% compared to the semiconductor chip after cutting. Summary of the invention

[0004] The embodiments described herein provide a method for preparing a chip packaging structure and a chip packaging structure, which are beneficial to reducing the size of the QFN packaging structure and have a higher degree of integration.

[0005] In a first aspect, according to the present disclosure, a method for preparing a chip packaging structure is provided, comprising:

[0006] Forming a second protective layer on the wafer, wherein the second protective layer includes a first opening and a second opening;

[0007] forming a first conductive connection structure in the first opening of the second protective layer, and after forming a second conductive connection structure at the second opening of the second protective layer, flip-chip connecting the chip to the wafer through the first conductive connection structure;

[0008] Forming a metal frame structure on a side of the second protective layer away from the wafer, wherein the metal frame structure covers the second conductive connection structure;

[0009] forming a third protective layer on a side of the metal frame structure away from the second protective layer;

[0010] At a cutting position between two adjacent chip packaging structures on a side of the wafer away from the second protective layer, the wafer is cut to form a cutting path, and polyimide is sprayed on the cutting path to form a polyimide layer on a side surface of the cutting path;

[0011] Grinding the third protective layer so that the third protective layer has the same height as the metal frame structure;

[0012] forming a first metal layer on a side of the third protective layer away from the second protective layer, wherein a vertical projection of the first metal layer on the wafer overlaps a vertical projection of the metal frame structure on the wafer;

[0013] The first metal layer, the metal frame structure and the second protection layer are cut at the cutting line positions to obtain a chip packaging structure.

[0014] In some embodiments of the present disclosure, before forming the first metal layer on the side of the third protective layer away from the second protective layer, the method further includes:

[0015] The metal frame structure is processed to form a step structure, and the step structure is away from one side of the chip.

[0016] In some embodiments of the present disclosure, before grinding the third protective layer so that the third protective layer has the same height as the metal frame structure, the method further includes:

[0017] A supporting layer is formed on a side of the first protective layer away from the wafer.

[0018] In some embodiments of the present disclosure, the method further comprises: cutting the wafer to form a cutting line at a cutting position between two adjacent chip packaging structures on a side of the wafer away from the second protective layer, and spraying polyimide on the cutting line. Before forming a polyimide layer on a side surface of the cutting line, the method further comprises:

[0019] Performing a thinning process on the wafer at a side of the wafer away from the second protective layer;

[0020] A first protective layer is formed on a side of the wafer away from the second protective layer.

[0021] In some embodiments of the present disclosure, before forming the first protective layer on the side of the wafer away from the second protective layer, the method further includes:

[0022] A second metal layer is formed on a side of the wafer away from the second protective layer.

[0023] In some embodiments of the present disclosure, the material of the first protective layer and the third protective layer is epoxy resin, and the material of the second protective layer is polyimide.

[0024] In a second aspect, according to the content of the present disclosure, there is provided a chip packaging structure, comprising: a wafer, a second protective layer, a chip, a third protective layer, a first metal layer, a metal frame structure, a conductive connection structure and a polyimide layer, wherein the conductive connection structure comprises a first conductive connection structure and a second conductive connection structure;

[0025] The first protective layer is located on a side of the wafer away from the chip, the second protective layer is located on a side of the wafer close to the chip, and the polyimide layer is located on a side wall of the wafer;

[0026] The second protective layer includes a first opening and a second opening, the first conductive connection structure is arranged in the first opening, the second conductive connection structure is arranged in the second opening, the metal frame structure covers the second conductive connection structure, the third protective layer is located between the metal frame structures, the first metal layer is located on the side of the metal frame structure away from the wafer, the vertical projection of the first metal layer on the wafer overlaps with the vertical projection of the metal frame structure on the wafer, the chip is electrically connected to the wafer through the first conductive connection structure, the first metal layer is electrically connected to the metal frame structure, the metal frame structure is electrically connected to the second conductive connection structure, and the second conductive connection structure is electrically connected to the wafer.

[0027] In some embodiments of the present disclosure, at least a portion of the metal frame structure includes a step structure, and the step structure is away from one side of the chip.

[0028] In some embodiments of the present disclosure, the thickness of the third protective layer is H1, the thickness of the chip is H2, and the height of the metal frame structure is H3, then H1, H2 and H3 satisfy: H2

[0029] In some embodiments of the present disclosure, a first protective layer and a second metal layer are further included, wherein the second metal layer is located on a side of the wafer away from the chip, and the first protective layer is located on a side of the second metal layer away from the wafer.

[0030] The preparation method of the chip packaging structure provided in the present invention is used for the preparation of the QFN packaging structure, which can package two chips together and achieve a higher degree of integration. In addition, in the preparation process, a metal structure including a plurality of metal frames is set on the wafer before cutting, and a polyimide layer is prepared on the side surface of the cutting path. Based on the properties of the polyimide layer, the particles of the polyimide are relatively small, and the thickness of the prepared polyimide layer is relatively thin. Therefore, the overall size of the chip packaging structure can be smaller. Furthermore, since the thickness of the prepared polyimide layer is relatively thin, the width of the cutting path needs to be narrower, which allows a larger number of chips to be accommodated on a wafer. Therefore, the preparation method of the chip packaging structure and the chip packaging structure provided in the embodiment of the present invention are conducive to reducing the size of the QFN packaging structure and achieving a higher degree of integration.

[0031] ​The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0033] Figure 1 is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present disclosure;

[0034] Figure 2A is a structural schematic diagram of another chip packaging structure provided by an embodiment of the present disclosure;

[0035] Figure 2B is a schematic diagram of a top view of a chip packaging structure provided by an embodiment of the present disclosure;

[0036] Figure 3 is a structural schematic diagram of another chip packaging structure provided by an embodiment of the present disclosure;

[0037] Figure 4 It is a schematic flow chart of a method for preparing a chip packaging structure provided by an embodiment of the present disclosure;

[0038] Figures 5A-5J is a process schematic diagram of a method for preparing a chip packaging structure provided by an embodiment of the present disclosure;

[0039] Figures 6A-6E It is a process schematic diagram of a method for preparing a chip packaging structure provided in an embodiment of the present disclosure.

[0040] Among them, 10, first protective layer; 20, first chip; 21, wafer; 30, second protective layer; 31, first opening; 32, second opening; 40, chip; 50, third protective layer; 60, first metal layer; 70, conductive connection structure; 71, first conductive connection structure; 72, second conductive connection structure; 80, metal frame; 81, metal structure; 82, third opening; 83, groove; 84, step structure; 90, second metal layer; 100, polyimide layer; 110, support layer.

[0041] In the drawings, reference numerals with the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] The term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0046] Furthermore, in all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0047] In the description of the present application, unless otherwise specified, "plurality" means more than two (including two), and similarly, "multiple groups" means more than two groups (including two).

[0048] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0049] Based on the problems existing in the prior art, the present disclosure provides a chip packaging structure. Figure 1 is a schematic diagram of the structure of the chip packaging structure provided by the embodiment of the present disclosure, such as Figure 1 As shown, the chip packaging structure includes: a first chip 20, a second protective layer 30, a second chip 40, a third protective layer 50, a first metal layer 60, a conductive connection structure 70, a metal frame 80 and a polyimide layer 100, the conductive connection structure 70 includes a first conductive connection structure 71 and a second conductive connection structure 72; the second protective layer 30 is located on a side of the first chip 20 close to the second chip 40, and the polyimide layer 100 is located on a side wall of the first chip 20; the second protective layer 30 includes a first opening 31 and a second opening 32, the first conductive connection structure 71 is arranged in the first opening 31, and the second conductive connection structure 72 is arranged in the second opening 32. 2 is disposed in the second opening 32, the metal frame 80 covers the second conductive connection structure 72, the third protection layer 50 is located between the metal frames 80, the first metal layer 60 is located on the side of the metal frame 80 away from the first chip 20, the vertical projection of the first metal layer 60 on the first chip 20 overlaps with the vertical projection of the metal frame 80 on the first chip 20, the second chip 40 is flip-chip connected to the first chip 20 through the first conductive connection structure 71, the first metal layer 60 is electrically connected to the metal frame 80, the metal frame 80 is electrically connected to the second conductive connection structure 72, and the second conductive connection structure 72 is electrically connected to the first chip 20.

[0050] In a specific embodiment, in combination with Figure 1 In the embodiment of the present disclosure, the prepared chip packaging structure includes a first chip 20 and a second chip 40, wherein the second chip 40 is a flip chip. The second chip 40 serves as the main control chip in the chip packaging structure provided by the embodiment of the present disclosure. The control logics of different functional modules in the first chip 20 are integrated on the second chip 40, and the first chip 20 is controlled by the second chip 40 to receive or output electrical signals. Specifically, the second chip 40 is electrically connected to the first metal layer through the first conductive connection structure 71, the first chip 20, the second conductive connection structure 72 and the metal frame 80, and then electrically connected to the external PCB circuit board through the first metal layer 60 to achieve output or reception of electrical signals. Compared with the prior art in which one chip is used to achieve reception or output of electrical signals of different functional modules, the chip packaging structure provided by the embodiment of the present disclosure has a higher degree of integration.

[0051] The chip packaging structure provided in the embodiment of the present disclosure is different from the traditional QFN chip packaging method (first cutting and then packaging). The chip packaging is completed in the process of preparing the chip. After cutting, it is a chip packaging structure without the need to perform the packaging process again. Compared with the prior art in which the chip packaging structure is formed by first cutting and then packaging, the overall volume of the chip packaging structure is reduced.

[0052] In a specific implementation manner, the specific structure of the chip packaging structure obtained based on the preparation process in the embodiment of the present disclosure is as follows: Figure 1 As shown, by setting a chip packaging structure including a first chip 20 and a second chip 40, the second chip 40 is electrically connected to the first chip 20 through a first conductive connection structure 71 in the first opening 31, the second chip 40 is smaller in size than the first chip 20, the first chip 20 is electrically connected to the first metal layer 60 through the second conductive connection structure 72 of the second opening 32 and the metal frame 80, and then electrically connected to the external PCB circuit board through the first metal layer 60. Specifically, after receiving the electrical signal transmitted by the external PCB circuit, the first metal layer 60 sends it to the first chip 20 through the metal frame 80 and the second conductive connection structure 72, the first chip 20 transmits it to the second chip 40 through the first conductive connection structure 71, or the second chip 40 outputs the electrical signal to the first chip 20 through the first conductive connection structure 71, the first chip 20 transmits the electrical signal output by the second chip 40 to the first metal layer 60 through the second conductive connection structure 72 and the metal frame 80, and outputs it through the electrical connection relationship between the first metal layer 60 and the external PCB circuit board.

[0053] In a specific implementation, the second protection layer 30 is located between the first chip 20 and the second chip 40 , and the second protection layer 30 serves as an insulation between the first chip 20 and the second chip 40 .

[0054] In the process of preparing the chip packaging structure, after cutting at the cutting position of two adjacent first chips on the side of the wafer away from the second protective layer by a cutting process, a polyimide layer 100 is formed on the side wall of the cut wafer by a process such as spraying to prevent the side wall of the cut first chip 20 from directly contacting the outside world. In addition, since the polyimide layer 100 is formed on the side surface of the cutting path, based on the properties of the polyimide layer 100, the particles of polyimide are relatively small, so the thickness of the prepared polyimide layer is thinner, and the overall volume of the prepared chip packaging structure is smaller.

[0055] In a specific implementation, the third protection layer 50 is disposed between the metal frames 80 , and the second chip 40 can be protected based on the third protection layer 50 and the second chip 40 can be insulated from the metal frame 80 based on the third protection layer 50 .

[0056] In a specific implementation, the metal frame 80 is provided to at least cover the second conductive connection structure 72 , so that the first metal layer 60 is electrically connected to the first chip 20 through the metal frame 80 and the second conductive connection structure 72 .

[0057] It should be noted that, in the embodiment of the present disclosure, the first conductive connection structure 71 set at the first opening 31 serves as a conductive connection structure between the first chip 20 and the second chip 40, and the second conductive connection structure 72 set at the second opening 32 serves as a conductive connection structure between the first chip 20 and the metal frame 80. In order to improve the overall integration of the chip packaging structure, the size of the second chip 40 is relatively small, and in order to improve the overall stability of the chip packaging structure, the metal frame 80 is set as wide as possible. Therefore, the first conductive connection structure 71 set at the first opening 31 is smaller in size than the second conductive connection structure 72 set at the second opening 32.

[0058] The chip packaging structure provided by the embodiment of the present disclosure includes a first chip, a second protective layer, a second chip, a third protective layer, a first metal layer, a metal frame, a conductive connection structure and a polyimide layer. The second chip is electrically connected to the first metal layer through the first conductive connection structure, the first chip, the second conductive connection structure and the metal frame structure. The second chip is flip-chip connected to the first chip through the first conductive connection structure, and then electrically connected to the external PCB circuit board through the first metal layer to achieve output or reception of electrical signals. The chip packaging structure provided by the embodiment of the present disclosure can realize chip packaging in the preparation process without the need to perform the packaging process after the preparation is completed. In the method for packaging the chip in the preparation process, a polyimide layer is prepared on the side surface of the cutting path. Based on the properties of the polyimide layer, the particles of polyimide are relatively small, and the thickness of the prepared polyimide layer is relatively thin, which is conducive to reducing the size of the QFN packaging structure and achieving higher integration.

[0059] In a specific embodiment, see Figure 1 The metal frame 80 includes a plurality of third openings 82 , and a vertical projection of any third opening 82 on the first chip 20 does not overlap with a vertical projection of the second opening 32 on the first chip 20 .

[0060] Specific, combined Figure 1 By setting the third opening 82 included in the metal frame 80 so that the vertical projection of the first chip 20 and the vertical projection of the second opening 32 on the first chip 20 do not overlap, a third protective layer 50 is formed in the third opening 82 of the metal frame 80, thereby achieving insulation between the second chip 40 and the metal frame 80 and electrical connection between the metal frame and the second conductive connection structure.

[0061] Specifically, the material of the metal frame 80 is a metal material with good electrical conductivity. Exemplarily, the material of the metal frame 80 includes copper.

[0062] In a specific embodiment, the metal frame 80 is disposed around the second chip 40 .

[0063] Specifically, the metal frame 80 serves as an integral frame of the chip packaging structure. By arranging the metal frame 80 around the second chip 40, the metal frame 80 serves as a supporting structure to provide space for flip-chip placement of the second chip 40, thereby improving the packaging of the chip packaging structure.

[0064] In a specific embodiment, Figure 2A is a schematic structural diagram of another chip packaging structure provided by an embodiment of the present disclosure, Figure 2B is a schematic diagram of a top view of a chip packaging structure provided by an embodiment of the present disclosure, such as Figure 2A and Figure 2B As shown, the metal frame is provided with a step structure 84 at the edge of the chip packaging structure.

[0065] Specifically, by setting a part of the metal frame 80 to include a step structure, after the first metal layer 60 is formed on the metal frame 80, during the process of electrical connection between the formed first metal layer 60 and the external PCB circuit board, a certain amount of metal tin will reflux and fall on the step structure 84, thereby improving the conductive connectivity between the first metal layer 60 and the external PCB circuit board.

[0066] It should be noted that Figure 2B The top view of the chip packaging structure before the first metal layer 60 is formed is exemplarily shown.

[0067] As a preferred embodiment, in the process of forming the step structure 84 on the metal frame 80, the metal structure is first processed to form a groove at the cutting line position between two adjacent first chips. When the cutting line is cut again, the groove after cutting forms a step structure 84, that is, the position of the step structure 84 does not overlap with the vertical projection of the first chip 20 and the vertical projection of the second opening 32 on the first chip 20.

[0068] In a specific embodiment, the thickness of the third protection layer 50 is H1, the thickness of the second chip 40 is H2, and the height of the metal frame 80 is H3, then H1, H2 and H3 satisfy: H2

[0069] Combination Figure 1 The thickness H1 of the third protective layer 50 is set to be the same as the height H3 of the metal frame 80, ensuring that the first metal layer 60 is electrically connected to the first chip 20 through the metal frame 80 and the second conductive connection structure 72, and the thickness H2 of the second chip 40 is set to be smaller than the height H3 of the metal frame 80, that is, the thickness H2 of the second chip 40 is smaller than the thickness H1 of the third protective layer 50, ensuring that the third protective layer 50 protects the chip.

[0070] Based on the above embodiments, Figure 3 is a schematic diagram of another chip packaging structure provided by an embodiment of the present disclosure, such as​ Figure 3 As shown, the chip packaging structure further includes a first protection layer 10 and a second metal layer 90 . The second metal layer 90 is located on a side of the first chip 20 away from the second chip 40 . The first protection layer 10 is located on a side of the second metal layer 90 away from the first chip 20 .

[0071] For details, see Figure 3 By setting the second metal layer 90 between the first protective layer 10 and the first chip 20, the second metal layer 90 acts as a heat-conducting layer to dissipate the heat generated by the first chip 20. The first protective layer 10 is set on the side of the second metal layer 90 away from the first chip 20. The first protective layer 10 is used to prevent the surface of the second metal layer 90 from directly contacting the outside, thereby protecting the second metal layer 90.

[0072] In a specific embodiment, the first protective layer 10, the second protective layer 30 and the third protective layer 50 are all insulating materials. In addition, the first protective layer 10 serves as a packaging structure for the first chip 20 away from the second chip 40, and the third protective layer 50 serves as a packaging structure for the second chip 40 away from the first chip 20.

[0073] It should be noted that, in the above embodiment, the materials of the first protective layer and the third protective layer have larger particles and higher hardness than the material of the second protective layer.

[0074] Furthermore, in the above embodiment, the materials of the first protective layer and the third protective layer are epoxy resin, and the material of the second protective layer is polyimide.

[0075] Based on the above embodiments, the present disclosure also provides a method for preparing a chip packaging structure. Figure 4 is a schematic diagram of a process for preparing a chip packaging structure provided by an embodiment of the present disclosure, Figure 5A-5J The process for preparing the chip packaging structure provided in the embodiment of the present disclosure is combined with Figure 1 , Figure 4 and Figure 5A-5J , the preparation method of the chip packaging structure includes:

[0076] S110 , forming a second protection layer on a wafer having a plurality of first chips.

[0077] The second protective layer includes a first opening and a second opening.

[0078] In a specific embodiment, in combination with Figure 5AFirst, a second protective layer 30 is formed on the first chip 20, and then a first opening 31 and a second opening 32 are formed on the second protective layer 30 by masking and other processes, wherein a flip-chip connection between the first chip 20 and the second chip 40 is realized at the position of the first opening 31, and an electrical connection between the first chip 20 and the first metal layer 60 is realized at the position of the second opening 32.

[0079] It should be noted that the first conductive connection structure 71 set in the first opening 31 serves as a conductive connection structure between the first chip 20 and the second chip 40, and the second conductive connection structure 72 set in the second opening 32 serves as a conductive connection structure between the first chip 20 and the metal frame 80. In order to improve the overall integration of the chip packaging structure, the size of the second chip 40 is relatively small, and in order to improve the overall stability of the chip packaging structure, the metal frame 80 is set as wide as possible. Therefore, the first conductive connection structure 71 set in the first opening 31 is smaller in size than the second conductive connection structure 72 set in the second opening 32.

[0080] S120, forming a first conductive connection structure in the first opening of the second protective layer, and after forming a second conductive connection structure at the second opening position of the second protective layer, flip-chip connecting the second chip to the first chip through the first conductive connection structure.

[0081] After forming the first opening 31 and the second opening 32 on the second protective layer 30, Figure 5B As shown, firstly, a third metal layer 301 (the material of the third metal layer is copper) is formed on the second protective layer 30, and the third metal layer 301 includes openings at positions corresponding to the first opening 31 and the second opening 32, and then solder paste is applied, such as Figure 5C As shown, a first conductive connection structure 71 is formed in the first opening 31, a second conductive connection structure 72 is formed in the second opening 32, and then the third metal layer 301 is removed. Figure 5D shown.

[0082] After the first conductive connection structure 71 is formed in the first opening 31, the second chip 40 is flip-chip connected at the first conductive connection structure 71. Figure 5E shown.

[0083] S130, disposing a metal structure including a plurality of metal frames on a side of the second protective layer away from the wafer, wherein the metal frames cover the second conductive connection structure.

[0084] Specifically, Figure 5EAs shown, by placing a metal structure 81 on the side of the first protective layer away from the wafer, the metal structure 81 includes a plurality of metal frames 80, and the metal frames 80 at least cover the second conductive connection structure, thereby providing a basis for the subsequent electrical connection of the first metal layer 60 with the first chip 20 through the metal frames 80 and the second conductive connection structure 72.

[0085] S140, forming a third protective layer on a side of the metal structure away from the second protective layer.

[0086] After the metal structure 81 is formed, a third protective layer 50 is formed. Fig. 5F The formed third protection layer 50 completely covers the metal structure 81 and the second chip 40 .

[0087] S150, cutting the wafer from a side of the wafer away from the second protective layer at a position between two adjacent first chips to form a cutting line, and spraying polyimide on the cutting line to form a polyimide layer on a surface of the cutting line.

[0088] In the preparation of Fig. 5F After the structure shown in FIG. 1 is formed, the wafer 21 is cut by a laser cutting process at a cutting position between two adjacent first chips 20 on a side of the wafer 21 away from the second protective layer to form a cutting path, and a polyimide layer is formed on the side surface of the cutting path by a spraying process, such as Figure 5G .

[0089] S160, grinding the third protective layer so that the third protective layer has the same height as the metal structure.

[0090] Since the plurality of first chips included in the wafer transmit electrical signals through the second conductive connection structure and the metal frame structure, the third protective layer 50 can be processed by chemical polishing or other processes so that the third protective layer 50 has the same height as the metal structure 81. Figure 5H .

[0091] S170, forming a first metal layer on a side of the third protective layer away from the second protective layer.

[0092] The vertical projection of the first metal layer on the wafer overlaps with the vertical projection of the metal structure on the wafer.

[0093] Then, a first metal layer 60 is formed by electroplating on the side of the third protective layer 50 away from the second protective layer 30. Specifically, the material of the first metal layer includes tin, such as Fig.5I .

[0094] S180, cutting the positions of the cutting paths again to obtain a plurality of separated chip packaging structures.

[0095] Finally, the position of the cutting path is cut again on the side of the first metal layer away from the third protective layer to obtain multiple phase-separated chip packaging structures, such as Figure 5J shown.

[0096] In a specific embodiment, the position of the cutting line is cut again on the side of the first metal layer away from the third protective layer to obtain a plurality of separated chip packaging structures, and the position of the cutting line is cut again using a physical cutting process. After the position of the cutting line is cut again, the entire chip is cleaned by a cleaning process to obtain a chip packaging structure.

[0097] It should be noted that in the above embodiment, in the process of cutting the wafer to form a cutting path from the side of the wafer away from the second protective layer, at the position between two adjacent first chips, based on the laser cutting process, it is inevitable that the second protective layer will be cut, but in the process of forming a polyimide layer on the surface of the cutting path (the formed polyimide layer is made of the same material as the second protective layer), a polyimide layer will also be formed on the second protective layer in the cutting path. Therefore, when the position of the cutting path is cut again to obtain a plurality of phase-separated chip packaging structures, the second cutting requires cutting the first metal layer, the metal structure and the polyimide layer.

[0098] The present disclosure provides a method for preparing a chip packaging structure, wherein the prepared chip packaging structure includes a first chip, a second protective layer, a second chip, a third protective layer, a first metal layer, a metal frame, a conductive connection structure and a polyimide layer. The second chip is electrically connected to the first metal layer via the first conductive connection structure, the first chip, the second conductive connection structure and the metal frame structure. The second chip is flip-chip connected to the first chip via the first conductive connection structure, and then electrically connected to an external PCB circuit board via the first metal layer to achieve output or reception of electrical signals. The chip packaging structure provided in the embodiment of the present disclosure can realize chip packaging in the preparation process, and there is no need to perform the packaging process after the preparation is completed. In the method of packaging the chip in the preparation process, a polyimide layer is prepared on the side surface of the cutting path. Based on the properties of the polyimide layer, the polyimide particles are relatively small, and the thickness of the prepared polyimide layer is thin. Therefore, the overall thickness of the chip packaging structure is small. Compared with the method of first cutting and then packaging the metal frame in the prior art (the overall thickness of the chip packaging structure prepared in this way is thicker), the preparation method of the chip packaging structure and the chip packaging structure provided in the embodiment of the present disclosure are conducive to reducing the size of the QFN packaging structure and having a higher degree of integration.

[0099] Based on the above embodiment, before executing step S150, the method further includes:

[0100] The wafer 21 is thinned on a side of the wafer 21 away from the second protective layer 30 ; and the first protective layer 10 is formed on a side of the wafer 21 away from the second protective layer 30 .

[0101] First, the wafer 21 is thinned on the side away from the second protective layer 30 to reduce the overall volume of the final chip packaging structure, and then the first protective layer 10 is formed on the side away from the second protective layer 30 of the wafer 21. Fig. 6A At this time, during the execution of step S150, at the cutting position between two adjacent first chips on the first protective layer away from the wafer, the first protective layer and the wafer are cut to form a cutting path, and polyimide is sprayed on the cutting path to form a polyimide layer on the side surface of the cutting path.

[0102] In addition, in the above embodiment, before the first protective layer is formed on the side of the wafer away from the second protective layer, the process further includes: forming a second metal layer 90 on the side of the wafer 21 away from the second protective layer 30 .

[0103] A second metal layer 90 is formed on the side of the wafer 21 away from the second protective layer 30. The metal layer 90 serves as a heat dissipation layer of the chip packaging structure. Figure 6B and 6C As shown, after the second metal layer is prepared, step S150-step S180 is performed. At this time, during the execution of step S150, the first protective layer, the second metal layer and the wafer are cut at the cutting position between two adjacent first chips on the side of the first protective layer away from the wafer to form a cutting path, and polyimide is sprayed on the cutting path to form a polyimide layer on the side surface of the cutting path.

[0104] In the embodiment of the present disclosure, the chip packaging structure formed by the above steps is a six-sided QFN chip packaging structure.

[0105] On the basis of the above embodiment, before executing step S160, it further includes: preparing a support layer on a side of the wafer away from the second protective layer.

[0106] After the wafer is cut to form a cutting path, a support layer 110 is first prepared on the side of the wafer 21 away from the second protective layer. The support layer 110 is a transparent adhesive. The support layer 110 is bonded to the uncut part of the wafer 21 to avoid deformation of the wafer to be cut. Fig.6D As shown, after the support layer 110 is prepared and formed, step S160 to step S180 are performed.

[0107] In a specific implementation, before executing step S160 , a support layer is prepared on a side of the wafer away from the second protective layer. At this time, after executing step S180 , the prepared chip packaging structure is separated from the support layer.

[0108] For example, the chip packaging structure formed by cutting can be sucked off the support layer by a suction nozzle to obtain the final chip packaging structure.

[0109] Specifically, the material of the support layer is a polymer synthetic material.

[0110] On the basis of the above embodiment, before executing step S170, the method further includes: processing the metal structure to form a groove at the location of the cutting path.

[0111] Specifically, Fig. 6E As shown, by preparing a groove 83 on a part of the metal structure 81, after the first metal layer is prepared on the metal structure 81, during the process of electrical connection between the prepared first metal layer 60 and the external PCB circuit board, a certain amount of metal tin will reflux and fall into the groove 83, thereby improving the conductive connectivity between the first metal layer 60 and the external PCB circuit board.

[0112] On the basis of the above embodiments, an embodiment of the present disclosure further provides an electronic device. The electronic device includes a chip packaging structure according to an embodiment of the present disclosure. The electronic device is, for example, an automotive electronic product or an intelligent terminal device, such as a tablet computer, a smart phone, etc.

[0113] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0114] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0115] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0116] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a chip packaging structure, characterized in that: include: Forming a second protective layer on a wafer having a plurality of first chips, wherein the second protective layer includes a first opening and a second opening; forming a first conductive connection structure in the first opening of the second protective layer, and after forming a second conductive connection structure at the second opening of the second protective layer, flip-chip connecting the second chip to the first chip on the wafer through the first conductive connection structure; A metal structure including a plurality of metal frames is arranged on a side of the second protective layer away from the wafer, wherein the metal frames cover the second conductive connection structure; forming a third protective layer on a side of the metal structure away from the second protective layer; Cutting the wafer to form a scribe line at a position between two adjacent first chips from a side of the wafer away from the second protective layer, and spraying polyimide on the scribe line to form a polyimide layer on a surface of the scribe line; Grinding the third protective layer so that the third protective layer has the same height as the metal structure; forming a first metal layer on a side of the third protective layer away from the second protective layer, wherein a vertical projection of the first metal layer on the wafer overlaps with a vertical projection of the metal structure on the wafer; The positions of the cutting paths are cut again to obtain a plurality of separated chip packaging structures.

2. The method according to claim 1, characterized in that: Before forming the first metal layer on the side of the third protective layer away from the second protective layer, the method further includes: The metal structure is processed to form grooves at the locations of the cutting streets.

3. The method according to claim 1, characterized in that Before grinding the third protective layer so that the third protective layer has the same height as the metal structure, the method further includes: Disposing a support layer on a side of the wafer away from the second protective layer; After cutting the first metal layer, the metal structure and the second protection layer at the position of the scribe line, the method further includes: separating the prepared chip packaging structure from the support layer.

4. The method according to claim 1, characterized in that: Cutting the wafer to form a scribe line at a position between two adjacent first chips from a side of the wafer away from the second protective layer, and spraying polyimide on the scribe line. Before forming a polyimide layer on a surface of the scribe line, the method further includes: Performing a thinning process on the wafer at a side of the wafer away from the second protective layer; A first protective layer is formed on a side of the wafer away from the second protective layer.

5. The method according to claim 4, characterized in that Before forming the first protective layer on the side of the wafer away from the second protective layer, the method further comprises: A second metal layer is formed on a side of the wafer away from the second protective layer.

6. The method according to claim 1, characterized in that The materials of the first protective layer and the third protective layer are epoxy resin, and the material of the second protective layer is polyimide.

7. A chip packaging structure, characterized in that: include: A first chip, a second protective layer, a second chip, a third protective layer, a first metal layer, a metal frame, a conductive connection structure and a polyimide layer, wherein the conductive connection structure includes a first conductive connection structure and a second conductive connection structure; The second protection layer is located on a side of the first chip close to the second chip, and the polyimide layer is located on a side wall of the first chip; The second protective layer includes a first opening and a second opening, the first conductive connection structure is arranged in the first opening, the second conductive connection structure is arranged in the second opening, the metal frame covers the second conductive connection structure, the third protective layer is located between the metal frames, the first metal layer is located on the side of the metal frame away from the first chip, the vertical projection of the first metal layer on the first chip overlaps with the vertical projection of the metal frame on the first chip, the second chip is flip-chip connected to the first chip through the first conductive connection structure, the first metal layer is electrically connected to the metal frame, the metal frame is electrically connected to the second conductive connection structure, and the second conductive connection structure is electrically connected to the first chip.

8. The chip packaging structure according to claim 7, characterized in that: The metal frame is arranged around the second chip; and the metal frame is provided with a step structure at an edge position of the chip packaging structure.

9. The chip packaging structure according to claim 7, characterized in that: The thickness of the third protective layer is H1, the thickness of the second chip is H2, and the height of the metal frame is H3, then H1, H2 and H3 satisfy: H2 <H1=H3。 10. The chip packaging structure according to claim 7, characterized in that: It also includes a first protection layer and a second metal layer, wherein the second metal layer is located on a side of the first chip away from the second chip, and the first protection layer is located on a side of the second metal layer away from the first chip.

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