Method and apparatus for fabricating and effectively etching a device structure

Abstract

The present application provides a method and apparatus for fabricating and effectively etching a device structure, relating to the technical field of semiconductor manufacturing processes, including: respectively determining a first etching rate of a hydrofluoric acid reagent for a silicon oxide layer and an oxidation isolation structure and a second etching rate of the hydrofluoric acid reagent for a silicon oxynitride layer, a third etching rate of a phosphoric acid reagent for the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent for a silicon nitride layer, and a fifth etching rate of the phosphoric acid reagent for the silicon oxide layer and the oxidation isolation structure; calculating a thickness of a part of the silicon oxynitride layer to be etched using the hydrofluoric acid reagent and a thickness of the remaining silicon oxynitride layer to be etched using the phosphoric acid reagent according to a target loss amount of the oxidation isolation structure, to obtain a total phosphoric acid etching time and a total hydrofluoric acid etching time that meet the required thickness of the oxidation isolation structure; using the phosphoric acid reagent and the hydrofluoric acid reagent to complete the etching of the wafer according to the corresponding etching times. The present application can achieve effective etching of the wafer while meeting the thickness requirements of the oxidation isolation structure.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor manufacturing processes, and particularly to a method and apparatus for fabricating and effectively etching a device structure. Background Art

[0002] As a commonly used device isolation technology in CMOS (Complementary Metal Oxide Semiconductor) silicon processes, LOCOS (LOCal Oxidation of Silicon) realizes the selective oxidation of silicon by using silicon nitride as a mask. Specifically, during the local oxidation of silicon, the area to be isolated is opened through photolithography and etching, and the isolated area is oxidized through a thermal oxidation process to form an oxide isolation structure, which from top to bottom is a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer, and a silicon substrate.

[0003] During the process of removing the above-mentioned film layers using an etchant, the conventional method is to use hydrofluoric acid to etch the upper silicon oxide layer of the structure, use hydrofluoric acid or hot phosphoric acid to etch the intermediate silicon oxynitride layer, and then use hot phosphoric acid to etch the underlying silicon nitride layer. Since hydrofluoric acid and phosphoric acid will also etch the silicon oxide on the oxide isolation structure during the etching process, making its thickness thinner and thinner, it is particularly important to select which reagent to use to etch the silicon oxynitride layer or how to combine hydrofluoric acid and hot phosphoric acid for the etching ratio of the silicon oxynitride layer, while ensuring the etching efficiency and reducing costs, and at the same time ensuring that the remaining thickness of the oxide isolation structure meets the device requirements, and at the same time being able to etch the silicon oxide layer, silicon oxynitride layer, and silicon nitride layer cleanly. Moreover, since the effective component ratio of fresh phosphoric acid changes during use, its etching rate for silicon oxynitride will change continuously with use, which further increases the difficulty of calculating the time required for etching silicon oxynitride by combining hydrofluoric acid and hot phosphoric acid.

[0004] In the practical process, an excessive etching method is often adopted, but the fact shows that even when using an excessive (excessive etching by 50 - 100%) etchant for etching, there will still be a phenomenon of incomplete etching, and excessive etching is extremely likely to cause excessive loss of the oxide layer of the oxide isolation structure, and the final remaining thickness after etching does not meet the standard. Since the requirements for the thickness of the isolation oxide layer on different integrated circuits will vary, the existing etching methods can not only not meet the requirements for the thickness of the isolation oxide layer of different integrated circuits, but also can not achieve freely adjusting the process according to different requirements to reach the remaining oxide isolation structure oxide layer thickness of different thicknesses. Summary of the Invention

[0005] In view of this, the purpose of the present application is to provide at least a method and device for manufacturing and effectively etching a device structure, which can calculate the thickness of silicon oxynitride to be etched by hydrofluoric acid and the thickness of silicon oxynitride to be etched by phosphoric acid within the upper limit of the thickness loss requirement of the oxidation isolation structure. At the same time, it can also calculate the etching time of hydrofluoric acid and phosphoric acid according to the used and new state of the current phosphoric acid, and can effectively etch the wafer while meeting the thickness loss requirement of the oxidation isolation structure.

[0006] The present application mainly includes the following aspects:

[0007] In a first aspect, the present application provides a method for manufacturing and effectively etching a device structure, including: providing a wafer after local isolation oxidation treatment, in which an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer, and a silicon substrate stacked in sequence from top to bottom are formed; measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, and the original thickness of the oxidation isolation structure; respectively determining the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer and the oxidation isolation structure, the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and the fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the oxidation isolation structure, where the third etching rate and the fifth etching rate vary with the continuous etching workload of phosphoric acid, and the continuous etching workload of phosphoric acid is the product of the cumulative number of wafers etched starting from new phosphoric acid and the time required for phosphoric acid to etch a single wafer; determining the target loss amount of the thickness of the oxidation isolation structure during continuous etching according to the original thickness of the oxidation isolation structure and the required thickness of the oxidation isolation structure; calculating the thickness and etching time of a part of the silicon oxynitride layer to be etched using the hydrofluoric acid reagent and the thickness and etching time of the remaining silicon oxynitride layer to be etched using the phosphoric acid reagent according to the target loss amount, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer, and the etching rate; obtaining the total hydrofluoric acid etching time for sequentially etching the silicon oxide layer and the silicon oxynitride layer using hydrofluoric acid and the total phosphoric acid etching time for sequentially etching the silicon oxynitride layer and the silicon nitride layer using phosphoric acid according to the thickness and etching time of the part of the silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer; using the phosphoric acid reagent and the hydrofluoric acid reagent to complete the etching of the silicon oxide layer, the silicon oxynitride layer, and the silicon nitride layer of the wafer according to the total hydrofluoric acid etching time and the total phosphoric acid etching time, and obtaining an oxidation isolation structure with the target thickness.

[0008] In a possible implementation manner, the total phosphoric acid etching time and the total hydrofluoric acid etching time to meet the required thickness of the oxidation isolation structure are determined by the following formula:

[0009] S = T(DHF3)×E a +T(HPO3)×f1(x)

[0010] In this formula, S represents the target loss amount corresponding to the oxidation isolation structure after the wafer etching is completed, and S = S 1 - S 2 , where S 1 represents the original thickness of the oxidation isolation structure before the wafer etching is carried out, and S 2 represents the required thickness of the oxidation isolation structure after the etching is completed, T(DHF3) represents the total etching time of hydrofluoric acid, and E a represents the first etching rate, T(HPO3) represents the total etching time of phosphoric acid, and f1(x) represents the fifth etching rate of the phosphoric acid fresh acid reagent on the oxidation isolation structure under the continuous etching workload x of phosphoric acid. The fifth etching rate changes as a function of the continuous etching workload x of phosphoric acid.

[0011] In a possible implementation manner, the total etching time of phosphoric acid and the total etching time of hydrofluoric acid are represented by the following formula:

[0012]

[0013] In this formula, T(DHF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer, T(DHF2) represents the etching time of the hydrofluoric acid reagent on a part of the silicon oxynitride layer, T(HPO1) represents the etching time of the phosphoric acid reagent on the silicon nitride layer, and T(HPO2) represents the etching time of the phosphoric acid reagent on the remaining silicon oxynitride layer.

[0014] In a possible implementation manner, the etching time of the hydrofluoric acid reagent on the silicon oxide layer is determined by the following formula:

[0015] T(DHF1) = (X / E a )

[0016] In this formula, X represents the thickness of the silicon oxide layer, and E a represents the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer.

[0017] In a possible implementation manner, the etching time of the hydrofluoric acid reagent on a part of the silicon oxynitride layer is determined by the following formula:

[0018] T(DHF2) = Z / E 1

[0019] In this formula, Z represents the thickness of the part of the silicon oxynitride layer etched with the hydrofluoric acid reagent, and E 1 represents the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer.

[0020] In a possible implementation manner, the etching time of the phosphoric acid reagent on the silicon nitride layer is determined by the following formula:

[0021] T(HPO1) = (Y / Eb )×n

[0022] In this formula, Y represents the thickness of the silicon nitride layer, and E b represents the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and n represents a given over-etching coefficient.

[0023] In a possible implementation, the etching time of the phosphoric acid reagent on the remaining silicon oxynitride layer is determined by the following formula:

[0024] T(HPO2) = (M - Z) / f2(x)

[0025] In this formula, M represents the thickness of the silicon oxynitride layer, f2(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous etching workload x of phosphoric acid, Z represents the thickness of the part of the silicon oxynitride layer etched by the hydrofluoric acid reagent, M - Z represents the thickness of the remaining silicon oxynitride layer after etching by the hydrofluoric acid reagent, and the remaining silicon oxynitride layer is etched by the phosphoric acid reagent.

[0026] In a possible implementation, the fifth etching rate of the phosphoric acid reagent on the oxidation isolation structure under the continuous etching workload x of phosphoric acid is determined by the following formula:

[0027] f1(x) = 9×10 -8 x 2 -0.0007x + 1.5945.

[0028] In a possible implementation, the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous etching workload x of phosphoric acid is determined by the following formula:

[0029] f2(x) = 10 -7 x 2 -0.0013x + 2.983.

[0030] Second aspect, an embodiment of the present application further provides a device structure manufacturing and effective etching apparatus, the apparatus comprising: a providing module configured to provide a wafer that has undergone local isolation oxidation treatment, an oxidation isolation structure, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer, and a silicon substrate are sequentially stacked from top to bottom in the wafer; a measuring module configured to measure the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, and the original thickness of the oxidation isolation structure; an etching rate determination module configured to respectively determine a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer and the oxidation isolation structure, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the oxidation isolation structure, wherein the third etching rate and the fifth etching rate vary with the continuous etching workload of the phosphoric acid, and the continuous etching workload of the phosphoric acid is the product of the number of wafers etched cumulatively starting from fresh phosphoric acid and the time required for the phosphoric acid to etch a single wafer; a loss amount determination module configured to determine a target loss amount of the thickness of the oxidation isolation structure during continuous etching according to the original thickness and the required thickness of the oxidation isolation structure; a first etching time determination module configured to respectively calculate the thickness and etching time of a part of the silicon oxynitride layer to be etched using the hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer to be etched using the phosphoric acid reagent according to the target loss amount, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer, and the etching rate; a second etching time determination module configured to obtain the total hydrofluoric acid etching time for sequentially etching the silicon oxide layer and the silicon oxynitride layer using hydrofluoric acid and the total phosphoric acid etching time for sequentially etching the silicon oxynitride layer and the silicon nitride layer using phosphoric acid according to the thickness and etching time of the part of the silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer; an etching module configured to use the phosphoric acid reagent and the hydrofluoric acid reagent to complete the etching of the silicon oxide layer, the silicon oxynitride layer, and the silicon nitride layer of the wafer according to the total hydrofluoric acid etching time and the total phosphoric acid etching time, and obtain an oxidation isolation structure with a target thickness.

[0031] A method and apparatus for fabricating and effectively etching a device structure provided by an embodiment of the present application include: respectively determining a first etching rate of a hydrofluoric acid reagent on a silicon oxide layer, a second etching rate of the hydrofluoric acid reagent on a silicon oxynitride layer, a third etching rate of a phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on a silicon nitride layer, and a fifth etching rate of the phosphoric acid reagent on an oxide isolation structure; according to a target loss amount value of the thickness of the oxide isolation structure during continuous etching, calculating and determining a thickness of a part of the silicon oxynitride to be etched by hydrofluoric acid and a thickness of the remaining silicon oxynitride to be etched by phosphoric acid, and further obtaining a total phosphoric acid etching time and a total hydrofluoric acid etching time that meet the required thickness of the oxide isolation structure; using the phosphoric acid reagent and the hydrofluoric acid reagent to complete the etching of the wafer according to the corresponding etching times. The method for fabricating and effectively etching the device structure provided by the present application realizes effective etching of the wafer while meeting the required thickness of the isolation structure.

[0032] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, provides detailed descriptions as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0034] Figure 1 Shows a schematic diagram of a local oxidation process of silicon provided by an embodiment of the present application;

[0035] Figure 2 Shows a schematic diagram of a silicon nitride removal process provided by an embodiment of the present application;

[0036] Figure 3 Shows a schematic diagram of a wafer structure obtained after a thermal oxidation process provided by an embodiment of the present application;

[0037] Figure 4 Shows a flowchart of a method for fabricating and effectively etching a device structure provided by an embodiment of the present application;

[0038] Figure 5 Shows a trend chart of the etching rate of a phosphoric acid reagent on silicon oxide with respect to the cumulative workload of newly used phosphoric acid (the product of the number of wafers etched cumulatively starting from newly used phosphoric acid and the time required for phosphoric acid to etch a single wafer);

[0039] Figure 6The figure shows a trend graph of the etching rate of a phosphoric acid reagent on silicon oxynitride with respect to the cumulative usage workload of fresh phosphoric acid (calculated from the start of fresh phosphoric acid as the product of the cumulative number of wafers etched and the time required for phosphoric acid to etch a single wafer).

[0040] Figure 7 The figure shows an effect diagram of wafer etching using a conventional etching method to remove the silicon nitride layer on a wafer.

[0041] Figure 8 The figure shows an effect diagram of wafer etching after removing the silicon nitride layer on a wafer by the method provided in this application according to an embodiment of this application.

[0042] Figure 9 The figure shows an effect diagram of a device structure slice after removing the silicon nitride layer on a wafer by the method provided in this application according to an embodiment of this application.

[0043] Figure 10 The figure shows a functional module diagram of the fabrication of a device structure and an effective etching device provided in an embodiment of this application.

[0044] Figure 11 The figure shows a schematic structural diagram of an electronic device provided in an embodiment of this application.

[0045] Symbol description in the figure: 101 is an oxide isolation structure; 102 is a silicon oxide layer; 103 is a silicon oxynitride layer; 104 is a silicon nitride layer; 105 is a pad oxide layer; 106 is a silicon substrate. Detailed implementation manners

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application. It should be understood that the accompanying drawings in this application are only for the purposes of illustration and description, and are not used to limit the protection scope of this application. Additionally, it should be understood that the schematic drawings are not drawn to actual scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of this application. It should be understood that the operations in the flowchart may not be implemented in sequence, and steps without a logical context relationship may be reversed in order or implemented simultaneously. Furthermore, those skilled in the art can add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of this application.

[0047] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Generally, the components of the embodiments of the present application described and illustrated in the accompanying drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but only represents the selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0048] Local oxidation of silicon, as a commonly used device isolation technology in CMOS silicon processes, realizes the selective oxidation of silicon through a silicon nitride mask. Please refer to Figure 1 , Figure 1 which shows a schematic diagram of a local oxidation of silicon process provided by an embodiment of the present application. As shown in B1, a pad oxide layer 105 and a silicon nitride layer 104 are first grown on a silicon substrate 106. As shown in B2, the area to be isolated is opened through photolithography and etching, and the area to be isolated is oxidized through a thermal oxidation process to form an oxide isolation structure 101. The component of the oxide isolation structure 101 is silicon oxide. Subsequently, a high-temperature phosphoric acid is used as an etchant to remove the silicon nitride layer 104, and a device structure with isolation function as shown in B4 is obtained.

[0049] Hydrofluoric acid is a conventional reagent for etching silicon oxide, and phosphoric acid is a conventional reagent for etching silicon nitride. Both hydrofluoric acid and phosphoric acid can etch silicon oxynitride.

[0050] Please refer to Figure 2 , Figure 2 which shows a schematic diagram of a silicon nitride removal process provided by an embodiment of the present application. As shown in Figure 1 and Figure 2 , during the removal process of the silicon nitride layer 104 shown in B3 - B4, the conventional removal method of the silicon nitride layer 104 is to first use hydrofluoric acid to remove the silicon oxide layer 102 formed on the surface of the silicon nitride layer, then rinse off the hydrofluoric acid with water, then use phosphoric acid to remove the silicon nitride layer 104, and finally rinse off the phosphoric acid with water.

[0051] During the process of etching away the silicon nitride layer 104 with phosphoric acid, the conventional practice is to remove the silicon nitride layer 104 with an excessive amount of phosphoric acid. However, facts have shown that even when an excessive amount (excessive etching by 50 - 100%) of phosphoric acid is used to remove the silicon nitride layer 104, there will still be a phenomenon of incomplete etching during the actual etching process.

[0052] Please refer to Figure 3 , Figure 3 which shows a schematic diagram of a wafer structure obtained after a thermal oxidation process provided by an embodiment of the present application. As shown in Figure 1and Figure 3 As shown in B2 - B3, during the process of forming the oxidation isolation structure 101, when the area to be isolated is oxidized through a thermal oxidation process, the silicon nitride layer 104 is affected by the thermal oxidation process, and a silicon oxide layer 102 is formed on the upper surface of the silicon nitride layer 104. A very thin silicon oxynitride layer 103 will be formed between the silicon oxide layer 102 and the silicon nitride layer 104. Due to the existence of the silicon oxynitride layer 103, hydrofluoric acid or phosphoric acid can be selectively used for etching, but the etching rates of the two are inconsistent, which will lead to different etching times.

[0053] In addition, since the oxidation isolation structure 101 is composed of silicon oxide, during the etching process of the silicon oxide layer 102, the silicon oxynitride layer 103, and the silicon nitride layer 104, both hydrofluoric acid and phosphoric acid will etch the oxidation isolation structure 101. Since the integrated circuit has certain requirements for the thickness of the oxidation isolation structure 101 corresponding to the wafer, the existing etching methods can neither effectively remove the silicon nitride nor meet the control of the thickness of the oxidation isolation structure, ultimately resulting in abnormal device structures.

[0054] Based on this, the embodiments of the present application provide a method, device, and electronic device for manufacturing and effectively etching a device structure. By meeting the thickness loss requirements of the isolation structure, effective etching of the wafer is achieved, specifically as follows:

[0055] Please refer to Figure 4 , Figure 4 which shows a flowchart of a method for manufacturing and effectively etching a device structure provided by the embodiments of the present application. As shown in Figure 4 and Figure 3 , the method provided by the embodiments of the present application includes the following steps:

[0056] S100: Provide a wafer that has undergone local isolation oxidation treatment.

[0057] An oxidation isolation structure, a silicon oxide layer 102, a silicon oxynitride layer 103, a silicon nitride layer 104, a pad oxide layer 105, and a silicon substrate 106 are sequentially stacked from top to bottom in the wafer.

[0058] S200: Measure the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, and the original thickness of the oxidation isolation structure.

[0059] The thickness of the silicon oxide layer is the thickness corresponding to the silicon oxide layer 102, and the thickness of the silicon nitride layer is the thickness corresponding to the silicon nitride layer 104.

[0060] S300. Determine the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer and the oxidation isolation structure, the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and the fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the oxidation isolation structure respectively.

[0061] Among them, the third etching rate and the fifth etching rate vary with the continuous etching workload of the phosphoric acid. The continuous etching workload of the phosphoric acid is the product of the cumulative number of wafers etched starting from the fresh phosphoric acid and the time required for the phosphoric acid to etch a single wafer.

[0062] S400. Determine the target loss amount of the thickness of the oxidation isolation structure during the continuous etching process according to the original thickness and the required thickness of the oxidation isolation structure.

[0063] S500. Calculate the thickness and etching time of the partial silicon oxynitride layer that needs to be etched with the hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched with the phosphoric acid reagent respectively according to the target loss amount, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer and the etching rate.

[0064] The etching rate includes the first etching rate, the second etching rate, the third etching rate, the fourth etching rate and the fifth etching rate.

[0065] S600. Obtain the total hydrofluoric acid etching time for sequentially etching the silicon oxide layer and the silicon oxynitride layer with the hydrofluoric acid and the total phosphoric acid etching time for sequentially etching the silicon oxynitride layer and the silicon nitride layer with the phosphoric acid according to the thickness and etching time of the partial silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer.

[0066] S700. Use the phosphoric acid reagent and the hydrofluoric acid reagent to complete the etching of the silicon oxide layer, the silicon oxynitride layer and the silicon nitride layer of the wafer according to the total hydrofluoric acid etching time and the total phosphoric acid etching time, and obtain the oxidation isolation structure with the target thickness.

[0067] In step S500, according to the thickness of the silicon oxide layer 102, the thickness of the silicon nitride layer 104, the thickness of the silicon oxynitride layer 103, the original thickness S of the oxidation isolation structure 1 and the target required thickness S of the oxidation isolation structure 2 , the first etching rate, the second etching rate, the third etching rate, the fourth etching rate and the fifth etching rate, calculate the thickness and etching time of the partial silicon oxynitride layer in the silicon oxynitride layer 103 that needs to be etched with the hydrofluoric acid, and then calculate the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched with the phosphoric acid, and further determine the total phosphoric acid etching time and the total hydrofluoric acid etching time that meet the required thickness S of the oxidation isolation structure 2 .

[0068] In local oxidation isolation technology, the following reactions occur in the silicon nitride layer on the wafer during the thermal oxidation process:

[0069] Si 3 N 4 (s) + 3 / 2O 2 (g) → 3SiO(g) + 2N 2 (g) ------ A.1

[0070] Si 3 N 4 (s) + 3O 2 (g) → 3SiO 2 (g) + 2N 2 (g) ------ A.2

[0071] Si 3 N 4 (s) + 5O 2 (g) → 3SiO 2 (g) + 4NO(g) ------ A.3

[0072] 4Si 3 N 4 (s) + 3O 2 (g) → 6Si 2 N 2 (s) + 2N 2 (g) ------ A.4

[0073] As can be seen from chemical equations A.1 to A.3, during the formation of the oxidation isolation structure in the thermal oxidation process of the silicon nitride layer, the surface of the silicon nitride layer 104 is affected by the thermal oxidation of silicon dioxide, and a silicon dioxide layer 102 will be formed on the surface of the silicon nitride layer 104. And as can be seen from chemical equation A.4, on the surface of the silicon nitride layer 104 during thermal oxidation growth with oxygen O 2 or hydrogen H 2 at a certain temperature condition (for example, the temperature is between 700 °C and 1180 °C), an interface layer, namely the silicon oxynitride layer 103, can be formed between the silicon dioxide layer 102 and the silicon nitride layer 104. The silicon oxynitride layer 103 is the conversion layer at the interface during the oxidation of silicon nitride. In the prior art, phosphoric acid is reused, and its effective components will gradually change with use. Therefore, the etching rate of the film layer also changes continuously with use.

[0074] In the process of removing the silicon nitride layer 104, first, hydrofluoric acid is used to remove the silicon oxide layer 102, and then phosphoric acid is used to remove the silicon nitride layer 104. Considering the silicon oxynitride layer 103 formed between the silicon nitride layer 104 and the silicon oxide layer 102 and the reuse of phosphoric acid, when the hydrofluoric acid used is not sufficient to etch away the silicon oxynitride layer 103, the silicon oxynitride layer 103 will be affected by the newness and oldness of the subsequent phosphoric acid reagent, and as a result, the silicon nitride cannot be effectively removed directly.

[0075] Based on this, in steps S100 to S700 provided in this application, in the process of removing the silicon nitride layer 104, through the thickness of the silicon oxide layer 102, the thickness of the silicon nitride layer 104, and the required thickness of the given oxidation isolation structure, on the premise of simultaneously meeting the required thickness of the oxidation isolation structure, the time for hydrofluoric acid to etch the silicon oxide layer 102, the thickness and etching time of a part of the silicon oxynitride layer that needs to be etched away by hydrofluoric acid, the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched away by phosphoric acid, and the etching time for phosphoric acid to etch the silicon nitride layer 104 are calculated. Then, the total etching time of hydrofluoric acid and the total etching time of phosphoric acid are further calculated. Phosphoric acid reagent and hydrofluoric acid reagent are used to remove the silicon oxide layer 102, the silicon oxynitride layer 103, and the silicon nitride layer 104 in sequence according to the total etching time of hydrofluoric acid and the total etching time of phosphoric acid, completing the etching of the wafer. In this process, the corresponding ratio of the total etching time of phosphoric acid and the total etching time of hydrofluoric acid is restricted by the required thickness of the oxidation isolation structure, so that when the finally obtained total etching time of phosphoric acid and the total etching time of hydrofluoric acid are used to remove silicon oxide, silicon oxynitride, and silicon nitride, not only can the silicon nitride layer be effectively removed finally, but also the required thickness of the oxidation isolation structure can be accurately controlled further to meet the different requirements of different integrated devices for the thickness of the oxidation isolation structure.

[0076] As Figure 3 shown, after the wafer undergoes the thermal oxidation process, an oxidation isolation structure 101, a silicon oxide layer 102, a silicon oxynitride layer 103, a silicon nitride layer 104, a pad oxide layer 105, and a silicon substrate 106 are formed. In step S200, the silicon nitride layer 104 and the silicon oxide layer 102 are measured to obtain the thickness X of the silicon oxide layer, the thickness Y of the silicon nitride layer, and the thickness M of the silicon oxynitride layer. Since the silicon oxynitride layer 103 is relatively thin and difficult to measure, according to experience, the general range corresponding to the thickness M of the silicon oxynitride layer is ( represents the length unit angstrom).

[0077] In addition, the thickness of the oxidation isolation structure also needs to be measured to obtain the original thickness S of the oxidation isolation structure before etching. 1 。

[0078] In step S300, through the analysis of the usage of the phosphoric acid reagent and the hydrofluoric acid reagent, it can be known that the first etching rate E of the hydrofluoric acid reagent on the silicon oxide layer 102 a , the fourth etching rate E of the phosphoric acid reagent on the silicon nitride layer 104 b , and the second etching rate E of the hydrofluoric acid reagent on the silicon oxynitride layer 103 1 are generally regularly stable and can be obtained through pre-tests. Generally, the second etching rate (angstroms per minute).

[0079] Specifically, before performing step S500, it is also necessary to preset a given over-etching coefficient n in advance and determine the continuous phosphoric acid etching workload x corresponding to the new phosphoric acid reagent. The continuous phosphoric acid etching workload x is the product of the number of wafers etched cumulatively starting from the new phosphoric acid and the time required for the phosphoric acid to etch a single wafer. Among them, the given over-etching coefficient n usually takes a value of 1.2 to 2 and can be set according to actual requirements. The continuous phosphoric acid etching workload x reflects the newness and oldness of the phosphoric acid. The continuous phosphoric acid etching workload x = the time for the phosphoric acid to etch a single wafer × the number of wafers etched cumulatively. The unit corresponding to the time for the phosphoric acid to etch a single wafer is minutes (min).

[0080] In step S400, it is also necessary to determine the required thickness S of the oxidation isolation structure 2 . According to the required thickness S of the oxidation isolation structure 2 and the original thickness S of the oxidation isolation structure 1 , the target loss amount of the thickness of the oxidation isolation structure during continuous etching is calculated as S = S 1 - S 2 .

[0081] In a preferred embodiment, in step S400, the total phosphoric acid etching time and the total hydrofluoric acid etching time that meet the required thickness of the oxidation isolation structure are determined through the following formula:

[0082] S = T(DHF3) × E a + T(HPO3) × f1(x) (1)

[0083] In formula (1), S represents the target loss amount corresponding to the oxidation isolation structure after wafer etching is completed, S = S 1 - S 2 , S 1 represents the original thickness of the oxidation isolation structure before wafer etching, S 2 represents the required thickness of the oxidation isolation structure after etching is completed, T(DHF3) represents the total hydrofluoric acid etching time, and E aE represents the first etching rate, T(HPO3) represents the total etching time of phosphoric acid, f1(x) represents the fifth etching rate of the phosphoric acid new acid reagent on the oxidation isolation structure under the continuous etching workload x of phosphoric acid, and the fifth etching rate changes as a function of the continuous etching workload x of phosphoric acid.

[0084] Among them, the first etching rate E a is pre-given. In this application, since the oxidation isolation structure is formed by the formation of the pad oxide layer 105, therefore, the first change data of the etching rate of the phosphoric acid reagent on silicon oxide with the continuous etching workload of phosphoric acid is collected in advance. According to the first change data, the first curve of the etching rate of the phosphoric acid reagent on silicon oxide with the continuous etching workload of phosphoric acid is plotted. According to the first curve, the first function expression for determining the fifth etching rate is created, where:

[0085] f1(x) = 9×10 -8 x 2 -0.0007x + 1.5945 (2)

[0086] Please refer to Figure 5 , Figure 5 which shows the change trend diagram of the etching rate of a phosphoric acid reagent on silicon oxide provided by the embodiment of the present application with the cumulative usage workload of the phosphoric acid new acid (the product of the number of wafers etched cumulatively from the start of the phosphoric acid new acid and the time required for the phosphoric acid to etch a single wafer). As Figure 5 shown, the abscissa is the continuous etching workload x of phosphoric acid, that is, the product of the number of wafers etched cumulatively from the start of the phosphoric acid new acid and the time required for the phosphoric acid to etch a single wafer, and the ordinate represents the etching rate of the phosphoric acid reagent on silicon oxide. The unit of the etching rate is (angstroms / minute), L1 represents the first curve of the etching rate of the phosphoric acid reagent on silicon oxide with the continuous etching workload of phosphoric acid, and the corresponding function expression of f1(x) created from the first curve L1 is:

[0087] f1(x) = 9×10 -8 x 2 -0.0007x + 1.5945

[0088] Because the component of the oxidation isolation structure is silicon oxide, therefore, substituting the continuous etching workload x of phosphoric acid into f1(x) = 9×10 -8 x 2 -0.0007x + 1.5945, the fifth etching rate of the phosphoric acid reagent on the oxidation isolation structure under the continuous etching workload x of phosphoric acid can be obtained.

[0089] In a preferred embodiment, the total etching time of phosphoric acid is represented by the following formula:

[0090] T(DHF3) = T(DHF1) + T(DHF2) (3)

[0091] In formula (3), T(DHF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer 102, and T(DHF2) represents the etching time of the hydrofluoric acid reagent on a part of the silicon oxynitride layer. The total etching time of the hydrofluoric acid is the sum of the etching time T(DHF1) of the hydrofluoric acid reagent on the silicon oxide layer 102 and the etching time T(DHF2) of the hydrofluoric acid reagent on a part of the silicon oxynitride layer.

[0092] In a specific embodiment, the etching time T(DHF1) of the hydrofluoric acid reagent on the silicon oxide layer 102 is determined by the following formula:

[0093] T(DHF1) = (X / E a ) (4)

[0094] In formula (4), X represents the thickness of the silicon oxide layer 102, and E a represents the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer 102.

[0095] In a specific embodiment, the first etching rate E a is given in advance. The first etching rate

[0096] In another preferred embodiment, the etching time T(DHF2) of the hydrofluoric acid reagent on a part of the silicon oxynitride layer is determined by the following formula:

[0097] T(DHF2) = Z / E 1 (5)

[0098] In formula (5), Z represents the thickness of the part of the silicon oxynitride layer etched with the hydrofluoric acid reagent, and E 1 represents the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer.

[0099] Generally, the second etching rate is stable at

[0100] In a preferred embodiment, the total etching time T(HPO3) of phosphoric acid is represented by the following formula:

[0101] T(HPO3) = T(HPO1) + T(HPO2) (6)

[0102] In formula (6), T(HPO1) represents the etching time of the phosphoric acid reagent on the silicon nitride layer 104, T(HPO2) represents the etching time of the phosphoric acid reagent on the remaining silicon oxynitride layer, and the total etching time of phosphoric acid T(HPO3) is the sum of the etching time T(HPO1) of the phosphoric acid reagent on the silicon nitride layer and the etching time T(HPO2) of the phosphoric acid reagent on the remaining silicon oxynitride layer.

[0103] In a preferred embodiment, the etching time T(HPO1) of the phosphoric acid reagent on the silicon nitride layer is determined by the following formula:

[0104] T(HPO1) = (Y / E b ) × n (7)

[0105] In formula (7), Y represents the thickness of the silicon nitride layer 104, E b represents the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and n represents a given over-etching coefficient.

[0106] Specifically, the fourth etching rate E b can be determined in advance according to the actual situation. The fourth etching rate The given over-etching coefficient n is given in advance, and n usually takes values between 1.2 and 2.

[0107] In another preferred embodiment, the etching time T(HPO2) of the phosphoric acid reagent on the remaining silicon oxynitride layer is determined by the following formula:

[0108] T(HPO2) = (M - Z) / f2(x) (8)

[0109] In formula (8), M represents the thickness of the silicon oxynitride layer, f2(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous etching workload x of phosphoric acid, Z represents the thickness of the part of the silicon oxynitride layer etched by the hydrofluoric acid reagent, M - Z represents the thickness of the remaining silicon oxynitride layer after being etched by the hydrofluoric acid reagent, and the remaining silicon oxynitride is etched by the phosphoric acid reagent.

[0110] In a specific embodiment, the second change data of the etching rate of the phosphoric acid reagent on the silicon oxynitride with respect to the continuous etching workload x of phosphoric acid is collected in advance. According to the second change data, a second curve of the etching rate of the phosphoric acid reagent on the silicon oxynitride with respect to the continuous etching workload of phosphoric acid is plotted. According to the second curve, a function expression corresponding to the third etching rate f2(x) is created, where:

[0111] f2(x) = 10 -7 x 2 -0.0013x + 2.983 (9)

[0112] Please refer to Figure 6 ,Figure 6 The trend diagram of the change of the etching rate of silicon oxynitride by a phosphoric acid reagent provided in an embodiment of the present application with the cumulative usage of phosphoric acid (the product of the cumulative number of wafers etched from the beginning of phosphoric acid and the time required for phosphoric acid to etch a single wafer) is shown. Figure 6 As shown, the horizontal axis is the phosphoric acid continuous etching workload x, the time unit is min (minutes), and the vertical axis represents the phosphoric acid reagent on the silicon oxynitride etching rate, the etching rate unit is / min, L2 represents the second curve of the third etching rate as the phosphoric acid continuous etching workload changes x, and the function expression f2(x)=10 is created from the second curve L2 -7 x 2 -0.0013x+2.983, substituting the phosphoric acid continuous etching workload x into formula (9), the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer 103 under the phosphoric acid continuous etching workload x can be obtained.

[0113] In a preferred embodiment, formula (1) and formula (3) to formula (8) are combined to obtain:

[0114] S={(X / E a )+Z / E 1}×E a +{(Y / E b )×n+(MZ) / f2(x)}×f1(x) (10)

[0115] Among them, the phosphoric acid continuous etching workload x is first determined, and the phosphoric acid continuous etching workload x is respectively substituted into formula (2) and formula (9) to determine the fifth etching rate f1(x) of the phosphoric acid reagent on the oxidation isolation structure 101 and the silicon oxide layer 102 and the third etching rate f2(x) of the phosphoric acid reagent on the silicon oxynitride layer 103 under the phosphoric acid continuous etching workload x.

[0116] The thickness X of the silicon oxide layer 102 and the first etching rate E of the hydrofluoric acid on the silicon oxide layer are a , the second etching rate E of the hydrofluoric acid reagent on the silicon oxynitride layer 103 1 , the thickness Y of the silicon nitride layer 104, and the fourth etching rate E of the phosphoric acid reagent on the silicon nitride layer 104 b, a given excess etching coefficient n, the thickness M of the silicon oxynitride layer 103, the fifth etching rate f1(x) corresponding to the phosphoric acid reagent under the phosphoric acid continuous etching workload x, the third etching rate f2(x) corresponding to the phosphoric acid continuous etching workload x, and the target loss amount S corresponding to the oxide isolation structure 101 after the wafer etching is completed are substituted into formula (10) for solution, and the silicon oxynitride layer thickness Z and etching time required to be etched by the hydrofluoric acid reagent in the silicon oxynitride layer 103, and the remaining silicon oxynitride thickness MZ and etching time required to be etched by the phosphoric acid reagent can be obtained.

[0117] After determining the thickness Z of the silicon oxynitride layer etched by the hydrofluoric acid reagent, formula (3) to formula (5) are combined to obtain:

[0118] T(DHF3)=(X / E a )+Z / E 1 (11)

[0119] The thickness of the silicon oxide layer is X, the first etching rate is E a , the thickness Z of the portion of the silicon oxynitride layer etched by the hydrofluoric acid reagent and the second etching rate E of the hydrofluoric acid reagent on the silicon oxynitride layer 103 1 Substituting into formula (11), the total hydrofluoric acid etching time can be obtained.

[0120] Combining formula (6) to formula (8), we get:

[0121] T(HPO3)=(Y / E b )×n+(MZ) / f2(x) (12)

[0122] The thickness Y of the silicon nitride layer 104 and the fourth etching rate E of the phosphoric acid reagent on the silicon nitride layer 104 are b , given the excess etching coefficient n, the thickness M of the silicon oxynitride layer 103, the thickness Z of the part of the silicon oxynitride layer etched by the hydrofluoric acid reagent, and the third etching rate f2(x) under the continuous phosphoric acid etching workload x are substituted into formula (12) to obtain the total phosphoric acid etching time.

[0123] In step S700, the etching of the wafer is completed by:

[0124] First, use hydrofluoric acid reagent to etch the silicon oxide layer 102 on the surface of the wafer and part of the silicon oxynitride layer of Z thickness. The etching time corresponding to the hydrofluoric acid reagent is the calculated total hydrofluoric acid etching time. Then rinse off the hydrofluoric acid reagent remaining on the surface of the wafer with water. Then, use phosphoric acid reagent to etch the silicon oxynitride layer and silicon nitride layer 104 of MZ thickness on the surface of the wafer. The etching time corresponding to the phosphoric acid reagent is the calculated total phosphoric acid etching time. Finally, rinse off the phosphoric acid reagent remaining on the surface of the wafer with water to complete the etching of the wafer.

[0125] In a specific embodiment, it is assumed that the original thickness of the oxidation isolation structure 101 grown after the wafer undergoes local isolation oxidation treatment and the measured thickness of the silicon nitride layer 104 The thickness of the silicon nitride layer 104 oxidized into silicon oxide (i.e., the corresponding thickness of the silicon oxide layer 102) Among them, the required thickness of the oxidation isolation structure That is, the target loss amount corresponding to the oxidation isolation structure after the wafer etching is completed or the silicon nitride layer is removed (The actual loss amount can fluctuate up and down All meet the requirements), given an over-etching coefficient n = 1.3, the thickness M of the silicon oxynitride layer 103 is set according to experience in this embodiment as ( Indicating angstrom per unit).

[0126] In addition, given: The first etching rate of the hydrofluoric acid reagent on the silicon oxide layer 102 The fourth etching rate of the phosphoric acid reagent on the silicon nitride layer 104 The second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer 103 The continuous etching workload x of the phosphoric acid reagent corresponding to the phosphoric acid = 2500 min.

[0127] In the process of removing the traditional silicon nitride layer:

[0128] Determine:

[0129] T(DHF)_nor = X / E a = 70 / 26 min = 2.69 min

[0130] T(HPO)_nor = (Y / E b )×n = 1500 / 50 min × 1.3 = 39 min

[0131] Among them, T(DHF)_nor represents the etching time corresponding to the hydrofluoric acid reagent calculated in the conventional silicon nitride layer removal method, and T(HPO)_nor represents the etching time corresponding to the phosphoric acid reagent calculated in the conventional silicon nitride layer removal method. Please refer to Figure 7 , Figure 7 shows a wafer etching effect diagram of using the conventional etching method to remove the silicon nitride layer on the wafer. As Figure 7 shown, there are still a large amount of residues in the silicon nitride layer using the conventional etching method, and the silicon nitride layer is not effectively removed.

[0132] For this application, it is calculated that:

[0133] T(DHF1) = (X / Ea ) = 70 / 26 min = 2.69 min

[0134] T(DHF2) = (Z / E 1 ) = Z / 1.26 min

[0135] T(HPO1) = (Y / E b ) × n = (1500 / 50) × 1.3 min = 39 min

[0136]

[0137] T(HPO2) = ((M - Z) / f2(x = 2500)) = ((13 - Z) / 0.4) min

[0138] Obtained from T(DHF1) and T(DHF2):

[0139] T(DHF3) = T(DHF1) + T(DHF2) = (2.69 + Z / 1.26) min

[0140] T(HPO3) = T(HPO1) + T(HPO2) = 39 + ((13 - Z) / 0.4) min

[0141] For T(DHF3) and T(HPO3), it is necessary to satisfy:

[0142] S = T(DHF3) × E a + T(HPO3) × f1(x = 2500)

[0143] Where:

[0144]

[0145]

[0146] That is, obtained:

[0147]

[0148] Finally, it can be obtained That is, in the case of the target loss of silicon oxide corresponding to the silicon oxide in the oxidation isolation structure being Under the required conditions, the thickness of silicon oxynitride removed by hydrofluoric acid is approximately equal to 0, that is, in this case, all the silicon oxynitride needs to be removed by phosphoric acid to meet the requirement of the silicon oxide loss in the oxidation isolation structure, that is, T(DHF3) = 2.69 min, T(HPO3) = 71.5 min.

[0149] Please refer to Figure 8 , Figure 8The figure shows the etching effect diagram of a wafer after removing the silicon nitride layer of the wafer provided by the method of the present application. As Figure 8 shown, etching the wafer using the phosphoric acid etching time and hydrofluoric acid etching time determined by the present application can effectively remove the silicon nitride layer, and the method of the present application also realizes accurate control of the required thickness of the isolation layer. On the premise of meeting the required thickness of the isolation layer, the effective removal of the silicon nitride layer is completed.

[0150] Based on the same inventive concept, the embodiments of the present application also provide a device structure manufacturing and effective etching device corresponding to the manufacturing and effective etching method of a device structure provided in the above embodiments. Since the principle of solving problems by the device in the embodiments of the present application is similar to the manufacturing and effective etching method of the device structure in the above embodiments of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0151] Please refer to Figure 9 , Figure 9 The figure shows the sectional view of the device structure after removing the silicon nitride layer of the wafer provided by the method of the present application. As Figure 9 shown, in combination with the target loss amount of the oxidation isolation structure given in the specific embodiment of step S700 (the actual loss amount can fluctuate up and down ), for the original thickness of the oxidation isolation structure, the target required thickness is (the target loss amount fluctuates up and down , that is, the actual remaining thickness of the oxidation isolation structure after the process is completed is between and , and both meet the process requirements). Applying T(DHF3) = 2.69 min and T(HPO3) = 71.5 min obtained by the method of the present application to etch the wafer, finally, the measured Figure 11 shows that the thicknesses of the isolation oxide layers on the left and right sides are 295.3 nm (i.e., ) and 295.61 nm (about ), respectively. The thicknesses of the isolation oxide layers on the left and right sides are between and , and the corresponding actual loss amounts meet the thickness requirements of the oxidation isolation structure of the present application. It can be seen that the method of the present application can achieve accurate control of the thickness of the oxidation isolation structure and prevent the oxidation isolation structure from being over-etched.

[0152] Please refer to Figure 10 , Figure 10 The figure shows the functional module diagram of a device structure manufacturing and effective etching device provided by the embodiments of the present application. As Figure 10 shown, the device includes:

[0153] Provide module 800 for providing a wafer after local isolation oxidation treatment, in which an oxidation isolation structure and a silicon oxide layer 102, a silicon oxynitride layer 103, a silicon nitride layer 104, a pad oxide layer 105, and a silicon substrate 106 are stacked in sequence from top to bottom.

[0154] Measurement module 810 for measuring the wafer to determine the thickness of the silicon oxide layer 102, the thickness of the silicon nitride layer 104, and the original thickness S of the oxidation isolation structure 1 。

[0155] Etch rate determination module 820 for respectively determining the first etch rate of hydrofluoric acid reagent on the silicon oxide layer 102 and the oxidation isolation structure 101, the second etch rate of hydrofluoric acid reagent on the silicon oxynitride layer 103, the third etch rate of phosphoric acid reagent on the silicon oxynitride layer 103, the fourth etch rate of phosphoric acid reagent on the silicon nitride layer 104, and the fifth etch rate of phosphoric acid reagent on the silicon oxide layer 102 and the oxidation isolation structure 101, where the third etch rate and the fifth etch rate vary with the continuous etching workload of phosphoric acid, and the continuous etching workload of phosphoric acid is the product of the cumulative number of etched wafers starting from fresh phosphoric acid and the time required for phosphoric acid to etch a single wafer.

[0156] Loss amount determination module 830 for determining the target loss amount of the thickness of the oxidation isolation structure during continuous etching according to the original thickness and the required thickness of the oxidation isolation structure.

[0157] First etch time determination module 840 for respectively calculating the thickness and etch time of a part of the silicon oxynitride layer that needs to be etched with hydrofluoric acid reagent and the thickness and etch time of the remaining silicon oxynitride layer that needs to be etched with phosphoric acid reagent according to the target loss amount, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer, and the etch rate.

[0158] Second etch time determination module 850 for obtaining the total hydrofluoric acid etch time for sequentially etching the silicon oxide layer and the silicon oxynitride layer with hydrofluoric acid and the total phosphoric acid etch time for sequentially etching the silicon oxynitride layer and the silicon nitride layer with phosphoric acid according to the thickness and etch time of a part of the silicon oxynitride layer and the thickness and etch time of the remaining silicon oxynitride layer.

[0159] Etch module 860 for using phosphoric acid reagent and hydrofluoric acid reagent to complete the etching of the silicon oxide layer, the silicon oxynitride layer, and the silicon nitride layer of the wafer according to the total hydrofluoric acid etch time and the total phosphoric acid etch time, and obtaining an oxidation isolation structure with a target thickness.

[0160] Based on the same application concept, please refer to Figure 11 , Figure 11The schematic structural diagram of an electronic device provided by an embodiment of the present application is shown. As Figure 11 shown, the electronic device 900 includes: a processor 910, a memory 920, and a bus 930. The memory 920 stores machine-readable instructions executable by the processor 910. When the electronic device 900 runs, communication is carried out between the processor 910 and the memory 920 through the bus 930. When the machine-readable instructions are run by the processor 910, the steps of the manufacturing and effective etching method of the device structure provided in any of the above embodiments are executed.

[0161] Based on the same inventive concept, an embodiment of the present application also provides a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is run by a processor, the steps of the manufacturing and effective etching method of the device structure provided in the above embodiment are executed.

[0162] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein. In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some communication interfaces. The indirect coupling or communication connection of the devices or units can be in electrical, mechanical, or other forms.

[0163] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0164] In addition, in each embodiment of the present application, the functional units can be integrated into one processing unit, or each unit exists physically alone, or two or more units can be integrated into one unit.

[0165] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs.

[0166] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. A method for manufacturing and effectively etching a device structure, characterized in that: The method comprises: Providing a wafer after local isolation oxidation treatment, wherein the wafer is formed with an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked in sequence from top to bottom; Measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, and the original thickness of the oxide isolation structure; Determine respectively a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer and the oxide isolation structure, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the oxide isolation structure, wherein the third etching rate and the fifth etching rate vary with the phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of etched wafers calculated from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer; Determining a target thickness loss amount of the oxide isolation structure during continuous etching according to an original thickness of the oxide isolation structure and a required thickness of the oxide isolation structure; According to the target loss amount, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer and the etching rate, respectively calculating the thickness and etching time of the portion of the silicon oxynitride layer that needs to be etched using a hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched using a phosphoric acid reagent; According to the thickness and etching time of the partial silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer, a total hydrofluoric acid etching time for sequentially etching the silicon oxide layer and the silicon oxynitride layer using hydrofluoric acid and a total phosphoric acid etching time for sequentially etching the silicon oxynitride layer and the silicon nitride layer using phosphoric acid are obtained; Phosphoric acid reagent and hydrofluoric acid reagent are used to complete the etching of the silicon oxide layer, silicon oxynitride layer and silicon nitride layer of the wafer according to the total etching time of hydrofluoric acid and the total etching time of phosphoric acid, and obtain an oxide isolation structure with a target thickness.

2. The method according to claim 1, characterized in that The total phosphoric acid etching time and the total hydrofluoric acid etching time to meet the required thickness of the oxide isolation structure are determined by the following formula: S=T(DHF3)×E a +T(HPO3)×f1(x) In this formula, S represents the target loss amount of the oxide isolation structure after the wafer etching is completed, S=S1-S2, S1 represents the original thickness of the oxide isolation structure before the wafer etching is performed, and S2 represents the required thickness of the oxide isolation structure after the etching is completed. T(DHF3) represents the total hydrofluoric acid etching time, Ea represents the first etching rate, T(HPO3) represents the total phosphoric acid etching time, f1(x) represents the fifth etching rate of the phosphoric acid new acid reagent on the oxidation isolation structure under the phosphoric acid continuous etching workload x, and the fifth etching rate varies as a function of the phosphoric acid continuous etching workload x.

3. The method according to claim 2, characterized in that The total phosphoric acid etching time and the total hydrofluoric acid etching time are expressed by the following formula: In this formula, T(DHF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer, T(DHF2) represents the etching time of the hydrofluoric acid reagent on part of the silicon oxynitride layer, T(HPO1) represents the etching time of the phosphoric acid reagent on the silicon nitride layer, and T(HPO2) represents the etching time of the phosphoric acid reagent on the remaining silicon oxynitride layer.

4. The method according to claim 3, characterized in that The etching time of the silicon oxide layer with hydrofluoric acid is determined by the following formula: In this formula, X represents the thickness of the silicon oxide layer, E a It represents the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer.

5. The method according to claim 3, characterized in that: The etching time of the hydrofluoric acid reagent on the silicon oxynitride layer is determined by the following formula: T(DHF2)=Z / E1 In the formula, Z represents the thickness of the portion of the silicon oxynitride layer etched by the hydrofluoric acid reagent, and E1 represents the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer.

6. The method according to claim 3, characterized in that The etching time of the silicon nitride layer with phosphoric acid reagent is determined by the following formula: T(HPO1)=(Y / E b ) × n In this formula, Y represents the thickness of the silicon nitride layer, E b It represents the fourth etching rate of phosphoric acid reagent on silicon nitride layer, and n represents a given excess etching coefficient.

7. The method according to claim 3, characterized in that The etching time of the remaining silicon oxynitride layer by phosphoric acid reagent is determined by the following formula: T(HPO2)=(MZ) / f2(x) In this formula, M represents the thickness of the silicon oxynitride layer, f2(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous phosphoric acid etching workload x, Z represents the thickness of the partial silicon oxynitride layer etched by the hydrofluoric acid reagent, and MZ represents the thickness of the remaining silicon oxynitride layer after etching with the hydrofluoric acid reagent, and the remaining silicon oxynitride layer is etched by the phosphoric acid reagent.

8. The method according to claim 2, characterized in that: The fifth etching rate of the phosphoric acid reagent on the oxidation isolation structure under the phosphoric acid continuous etching workload x is determined by the following formula: f1(x)=9×10 -8 x 2 -0.0007x+1.5945 Among them, the unit corresponding to the phosphoric acid continuous etching workload x is min, and the unit corresponding to f1(x) is 9. The method according to claim 7, characterized in that: The third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the phosphoric acid continuous etching workload x is determined by the following formula: f2(x)=10 -7 x 2 -0.0013x+2.983 In this formula, f2(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the phosphoric acid continuous etching workload x, where the unit corresponding to the phosphoric acid continuous etching workload x is min, and the unit corresponding to f2(x) is 10. A device structure manufacturing and effective etching device, characterized in that: The device comprises: A module is provided, for providing a wafer after local isolation oxidation treatment, wherein the wafer is formed with an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked in sequence from top to bottom; A measurement module, used to measure the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the original thickness of the oxide isolation structure; An etching rate determination module is used to respectively determine a first etching rate of a hydrofluoric acid reagent on a silicon oxide layer and an oxidation isolation structure, a second etching rate of a hydrofluoric acid reagent on a silicon oxynitride layer, a third etching rate of a phosphoric acid reagent on a silicon oxynitride layer, a fourth etching rate of a phosphoric acid reagent on a silicon nitride layer, and a fifth etching rate of a phosphoric acid reagent on a silicon oxide layer and an oxidation isolation structure, wherein the third etching rate and the fifth etching rate vary with a phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of wafers etched from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer; A loss amount determination module is used to determine a target loss amount of thickness of the oxide isolation structure during continuous etching according to an original thickness of the oxide isolation structure and a required thickness of the oxide isolation structure; A first etching time determination module is used to calculate the thickness and etching time of a portion of the silicon oxynitride layer that needs to be etched using a hydrofluoric acid reagent, and the thickness and etching time of the remaining silicon oxynitride layer that needs to be etched using a phosphoric acid reagent, respectively, according to the target loss amount, the silicon oxide layer thickness, the silicon nitride layer thickness, the silicon oxynitride layer thickness and the etching rate; A second etching time determination module is used to obtain a total hydrofluoric acid etching time for sequentially etching the silicon oxide layer and the silicon oxynitride layer using hydrofluoric acid and a total phosphoric acid etching time for sequentially etching the silicon oxynitride layer and the silicon nitride layer using phosphoric acid according to the thickness and etching time of the partial silicon oxynitride layer and the thickness and etching time of the remaining silicon oxynitride layer; The etching module is used to use phosphoric acid reagent and hydrofluoric acid reagent to etch the silicon oxide layer, silicon oxynitride layer and silicon nitride layer of the wafer according to the total etching time of hydrofluoric acid and the total etching time of phosphoric acid, and obtain an oxide isolation structure with a target thickness.

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