Method for making interconnected through holes

Abstract

A conductive layer is fabricated on a substrate having an upper surface formed from a dielectric material in which electrical conductors or contacts are embedded. Subsequently, a dielectric layer is fabricated on the conductive layer. An opening is formed in the dielectric layer and then filled with a conductive material to form a conductive via, after which the dielectric material and the via are planarized to a coplanar level. Thereafter, at least one hard mask line is formed that overlaps the through-hole such that a shoulder of the through-hole extends on each side of the hard mask line. The dielectric material and the conductive material of the vias and the conductive layer are then removed in areas not covered by the hard mask lines, resulting in a conductive line having interconnecting vias on a top surface thereof. The interconnect via is aligned with a width of the conductive line. The hard mask lines are removed and a planar dielectric surface is fabricated, wherein the top of the interconnect via is coplanar with the planar dielectric surface.

Description

Technical Field

[0001] The present invention relates to semiconductor processing, and more particularly to the formation of interconnect vias between conductors of two levels of a multi-level interconnect structure of a semiconductor chip. Background Art

[0002] Semiconductor-based integrated circuits continue to evolve toward smaller and smaller dimensions, resulting in ongoing processing challenges. Multilayer conductive structures are typically built into individual wire layers with interconnect vias formed between the wires of the various layers. As dimensions shrink, conventional photolithography and etching processes are no longer able to ensure acceptable alignment between the interconnect via and the underlying wire connected to the via.

[0003] Many methods have been developed that enable nanometer-sized interconnect vias to be self-aligned to the conductive (usually metal) lines of the underlying layers. Patent publication US2017256451 discloses a method in which metal lines of the lower levels are formed by a patterning step using a hard mask in the form of a line array, and in which the hard mask lines are maintained on the metal lines, except at the via locations. At these locations, the hard mask is locally removed by lithography and selective etching to produce self-aligned via openings, which are subsequently filled by a damascene metal filling process. However, after the metal lines are patterned, the hard mask lines are reduced in size and / or oxidized, which can make it difficult to make via openings, especially at the deepest levels of a multi-level interconnect structure, where the in-plane dimensions of the via openings may be on the order of a few nanometers.

[0004] Furthermore, residual hard mask material may increase interlayer capacitance, so there is interest in using hard mask materials with low relative dielectric constants. These difficulties reduce the number of suitable choices for hard mask materials, as materials that exhibit low dielectric constants may not necessarily enable good etch selectivity. Summary of the invention

[0005] The present invention aims to provide a solution to the problem indicated above. This object is achieved by a method according to the attached claims. Therefore, the present invention relates to a method for making an interconnection via for connecting a lower conductor to an upper conductor overlying the lower conductor. In the present description and claims, the term "conductor" is intended to refer to a "conductive wire".

[0006] The method is particularly suitable for forming interconnect vias that are nanometer-sized in three orthogonal directions (i.e., in terms of their width, length, and height). In the present context, the term "nanometer-sized" should be understood as having at least one dimension from a few nanometers to tens of nanometers. For example, a nanometer-sized wire is a wire with a nanometer-sized width and height. A nanometer-sized interconnect via is a via with a nanometer-sized width, length, and height.

[0007] According to the invention, a conductive layer is made on a substrate having an upper surface formed of a dielectric material in which an electrical conductor or contact is embedded. The substrate may be, for example, a process wafer on which one or more layers of the FEOL portion and the BEOL portion have been made according to a given layout of a plurality of integrated circuits arranged on the wafer. Subsequently, a dielectric layer is made on the conductive layer. An opening is formed in the dielectric layer, which is then filled with a conductive material, after which the conductive material is flattened to the level of the dielectric material, so that a conductive via is formed in the opening. Thereafter, at least one hard mask line is formed, which overlaps the via so that the shoulder of the via extends on each side of the hard mask line. The dielectric material, the conductive material of the via and the conductive material of the conductive layer are subsequently removed in the area not covered by the hard mask line, thereby obtaining a conductive line having an interconnecting via on its top surface. The interconnecting via is formed by removing the shoulder of the initial via so that the interconnecting via is aligned with the width of the conductor. A second dielectric material is then made and flattened to the top level of the hard mask line. The hard mask line and the upper portion of the second dielectric material are then removed (simultaneously or consecutively) so that a planar dielectric surface is made with the top of the interconnect via coplanar with the planar dielectric surface. Conductive lines of the next level of the interconnect structure can be formed on the planar surface.

[0008] According to a preferred embodiment, a set of parallel conductive lines is formed, on one or more of which a number of self-aligned interconnecting vias are formed, said interconnecting vias being made according to the method of the invention. In the latter case, the second dielectric material is deposited in the spaces between the lines. According to a preferred embodiment, this is done in such a way that air gaps are formed between adjacent lines.

[0009] The method of the present invention is different from the existing method in the following steps of a specific order: after the initial through hole is formed on the top of the blanket conductive layer, the wire of the lower level is etched. The initial through hole obtained by filling the opening becomes an interconnection through hole, and the interconnection through hole is therefore self-aligned with the width of the wire below. The formation (including etching and cleaning steps) and filling of the opening for making the initial through hole are easier, because the width of the opening in the direction perpendicular to the wire is greater than the line width. This results in good through hole to the wire contact formation below, and thus lower inter-wafer non-uniformity, lower through hole resistance and excellent reliability. With regard to the interlayer capacitance of the resulting multi-level interconnect structure, an advantage is that the hard mask line is removed after the formation of the interconnection through hole. In addition, the air gap between the lines can be expanded to the level of the interconnection through hole, thereby providing significant further improvement in capacitance.

[0010] The present invention particularly relates to a method for making an interconnection via for connecting a lower conductive line in a first level of a multi-level interconnection structure to an upper conductive line in a second level covering the first level. The terms first level and second level refer to any two consecutive levels of an interconnection structure. The method comprises the following steps:

[0011] providing a substrate having an upper surface formed of a dielectric material in which electrical conductors or contacts are embedded,

[0012] forming a layer of a first conductive material on the upper surface, and forming a dielectric layer formed of a first dielectric material on the layer of the first conductive material,

[0013] making an opening in the dielectric layer so as to expose the first conductive material at the bottom of the opening,

[0014] filling the opening with a second conductive material which may be the same as or different from the first conductive material,

[0015] planarizing the surface of the dielectric layer so as to obtain a conductive via embedded in the dielectric layer, wherein the upper surface of the via is coplanar with the upper surface of the dielectric layer, these upper surfaces forming a planarized surface,

[0016] forming a hard mask layer on the planarized surface,

[0017] patterning the hard mask layer to form hard mask lines that overlap an upper surface of the via such that a shoulder of the via extends laterally on each side of the hard mask lines,

[0018] removing the dielectric layer and the first and second conductive materials in areas not covered by the hard mask lines, thereby obtaining conductive lines, wherein interconnect vias are formed on the conductive lines by removing the shoulders of the vias so that the width of the interconnect vias is aligned with the width of the conductive lines,

[0019] forming a layer of a second dielectric material, the second dielectric material being the same as or different from the first dielectric material, wherein the second dielectric material encapsulates the hard mask line,

[0020] planarizing the second dielectric material layer to a level of a top of the hard mask line,

[0021] The hard mask lines and upper portions of the second dielectric material are removed, thereby producing a planar surface formed of the second dielectric material, wherein the interconnect via is embedded in the planar surface and has a top surface coplanar with the planar surface.

[0022] According to an embodiment, the hard mask line is one of an array of parallel lines.

[0023] According to an embodiment, the second dielectric material is deposited in such a way that air gaps are created between adjacent conductive lines.

[0024] According to an embodiment, an air gap is formed on each side of the conductive line on which the interconnection via is formed, and wherein the two air gaps have a top portion overlapping a lower portion of a height of the interconnection via.

[0025] According to an embodiment, the height (H1) of the top portions of the two air gaps is at least 50% of the height of the interconnecting vias.

[0026] According to an embodiment, the interconnect vias have nanometer-sized dimensions in three orthogonal directions.

[0027] According to an embodiment, the height of the interconnect via is between 10 nm and 30 nm.

[0028] According to an embodiment, the opening is filled by a bottom-up filling technique and wherein the step of planarizing the surface of the dielectric layer is performed without a CMP (chemical mechanical polishing) step.

[0029] According to an embodiment, the first and second conductive materials are selected from the group consisting of Ru, W and Mo.

[0030] According to an embodiment, the first and second dielectric materials are SiO 2 or low-K materials.

[0031] According to an embodiment, an adhesive layer is produced on the substrate before forming the layer of the first conductive material, and / or wherein an adhesive layer is produced on the layer of the first conductive material before forming the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 9 The key steps of the method according to the embodiment of the present invention are explained.

[0033] Fig.10 and Fig.11 An embodiment is illustrated in which air gaps are created between adjacent conductive lines.

[0034] Fig.12 is a cross-sectional view of a more realistic appearance of an air gap and its associated dimensions in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0035] One embodiment of the method of the present invention will now be described in detail.Any references to material selection and dimensions are included by way of example only and do not limit the scope of the present invention which is defined solely by the appended claims.

[0036] Figure 1 A small portion of a substrate including a base portion 1 is shown, which can be a nano-sized upper slice of a silicon process wafer after front-end-of-line (FEOL) processing and a portion of back-end-of-line (BEOL) processing. As known to those skilled in the art of semiconductor processing, the FEOL process includes a series of processing steps for making a large number of semiconductor devices, such as transistors and diodes, on a typical silicon wafer according to the layout of several integrated circuit chips. The BEOL processing adds a multi-level interconnect structure on top of the FEOL portion of the chip, the interconnect structure including multiple levels of conductive lines that are interconnected by vertical interconnects (referred to as "interconnect vias" in this specification) according to a predefined interconnection scheme. The interconnection levels are usually labeled Metal0, Metal1, Metal2, etc. (abbreviated as M0, M1, M2, etc.) because the line material is usually a metal such as Cu, W or Ru. The deepest level M0 includes connections that are in direct contact with active devices in the FEOL and is also called the middle process part (MOL) of the integrated circuit.

[0037] The top surface of the substrate portion 1 is formed of a dielectric material, such as SiO2 or a low-K dielectric, on which the wires of the interconnect level Mi will be formed. Embedded in the dielectric layer are electrical conductors or contacts, which may include wires in the level Mi-1 or interconnect vias intended to connect the wires of the level Mx to the wires of the level Mi-1, or if the level Mi-1 is the M0 level (MOL) then to the source or drain of the transistors of the FEOL part.

[0038] The method of the invention comprises method steps for forming one or more lines of any level Mi and one or more interconnecting vias towards lines of level Mi+1, i=0, 1, 2, 3, . . . . .

[0039] like Figure 1 As shown, two layers are made on the top surface of the base part 1. The first layer 2 is a conductive layer. For deep layers of the BEOL (e.g. i=1 to 3), this can be a layer of, for example, Ru, W or Mo. For some materials, such as Ru, it may be necessary to provide an adhesion layer, such as a thin TiN layer, between the base substrate 1 and the Ru layer 2.

[0040] On top of the conductive layer 2, a layer 3 of dielectric material, such as SiO2 or a low-K dielectric, is deposited. Depending on the material of layer 2, an adhesive layer may again be required between the conductive layer 2 and the dielectric layer 3. However, an exemplary case is shown in which no adhesive layer is applied. The thickness of the individual layers depends on the metallization level to which the method is applied, i.e. the value of i. The method of the present invention can be applied to the deepest levels and provides the greatest benefits at these levels, given the importance of controlling the alignment of the vias to nanometer-sized dimensions that can be applied to these deep levels. For example, for i=2 (making of interconnect vias between M2 and M3), the thickness of layer 2 can be on the order of 25nm, while the thickness of layer 3 can be on the order of 15nm.

[0041] refer to Figure 2 , an opening 4 is now formed in the dielectric layer 3. In most cases, especially at deeper levels, a plurality of such openings are formed simultaneously at each desired via location on the wafer. The opening 4 is a cavity that opens to the surface of the dielectric layer 3. The opening 4 is shown as having a rectangular cross section, but the opening can be shaped differently, for example with an elliptical or circular cross section. For i=2, the lateral dimensions of the opening can be, for example, of the order of 18 nm in the x- and y-directions, cf. Figure 2 , orthogonal axes included in . A known way to make openings of these sizes is to apply a hard mask formed by a stack of SOC (spin on carbon), SOG (spin on glass) and photoresist. The photoresist is patterned to form an opening larger than the target size, and a shrinking technique is applied to achieve the desired size of the opening 4. Such shrinking techniques are known and their details are not needed here. For larger values ​​of i, i.e. at higher levels in the BEOL stack, a more straightforward lithography and etching process can be used because the lateral dimensions of the opening will be larger at these levels.

[0042] The bottom of the opening 4 is formed by the conductive material of layer 2. Therefore, if there is an adhesive layer between layer 2 and layer 3, it is necessary to remove the adhesive layer selectively with respect to the material of layer 2.

[0043] Subsequently, the opening 4 is filled with a second conductive material which may be the same as or different from the conductive material of layer 2. An additional conductive adhesive liner on the bottom of the opening 4 may be required before filling the opening with the second material.

[0044] Filling the opening 4 can be done by known techniques such as CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), which will result in a thick layer of the second conductive material on top of the dielectric layer 3. This layer is then removed by grinding and CMP (Chemical Mechanical Polishing) until a layer such as Figure 3The planarized surface shown is formed by the dielectric material of layer 3, with islands 5 of conductive material coplanar therewith. Island 5 forms the top surface of a via 6 of conductive material that is in electrical contact with the underlying conductive layer 2. Via 6 is Figure 3 The vias are represented by several auxiliary lines that help visualize the location of the vias relative to Layers 2 and 3.

[0045] Another way to fill the opening 4 is by a bottom-up filling technique (known per se), in which the via 6 is created from the bottom of the opening 4 and the via material is not deposited on the dielectric layer 3 until the opening is filled. This produces only a thin layer of conductive material on the dielectric layer 3, which can be removed by a wet etching process without the need for CMP. This approach enables better control of the height of the via 6.

[0046] refer to Figure 4 A hard mask layer is then produced on the planarized surface and patterned according to a regular pattern of parallel lines 7 oriented in the x-direction and having substantially the same width and height.

[0047] The width of line 7 is less than the y dimension of island 5, for example for i=2, line 7 may have a width and pitch of approximately 9 nm. As shown, one line 7a overlaps via 6 so that the lateral shoulders 6a and 6b of via 6 extend on both sides of said line 7a without overlapping with adjacent lines 7b and 7c. Preferably and as shown, the lithography and etching steps for making line 7 are configured to make line 7a concentric with respect to said y dimension of via 6. However, unavoidable overlap errors of 1 or 2 nm may lead to slight deviations from this theoretical situation. In any case, line 7 is formed in such a way that the two shoulders 6a and 6b of the conductive via 6 are exposed on both sides of the hard mask line 7a.

[0048] One or more etching steps are then performed to transfer the hard mask line pattern to the underlying layers. Figure 5 and Figure 6 The images shown illustrate a two-step process, but depending on the material and size of the application, a one-step process may also be appropriate. Figure 5 As can be seen in FIG. 1 , in the area not covered by the hard mask line 7 , the dielectric layer 3 is selectively removed relative to the conductive via 6 , thereby forming the dielectric line 3 on the conductive layer 2 and exposing the shoulders 6 a and 6 b of the via 6 . Figure 6 In the second etching step shown, the vias 6 and the conductive material of the underlying layer 2 are etched in the areas not covered by the hard mask lines 7, thereby producing parallel conductive lines 8a, 8b and 8c.

[0049] In a second etching step, shoulders 6a and 6b of conductive via 6 are removed. What remains of initial via 6 is interconnect via 10 aligned with the width of underlying conductive line 8a. Dielectric line 3 on top of conductive line 8a is interrupted by interconnect via 10.

[0050] Since the initial via 6 is formed before forming the conductive line 8a, the alignment of the interconnecting via 10 with the y-dimension of the conductive line 8a is in fact self-aligning: the interconnecting via 6 automatically aligns with the conductive line 8a due to the nature of the production process.

[0051] In the x-direction, the dimension of the interconnecting via 10 is substantially the same as the x-dimension of the initial via 6 .

[0052] exist Figure 5 and Figure 6 In the figures, the hard mask lines 7 are shown as having an initial thickness prior to the etching step illustrated in these images, which represents an ideal case where the etching selectivity is about 100%. In practice, the thickness of the hard mask lines 7 may be slightly reduced and / or become partially oxidized. However, these possible occurrences do not affect the performance of subsequent method steps according to the present invention. Furthermore, the present invention is explained with respect to an embodiment in which a set of parallel lines 7 are formed, which will almost always be the case, especially at deeper BEOL levels, but the present invention is theoretically applicable to a single line 7a configured to form a single conductive line with self-aligned interconnect vias formed thereon.

[0053] The remainder of the method includes removing the hard mask lines 7 and embedding interconnect vias 10 in the dielectric layer in preparation for making the next interconnect level on the dielectric layer. Figure 7-9 and 10-12 describe two alternative ways of achieving this.

[0054] refer to Figure 7 , a dielectric material 11 is formed on the obtained conductive lines 8a-8c and interconnecting vias 10. Figure 7 In the first embodiment shown, dielectric material 11 is formed in such a way that it completely fills the spaces between conductive lines 8a-8c and completely encapsulates conductive lines 8a-8c, dielectric line 3 and hard mask line 7. Dielectric material 11 may or may not be the same material as layer 3, such as SiO2 or a low-K dielectric material.

[0055] Then, if Figure 8 As shown, the top surface of the dielectric material 11 is planarized until the hard mask line 7 is exposed, and as shown in FIG. Fig. 9 As shown, the hard mask lines 7 and the dielectric material between these hard mask lines are removed. The latter step can be completed by a cyclic dry etching process that removes both the dielectric material 11 and the hard mask material 7. Preferably, no CMP is used to obtain Fig. 9The hard mask material is completely removed, which is an advantage over many prior art methods in terms of avoiding parasitic capacitances that may be caused by the hard mask material, the possibility to select the hard mask based solely on etch related properties (such as etch selectivity relative to the material of layers 2 and 3 and via 6), and the ability to remove the hard mask line 7 and the second dielectric material 11 simultaneously.

[0056] refer to Fig. 9 , the result of the method of the invention is a dielectric surface 12 with which the top surface of the interconnect via 10 is coplanar. This surface is ready to receive on it another conductive layer which is subsequently patterned to form the conductive lines of the next BEOL level Mi+1. For i=2, this is the M3 level. These M3 lines can be oriented in the y direction and have a width of the order of the x dimension of the interconnect via 10. The fabrication of these M3 lines (or Mi+1 lines in general) can be achieved according to known methods.

[0057] Fig.10 and Fig.11 Another embodiment is illustrated, according to which the dielectric material 11 is deposited in such a way that the spaces between adjacent conductive lines 8a-8c are not completely filled. Instead, so-called air gaps 15 are formed. This is a known phenomenon, and methods for intentionally forming these air gaps are well known in the prior art. After the dielectric material 11 is deposited in this way, a planarization step and removal of the hard mask line 7 are performed in the same way as described above, so as to obtain the following: Fig.11 Image shown.

[0058] exist Fig.10 and Fig.11 In FIG. 1 , the air gap 15 is represented as having no dielectric material deposited below a given level in the z direction, but this is only a symbolic representation. In reality, some dielectric material is deposited on the side walls of the wires 8 a - 8 c and on the substrate 1 , while a gas-filled cavity of more or less elliptical cross-section remains in the space between the wires. This more realistic representation is shown in FIG. Fig.12 As shown in the cross-sectional view.

[0059] It is known that including air gaps between adjacent conductive lines significantly reduces the capacitance of the insulating material of the interconnect structure. Forming air gaps in structures where interconnect vias are made by the method according to the present invention is particularly advantageous. This is because the specific sequence of process steps enables the creation of higher air gaps compared to other processing methods. This is particularly advantageous in Fig.12 8a / 8b and 8a / 8c has a top portion 15a directly adjacent to the interconnect via 10. This arrangement of the air gap results in a significant reduction in the fringe capacitance between the via and the adjacent conductor in the interconnect structure. The overlap between the air gap 15 and the interconnect via 10 is represented as Fig.12, where H2 represents the thickness of the remaining dielectric material above the air gap 15, where H1+H2 substantially corresponds to the height of the interconnect via 10. H2 needs to be large enough to ensure that the planarized surface 12 is uniform. According to a preferred embodiment, the via height is adjusted so that H1 is as high as possible relative to the via height. The overlap height H1 is preferably at least 50% of the via height. For example, at i=2, H2 is preferably at least 5nm, and the via height can be configured between 10nm and 30nm, so that H1 can be 50% or up to 83%, depending on the via height.

[0060] The present invention is applicable to any production process of a multi-level interconnect structure, such as the BEOL portion of a semiconductor chip or the back power delivery network of a chip. Although the present invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary rather than restrictive. By studying the drawings, the present disclosure and the appended claims, a person skilled in the art may understand and implement other variations of the disclosed embodiments in practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are stated in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

[0061] Unless specified, descriptions of a layer being present, deposited or fabricated 'on' another layer or substrate include the following options:

[0062] The layer is present, produced or deposited directly on the other layer or substrate, i.e. in physical contact with the other layer or substrate, and

[0063] The layer is present, produced or deposited on one or a stack of intermediate layers between the layer and the further layer or substrate.

Claims

1. A method for making an interconnection via (10) for connecting a lower conductive line (8a) in a first level of a multi-level interconnection structure to an upper conductive line in a second level covering the first level, the method comprising the following steps: providing a substrate (1) having an upper surface formed of a dielectric material in which electrical conductors or contacts are embedded, A layer (2) of a first conductive material is formed on the upper surface, and a dielectric layer (3) formed of a first dielectric material is formed on the layer (2) of the first conductive material, making an opening (4) in the dielectric layer (3) so as to expose the first conductive material at the bottom of the opening (4), filling the opening (4) with a second conductive material which is the same as or different from the first conductive material, planarizing the surface of the dielectric layer (3) to obtain a conductive via (6) embedded in the dielectric layer (3), wherein the upper surface (5) of the via (6) is coplanar with the upper surface of the dielectric layer (3), these upper surfaces forming a planarized surface, forming a hard mask layer on the planarized surface, patterning the hard mask layer to form a hard mask line (7a) overlapping the upper surface (5) of the through hole (6) so that shoulders (6a, 6b) of the through hole (6) extend laterally on each side of the hard mask line (7a), removing the dielectric layer (3) and the first and second conductive materials in the areas not covered by the hard mask lines (7a) to obtain conductive lines (8a), wherein interconnecting vias (10) are formed on the conductive lines by removing the shoulders of the vias (6) so that the width of the interconnecting vias (10) is aligned with the width of the conductive lines (8a), forming a layer (11) of a second dielectric material, the second dielectric material being the same as or different from the first dielectric material, wherein the second dielectric material encapsulates the hard mask line (7a), planarizing the second dielectric material layer (11) to the top level of the hard mask line (7a), The hard mask line (7a) and an upper portion of the second dielectric material are removed to produce a planar surface (12) formed of the second dielectric material, wherein the interconnect via (10) is embedded in the planar surface (12) and has a top surface coplanar with the planar surface (12).

2. The method according to claim 1, characterized in that: The hard mask line (7a) is one of an array of parallel lines (7).

3. The method according to claim 2, characterized in that The second dielectric material is deposited in such a way that air gaps (15) are created between adjacent conductive lines (8).

4. The method according to claim 3, characterized in that An air gap (15) is formed on each side of the conductive line (8a) on which the interconnection via (10) is formed on top, and wherein the two air gaps have a top portion (15a) overlapping a lower portion of the height of the interconnection via (10).

5. The method according to claim 4, characterized in that The height (H1) of the top portions (15a) of the two air gaps is at least 50% of the height of the interconnection vias (10).

6. The method according to any one of the preceding claims, characterized in that The interconnecting through-holes (10) have nano-sized dimensions in three orthogonal directions.

7. The method according to claim 6, characterized in that The height of the interconnecting through-hole (10) is between 10 nm and 30 nm.

8. The method according to any one of the preceding claims, characterized in that The opening (4) is filled by a bottom-up filling technique, and the step of planarizing the surface of the dielectric layer (3) is performed without a chemical mechanical polishing (CMP) step.

9. The method according to any one of the preceding claims, characterized in that The first conductive material and the second conductive material are selected from the group consisting of Ru, W, and Mo.

10. The method according to any one of the preceding claims, characterized in that The first dielectric material and the second dielectric material are SiO 2 or low-K materials.

11. The method according to any one of the preceding claims, characterized in that An adhesive layer is formed on the substrate (1) before forming the layer (2) of the first conductive material, and / or an adhesive layer is formed on the layer (2) of the first conductive material before forming the dielectric layer (3).

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